diff options
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/Makefile | 2 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch | 4 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h | 2 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/main.c | 8 | ||||
| -rw-r--r-- | demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c | 34 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/hal_lld.c | 32 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/hal_lld.h | 11 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/stm32_registry.h | 1 |
9 files changed, 73 insertions, 27 deletions
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile b/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile index 27657cab7..fd027130d 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+ USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch index 231d19717..798eef66e 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/debug/RT-STM32H743I-NUCLEO144 (OpenOCD, Flash and Run).launch @@ -33,9 +33,9 @@ <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> -<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)" val="4"/></contentList>"/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="CR3-pwr-init_pwr-(format)" val="4"/><content id="CR2-pwr-init_pwr-(format)" val="4"/><content id="CSR1-pwr-init_pwr-(format)" val="4"/><content id="CR1-pwr-init_pwr-(format)" val="4"/><content id="RESERVED10-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HLPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LLPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3LPENR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED9-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LENR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3ENR-rcc-stm32_clock_init-(format)" val="4"/><content id="RSR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED8-rcc-stm32_clock_init-(format)" val="4"/><content id="D3AMR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED7-rcc-stm32_clock_init-(format)" val="4"/><content id="GCR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB4RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB2RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1HRSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB1LRSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="APB3RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB4RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB2RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB1RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="AHB3RSTR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED6-rcc-stm32_clock_init-(format)" val="4"/><content id="CSR-rcc-stm32_clock_init-(format)" val="4"/><content id="BDCR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED5-rcc-stm32_clock_init-(format)" val="4"/><content id="CICR-rcc-stm32_clock_init-(format)" val="4"/><content id="CIFR-rcc-stm32_clock_init-(format)" val="4"/><content id="CIER-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED4-rcc-stm32_clock_init-(format)" val="4"/><content id="D3CCIPR-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CCIP2R-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CCIP1R-rcc-stm32_clock_init-(format)" val="4"/><content id="D1CCIPR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED3-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL3FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL3DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL2FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL2DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL1FRACR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLL1DIVR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLLCFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="PLLCKSELR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED2-rcc-stm32_clock_init-(format)" val="4"/><content id="D3CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="D2CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="D1CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED1-rcc-stm32_clock_init-(format)" val="4"/><content id="CFGR-rcc-stm32_clock_init-(format)" val="4"/><content id="RESERVED0-rcc-stm32_clock_init-(format)" val="4"/><content id="CRRCR-rcc-stm32_clock_init-(format)" val="4"/><content id="ICSCR-rcc-stm32_clock_init-(format)" val="4"/><content id="CR-rcc-stm32_clock_init-(format)" val="4"/><content id="rcc-stm32_clock_init-(format)" val="4"/><content id="r3-(format)" val="4"/><content id="r2-(format)" val="4"/><content id="delta-next-vtlist-null-_idle_thread.lto_priv.25-(format)" val="4"/></contentList>"/> <stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> -<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList> <memoryBlockExpressionItem> <expression text="0x0"/> </memoryBlockExpressionItem> </memoryBlockExpressionList> "/> +<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList> <memoryBlockExpressionItem> <expression text="0x0"/> </memoryBlockExpressionItem> <memoryBlockExpressionItem> <expression text="0x11087000"/> </memoryBlockExpressionItem> </memoryBlockExpressionList> "/> <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32H743I-NUCLEO144"/> <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h index fc148a68e..5aec384f3 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/halconf.h @@ -34,7 +34,7 @@ * @brief Enables the PAL subsystem.
*/
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
-#define HAL_USE_PAL FALSE
+#define HAL_USE_PAL TRUE
#endif
/**
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c index 98d13a7c6..c070cd9a9 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/main.c +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/main.c @@ -29,9 +29,9 @@ static THD_FUNCTION(Thread1, arg) { (void)arg;
chRegSetThreadName("blinker");
while (true) {
-// palSetLine(LINE_ARD_D13);
+ palSetLine(LINE_ARD_D13);
chThdSleepMilliseconds(500);
-// palClearLine(LINE_ARD_D13);
+ palClearLine(LINE_ARD_D13);
chThdSleepMilliseconds(500);
}
}
@@ -54,8 +54,8 @@ int main(void) { /*
* ARD_D13 is programmed as output (board LED).
*/
-// palClearLine(LINE_ARD_D13);
-// palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
+ palClearLine(LINE_ARD_D13);
+ palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL);
/*
* Activates the serial driver 1 using the driver default configuration.
diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h index 9336ca4de..39359e7c6 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h @@ -45,12 +45,10 @@ * Register constants are taken from the ST header.
*/
#define STM32_VOS STM32_VOS_SCALE1
-#define STM32_PWR_CR1 (PWR_CR1_PVDEN | \
- PWR_CR1_SVOS_1 | \
+#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | \
PWR_CR1_SVOS_0)
#define STM32_PWR_CR2 (PWR_CR2_BREN)
-#define STM32_PWR_CR3 (PWR_CR3_SCUEN | \
- PWR_CR3_LDOEN | \
+#define STM32_PWR_CR3 (PWR_CR3_LDOEN | \
PWR_CR3_USBREGEN | \
PWR_CR3_USB33DEN)
#define STM32_PWR_CPUCR 0
diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c index 85d16a375..f8ac6b761 100644 --- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c @@ -158,8 +158,13 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Multiple channel setting of the same channel not allowed, first disable
it. This is done because on STM32 the same channel cannot be mapped on
multiple ports.*/
+#if defined(STM32_EXTI_ENHANCED)
+ osalDbgAssert(((EXTI->RTSR1 & padmask) == 0U) &&
+ ((EXTI->FTSR1 & padmask) == 0U), "channel already in use");
+#else
osalDbgAssert(((EXTI->RTSR & padmask) == 0U) &&
((EXTI->FTSR & padmask) == 0U), "channel already in use");
+#endif
/* Index and mask of the SYSCFG CR register to be used.*/
cridx = (uint32_t)pad >> 2U;
@@ -174,6 +179,20 @@ void _pal_lld_enablepadevent(ioportid_t port, SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
/* Programming edge registers.*/
+#if defined(STM32_EXTI_ENHANCED)
+ if (mode & PAL_EVENT_MODE_RISING_EDGE)
+ EXTI->RTSR1 |= padmask;
+ else
+ EXTI->RTSR1 &= ~padmask;
+ if (mode & PAL_EVENT_MODE_FALLING_EDGE)
+ EXTI->FTSR1 |= padmask;
+ else
+ EXTI->FTSR1 &= ~padmask;
+
+ /* Programming interrupt and event registers.*/
+ EXTI_D1->IMR1 |= padmask;
+ EXTI_D1->EMR1 &= ~padmask;
+#else
if (mode & PAL_EVENT_MODE_RISING_EDGE)
EXTI->RTSR |= padmask;
else
@@ -186,6 +205,7 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Programming interrupt and event registers.*/
EXTI->IMR |= padmask;
EXTI->EMR &= ~padmask;
+#endif
}
/**
@@ -200,8 +220,13 @@ void _pal_lld_enablepadevent(ioportid_t port, void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
uint32_t padmask, rtsr1, ftsr1;
+#if defined(STM32_EXTI_ENHANCED)
+ rtsr1 = EXTI->RTSR1;
+ ftsr1 = EXTI->FTSR1;
+#else
rtsr1 = EXTI->RTSR;
ftsr1 = EXTI->FTSR;
+#endif
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@@ -222,12 +247,21 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { osalDbgAssert(crport == portidx, "channel mapped on different port");
+#if defined(STM32_EXTI_ENHANCED)
+ /* Disabling channel.*/
+ EXTI_D1->IMR1 &= ~padmask;
+ EXTI_D1->EMR1 &= ~padmask;
+ EXTI->RTSR1 = rtsr1 & ~padmask;
+ EXTI->FTSR1 = ftsr1 & ~padmask;
+ EXTI_D1->PR1 = padmask;
+#else
/* Disabling channel.*/
EXTI->IMR &= ~padmask;
EXTI->EMR &= ~padmask;
EXTI->RTSR = rtsr1 & ~padmask;
EXTI->FTSR = ftsr1 & ~padmask;
EXTI->PR = padmask;
+#endif
#if PAL_USE_CALLBACKS || PAL_USE_WAIT
/* Callback cleared and/or thread reset.*/
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c index ef8a6fae9..e39f06ec2 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -36,7 +36,7 @@ * @brief CMSIS system core clock variable.
* @note It is declared in system_stm32f7xx.h.
*/
-uint32_t SystemCoreClock = STM32_HCLK;
+uint32_t SystemCoreClock = STM32_C_CK;
/*===========================================================================*/
/* Driver local variables and types. */
@@ -92,23 +92,22 @@ static inline void init_bkp_domain(void) { * @brief Initializes the PWR unit.
*/
static inline void init_pwr(void) {
+#if 0
+ PWR_TypeDef *pwr = PWR; /* For inspection.*/
+ (void)pwr;
+#endif
- PWR->CR1 = STM32_PWR_CR1;
+ PWR->CR1 = STM32_PWR_CR1 | 0xF0000000;
PWR->CR2 = STM32_PWR_CR2;
PWR->CR3 = STM32_PWR_CR3;
- PWR->CR1 = STM32_PWR_CR1;
PWR->CPUCR = STM32_PWR_CPUCR;
PWR->D3CR = STM32_VOS;
while ((PWR->CSR1 & PWR_CSR1_ACTVOS) == 0)
;
#if STM32_PWR_CR2 & PWR_CR2_BREN
- while ((PWR->CR2 & PWR_CR2_BRRDY) == 0)
- ;
- rccEnableBKPRAM(false);
-#endif
-#if STM32_PWR_CR3 & PWR_CR3_USB33DEN
- while ((PWR->CR3 & PWR_CR3_USB33RDY) == 0)
- ;
+// while ((PWR->CR2 & PWR_CR2_BRRDY) == 0)
+// ;
+// rccEnableBKPRAM(false);
#endif
}
@@ -158,8 +157,19 @@ void hal_lld_init(void) { * @special
*/
void stm32_clock_init(void) {
+#if 0
+ RCC_TypeDef *rcc = RCC; /* For inspection.*/
+ (void)rcc;
+#endif
#if STM32_NO_INIT == FALSE
+#if !defined(STM32_DISABLE_ERRATA_2_2_15)
+ /* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data
+ read corruption.
+ AXI->TARG7_FN_MOD.*/
+ *((volatile uint32_t *)0x51000000 + 0x1108 + 0x7000) = 0x00000001U;
+#endif
+
/* PWR initialization.*/
init_pwr();
@@ -326,7 +336,7 @@ void stm32_clock_init(void) { from HSI.*/
#if STM32_SW != STM32_SW_HSI_CK
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
- while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 3U))
;
#endif
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index e29b9423d..9f9818f18 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -538,8 +538,7 @@ * @brief PWR CR1 initializer.
*/
#if !defined(STM32_PWR_CR1) || defined(__DOXYGEN__)
-#define STM32_PWR_CR1 (PWR_CR1_PVDEN | \
- PWR_CR1_SVOS_1 | \
+#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | \
PWR_CR1_SVOS_0)
#endif
@@ -554,8 +553,7 @@ * @brief PWR CR3 initializer.
*/
#if !defined(STM32_PWR_CR3) || defined(__DOXYGEN__)
-#define STM32_PWR_CR3 (PWR_CR3_SCUEN | \
- PWR_CR3_LDOEN | \
+#define STM32_PWR_CR3 (PWR_CR3_LDOEN | \
PWR_CR3_USBREGEN | \
PWR_CR3_USB33DEN)
#endif
@@ -2069,6 +2067,11 @@ #endif
/**
+ * @brief Core clock.
+ */
+#define STM32_C_CK STM32_SYS_D1CPRE_CK
+
+/**
* @brief HCLK clock.
*/
#if (STM32_D1HPRE == STM32_D1HPRE_DIV1) || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h index df64d5a39..b615d32e4 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -77,6 +77,7 @@ #define STM32_ETH_NUMBER 61
/* EXTI attributes.*/
+#define STM32_EXTI_ENHANCED
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
|