diff options
| -rw-r--r-- | os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h | 24 | ||||
| -rw-r--r-- | testhal/SPC563Mxx/ADC/mcuconf.h | 20 |
2 files changed, 43 insertions, 1 deletions
diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h index 667f9648b..a0ded1eb4 100644 --- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h +++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h @@ -267,6 +267,21 @@ #define ADC_ACR_RESSEL_8BITS (2U << 6)
/** @} */
+/**
+ * @name ADC PUDCRx registers definitions
+ * @{
+ */
+#define ADC_PUDCR_NONE 0x0000
+#define ADC_PUDCR_UP_200K 0x1100
+#define ADC_PUDCR_UP_100K 0x1200
+#define ADC_PUDCR_UP_5K 0x1300
+#define ADC_PUDCR_DOWN_200K 0x2100
+#define ADC_PUDCR_DOWN_100K 0x2200
+#define ADC_PUDCR_DOWN_5K 0x2300
+#define ADC_PUDCR_UP_DOWN_200K 0x3100
+#define ADC_PUDCR_UP_DOWN_100K 0x3200
+/** @} */
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -424,7 +439,14 @@ * @brief Initialization value for PUDCRx registers.
*/
#if !defined(SPC5_ADC_PUDCR) || defined(__DOXYGEN__)
-#define SPC5_ADC_PUDCR {0, 0, 0, 0, 0, 0, 0, 0}
+#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE}
#endif
/** @} */
diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h index bca85fb65..b3f742baf 100644 --- a/testhal/SPC563Mxx/ADC/mcuconf.h +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -51,7 +51,27 @@ #define SPC5_ADC_USE_ADC1_Q3 TRUE
#define SPC5_ADC_USE_ADC1_Q4 TRUE
#define SPC5_ADC_USE_ADC1_Q5 TRUE
+#define SPC5_ADC_FIFO0_DMA_PRIO 12
+#define SPC5_ADC_FIFO1_DMA_PRIO 12
+#define SPC5_ADC_FIFO2_DMA_PRIO 12
+#define SPC5_ADC_FIFO3_DMA_PRIO 12
+#define SPC5_ADC_FIFO4_DMA_PRIO 12
+#define SPC5_ADC_FIFO5_DMA_PRIO 12
+#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
+#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
+#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
+#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12
+#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12
+#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12
#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
+#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE, \
+ ADC_PUDCR_NONE}
/*
* SERIAL driver system settings.
|