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-rw-r--r--demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h9
-rw-r--r--os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h21
-rw-r--r--os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c28
-rw-r--r--os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h45
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/platform.mk1
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h4
-rw-r--r--readme.txt2
-rw-r--r--testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h9
-rw-r--r--tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl9
9 files changed, 124 insertions, 4 deletions
diff --git a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
index 0fc6fee66..df84ecf33 100644
--- a/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32L4R5ZI-NUCLEO144/cfg/mcuconf.h
@@ -140,6 +140,15 @@
/*
* DAC driver system settings.
*/
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
+#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
/*
* GPT driver system settings.
diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
index 27f3c6ff0..99a8f5244 100644
--- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
@@ -494,7 +494,6 @@
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_DMA_SUPPORTS_DMAMUX
-
#if STM32_ADC_USE_ADC1 && !defined(STM32_ADC_ADC1_DMA_CHANNEL)
#error "ADC1 DMA channel not defined"
#endif
@@ -552,6 +551,26 @@
#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
+#if STM32_ADC_USE_ADC1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC2"
+#endif
+
+#if STM32_ADC_USE_ADC3 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_USE_ADC4 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC4_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC4"
+#endif
+
/* ADC clock source checks.*/
#if defined(STM32F3XX)
#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
index 0f041110e..811918495 100644
--- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
+++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
@@ -87,7 +87,11 @@ static const dacparams_t dma1_ch1_params = {
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
+#if STM32_DMA_SUPPORTS_DMAMUX
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_CHANNEL),
+#else
.dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
+#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
@@ -103,7 +107,11 @@ static const dacparams_t dma1_ch2_params = {
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
+#if STM32_DMA_SUPPORTS_DMAMUX
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_CHANNEL),
+#else
.dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
+#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
@@ -119,7 +127,11 @@ static const dacparams_t dma2_ch1_params = {
.dataoffset = 0U,
.regshift = 0U,
.regmask = 0xFFFF0000U,
+#if STM32_DMA_SUPPORTS_DMAMUX
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_CHANNEL),
+#else
.dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
+#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
@@ -135,7 +147,11 @@ static const dacparams_t dma1_ch2_params = {
.dataoffset = CHANNEL_DATA_OFFSET,
.regshift = 16U,
.regmask = 0x0000FFFFU,
+#if STM32_DMA_SUPPORTS_DMAMUX
+ .dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_CHANNEL),
+#else
.dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
+#endif
.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
@@ -227,12 +243,18 @@ void dac_lld_start(DACDriver *dacp) {
#if STM32_DAC_USE_DAC1_CH1
if (&DACD1 == dacp) {
rccEnableDAC1(true);
+#if STM32_DMA_SUPPORTS_DMAMUX
+ dmaSetRequestSource(dacp->params->dma, STM32_DMAMUX1_DAC1_CH1);
+#endif
}
#endif
#if STM32_DAC_USE_DAC1_CH2
if (&DACD2 == dacp) {
rccEnableDAC1(true);
+#if STM32_DMA_SUPPORTS_DMAMUX
+ dmaSetRequestSource(dacp->params->dma, STM32_DMAMUX1_DAC1_CH2);
+#endif
channel = 1;
}
#endif
@@ -240,12 +262,18 @@ void dac_lld_start(DACDriver *dacp) {
#if STM32_DAC_USE_DAC2_CH1
if (&DACD3 == dacp) {
rccEnableDAC2(true);
+#if STM32_DMA_SUPPORTS_DMAMUX
+ dmaSetRequestSource(dacp->params->dma, STM32_DMAMUX1_DAC2_CH1);
+#endif
}
#endif
#if STM32_DAC_USE_DAC2_CH2
if (&DACD4 == dacp) {
rccEnableDAC2(true);
+#if STM32_DMA_SUPPORTS_DMAMUX
+ dmaSetRequestSource(dacp->params->dma, STM32_DMAMUX1_DAC2_CH2);
+#endif
channel = 1;
}
#endif
diff --git a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
index f95afc0fb..c2b74f6b4 100644
--- a/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
+++ b/os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.h
@@ -182,6 +182,28 @@
/* The following checks are only required when there is a DMA able to
reassign streams to different channels.*/
#if STM32_ADVANCED_DMA
+
+#if STM32_DMA_SUPPORTS_DMAMUX
+
+/* Check on the presence of the DMA channel settings in mcuconf.h.*/
+#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_CHANNEL)
+#error "DAC1 CH1 DMA channel not defined"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && !defined(STM32_DAC_DAC1_CH2_DMA_CHANNEL)
+#error "DAC1 CH2 DMA channel not defined"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && !defined(STM32_DAC_DAC2_CH1_DMA_CHANNEL)
+#error "DAC2 CH1 DMA channel not defined"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && !defined(STM32_DAC_DAC2_CH2_DMA_CHANNEL)
+#error "DAC2 CH2 DMA channel not defined"
+#endif
+
+#else /* !STM32_DMA_SUPPORTS_DMAMUX */
+
/* Check on the presence of the DMA streams settings in mcuconf.h.*/
#if STM32_DAC_USE_DAC1_CH1 && !defined(STM32_DAC_DAC1_CH1_DMA_STREAM)
#error "DAC1 CH1 DMA stream not defined"
@@ -219,8 +241,31 @@
!STM32_DMA_IS_VALID_ID(STM32_DAC_DAC2_CH2_DMA_STREAM, STM32_DAC2_CH2_DMA_MSK)
#error "invalid DMA stream associated to DAC2 CH2"
#endif
+
+#endif /* !STM32_DMA_SUPPORTS_DMAMUX */
+
#endif /* STM32_ADVANCED_DMA */
+#if STM32_DAC_USE_DAC1_CH1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to DAC1 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC1_CH2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC1_CH2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to DAC1 CH2"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH1 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to DAC2 CH1"
+#endif
+
+#if STM32_DAC_USE_DAC2_CH2 && \
+ !STM32_DMA_IS_VALID_PRIORITY(STM32_DAC_DAC2_CH2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to DAC2 CH2"
+#endif
+
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
diff --git a/os/hal/ports/STM32/STM32L4xx+/platform.mk b/os/hal/ports/STM32/STM32L4xx+/platform.mk
index 38865ba9e..dba1d5516 100644
--- a/os/hal/ports/STM32/STM32L4xx+/platform.mk
+++ b/os/hal/ports/STM32/STM32L4xx+/platform.mk
@@ -23,6 +23,7 @@ endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk
+include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv3/driver.mk
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h b/os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h
index d500a2050..11a208b61 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h
@@ -38,8 +38,8 @@
#define STM32_DMAMUX1_REQ_GEN2 3
#define STM32_DMAMUX1_REQ_GEN3 4
#define STM32_DMAMUX1_ADC1 5
-#define STM32_DMAMUX1_DAC1 6
-#define STM32_DMAMUX1_DAC2 7
+#define STM32_DMAMUX1_DAC1_CH1 6
+#define STM32_DMAMUX1_DAC1_CH2 7
#define STM32_DMAMUX1_TIM6_UP 8
#define STM32_DMAMUX1_TIM7_UP 9
#define STM32_DMAMUX1_SPI1_RX 10
diff --git a/readme.txt b/readme.txt
index b3994436f..d0763af1c 100644
--- a/readme.txt
+++ b/readme.txt
@@ -91,7 +91,7 @@
*****************************************************************************
*** Next ***
-- NEW: STM32 DMAv1, ADCv3, I2Cv2 and SPIv2 are now DMAMUX-aware.
+- NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2 and SPIv2 are now DMAMUX-aware.
- NEW: Introduced support for STM32L4+ devices.
- NEW: Independent TRNG driver model added to HAL.
- NEW: TRNG API now takes a new "size" parameter, the API can now generate
diff --git a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
index 8376b0103..9b88fd665 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -140,6 +140,15 @@
/*
* DAC driver system settings.
*/
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 11
+#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 12
/*
* GPT driver system settings.
diff --git a/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl
index 690e52772..682e88bcc 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32l4r5xx/mcuconf.h.ftl
@@ -151,6 +151,15 @@
/*
* DAC driver system settings.
*/
+#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
+#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
+#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
+#define STM32_DAC_DAC1_CH1_DMA_CHANNEL ${doc.STM32_DAC_DAC1_CH1_DMA_CHANNEL!"11"}
+#define STM32_DAC_DAC1_CH2_DMA_CHANNEL ${doc.STM32_DAC_DAC1_CH2_DMA_CHANNEL!"12"}
/*
* GPT driver system settings.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 13:51:52 +0000