diff options
| -rw-r--r-- | os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c | 30 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/mcuconf.h | 2 |
2 files changed, 11 insertions, 21 deletions
diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c index f5ee5db58..d159698a4 100644 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c @@ -779,10 +779,6 @@ void spi_lld_init(void) { SPID1.tx1_channel = EDMA_ERROR;
SPID1.tx2_channel = EDMA_ERROR;
SPID1.rx_channel = EDMA_ERROR;
- SPC5_DSPI0_ENABLE_CLOCK();
- SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI0_MCR;
- SPC5_DSPI0_DISABLE_CLOCK();
INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI0 */
@@ -793,10 +789,6 @@ void spi_lld_init(void) { SPID2.tx1_channel = EDMA_ERROR;
SPID2.tx2_channel = EDMA_ERROR;
SPID2.rx_channel = EDMA_ERROR;
- SPC5_DSPI1_ENABLE_CLOCK();
- SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI1_MCR;
- SPC5_DSPI1_DISABLE_CLOCK();
INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI1 */
@@ -807,10 +799,6 @@ void spi_lld_init(void) { SPID3.tx1_channel = EDMA_ERROR;
SPID3.tx2_channel = EDMA_ERROR;
SPID3.rx_channel = EDMA_ERROR;
- SPC5_DSPI2_ENABLE_CLOCK();
- SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI2_MCR;
- SPC5_DSPI2_DISABLE_CLOCK();
INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI2 */
@@ -821,10 +809,6 @@ void spi_lld_init(void) { SPID4.tx1_channel = EDMA_ERROR;
SPID4.tx2_channel = EDMA_ERROR;
SPID4.rx_channel = EDMA_ERROR;
- SPC5_DSPI3_ENABLE_CLOCK();
- SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI3_MCR;
- SPC5_DSPI3_DISABLE_CLOCK();
INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI3 */
@@ -835,10 +819,6 @@ void spi_lld_init(void) { SPID5.tx1_channel = EDMA_ERROR;
SPID5.tx2_channel = EDMA_ERROR;
SPID5.rx_channel = EDMA_ERROR;
- SPC5_DSPI4_ENABLE_CLOCK();
- SPC5_DSPI4.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
- SPC5_SPI_DSPI4_MCR;
- SPC5_DSPI4_DISABLE_CLOCK();
INTC.PSR[SPC5_DSPI4_TFFF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO;
#endif /* SPC5_SPI_USE_DSPI4 */
}
@@ -864,6 +844,8 @@ void spi_lld_start(SPIDriver *spip) { spip->tx1_channel = edmaChannelAllocate(&spi_dspi0_tx1_dma_config);
spip->tx2_channel = edmaChannelAllocate(&spi_dspi0_tx2_dma_config);
spip->rx_channel = edmaChannelAllocate(&spi_dspi0_rx_dma_config);
+ SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI0_MCR;
}
#endif /* SPC5_SPI_USE_DSPI0 */
@@ -873,6 +855,8 @@ void spi_lld_start(SPIDriver *spip) { spip->tx1_channel = edmaChannelAllocate(&spi_dspi1_tx1_dma_config);
spip->tx2_channel = edmaChannelAllocate(&spi_dspi1_tx2_dma_config);
spip->rx_channel = edmaChannelAllocate(&spi_dspi1_rx_dma_config);
+ SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI1_MCR;
}
#endif /* SPC5_SPI_USE_DSPI1 */
@@ -882,6 +866,8 @@ void spi_lld_start(SPIDriver *spip) { spip->tx1_channel = edmaChannelAllocate(&spi_dspi2_tx1_dma_config);
spip->tx2_channel = edmaChannelAllocate(&spi_dspi2_tx2_dma_config);
spip->rx_channel = edmaChannelAllocate(&spi_dspi2_rx_dma_config);
+ SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI2_MCR;
}
#endif /* SPC5_SPI_USE_DSPI2 */
@@ -891,6 +877,8 @@ void spi_lld_start(SPIDriver *spip) { spip->tx1_channel = edmaChannelAllocate(&spi_dspi3_tx1_dma_config);
spip->tx2_channel = edmaChannelAllocate(&spi_dspi3_tx2_dma_config);
spip->rx_channel = edmaChannelAllocate(&spi_dspi3_rx_dma_config);
+ SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI3_MCR;
}
#endif /* SPC5_SPI_USE_DSPI3 */
@@ -900,6 +888,8 @@ void spi_lld_start(SPIDriver *spip) { spip->tx1_channel = edmaChannelAllocate(&spi_dspi4_tx1_dma_config);
spip->tx2_channel = edmaChannelAllocate(&spi_dspi4_tx2_dma_config);
spip->rx_channel = edmaChannelAllocate(&spi_dspi4_rx_dma_config);
+ SPC5_DSPI4.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI4_MCR;
}
#endif /* SPC5_SPI_USE_DSPI5 */
diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h index 922e4efc6..384741bdd 100644 --- a/testhal/SPC56ELxx/SPI/mcuconf.h +++ b/testhal/SPC56ELxx/SPI/mcuconf.h @@ -41,7 +41,7 @@ #define SPC5_FMPLL1_IDF_VALUE 5
#define SPC5_FMPLL1_NDIV_VALUE 60
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
-#define SPC5_SYSCLK_DIVIDER_VALUE 1
+#define SPC5_SYSCLK_DIVIDER_VALUE 2
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
#define SPC5_MCONTROL_DIVIDER_VALUE 15
#define SPC5_SWG_DIVIDER_VALUE 2
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