diff options
24 files changed, 1352 insertions, 177 deletions
diff --git a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h index ae6a7a125..28ae05e73 100644 --- a/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-FATFS-GCC/mcuconf.h @@ -25,11 +25,7 @@ * is enabled in halconf.h.
*
* IRQ priorities:
- * 15 Lowest, priority level reserved for PENDSV.
- * 14...4 Normal IRQs priority levels (0x80 used by SYSTICK).
- * 3 Used by SVCALL, do not share.
- * 2...0 Fast interrupts, can preempt the kernel but cannot use it
- * directly.
+ * 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
@@ -45,14 +41,14 @@ */
#define USE_STM32_ADC1 TRUE
#define STM32_ADC1_DMA_PRIORITY 3
-#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
+#define STM32_ADC1_IRQ_PRIORITY 5
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
/*
* CAN driver system settings.
*/
#define USE_STM32_CAN1 TRUE
-#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
+#define STM32_CAN1_IRQ_PRIORITY 11
/*
* PWM driver system settings.
@@ -61,10 +57,10 @@ #define USE_STM32_PWM2 FALSE
#define USE_STM32_PWM3 FALSE
#define USE_STM32_PWM4 FALSE
-#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
-#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
-#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
-#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
+#define STM32_PWM1_IRQ_PRIORITY 7
+#define STM32_PWM2_IRQ_PRIORITY 7
+#define STM32_PWM3_IRQ_PRIORITY 7
+#define STM32_PWM4_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
@@ -76,12 +72,12 @@ #define USE_STM32_UART4 FALSE
#define USE_STM32_UART5 FALSE
#endif
-#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
-#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
-#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART1_PRIORITY 12
+#define STM32_USART2_PRIORITY 12
+#define STM32_USART3_PRIORITY 12
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
-#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
-#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_UART4_PRIORITY 12
+#define STM32_UART5_PRIORITY 12
#endif
/*
@@ -91,6 +87,6 @@ #define USE_STM32_SPI2 TRUE
#define STM32_SPI1_DMA_PRIORITY 2
#define STM32_SPI2_DMA_PRIORITY 2
-#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
-#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
+#define STM32_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI2_IRQ_PRIORITY 10
#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/Makefile b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile new file mode 100644 index 000000000..36567e197 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/Makefile @@ -0,0 +1,204 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -mabi=apcs-gnu -falign-functions=16
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable register caching optimization (read documentation).
+ifeq ($(USE_CURRP_CACHING),)
+ USE_CURRP_CACHING = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FWLIB),)
+ USE_FWLIB = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Define linker script file here
+LDSCRIPT= ch.ld
+
+# Imported source files
+CHIBIOS = ../..
+include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
+include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F10x/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/test/test.mk
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/evtimer.c \
+ $(CHIBIOS)/os/various/syscalls.c \
+ main.c +
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM) \
+ $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/vectors.s
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m3
+
+TRGT = arm-elf-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS = -DSTM32F10X_MD
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+ifeq ($(USE_FWLIB),yes)
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+ CSRC += $(STM32SRC)
+ INCDIR += $(STM32INC)
+ USE_OPT += -DUSE_STDPERIPH_DRIVER
+endif
+
+include $(CHIBIOS)/os/ports/GCC/ARM/rules.mk
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld b/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld new file mode 100644 index 000000000..1405765cd --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/ch.ld @@ -0,0 +1,94 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * ST32F103 memory setup.
+ */
+__main_stack_size__ = 0x0200;
+__process_stack_size__ = 0x0400;
+__stacks_total_size__ = __main_stack_size__ + __process_stack_size__;
+
+MEMORY
+{
+ flash : org = 0x08000000, len = 128k
+ ram : org = 0x20000000, len = 20k
+}
+
+__ram_start__ = ORIGIN(ram);
+__ram_size__ = LENGTH(ram);
+__ram_end__ = __ram_start__ + __ram_size__;
+
+SECTIONS
+{
+ . = 0;
+
+ .text : ALIGN(16) SUBALIGN(16)
+ {
+ _text = .;
+ KEEP(*(vectors));
+ *(.text)
+ *(.text.*);
+ *(.rodata);
+ *(.rodata.*);
+ *(.glue_7t);
+ *(.glue_7);
+ *(.gcc*);
+ *(.ctors);
+ *(.dtors);
+ . = ALIGN(4);
+ _etext = .;
+ } > flash
+
+ _textdata = _etext;
+
+ .data :
+ {
+ _data = .;
+ *(.data)
+ . = ALIGN(4);
+ *(.data.*)
+ . = ALIGN(4);
+ *(.ramtext)
+ . = ALIGN(4);
+ _edata = .;
+ } > ram AT > flash
+
+ .bss :
+ {
+ _bss_start = .;
+ *(.bss)
+ . = ALIGN(4);
+ *(.bss.*)
+ . = ALIGN(4);
+ *(COMMON)
+ . = ALIGN(4);
+ _bss_end = .;
+ } > ram
+
+ /DISCARD/ :
+ {
+ *(.eh_*)
+ }
+}
+
+PROVIDE(end = .);
+_end = .;
+
+__heap_base__ = _end;
+__heap_end__ = __ram_end__ - __stacks_total_size__;
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h new file mode 100644 index 000000000..046d28300 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/chconf.h @@ -0,0 +1,483 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/* Kernel parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Nested locks.
+ * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock()
+ * operations is allowed.<br>
+ * For performance and code size reasons the recommended setting
+ * is to leave this option disabled.<br>
+ * You may use this option if you need to merge ChibiOS/RT with
+ * external libraries that require nested lock/unlock operations.
+ *
+ * @note T he default is @p FALSE.
+ */
+#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__)
+#define CH_USE_NESTED_LOCKS FALSE
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_COREMEM.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/*===========================================================================*/
+/* Performance options. */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/**
+ * @brief Exotic optimization.
+ * @details If defined then a CPU register is used as storage for the global
+ * @p currp variable. Caching this variable in a register greatly
+ * improves both space and time OS efficiency. A side effect is that
+ * one less register has to be saved during the context switch
+ * resulting in lower RAM usage and faster context switch.
+ *
+ * @note This option is only usable with the GCC compiler and is only useful
+ * on processors with many registers like ARM cores.
+ * @note If this option is enabled then ALL the libraries linked to the
+ * ChibiOS/RT code <b>must</b> be recompiled with the GCC option @p
+ * -ffixed-@<reg@>.
+ * @note This option must be enabled in the Makefile, it is listed here for
+ * documentation only.
+ */
+#if defined(__DOXYGEN__)
+#define CH_CURRP_REGISTER_CACHE "reg"
+#endif
+
+/*===========================================================================*/
+/* Subsystem options. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/*===========================================================================*/
+/* Debug options. */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/*===========================================================================*/
+/* Kernel hooks. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure hook.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+struct { \
+ /* Add threads custom fields here.*/ \
+};
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitily from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h new file mode 100644 index 000000000..763b0019a --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/halconf.h @@ -0,0 +1,152 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+/*
+ * HAL configuration file, this file allows to enable or disable the various
+ * device drivers from your application. You may also use this file in order
+ * to override the device drivers default settings.
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+/*
+ * Uncomment the following line in order to include a mcu-related
+ * settings file. This file can be used to include platform specific
+ * header files or to override the low level drivers settings.
+ */
+#include "mcuconf.h"
+
+/*===========================================================================*/
+/* PAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__)
+#define CH_HAL_USE_PAL TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__)
+#define CH_HAL_USE_ADC FALSE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__)
+#define CH_HAL_USE_CAN FALSE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__)
+#define CH_HAL_USE_MAC FALSE
+#endif
+
+/*===========================================================================*/
+/* PWM driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__)
+#define CH_HAL_USE_PWM FALSE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define CH_HAL_USE_SERIAL TRUE
+#endif
+
+/*
+ * Default SERIAL settings overrides (uncomment to override).
+ */
+/*#define SERIAL_DEFAULT_BITRATE 38400*/
+/*#define SERIAL_BUFFERS_SIZE 64*/
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__)
+#define CH_HAL_USE_SPI FALSE
+#endif
+
+/*
+ * Default SPI settings overrides (uncomment to override).
+ */
+/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define CH_HAL_USE_MMC_SPI FALSE
+#endif
+
+/*
+ * Default MMC_SPI settings overrides (uncomment to override).
+ */
+/*#define MMC_SECTOR_SIZE 512*/
+/*#define MMC_NICE_WAITING TRUE*/
+/*#define MMC_POLLING_INTERVAL 10*/
+/*#define MMC_POLLING_DELAY 10*/
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/main.c b/demos/ARMCM3-STM32F103-GCC-ALT/main.c new file mode 100644 index 000000000..0072f0958 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/main.c @@ -0,0 +1,69 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+/*
+ * Red LEDs blinker thread, times are in milliseconds.
+ */
+static WORKING_AREA(waThread1, 128);
+static msg_t Thread1(void *arg) {
+
+ (void)arg;
+ while (TRUE) {
+ palClearPad(IOPORT3, GPIOC_LED);
+ chThdSleepMilliseconds(500);
+ palSetPad(IOPORT3, GPIOC_LED);
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
+
+/*
+ * Entry point, note, the main() function is already a thread in the system
+ * on entry.
+ */
+int main(int argc, char **argv) {
+
+ (void)argc;
+ (void)argv;
+
+ /*
+ * Activates the serial driver 2 using the driver default configuration.
+ */
+ sdStart(&SD2, NULL);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing except
+ * sleeping in a loop and check the button state.
+ */
+ while (TRUE) {
+ if (palReadPad(IOPORT1, GPIOA_BUTTON))
+ TestThread(&SD2);
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h b/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h new file mode 100644 index 000000000..28ae05e73 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/mcuconf.h @@ -0,0 +1,92 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * STM32 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_SYSCLK 72
+
+/*
+ * ADC driver system settings.
+ */
+#define USE_STM32_ADC1 TRUE
+#define STM32_ADC1_DMA_PRIORITY 3
+#define STM32_ADC1_IRQ_PRIORITY 5
+#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
+
+/*
+ * CAN driver system settings.
+ */
+#define USE_STM32_CAN1 TRUE
+#define STM32_CAN1_IRQ_PRIORITY 11
+
+/*
+ * PWM driver system settings.
+ */
+#define USE_STM32_PWM1 TRUE
+#define USE_STM32_PWM2 FALSE
+#define USE_STM32_PWM3 FALSE
+#define USE_STM32_PWM4 FALSE
+#define STM32_PWM1_IRQ_PRIORITY 7
+#define STM32_PWM2_IRQ_PRIORITY 7
+#define STM32_PWM3_IRQ_PRIORITY 7
+#define STM32_PWM4_IRQ_PRIORITY 7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define USE_STM32_USART1 FALSE
+#define USE_STM32_USART2 TRUE
+#define USE_STM32_USART3 FALSE
+#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+#define USE_STM32_UART4 FALSE
+#define USE_STM32_UART5 FALSE
+#endif
+#define STM32_USART1_PRIORITY 12
+#define STM32_USART2_PRIORITY 12
+#define STM32_USART3_PRIORITY 12
+#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
+#define STM32_UART4_PRIORITY 12
+#define STM32_UART5_PRIORITY 12
+#endif
+
+/*
+ * SPI driver system settings.
+ */
+#define USE_STM32_SPI1 TRUE
+#define USE_STM32_SPI2 TRUE
+#define STM32_SPI1_DMA_PRIORITY 2
+#define STM32_SPI2_DMA_PRIORITY 2
+#define STM32_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()
diff --git a/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt b/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt new file mode 100644 index 000000000..353dd2658 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC-ALT/readme.txt @@ -0,0 +1,28 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M3 STM32F103. **
+*****************************************************************************
+
+** TARGET **
+
+The demo will on an Olimex STM32-P103 board.
+
+** The Demo **
+
+The demo flashes the board LED using a thread, by pressing the button located
+on the board the test procedure is activated with output on the serial port
+COM2 (USART2).
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain,
+YAGARTO and an experimental WinARM build including GCC 4.3.0.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distribited
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/demos/ARMCM3-STM32F103-GCC/mcuconf.h b/demos/ARMCM3-STM32F103-GCC/mcuconf.h index ae6a7a125..28ae05e73 100644 --- a/demos/ARMCM3-STM32F103-GCC/mcuconf.h +++ b/demos/ARMCM3-STM32F103-GCC/mcuconf.h @@ -25,11 +25,7 @@ * is enabled in halconf.h.
*
* IRQ priorities:
- * 15 Lowest, priority level reserved for PENDSV.
- * 14...4 Normal IRQs priority levels (0x80 used by SYSTICK).
- * 3 Used by SVCALL, do not share.
- * 2...0 Fast interrupts, can preempt the kernel but cannot use it
- * directly.
+ * 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
@@ -45,14 +41,14 @@ */
#define USE_STM32_ADC1 TRUE
#define STM32_ADC1_DMA_PRIORITY 3
-#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
+#define STM32_ADC1_IRQ_PRIORITY 5
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
/*
* CAN driver system settings.
*/
#define USE_STM32_CAN1 TRUE
-#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
+#define STM32_CAN1_IRQ_PRIORITY 11
/*
* PWM driver system settings.
@@ -61,10 +57,10 @@ #define USE_STM32_PWM2 FALSE
#define USE_STM32_PWM3 FALSE
#define USE_STM32_PWM4 FALSE
-#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
-#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
-#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
-#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
+#define STM32_PWM1_IRQ_PRIORITY 7
+#define STM32_PWM2_IRQ_PRIORITY 7
+#define STM32_PWM3_IRQ_PRIORITY 7
+#define STM32_PWM4_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
@@ -76,12 +72,12 @@ #define USE_STM32_UART4 FALSE
#define USE_STM32_UART5 FALSE
#endif
-#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
-#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
-#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART1_PRIORITY 12
+#define STM32_USART2_PRIORITY 12
+#define STM32_USART3_PRIORITY 12
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
-#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
-#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_UART4_PRIORITY 12
+#define STM32_UART5_PRIORITY 12
#endif
/*
@@ -91,6 +87,6 @@ #define USE_STM32_SPI2 TRUE
#define STM32_SPI1_DMA_PRIORITY 2
#define STM32_SPI2_DMA_PRIORITY 2
-#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
-#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
+#define STM32_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI2_IRQ_PRIORITY 10
#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()
diff --git a/docs/reports/STM32F103-72.txt b/docs/reports/STM32F103-72.txt index ea962014c..4d3d89417 100644 --- a/docs/reports/STM32F103-72.txt +++ b/docs/reports/STM32F103-72.txt @@ -7,7 +7,7 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states) ***
*** Kernel: 1.5.4unstable
*** GCC Version: 4.4.2
-*** Architecture: ARM
+*** Architecture: ARMv7-M
*** Core Variant: Cortex-M3
*** Platform: STM32
*** Test Board: Olimex STM32-P103
diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c index c543b2c73..020b3c688 100644 --- a/os/hal/platforms/STM32/adc_lld.c +++ b/os/hal/platforms/STM32/adc_lld.c @@ -155,7 +155,8 @@ void adc_lld_start(ADCDriver *adcp) { #if USE_STM32_ADC1
if (&ADCD1 == adcp) {
dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
- NVICEnableVector(DMA1_Channel1_IRQn, STM32_ADC1_IRQ_PRIORITY);
+ NVICEnableVector(DMA1_Channel1_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_ADC1_IRQ_PRIORITY));
DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR;
RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
}
diff --git a/os/hal/platforms/STM32/adc_lld.h b/os/hal/platforms/STM32/adc_lld.h index 134fb9ba4..2b9ac2dd7 100644 --- a/os/hal/platforms/STM32/adc_lld.h +++ b/os/hal/platforms/STM32/adc_lld.h @@ -77,11 +77,9 @@ /**
* @brief ADC1 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_ADC1_IRQ_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
+#define STM32_ADC1_IRQ_PRIORITY 5
#endif
/**
diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c index 4b24ec810..6fe3cf30d 100644 --- a/os/hal/platforms/STM32/can_lld.c +++ b/os/hal/platforms/STM32/can_lld.c @@ -174,10 +174,14 @@ void can_lld_start(CANDriver *canp) { /* Clock activation.*/
#if USE_STM32_CAN1
if (&CAND1 == canp) {
- NVICEnableVector(USB_HP_CAN1_TX_IRQn, STM32_CAN1_IRQ_PRIORITY);
- NVICEnableVector(USB_LP_CAN1_RX0_IRQn, STM32_CAN1_IRQ_PRIORITY);
- NVICEnableVector(CAN1_RX1_IRQn, STM32_CAN1_IRQ_PRIORITY);
- NVICEnableVector(CAN1_SCE_IRQn, STM32_CAN1_IRQ_PRIORITY);
+ NVICEnableVector(USB_HP_CAN1_TX_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));
+ NVICEnableVector(USB_LP_CAN1_RX0_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));
+ NVICEnableVector(CAN1_RX1_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));
+ NVICEnableVector(CAN1_SCE_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
}
#endif
diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h index 0e1d0fee0..85d86b0cb 100644 --- a/os/hal/platforms/STM32/can_lld.h +++ b/os/hal/platforms/STM32/can_lld.h @@ -83,11 +83,9 @@ /**
* @brief CAN1 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
+#define STM32_CAN1_IRQ_PRIORITY 11
#endif
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index b28795ad9..817147026 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -76,9 +76,6 @@ void hal_lld_init(void) { /* Note: PRIGROUP 4:0 (4:4).*/
SCB->AIRCR = (0x05FA << SCB_AIRCR_VECTKEY_Pos) |
(3 << SCB_AIRCR_PRIGROUP_Pos);
- NVICSetSystemHandlerPriority(HANDLER_SVCALL, CORTEX_PRIORITY_SVCALL);
- NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
- NVICSetSystemHandlerPriority(HANDLER_PENDSV, CORTEX_PRIORITY_PENDSV);
/* SysTick initialization using the system clock.*/
SysTick->LOAD = SYSCLK / CH_FREQUENCY - 1;
diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c index 7e39964c3..ab0649b70 100644 --- a/os/hal/platforms/STM32/pwm_lld.c +++ b/os/hal/platforms/STM32/pwm_lld.c @@ -271,26 +271,31 @@ void pwm_lld_start(PWMDriver *pwmp) { /* Clock activation.*/
#if USE_STM32_PWM1
if (&PWMD1 == pwmp) {
- NVICEnableVector(TIM1_UP_IRQn, STM32_PWM1_IRQ_PRIORITY);
- NVICEnableVector(TIM1_CC_IRQn, STM32_PWM1_IRQ_PRIORITY);
+ NVICEnableVector(TIM1_UP_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY));
+ NVICEnableVector(TIM1_CC_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY);
RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
}
#endif
#if USE_STM32_PWM2
if (&PWMD2 == pwmp) {
- NVICEnableVector(TIM2_IRQn, STM32_PWM2_IRQ_PRIORITY);
+ NVICEnableVector(TIM2_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_PWM2_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
}
#endif
#if USE_STM32_PWM3
if (&PWMD3 == pwmp) {
- NVICEnableVector(TIM3_IRQn, STM32_PWM3_IRQ_PRIORITY);
+ NVICEnableVector(TIM3_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_PWM3_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
}
#endif
#if USE_STM32_PWM4
if (&PWMD4 == pwmp) {
- NVICEnableVector(TIM4_IRQn, STM32_PWM4_IRQ_PRIORITY);
+ NVICEnableVector(TIM4_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_PWM4_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;
}
#endif
diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h index a16b248b1..4249a8514 100644 --- a/os/hal/platforms/STM32/pwm_lld.h +++ b/os/hal/platforms/STM32/pwm_lld.h @@ -80,38 +80,30 @@ /**
* @brief PWM1 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM1_IRQ_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
+#define STM32_PWM1_IRQ_PRIORITY 7
#endif
/**
* @brief PWM2 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM2_IRQ_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
+#define STM32_PWM2_IRQ_PRIORITY 7
#endif
/**
* @brief PWM3 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM3_IRQ_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
+#define STM32_PWM3_IRQ_PRIORITY 7
#endif
/**
* @brief PWM4 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM4_IRQ_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
+#define STM32_PWM4_IRQ_PRIORITY 7
#endif
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c index 33ccd44c1..99a8653ca 100644 --- a/os/hal/platforms/STM32/serial_lld.c +++ b/os/hal/platforms/STM32/serial_lld.c @@ -327,32 +327,37 @@ void sd_lld_start(SerialDriver *sdp) { #if USE_STM32_USART1
if (&SD1 == sdp) {
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
- NVICEnableVector(USART1_IRQn, STM32_USART1_PRIORITY);
+ NVICEnableVector(USART1_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_USART1_PRIORITY));
}
#endif
#if USE_STM32_USART2
if (&SD2 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
- NVICEnableVector(USART2_IRQn, STM32_USART2_PRIORITY);
+ NVICEnableVector(USART2_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_USART2_PRIORITY));
}
#endif
#if USE_STM32_USART3
if (&SD3 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
- NVICEnableVector(USART3_IRQn, STM32_USART3_PRIORITY);
+ NVICEnableVector(USART3_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_USART3_PRIORITY));
}
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
#if USE_STM32_UART4
if (&SD4 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_UART4EN;
- NVICEnableVector(UART4_IRQn, STM32_UART4_PRIORITY);
+ NVICEnableVector(UART4_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_UART4_PRIORITY));
}
#endif
#if USE_STM32_UART5
if (&SD5 == sdp) {
RCC->APB1ENR |= RCC_APB1ENR_UART5EN;
- NVICEnableVector(UART5_IRQn, STM32_UART5_PRIORITY);
+ NVICEnableVector(UART5_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_UART5_PRIORITY));
}
#endif
#endif
diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h index eb625230b..861582d54 100644 --- a/os/hal/platforms/STM32/serial_lld.h +++ b/os/hal/platforms/STM32/serial_lld.h @@ -87,48 +87,38 @@ /**
* @brief USART1 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART1_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART1_PRIORITY 12
#endif
/**
* @brief USART2 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART2_PRIORITY 12)
#endif
/**
* @brief USART3 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART3_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART3_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_USART3_PRIORITY 12
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
/**
* @brief UART4 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_UART4_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_UART4_PRIORITY 12
#endif
/**
* @brief UART5 interrupt priority level setting.
- * @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
- * @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_UART5_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
+#define STM32_UART5_PRIORITY 12
#endif
#endif
diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c index 37961c2a7..af4fdfc3d 100644 --- a/os/hal/platforms/STM32/spi_lld.c +++ b/os/hal/platforms/STM32/spi_lld.c @@ -218,16 +218,20 @@ void spi_lld_start(SPIDriver *spip) { #if USE_STM32_SPI1
if (&SPID1 == spip) {
dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
- NVICEnableVector(DMA1_Channel2_IRQn, STM32_SPI1_IRQ_PRIORITY);
- NVICEnableVector(DMA1_Channel3_IRQn, STM32_SPI1_IRQ_PRIORITY);
+ NVICEnableVector(DMA1_Channel2_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY));
+ NVICEnableVector(DMA1_Channel3_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY));
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
}
#endif
#if USE_STM32_SPI2
if (&SPID2 == spip) {
dmaEnable(DMA1_ID); /* NOTE: Must be enabled before the IRQs.*/
- NVICEnableVector(DMA1_Channel4_IRQn, STM32_SPI2_IRQ_PRIORITY);
- NVICEnableVector(DMA1_Channel5_IRQn, STM32_SPI2_IRQ_PRIORITY);
+ NVICEnableVector(DMA1_Channel4_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY));
+ NVICEnableVector(DMA1_Channel5_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY));
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
}
#endif
diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h index 8afe01e93..a6ccb8467 100644 --- a/os/hal/platforms/STM32/spi_lld.h +++ b/os/hal/platforms/STM32/spi_lld.h @@ -78,18 +78,16 @@ /**
* @brief SPI1 interrupt priority level setting.
- * @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
*/
#if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
+#define STM32_SPI1_IRQ_PRIORITY 10
#endif
/**
* @brief SPI2 interrupt priority level setting.
- * @note @p BASEPRI_KERNEL >= @p STM32_SPI2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
*/
#if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
+#define STM32_SPI2_IRQ_PRIORITY 10
#endif
/**
diff --git a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h index a3b481037..a5aed8126 100644 --- a/os/ports/GCC/ARMCM3/STM32F103/cmparams.h +++ b/os/ports/GCC/ARMCM3/STM32F103/cmparams.h @@ -31,13 +31,6 @@ #ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
-/*===========================================================================*/
-/* Constants parameters. */
-/*===========================================================================*/
-
-#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
-#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
-
/**
* @brief Cortex core model.
*/
@@ -55,67 +48,9 @@ /**
* @brief Number of bits in priority masks.
- * @details The available number of priority levels is equal to
- * (1 << @p CORTEX_PRIORITY_BITS).
*/
#define CORTEX_PRIORITY_BITS 4
-/**
- * @brief Priority to priority mask conversion macro.
- */
-#define CORTEX_PRIORITY(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
-
-/*===========================================================================*/
-/* Configurable parameters. */
-/*===========================================================================*/
-
-/**
- * @brief BASEPRI user level, 0 = disabled.
- */
-#ifndef CORTEX_BASEPRI_USER
-#define CORTEX_BASEPRI_USER CORTEX_PRIORITY(0)
-#endif
-
-/**
- * @brief BASEPRI level within kernel lock.
- * @details Priority levels higher than this one (lower values) are unaffected
- * by the OS activity and can be classified as fast interrupt sources,
- * see @ref interrupt_classes.
- */
-#ifndef CORTEX_BASEPRI_KERNEL
-#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY(4)
-#endif
-
-/**
- * @brief SVCALL handler priority.
- * @note This priority must always be one level above the @p BASEPRI_KERNEL
- * value.
- * @note It is recommended, but not mandatory, to leave this priority level
- * for this handler alone.
- */
-#ifndef CORTEX_PRIORITY_SVCALL
-#define CORTEX_PRIORITY_SVCALL CORTEX_PRIORITY(3)
-#endif
-
-/**
- * @brief SYSTICK handler priority.
- */
-#ifndef CORTEX_PRIORITY_SYSTICK
-#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(8)
-#endif
-
-/**
- * @brief PENDSV handler priority.
- * @note It is recommended to leave this priority level for this handler
- * alone.
- * @note This is a reserved handler and its priority must always be the
- * lowest priority in the system in order to be always executed last
- * in the interrupt servicing chain.
- */
-#ifndef CORTEX_PRIORITY_PENDSV
-#define CORTEX_PRIORITY_PENDSV CORTEX_PRIORITY(15)
-#endif
-
#endif /* _CMPARAMS_H_ */
/** @} */
diff --git a/os/ports/GCC/ARMCM3/chcore.h b/os/ports/GCC/ARMCM3/chcore.h index 8c7c5fd69..a720d9ffb 100644 --- a/os/ports/GCC/ARMCM3/chcore.h +++ b/os/ports/GCC/ARMCM3/chcore.h @@ -28,6 +28,8 @@ #ifndef _CHCORE_H_
#define _CHCORE_H_
+#include "nvic.h"
+
/*===========================================================================*/
/* Port constants. */
/*===========================================================================*/
@@ -39,44 +41,171 @@ */
#define CORTEX_PORT_MODE_ENDOSWITCH
+#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
+#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */
+#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
+#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */
+
+/* Inclusion of the Cortex-Mx implementation specific parameters.*/
+#include "cmparams.h"
+
+/* Cortex model check, only M3 right now.*/
+#if (CORTEX_MODEL == CORTEX_M3)
+#else
+#error "unknown or unsupported Cortex-M model"
+#endif
+
+
+/*===========================================================================*/
+/* Port derived parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Priority masking support.
+ */
+#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__)
+#define CORTEX_SUPPORTS_BASEPRI TRUE
+#else
+#define CORTEX_SUPPORTS_BASEPRI FALSE
+#endif
+
+/**
+ * @brief Total priority levels.
+ */
+#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS)
+
+/**
+ * @brief Minimum priority level.
+ * @details This minimum priority level is calculated from the number of
+ * priority bits supported by the specific Cortex-Mx implementation.
+ */
+#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1)
+
+/**
+ * @brief Maximum priority level.
+ * @details The maximum allowed priority level is always zero.
+ */
+#define CORTEX_MAXIMUM_PRIORITY 0
+
+/*===========================================================================*/
+/* Port macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Priority level verification macro.
+ */
+#define CORTEX_IS_VALID_PRIORITY(n) \
+ (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS))
+
+/**
+ * @brief Priority level to priority mask conversion macro.
+ */
+#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
+
/*===========================================================================*/
/* Port configurable parameters. */
/*===========================================================================*/
/**
- * @brief Enables the use of the WFI ins.
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
*/
#ifndef CORTEX_ENABLE_WFI_IDLE
#define CORTEX_ENABLE_WFI_IDLE FALSE
#endif
+/**
+ * @brief SYSTICK handler priority.
+ * @note The default is calculated as the priority level in the middle
+ * of the priority range.
+ */
+#ifndef CORTEX_PRIORITY_SYSTICK
+#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1)
+#else
+/* If it is externally redefined then better perform a validity check on it.*/
+#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK)
+#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK"
+#endif
+#endif
+
+/**
+ * @brief BASEPRI user level.
+ */
+#ifndef CORTEX_BASEPRI_USER
+#define CORTEX_BASEPRI_USER CORTEX_PRIORITY_MASK(0)
+#endif
+
+/**
+ * @brief BASEPRI level within kernel lock.
+ * @details Priority levels higher than this one (lower values) are unaffected
+ * by the OS activity and can be classified as fast interrupt sources,
+ * see @ref interrupt_classes.
+ */
+#ifndef CORTEX_BASEPRI_KERNEL
+#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_MAXIMUM_PRIORITY+4)
+#endif
+
+/**
+ * @brief PENDSV handler priority.
+ * @note This priority must always be the lowest one.
+ * @note It is recommended, but not mandatory, to leave this priority level
+ * for this handler alone.
+ */
+#ifndef CORTEX_PRIORITY_PENDSV
+#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY
+#endif
+
+/**
+ * @brief SVCALL handler priority.
+ * @note This priority must always be one level above the
+ * @p CORTEX_MAXIMUM_PRIORITY value.
+ * @note It is recommended, but not mandatory, to leave this priority level
+ * for this handler alone.
+ */
+#ifndef CORTEX_PRIORITY_SVCALL
+#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 3)
+#endif
+
/*===========================================================================*/
/* Port exported info. */
/*===========================================================================*/
+#if defined(__DOXYGEN__)
/**
- * @brief Name of the implemented architecture.
+ * @brief Macro defining the ARM architecture.
*/
-#define CH_ARCHITECTURE_NAME "ARM"
+#define CH_ARCHITECTURE_ARM_vxm
-/* Inclusion of the Cortex-M3 implementation specific parameters.*/
-#include "cmparams.h"
-
-/* Generating model-dependent info.*/
-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
- * @brief Macro defining the ARM Cortex-M3 architecture.
+ * @brief Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_ARMCM3
+#define CH_ARCHITECTURE_NAME "ARMvx-M"
/**
* @brief Name of the architecture variant (optional).
*/
+#define CH_CORE_VARIANT_NAME "Cortex-Mx"
+#elif CORTEX_MODEL == CORTEX_M4
+#define CH_ARCHITECTURE_ARM_v7M
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
+#define CH_CORE_VARIANT_NAME "Cortex-M4"
+#elif CORTEX_MODEL == CORTEX_M3
+#define CH_ARCHITECTURE_ARM_v7M
+#define CH_ARCHITECTURE_NAME "ARMv7-M"
#define CH_CORE_VARIANT_NAME "Cortex-M3"
-#else
-#error "this ports only supports the Cortex-M3 architecture"
+#elif CORTEX_MODEL == CORTEX_M1
+#define CH_ARCHITECTURE_ARM_v6M
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+#define CH_CORE_VARIANT_NAME "Cortex-M1"
+#elif CORTEX_MODEL == CORTEX_M0
+#define CH_ARCHITECTURE_ARM_v6M
+#define CH_ARCHITECTURE_NAME "ARMv6-M"
+#define CH_CORE_VARIANT_NAME "Cortex-M0"
#endif
+/*===========================================================================*/
+/* Port implementation part. */
+/*===========================================================================*/
+
/**
* @brief 32 bits stack and memory alignment enforcement.
*/
@@ -231,9 +360,15 @@ struct context { /**
* @brief Port-related initialization code.
- * @note This function is empty in this port.
*/
-#define port_init()
+#define port_init() { \
+ NVICSetSystemHandlerPriority(HANDLER_SVCALL, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \
+ NVICSetSystemHandlerPriority(HANDLER_PENDSV, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_PENDSV)); \
+ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \
+ CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \
+}
/**
* @brief Kernel-lock action.
diff --git a/os/ports/GCC/ARMCMx/chcore.h b/os/ports/GCC/ARMCMx/chcore.h index 779485385..d858a806d 100644 --- a/os/ports/GCC/ARMCMx/chcore.h +++ b/os/ports/GCC/ARMCMx/chcore.h @@ -60,8 +60,7 @@ /**
* @brief Priority masking support.
*/
-#if (CORTEX_MODEL == CORTEX_M3) || (CORTEX_MODEL == CORTEX_M4) || \
- defined(__DOXYGEN__)
+#if defined(CH_ARCHITECTURE_ARM_v7M) || defined(__DOXYGEN__)
#define CORTEX_SUPPORTS_BASEPRI TRUE
#else
#define CORTEX_SUPPORTS_BASEPRI FALSE
|