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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-11 12:09:26 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-11 12:09:26 +0000 |
| commit | 8041eaf33c2f50f2ef7ed5580d1fb4741c9431c9 (patch) | |
| tree | 149bdef5cf8d5d9d9109a1a41e8ee76212a14328 /testhal | |
| parent | 8d2cce8eed6a41f0ba315a77723e25c77ae260fc (diff) | |
| download | ChibiOS-8041eaf33c2f50f2ef7ed5580d1fb4741c9431c9.tar.gz ChibiOS-8041eaf33c2f50f2ef7ed5580d1fb4741c9431c9.tar.bz2 ChibiOS-8041eaf33c2f50f2ef7ed5580d1fb4741c9431c9.zip | |
DSPI working on SPC56ELxx.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5833 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal')
| -rw-r--r-- | testhal/SPC560Pxx/SPI/main.c | 2 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/.project | 2 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/Makefile | 2 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/main.c | 2 | ||||
| -rw-r--r-- | testhal/SPC56ELxx/SPI/mcuconf.h | 53 |
5 files changed, 57 insertions, 4 deletions
diff --git a/testhal/SPC560Pxx/SPI/main.c b/testhal/SPC560Pxx/SPI/main.c index 5be1f0e17..1178c7377 100644 --- a/testhal/SPC560Pxx/SPI/main.c +++ b/testhal/SPC560Pxx/SPI/main.c @@ -111,7 +111,7 @@ int main(void) { for (i = 0; i < sizeof(txbuf); i++)
txbuf[i] = (uint8_t)i;
- /* Starting driver for test, DSPI_B I/O pins setup.*/
+ /* Starting driver for test, DSPI_1 I/O pins setup.*/
spiStart(&SPID1, &ls_spicfg);
SIU.PCR[37].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
SIU.PCR[38].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
diff --git a/testhal/SPC56ELxx/SPI/.project b/testhal/SPC56ELxx/SPI/.project index 3029087d0..c5157f21e 100644 --- a/testhal/SPC56ELxx/SPI/.project +++ b/testhal/SPC56ELxx/SPI/.project @@ -27,7 +27,7 @@ <link>
<name>board</name>
<type>2</type>
- <locationURI>CHIBIOS/boards/ST_EVB_SPC560P</locationURI>
+ <locationURI>CHIBIOS/boards/ST_EVB_SPC56EL</locationURI>
</link>
<link>
<name>os</name>
diff --git a/testhal/SPC56ELxx/SPI/Makefile b/testhal/SPC56ELxx/SPI/Makefile index ea777f395..afc709b93 100644 --- a/testhal/SPC56ELxx/SPI/Makefile +++ b/testhal/SPC56ELxx/SPI/Makefile @@ -59,7 +59,7 @@ include $(CHIBIOS)/os/kernel/kernel.mk #include $(CHIBIOS)/test/test.mk
# Define linker script file here
-LDSCRIPT= $(PORTLD)/SPC56EL70_LSM.ld
+LDSCRIPT= $(PORTLD)/SPC56EL60_LSM.ld
# C sources here.
CSRC = $(PORTSRC) \
diff --git a/testhal/SPC56ELxx/SPI/main.c b/testhal/SPC56ELxx/SPI/main.c index 5be1f0e17..06ef48689 100644 --- a/testhal/SPC56ELxx/SPI/main.c +++ b/testhal/SPC56ELxx/SPI/main.c @@ -111,7 +111,7 @@ int main(void) { for (i = 0; i < sizeof(txbuf); i++)
txbuf[i] = (uint8_t)i;
- /* Starting driver for test, DSPI_B I/O pins setup.*/
+ /* Starting driver for test, DSPI_0 I/O pins setup.*/
spiStart(&SPID1, &ls_spicfg);
SIU.PCR[37].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */
SIU.PCR[38].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */
diff --git a/testhal/SPC56ELxx/SPI/mcuconf.h b/testhal/SPC56ELxx/SPI/mcuconf.h index 435c18e86..922e4efc6 100644 --- a/testhal/SPC56ELxx/SPI/mcuconf.h +++ b/testhal/SPC56ELxx/SPI/mcuconf.h @@ -217,3 +217,56 @@ SPC5_ME_PCTL_LP(2))
#define SPC5_ICU_ETIMER2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
SPC5_ME_PCTL_LP(0))
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 TRUE
+#define SPC5_SPI_USE_DSPI1 TRUE
+#define SPC5_SPI_USE_DSPI2 TRUE
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#define SPC5_SPI_DSPI0_DMA_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_PRIO 10
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
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