Fixed small errors caused by recent changes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12520 110e8d01-0319-4d1e-a829-52ad28d1bb01

6 files changed, 106 insertions, 106 deletions

diff --git a/testhal/STM32/STM32F4xx/DMA_STORM/main.c b/testhal/STM32/STM32F4xx/DMA_STORM/main.c
index 1eecad767..fa5ac83ea 100644
--- a/testhal/STM32/STM32F4xx/DMA_STORM/main.c
+++ b/testhal/STM32/STM32F4xx/DMA_STORM/main.c
@@ -38,11 +38,9 @@ static virtual_timer_t adcvt;
 

 static adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];

 

-static void adccallback(ADCDriver *adcp, adcsample_t *buffer, size_t n) {

+static void adccallback(ADCDriver *adcp) {

 

   (void)adcp;

-  (void)buffer;

-  (void)n;

 

   chSysLockFromISR();

   chVTSetI(&adcvt, TIME_MS2I(10), tmo, (void *)"ADC timeout");

@@ -62,7 +60,7 @@ static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) {
  * Channels:    IN11, IN12, IN11, IN12, IN11, IN12, Sensor, VRef.

  */

 static const ADCConversionGroup adcgrpcfg2 = {

-  TRUE,

+  true,

   ADC_GRP2_NUM_CHANNELS,

   adccallback,

   adcerrorcallback,

@@ -71,7 +69,9 @@ static const ADCConversionGroup adcgrpcfg2 = {
   ADC_SMPR1_SMP_AN12(ADC_SAMPLE_56) | ADC_SMPR1_SMP_AN11(ADC_SAMPLE_56) |

   ADC_SMPR1_SMP_SENSOR(ADC_SAMPLE_144) | ADC_SMPR1_SMP_VREF(ADC_SAMPLE_144),

   0,                        /* SMPR2 */

-  ADC_SQR1_NUM_CH(ADC_GRP2_NUM_CHANNELS),

+  0,                        /* HTR */

+  0,                        /* LTR */

+  0,                        /* SQR1 */

   ADC_SQR2_SQ8_N(ADC_CHANNEL_SENSOR) | ADC_SQR2_SQ7_N(ADC_CHANNEL_VREFINT),

   ADC_SQR3_SQ6_N(ADC_CHANNEL_IN12)   | ADC_SQR3_SQ5_N(ADC_CHANNEL_IN11) |

   ADC_SQR3_SQ4_N(ADC_CHANNEL_IN12)   | ADC_SQR3_SQ3_N(ADC_CHANNEL_IN11) |

diff --git a/testhal/STM32/STM32L1xx/DAC/main.c b/testhal/STM32/STM32L1xx/DAC/main.c
index 28ce69ffe..3540dc778 100644
--- a/testhal/STM32/STM32L1xx/DAC/main.c
+++ b/testhal/STM32/STM32L1xx/DAC/main.c
@@ -59,16 +59,16 @@ static const dacsample_t dac_buffer[DAC_BUFFER_SIZE] = {
  * DAC streaming callback.

  */

 size_t nx = 0, ny = 0, nz = 0;

-static void end_cb1(DACDriver *dacp, dacsample_t *buffer, size_t n) {

+static void end_cb1(DACDriver *dacp) {

 

   (void)dacp;

 

   nz++;

-  if (dac_buffer == buffer) {

-    nx += n;

+  if (dacIsBufferComplete(dacp)) {

+    nx += DAC_BUFFER_SIZE / 2;

   }

   else {

-    ny += n;

+    ny += DAC_BUFFER_SIZE / 2;

   }

 

   if ((nz % 1000) == 0) {

diff --git a/testhal/STM32/multi/USB_CDC/Makefile b/testhal/STM32/multi/USB_CDC/Makefile
index 9da8633f9..74cef0040 100644
--- a/testhal/STM32/multi/USB_CDC/Makefile
+++ b/testhal/STM32/multi/USB_CDC/Makefile
@@ -9,7 +9,7 @@ all:
 	@echo ====================================================================

 	@echo

 	@echo === Building for STM32L4R5-Nucleo144 ===============================

-	@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make all

+	@make --no-print-directory -f ./make/stm32l4r5_nucleo144.make all

 	@echo ====================================================================

 	@echo

 	@echo === Building for STM32F303-Discovery ===============================

@@ -33,7 +33,7 @@ clean:
 	@echo

 	-@make --no-print-directory -f ./make/stm32l476_discovery.make clean

 	@echo

-	-@make --no-print-directory -f ./make/stm32l4r5zi_nucleo144.make clean

+	-@make --no-print-directory -f ./make/stm32l4r5_nucleo144.make clean

 	@echo

 	-@make --no-print-directory -f ./make/stm32f303_discovery.make clean

 	@echo

diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
index 3920704a5..3500ef385 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -185,8 +185,8 @@
 #define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC12                 TRUE

 #define STM32_ADC_USE_ADC3                  FALSE

-#define STM32_ADC_ADC12_DMA_CHANNEL         STM32_DMA_STREAM_ID_ANY

-#define STM32_ADC_ADC3_BDMA_CHANNEL         STM32_BDMA_STREAM_ID_ANY

+#define STM32_ADC_ADC12_DMA_STREAM          STM32_DMA_STREAM_ID_ANY

+#define STM32_ADC_ADC3_BDMA_STREAM          STM32_BDMA_STREAM_ID_ANY

 #define STM32_ADC_ADC12_DMA_PRIORITY        2

 #define STM32_ADC_ADC3_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

@@ -214,8 +214,8 @@
 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL      STM32_DMA_STREAM_ID_ANY

-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL      STM32_DMA_STREAM_ID_ANY

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

 

 /*

  * GPT driver system settings.

@@ -253,14 +253,14 @@
 #define STM32_I2C_USE_I2C3                  FALSE

 #define STM32_I2C_USE_I2C4                  FALSE

 #define STM32_I2C_BUSY_TIMEOUT              50

-#define STM32_I2C_I2C1_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_I2C_I2C1_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_I2C_I2C2_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_I2C_I2C2_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_I2C_I2C3_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_I2C_I2C3_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_I2C_I2C4_RX_BDMA_CHANNEL      STM32_BDMA_STREAM_ID_ANY

-#define STM32_I2C_I2C4_TX_BDMA_CHANNEL      STM32_BDMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C4_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_I2C_I2C4_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

 #define STM32_I2C_I2C1_IRQ_PRIORITY         5

 #define STM32_I2C_I2C2_IRQ_PRIORITY         5

 #define STM32_I2C_I2C3_IRQ_PRIORITY         5

@@ -335,7 +335,7 @@
 #define STM32_SDC_SDMMC_WRITE_TIMEOUT       1000

 #define STM32_SDC_SDMMC_READ_TIMEOUT        1000

 #define STM32_SDC_SDMMC_CLOCK_DELAY         10

-#define STM32_SDC_SDMMC1_DMA_CHANNEL        STM32_DMA_STREAM_ID_ANY

+#define STM32_SDC_SDMMC1_DMA_STREAM         STM32_DMA_STREAM_ID_ANY

 #define STM32_SDC_SDMMC1_DMA_PRIORITY       3

 #define STM32_SDC_SDMMC1_IRQ_PRIORITY       9

 

@@ -368,18 +368,18 @@
 #define STM32_SPI_USE_SPI4                  FALSE

 #define STM32_SPI_USE_SPI5                  FALSE

 #define STM32_SPI_USE_SPI6                  FALSE

-#define STM32_SPI_SPI1_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI1_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI2_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI2_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI3_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI3_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI4_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI4_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI5_RX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI5_TX_DMA_CHANNEL       STM32_DMA_STREAM_ID_ANY

-#define STM32_SPI_SPI6_RX_BDMA_CHANNEL      STM32_BDMA_STREAM_ID_ANY

-#define STM32_SPI_SPI6_TX_BDMA_CHANNEL      STM32_BDMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI6_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

+#define STM32_SPI_SPI6_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY

 #define STM32_SPI_SPI1_DMA_PRIORITY         1

 #define STM32_SPI_SPI2_DMA_PRIORITY         1

 #define STM32_SPI_SPI3_DMA_PRIORITY         1

@@ -411,22 +411,22 @@
 #define STM32_UART_USE_USART6               FALSE

 #define STM32_UART_USE_UART7                FALSE

 #define STM32_UART_USE_UART8                FALSE

-#define STM32_UART_USART1_RX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART1_TX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART2_RX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART2_TX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART3_RX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART3_TX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART4_RX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART4_TX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART5_RX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART5_TX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART6_RX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_USART6_TX_DMA_CHANNEL    STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART7_RX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART7_TX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART8_RX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

-#define STM32_UART_UART8_TX_DMA_CHANNEL     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART7_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART7_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART8_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART8_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

 #define STM32_UART_USART3_IRQ_PRIORITY      12

diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
index 3c6b8c5c1..c1fc3156f 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32l4r5_nucleo144/mcuconf.h
@@ -128,7 +128,7 @@
  */

 #define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

-#define STM32_ADC_ADC1_DMA_CHANNEL          10

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID_ANY

 #define STM32_ADC_ADC1_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

@@ -150,8 +150,8 @@
 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL      11

-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL      12

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

 

 /*

  * GPT driver system settings.

@@ -180,12 +180,12 @@
 #define STM32_I2C_USE_I2C2                  FALSE

 #define STM32_I2C_USE_I2C3                  FALSE

 #define STM32_I2C_BUSY_TIMEOUT              50

-#define STM32_I2C_I2C1_RX_DMA_CHANNEL       6

-#define STM32_I2C_I2C1_TX_DMA_CHANNEL       7

-#define STM32_I2C_I2C2_RX_DMA_CHANNEL       8

-#define STM32_I2C_I2C2_TX_DMA_CHANNEL       9

-#define STM32_I2C_I2C3_RX_DMA_CHANNEL       8

-#define STM32_I2C_I2C3_TX_DMA_CHANNEL       9

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

 #define STM32_I2C_I2C1_IRQ_PRIORITY         5

 #define STM32_I2C_I2C2_IRQ_PRIORITY         5

 #define STM32_I2C_I2C3_IRQ_PRIORITY         5

@@ -261,12 +261,12 @@
 #define STM32_SPI_USE_SPI1                  FALSE

 #define STM32_SPI_USE_SPI2                  FALSE

 #define STM32_SPI_USE_SPI3                  FALSE

-#define STM32_SPI_SPI1_RX_DMA_CHANNEL       0

-#define STM32_SPI_SPI1_TX_DMA_CHANNEL       1

-#define STM32_SPI_SPI2_RX_DMA_CHANNEL       2

-#define STM32_SPI_SPI2_TX_DMA_CHANNEL       3

-#define STM32_SPI_SPI3_RX_DMA_CHANNEL       4

-#define STM32_SPI_SPI3_TX_DMA_CHANNEL       5

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

 #define STM32_SPI_SPI1_DMA_PRIORITY         1

 #define STM32_SPI_SPI2_DMA_PRIORITY         1

 #define STM32_SPI_SPI3_DMA_PRIORITY         1

@@ -294,16 +294,16 @@
 #define STM32_UART_USE_USART3               FALSE

 #define STM32_UART_USE_UART4                FALSE

 #define STM32_UART_USE_UART5                FALSE

-#define STM32_UART_USART1_RX_DMA_CHANNEL    13

-#define STM32_UART_USART1_TX_DMA_CHANNEL    0

-#define STM32_UART_USART2_RX_DMA_CHANNEL    1

-#define STM32_UART_USART2_TX_DMA_CHANNEL    2

-#define STM32_UART_USART3_RX_DMA_CHANNEL    3

-#define STM32_UART_USART3_TX_DMA_CHANNEL    4

-#define STM32_UART_UART4_RX_DMA_CHANNEL     5

-#define STM32_UART_UART4_TX_DMA_CHANNEL     6

-#define STM32_UART_UART5_RX_DMA_CHANNEL     7

-#define STM32_UART_UART5_TX_DMA_CHANNEL     8

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

 #define STM32_UART_USART3_IRQ_PRIORITY      12

@@ -337,8 +337,8 @@
 #define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1

 #define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10

 #define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10

-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9

-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10

+#define STM32_WSPI_OCTOSPI1_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_WSPI_OCTOSPI2_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

 #define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1

 #define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1

 #define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10

diff --git a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
index 4bd9b9feb..d65c34433 100644
--- a/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
+++ b/testhal/STM32/multi/WSPI-MFS/cfg/stm32l4r9_discovery/mcuconf.h
@@ -128,7 +128,7 @@
  */

 #define STM32_ADC_COMPACT_SAMPLES           FALSE

 #define STM32_ADC_USE_ADC1                  FALSE

-#define STM32_ADC_ADC1_DMA_CHANNEL          10

+#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID_ANY

 #define STM32_ADC_ADC1_DMA_PRIORITY         2

 #define STM32_ADC_ADC12_IRQ_PRIORITY        5

 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     5

@@ -150,8 +150,8 @@
 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10

 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2

 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2

-#define STM32_DAC_DAC1_CH1_DMA_CHANNEL      11

-#define STM32_DAC_DAC1_CH2_DMA_CHANNEL      12

+#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

+#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY

 

 /*

  * GPT driver system settings.

@@ -180,12 +180,12 @@
 #define STM32_I2C_USE_I2C2                  FALSE

 #define STM32_I2C_USE_I2C3                  FALSE

 #define STM32_I2C_BUSY_TIMEOUT              50

-#define STM32_I2C_I2C1_RX_DMA_CHANNEL       6

-#define STM32_I2C_I2C1_TX_DMA_CHANNEL       7

-#define STM32_I2C_I2C2_RX_DMA_CHANNEL       8

-#define STM32_I2C_I2C2_TX_DMA_CHANNEL       9

-#define STM32_I2C_I2C3_RX_DMA_CHANNEL       8

-#define STM32_I2C_I2C3_TX_DMA_CHANNEL       9

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

 #define STM32_I2C_I2C1_IRQ_PRIORITY         5

 #define STM32_I2C_I2C2_IRQ_PRIORITY         5

 #define STM32_I2C_I2C3_IRQ_PRIORITY         5

@@ -261,12 +261,12 @@
 #define STM32_SPI_USE_SPI1                  FALSE

 #define STM32_SPI_USE_SPI2                  FALSE

 #define STM32_SPI_USE_SPI3                  FALSE

-#define STM32_SPI_SPI1_RX_DMA_CHANNEL       0

-#define STM32_SPI_SPI1_TX_DMA_CHANNEL       1

-#define STM32_SPI_SPI2_RX_DMA_CHANNEL       2

-#define STM32_SPI_SPI2_TX_DMA_CHANNEL       3

-#define STM32_SPI_SPI3_RX_DMA_CHANNEL       4

-#define STM32_SPI_SPI3_TX_DMA_CHANNEL       5

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY

 #define STM32_SPI_SPI1_DMA_PRIORITY         1

 #define STM32_SPI_SPI2_DMA_PRIORITY         1

 #define STM32_SPI_SPI3_DMA_PRIORITY         1

@@ -294,16 +294,16 @@
 #define STM32_UART_USE_USART3               FALSE

 #define STM32_UART_USE_UART4                FALSE

 #define STM32_UART_USE_UART5                FALSE

-#define STM32_UART_USART1_RX_DMA_CHANNEL    13

-#define STM32_UART_USART1_TX_DMA_CHANNEL    0

-#define STM32_UART_USART2_RX_DMA_CHANNEL    1

-#define STM32_UART_USART2_TX_DMA_CHANNEL    2

-#define STM32_UART_USART3_RX_DMA_CHANNEL    3

-#define STM32_UART_USART3_TX_DMA_CHANNEL    4

-#define STM32_UART_UART4_RX_DMA_CHANNEL     5

-#define STM32_UART_UART4_TX_DMA_CHANNEL     6

-#define STM32_UART_UART5_RX_DMA_CHANNEL     7

-#define STM32_UART_UART5_TX_DMA_CHANNEL     8

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

 #define STM32_UART_USART1_IRQ_PRIORITY      12

 #define STM32_UART_USART2_IRQ_PRIORITY      12

 #define STM32_UART_USART3_IRQ_PRIORITY      12

@@ -337,8 +337,8 @@
 #define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1

 #define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY    10

 #define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY    10

-#define STM32_WSPI_OCTOSPI1_DMA_CHANNEL     9

-#define STM32_WSPI_OCTOSPI2_DMA_CHANNEL     10

+#define STM32_WSPI_OCTOSPI1_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

+#define STM32_WSPI_OCTOSPI2_DMA_STREAM      STM32_DMA_STREAM_ID_ANY

 #define STM32_WSPI_OCTOSPI1_DMA_PRIORITY    1

 #define STM32_WSPI_OCTOSPI2_DMA_PRIORITY    1

 #define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10