diff options
| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-08-14 18:08:04 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-08-14 18:08:04 +0000 |
| commit | bfa1ba111db2b1f1366b6b33dbd0cf8ff86b5733 (patch) | |
| tree | 7596d57d1227c90986288d7953b95896c08887a2 /testhal/STM32F4xx/PWM-ICU | |
| parent | f0323b067c40d2a7eec4f67942606a371044654f (diff) | |
| download | ChibiOS-bfa1ba111db2b1f1366b6b33dbd0cf8ff86b5733.tar.gz ChibiOS-bfa1ba111db2b1f1366b6b33dbd0cf8ff86b5733.tar.bz2 ChibiOS-bfa1ba111db2b1f1366b6b33dbd0cf8ff86b5733.zip | |
I2C. Priorities rebalanced. I2C pushed over other peripherals as a workaround on buggy i2c cell in STM32.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4570 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'testhal/STM32F4xx/PWM-ICU')
| -rw-r--r-- | testhal/STM32F4xx/PWM-ICU/mcuconf.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/testhal/STM32F4xx/PWM-ICU/mcuconf.h b/testhal/STM32F4xx/PWM-ICU/mcuconf.h index e84c9dddc..9498f9303 100644 --- a/testhal/STM32F4xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32F4xx/PWM-ICU/mcuconf.h @@ -76,10 +76,10 @@ #define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
-#define STM32_ADC_IRQ_PRIORITY 5
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_IRQ_PRIORITY 6
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
@@ -227,12 +227,12 @@ #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
-#define STM32_I2C_I2C1_IRQ_PRIORITY 6
-#define STM32_I2C_I2C2_IRQ_PRIORITY 6
-#define STM32_I2C_I2C3_IRQ_PRIORITY 6
-#define STM32_I2C_I2C1_DMA_PRIORITY 1
-#define STM32_I2C_I2C2_DMA_PRIORITY 1
-#define STM32_I2C_I2C3_DMA_PRIORITY 1
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
|