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authorgdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01>2018-10-28 15:32:45 +0000
committergdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01>2018-10-28 15:32:45 +0000
commit9487a1f58c40b5cc3bc98c0eb14dfd1a0c18b8c2 (patch)
tree3b201d8918c53062ce8278365c6e95b456689dda /testhal/STM32/multi/WSPI-MFS/main.c
parentf42818b0a2bf0596c02830b761c365776a9194a7 (diff)
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OCTOSPI driver and demo, to be tested.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12395 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'testhal/STM32/multi/WSPI-MFS/main.c')
-rw-r--r--testhal/STM32/multi/WSPI-MFS/main.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/testhal/STM32/multi/WSPI-MFS/main.c b/testhal/STM32/multi/WSPI-MFS/main.c
index 826daab70..0bce0c7f3 100644
--- a/testhal/STM32/multi/WSPI-MFS/main.c
+++ b/testhal/STM32/multi/WSPI-MFS/main.c
@@ -26,11 +26,22 @@
#include "portab.h"
+#if defined(STM32_WSPI_USE_OCTOSPI1)
/* 16MB device, 2 cycles delay after NCS.*/
const WSPIConfig WSPIcfg1 = {
.end_cb = NULL,
- .dcr = STM32_DCR_FSIZE(24) | STM32_DCR_CSHT(1)
+ .dcr1 = STM32_DCR1_DEVSIZE(24U) | STM32_DCR1_CSHT(1U),
+ .dcr2 = 0U,
+ .dcr3 = 0U,
+ .dcr4 = 0U
};
+#else /* It is a quad SPI.*/
+/* 16MB device, 2 cycles delay after NCS.*/
+const WSPIConfig WSPIcfg1 = {
+ .end_cb = NULL,
+ .dcr = STM32_DCR_FSIZE(24U) | STM32_DCR_CSHT(1U)
+};
+#endif
const SNORConfig snorcfg1 = {
.busp = &WSPID1,