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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-05-22 11:51:17 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-05-22 11:51:17 +0000
commitee268d12c253ed336543b235b3af3ba9e9ff7b80 (patch)
tree913b0dd9035458e8c9b862c8e54d72b979b0a401 /os
parent2a6ece58eaac63be0baf6505c2de4785b5e5b0ed (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2997 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r--os/ports/GCC/AVR/chcore.h16
-rw-r--r--os/ports/GCC/MSP430/chcore.h16
-rw-r--r--os/ports/GCC/PPC/chcore.h24
-rw-r--r--os/ports/GCC/SIMIA32/chcore.h14
4 files changed, 55 insertions, 15 deletions
diff --git a/os/ports/GCC/AVR/chcore.h b/os/ports/GCC/AVR/chcore.h
index 5e1c4d954..2d33b205d 100644
--- a/os/ports/GCC/AVR/chcore.h
+++ b/os/ports/GCC/AVR/chcore.h
@@ -36,7 +36,7 @@
* @brief If enabled allows the idle thread to enter a low power mode.
*/
#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE 0
+#define ENABLE_WFI_IDLE 0
#endif
/**
@@ -47,12 +47,22 @@
/**
* @brief Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_NAME "AVR"
+#define CH_ARCHITECTURE_NAME "AVR"
/**
* @brief Name of the architecture variant (optional).
*/
-#define CH_CORE_VARIANT_NAME "MegaAVR"
+#define CH_CORE_VARIANT_NAME "MegaAVR"
+
+/**
+ * @brief Name of the compiler supported by this port.
+ */
+#define CH_COMPILER_NAME "GCC "__VERSION__
+
+/**
+ * @brief Port-specific information string.
+ */
+#define CH_PORT_INFO "None"
/**
* @brief 8 bits stack and memory alignment enforcement.
diff --git a/os/ports/GCC/MSP430/chcore.h b/os/ports/GCC/MSP430/chcore.h
index f70a34438..3e3d5b5d1 100644
--- a/os/ports/GCC/MSP430/chcore.h
+++ b/os/ports/GCC/MSP430/chcore.h
@@ -36,7 +36,7 @@
* @brief Enables the use of a wait state in the idle thread loop.
*/
#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE 0
+#define ENABLE_WFI_IDLE 0
#endif
/**
@@ -47,12 +47,22 @@
/**
* @brief Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_NAME "MSP430"
+#define CH_ARCHITECTURE_NAME "MSP430"
/**
* @brief Name of the architecture variant (optional).
*/
-#define CH_CORE_VARIANT_NAME "MSP430"
+#define CH_CORE_VARIANT_NAME "MSP430"
+
+/**
+ * @brief Name of the compiler supported by this port.
+ */
+#define CH_COMPILER_NAME "GCC "__VERSION__
+
+/**
+ * @brief Port-specific information string.
+ */
+#define CH_PORT_INFO "None"
/**
* @brief 16 bits stack and memory alignment enforcement.
diff --git a/os/ports/GCC/PPC/chcore.h b/os/ports/GCC/PPC/chcore.h
index 30e5f717c..6504532ac 100644
--- a/os/ports/GCC/PPC/chcore.h
+++ b/os/ports/GCC/PPC/chcore.h
@@ -37,12 +37,12 @@
* @brief Enables the use of the @p WFI instruction.
*/
#ifndef ENABLE_WFI_IDLE
-#define ENABLE_WFI_IDLE 0
+#define ENABLE_WFI_IDLE 0
#endif
/* Core variants identifiers.*/
-#define PPC_VARIANT_e200z3 3 /**< e200z3 core identifier. */
-#define PPC_VARIANT_e200z4 4 /**< e200z4 core identifier. */
+#define PPC_VARIANT_e200z3 3 /**< e200z3 core identifier. */
+#define PPC_VARIANT_e200z4 4 /**< e200z4 core identifier. */
/**
* @brief Core variant selector.
@@ -50,7 +50,7 @@
* possibly code paths and structures into the port layer.
*/
#if !defined(PPC_VARIANT) || defined(__DOXYGEN__)
-#define PPC_VARIANT PPC_VARIANT_e200z3
+#define PPC_VARIANT PPC_VARIANT_e200z3
#endif
/**
@@ -61,20 +61,30 @@
/**
* @brief Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_NAME "PowerPC"
+#define CH_ARCHITECTURE_NAME "Power Architecture"
/**
* @brief Name of the architecture variant.
*/
#if (PPC_VARIANT == PPC_VARIANT_e200z3) || defined(__DOXYGEN__)
-#define CH_CORE_VARIANT_NAME "e200z3"
+#define CH_CORE_VARIANT_NAME "e200z3"
#elif PPC_VARIANT == PPC_VARIANT_e200z4
-#define CH_CORE_VARIANT_NAME "e200z4"
+#define CH_CORE_VARIANT_NAME "e200z4"
#else
#error "unknown or unsupported PowerPC variant specified"
#endif
/**
+ * @brief Name of the compiler supported by this port.
+ */
+#define CH_COMPILER_NAME "GCC "__VERSION__
+
+/**
+ * @brief Port-specific information string.
+ */
+#define CH_PORT_INFO "None"
+
+/**
* @brief Base type for stack and memory alignment.
*/
typedef struct {
diff --git a/os/ports/GCC/SIMIA32/chcore.h b/os/ports/GCC/SIMIA32/chcore.h
index 05dc05db4..3d5c62b23 100644
--- a/os/ports/GCC/SIMIA32/chcore.h
+++ b/os/ports/GCC/SIMIA32/chcore.h
@@ -34,12 +34,22 @@
/**
* Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_NAME "Simulator"
+#define CH_ARCHITECTURE_NAME "Simulator"
/**
* @brief Name of the architecture variant (optional).
*/
-#define CH_CORE_VARIANT_NAME "x86 (integer only)"
+#define CH_CORE_VARIANT_NAME "x86 (integer only)"
+
+/**
+ * @brief Name of the compiler supported by this port.
+ */
+#define CH_COMPILER_NAME "GCC "__VERSION__
+
+/**
+ * @brief Port-specific information string.
+ */
+#define CH_PORT_INFO "No preemption"
/**
* 16 bytes stack alignment.