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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-22 12:43:39 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-22 12:43:39 +0000 |
| commit | e9ffaf9bdc231c69adffd5486c2949f21390e6e1 (patch) | |
| tree | 6e70b0f2705345ca8a6d354dab9364ce07529659 /os | |
| parent | c0a616c52b6c00aeee8917329bf8659d3062a7bc (diff) | |
| download | ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.tar.gz ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.tar.bz2 ChibiOS-e9ffaf9bdc231c69adffd5486c2949f21390e6e1.zip | |
Forked SPC5 drivers from SPC5-HAL project, not all of them, just the one needed for supporting the PPC port.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10679 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
82 files changed, 88526 insertions, 0 deletions
diff --git a/os/hal/ports/SPC5/LLD/DSPI_v1/cfg/hal_spi_lld_cfg.c.ftl b/os/hal/ports/SPC5/LLD/DSPI_v1/cfg/hal_spi_lld_cfg.c.ftl new file mode 100644 index 000000000..eaa8e0960 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/DSPI_v1/cfg/hal_spi_lld_cfg.c.ftl @@ -0,0 +1,119 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="hal_spi_lld_cfg.c" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_spi_lld_cfg.c
+ * @brief SPI Driver configuration code.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+#include "hal_spi_lld_cfg.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+[#list conf.instance.dspi_settings.spi_configurations.configs.spi_configuration_settings as settings]
+ [#assign name = settings.symbolic_name.value[0]?trim /]
+ [#-- Transfer group.--]
+ [#assign cpol = settings.transfer.clock_polarity[0].@index[0]?trim?number /]
+ [#assign cpha = settings.transfer.clock_phase[0].@index[0]?trim?number /]
+ [#assign frame_size = settings.transfer.frame_size[0].@index[0]?trim?number + 4 /]
+ [#assign frame_ordering = settings.transfer.frame_ordering[0].@index[0]?trim?number /]
+ [#-- Timings group.--]
+ [#assign brp = settings.timings.baud_rate_prescaler.value[0]?trim /]
+ [#assign brd = settings.timings.baud_rate_divider.value[0]?trim /]
+ [#assign dbr = (settings.timings.double_baud_rate.value[0]?trim?lower_case == "true") /]
+ [#assign cssckp = settings.timings.cssck_prescaler.value[0]?trim /]
+ [#assign cssckd = settings.timings.cssck_divider.value[0]?trim /]
+ [#assign ascp = settings.timings.asc_prescaler.value[0]?trim /]
+ [#assign ascd = settings.timings.asc_divider.value[0]?trim /]
+ [#assign dtp = settings.timings.dt_prescaler.value[0]?trim /]
+ [#assign dtd = settings.timings.dt_divider.value[0]?trim /]
+ [#-- Chip Select group.--]
+ [#assign mode = settings.chip_select.mode[0].@index[0]?trim?number /]
+ [#assign gpio_port = settings.chip_select.gpio_port.value[0]?trim /]
+ [#assign gpio_bit = settings.chip_select.gpio_bit.value[0]?trim?number /]
+ [#assign pcs_line = settings.chip_select.pcs_line[0].@index[0]?trim?number /]
+ [#-- Notifications group.--]
+ [#assign cb = settings.notifications.transfer_complete_callback.value[0]?string?trim /]
+ [#if cb == ""]
+ [#assign cb = "NULL" /]
+ [/#if]
+/**
+ * @brief Structure defining the SPI configuration "${name}".
+ */
+const SPIConfig spi_config_${name} = {
+ ${cb},
+ ${gpio_port},
+ ${gpio_bit},
+ 0 | SPC5_CTAR_FMSZ(${frame_size})[#rt]
+ [#if dbr]
+ | SPC5_CTAR_DBR[#rt]
+ [/#if]
+ [#if cpol != 0]
+ | SPC5_CTAR_CPOL[#rt]
+ [/#if]
+ [#if cpha != 0]
+ | SPC5_CTAR_CPHA[#rt]
+ [/#if]
+ [#if frame_ordering != 0]
+ | SPC5_CTAR_LSBFE[#rt]
+ [/#if]
+ |
+ SPC5_CTAR_PCSSCK_${cssckp} | SPC5_CTAR_PASC_${ascp} |
+ SPC5_CTAR_PDT_${dtp} | SPC5_CTAR_PBR_${brp} |
+ SPC5_CTAR_CSSCK_${cssckd} | SPC5_CTAR_ASC_${ascd} |
+ SPC5_CTAR_DT_${dtd} | SPC5_CTAR_BR_${brd},
+ 0[#rt]
+ [#if mode != 1]
+ | SPC5_PUSHR_CONT[#rt]
+ [/#if]
+ | SPC5_PUSHR_CTAS(0) | SPC5_PUSHR_PCS(${pcs_line})
+};
+
+[/#list]
+ /*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+ /*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/DSPI_v1/cfg/hal_spi_lld_cfg.h.ftl b/os/hal/ports/SPC5/LLD/DSPI_v1/cfg/hal_spi_lld_cfg.h.ftl new file mode 100644 index 000000000..995fd8ae6 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/DSPI_v1/cfg/hal_spi_lld_cfg.h.ftl @@ -0,0 +1,87 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="hal_spi_lld_cfg.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_spi_lld_cfg.h
+ * @brief SPI Driver configuration macros and structures.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef _SPI_LLD_CFG_H_
+#define _SPI_LLD_CFG_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/* List of the SPIConfig structures defined in spi_lld_cfg.c.*/
+[#list conf.instance.dspi_settings.spi_configurations.configs.spi_configuration_settings as settings]
+extern const SPIConfig spi_config_${settings.symbolic_name.value[0]?trim};
+[/#list]
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ /* List of the callback functions referenced from the SPIConfig
+ structures in spi_lld_cfg.c.*/
+[#assign transfer_complete_callbacks = []]
+[#list conf.instance.dspi_settings.spi_configurations.configs.spi_configuration_settings as settings]
+ [#assign callback = settings.notifications.transfer_complete_callback.value[0]?string?trim /]
+ [#if callback != ""]
+ [#if !transfer_complete_callbacks?seq_contains(callback)]
+ [#assign transfer_complete_callbacks = transfer_complete_callbacks + [callback]]
+ [/#if]
+ [/#if]
+[/#list]
+[#list transfer_complete_callbacks?sort as cb]
+ void ${cb}(SPIDriver *spip);
+[/#list]
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* _SPI_LLD_CFG_H_ */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.c b/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.c new file mode 100644 index 000000000..bc4fd57b2 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.c @@ -0,0 +1,1870 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/DSPI_v1/hal_spi_lld.c
+ * @brief SPC5xx SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/* Some forward declarations.*/
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE
+static void spi_serve_rx_dma_irq(edma_channel_t channel, void *p);
+#endif
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+static void spi_serve_tx_dma_irq(edma_channel_t channel, void *p);
+#endif
+
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE
+static void spi_serve_dma_error_irq(edma_channel_t channel,
+ void *p,
+ uint32_t esr);
+#endif
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* Excluded PUSHR bits.*/
+#define DSPI_PUSHR_EXCLUDED_BITS (SPC5_PUSHR_CTAS_MASK | \
+ SPC5_PUSHR_EOQ | \
+ SPC5_PUSHR_TXDATA_MASK)
+
+#define DSPI_POPR8_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 3)
+#define DSPI_POPR16_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 2)
+
+/* Set of macros dealing with the variable number of DMAs depending on
+ the chosen mode.*/
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+#define spi_lld_setdma(spip, tx1_cfg, tx2_cfg, rx_cfg) { \
+ (spip)->tx1_channel = edmaChannelAllocate(&(tx1_cfg)); \
+ (spip)->tx2_channel = edmaChannelAllocate(&(tx2_cfg)); \
+ (spip)->rx_channel = edmaChannelAllocate(&(rx_cfg)); \
+}
+#endif
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_ONLY
+#define spi_lld_setdma(spip, tx1_cfg, tx2_cfg, rx_cfg) { \
+ (spip)->rx_channel = edmaChannelAllocate(&(rx_cfg)); \
+}
+#endif
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+#define spi_lld_setdma(spip, tx1_cfg, tx2_cfg, rx_cfg) { \
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SPID1 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/**
+ * @brief SPID2 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/**
+ * @brief SPID3 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
+SPIDriver SPID3;
+#endif
+
+/**
+ * @brief SPID4 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
+SPIDriver SPID4;
+#endif
+
+/**
+ * @brief SPID5 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
+SPIDriver SPID5;
+#endif
+
+/**
+ * @brief SPID6 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI5 || defined(__DOXYGEN__)
+SPIDriver SPID6;
+#endif
+
+/**
+ * @brief SPID7 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI6 || defined(__DOXYGEN__)
+SPIDriver SPID7;
+#endif
+
+/**
+ * @brief SPID8 driver identifier.
+ */
+#if SPC5_SPI_USE_DSPI7 || defined(__DOXYGEN__)
+SPIDriver SPID8;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI0 TX1.
+ */
+static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
+ SPC5_SPI_DSPI0_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI0_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID1
+};
+
+/**
+ * @brief DMA configuration for DSPI0 TX2.
+ */
+static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
+ SPC5_SPI_DSPI0_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID1
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI0 RX.
+ */
+static const edma_channel_config_t spi_dspi0_rx_dma_config = {
+ SPC5_SPI_DSPI0_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI0_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI0_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID1
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI0 */
+
+#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI1 TX1.
+ */
+static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
+ SPC5_SPI_DSPI1_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI1_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID2
+};
+
+/**
+ * @brief DMA configuration for DSPI1 TX2.
+ */
+static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
+ SPC5_SPI_DSPI1_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID2
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI1 RX.
+ */
+static const edma_channel_config_t spi_dspi1_rx_dma_config = {
+ SPC5_SPI_DSPI1_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI1_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI1_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID2
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI1 */
+
+#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI2 TX1.
+ */
+static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
+ SPC5_SPI_DSPI2_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI2_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID3
+};
+
+/**
+ * @brief DMA configuration for DSPI2 TX2.
+ */
+static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
+ SPC5_SPI_DSPI2_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID3
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI2 RX.
+ */
+static const edma_channel_config_t spi_dspi2_rx_dma_config = {
+ SPC5_SPI_DSPI2_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI2_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI2_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID3
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI2 */
+
+#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI3 TX1.
+ */
+static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
+ SPC5_SPI_DSPI3_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI3_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID4
+};
+
+/**
+ * @brief DMA configuration for DSPI3 TX2.
+ */
+static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
+ SPC5_SPI_DSPI3_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID4
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI3 RX.
+ */
+static const edma_channel_config_t spi_dspi3_rx_dma_config = {
+ SPC5_SPI_DSPI3_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI3_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI3_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID4
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI3 */
+
+#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI4 TX1.
+ */
+static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
+ SPC5_SPI_DSPI4_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI4_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID5
+};
+
+/**
+ * @brief DMA configuration for DSPI4 TX2.
+ */
+static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
+ SPC5_SPI_DSPI4_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID5
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI4 RX.
+ */
+static const edma_channel_config_t spi_dspi4_rx_dma_config = {
+ SPC5_SPI_DSPI4_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI4_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI4_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID5
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI4 */
+
+#if SPC5_SPI_USE_DSPI5 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI5 TX1.
+ */
+static const edma_channel_config_t spi_dspi5_tx1_dma_config = {
+ SPC5_SPI_DSPI5_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI5_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI5_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID6
+};
+
+/**
+ * @brief DMA configuration for DSPI5 TX2.
+ */
+static const edma_channel_config_t spi_dspi5_tx2_dma_config = {
+ SPC5_SPI_DSPI5_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI5_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID6
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI5 RX.
+ */
+static const edma_channel_config_t spi_dspi5_rx_dma_config = {
+ SPC5_SPI_DSPI5_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI5_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI5_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID6
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI5 */
+
+#if SPC5_SPI_USE_DSPI6 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI6 TX1.
+ */
+static const edma_channel_config_t spi_dspi6_tx1_dma_config = {
+ SPC5_SPI_DSPI6_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI6_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI6_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID7
+};
+
+/**
+ * @brief DMA configuration for DSPI6 TX2.
+ */
+static const edma_channel_config_t spi_dspi6_tx2_dma_config = {
+ SPC5_SPI_DSPI6_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI6_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID7
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI6 RX.
+ */
+static const edma_channel_config_t spi_dspi6_rx_dma_config = {
+ SPC5_SPI_DSPI6_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI6_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI6_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID7
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI6 */
+
+#if SPC5_SPI_USE_DSPI7 || defined(__DOXYGEN__)
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI7 TX1.
+ */
+static const edma_channel_config_t spi_dspi7_tx1_dma_config = {
+ SPC5_SPI_DSPI7_TX1_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI7_TX1_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI7_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID8
+};
+
+/**
+ * @brief DMA configuration for DSPI7 TX2.
+ */
+static const edma_channel_config_t spi_dspi7_tx2_dma_config = {
+ SPC5_SPI_DSPI7_TX2_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ 0,
+#endif
+ SPC5_SPI_DSPI7_DMA_IRQ_PRIO,
+ spi_serve_tx_dma_irq, spi_serve_dma_error_irq, &SPID8
+};
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief DMA configuration for DSPI7 RX.
+ */
+static const edma_channel_config_t spi_dspi7_rx_dma_config = {
+ SPC5_SPI_DSPI7_RX_DMA_CH_ID,
+#if SPC5_EDMA_HAS_MUX
+ SPC5_DSPI7_RX_DMA_DEV_ID,
+#endif
+ SPC5_SPI_DSPI7_DMA_IRQ_PRIO,
+ spi_serve_rx_dma_irq, spi_serve_dma_error_irq, &SPID8
+};
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+#endif /* SPC5_SPI_USE_DSPI7 */
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Initializes the invariant part of the @p SPIDriver structure.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] dspi the physical DSPI unit to be associated to the object
+ *
+ * @notapi
+ */
+static void spi_lld_obj_init(SPIDriver *spip, struct spc5_dspi *dspi) {
+
+ spip->dspi = dspi;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+ spip->tx1_channel = EDMA_ERROR;
+ spip->tx2_channel = EDMA_ERROR;
+#endif
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE
+ spip->rx_channel = EDMA_ERROR;
+#endif
+}
+
+/**
+ * @brief DSPI unit setup for transfer.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+static void spi_dspi_start(SPIDriver *spip) {
+
+ spip->dspi->SR.R = spip->dspi->SR.R;
+ spip->dspi->MCR.B.HALT = 0;
+}
+
+/**
+ * @brief DSPI unit transfer stop.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+static void spi_dspi_stop(SPIDriver *spip) {
+
+ /* Stops the DSPI and clears the queues.*/
+ spip->dspi->MCR.R |= SPC5_MCR_HALT | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
+}
+
+/**
+ * @brief Prefills the TX FIFO with idle frames.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in,out] np pointer to the number of frames to send, must be
+ * greater than zero, contains the number of remaining
+ * frames on return
+ *
+ * @notapi
+ */
+static void spi_dspi_prefill_txfifo_idle(SPIDriver *spip, size_t *np) {
+ uint32_t cmd = spip->config->pushr;
+
+ while (spip->dspi->SR.B.TXCTR < SPC5_DSPI_FIFO_DEPTH) {
+ if (--(*np) == 0) {
+ spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | 0xFFFF) & ~SPC5_PUSHR_CONT;
+ break;
+ }
+ spip->dspi->PUSHR.R = cmd | 0x0000FFFF;
+ }
+}
+
+/**
+ * @brief Prefills the TX FIFO using 8 bits frames.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in,out] np pointer to the number of frames to send, must be
+ * greater than zero, contains the number of remaining
+ * frames on return
+ * @param[in,out] txpp pointer to the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+static void spi_dspi_prefill_txfifo8(SPIDriver *spip,
+ size_t *np,
+ const uint8_t **txpp) {
+ uint32_t cmd = spip->config->pushr;
+
+ while (spip->dspi->SR.B.TXCTR < SPC5_DSPI_FIFO_DEPTH) {
+ uint32_t frame = **txpp;
+ (*txpp)++;
+
+ if (--(*np) == 0) {
+ spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | frame) & ~SPC5_PUSHR_CONT;
+ break;
+ }
+ spip->dspi->PUSHR.R = cmd | frame;
+ }
+}
+
+/**
+ * @brief Prefills the TX FIFO using 16 bits frames.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in,out] np pointer to the number of frames to send, must be
+ * greater than zero, contains the number of remaining
+ * frames on return
+ * @param[in,out] txpp pointer to the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+static void spi_dspi_prefill_txfifo16(SPIDriver *spip,
+ size_t *np,
+ const uint16_t **txpp) {
+ uint32_t cmd = spip->config->pushr;
+
+ while (spip->dspi->SR.B.TXCTR < SPC5_DSPI_FIFO_DEPTH) {
+ uint32_t frame = **txpp;
+ (*txpp)++;
+
+ if (--(*np) == 0) {
+ spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | cmd | frame) & ~SPC5_PUSHR_CONT;
+ break;
+ }
+ spip->dspi->PUSHR.R = cmd | frame;
+ }
+}
+
+/**
+ * @brief Starts reception using DMA ignoring the received data.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ *
+ * @notapi
+ */
+static void spi_start_rx_ignore(SPIDriver *spip, size_t n) {
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ /* Setting up the fields required for operation continuation.*/
+ spip->rx_ptr = NULL;
+ spip->rx_cnt = n;
+
+#else /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+ static uint32_t datasink;
+
+ edmaChannelSetup(spip->rx_channel, /* channel. */
+ DSPI_POPR8_ADDRESS(spip), /* src. */
+ &datasink, /* dst. */
+ 0, /* soff, do not advance. */
+ 0, /* doff, do not advance. */
+ 0, /* ssize, 8 bits transfers. */
+ 0, /* dsize, 8 bits transfers. */
+ 1, /* nbytes, always one. */
+ n, /* iter. */
+ 0, /* slast. */
+ 0, /* dlast. */
+ EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
+
+ edmaChannelStart(spip->rx_channel);
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+}
+
+/**
+ * @brief Starts reception using DMA for frames up to 8 bits.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+static void spi_start_rx8(SPIDriver *spip, size_t n, uint8_t *rxbuf) {
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ /* Setting up the fields required for operation continuation.*/
+ spip->rx_ptr8 = rxbuf;
+ spip->rx_cnt = n;
+
+#else /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+ edmaChannelSetup(spip->rx_channel, /* channel. */
+ DSPI_POPR8_ADDRESS(spip), /* src. */
+ rxbuf, /* dst. */
+ 0, /* soff, do not advance. */
+ 1, /* doff, advance by one. */
+ 0, /* ssize, 8 bits transfers. */
+ 0, /* dsize, 8 bits transfers. */
+ 1, /* nbytes, always one. */
+ n, /* iter. */
+ 0, /* slast. */
+ 0, /* dlast. */
+ EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
+
+ edmaChannelStart(spip->rx_channel);
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+}
+
+/**
+ * @brief Starts reception using DMA for frames up to 16 bits.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+static void spi_start_rx16(SPIDriver *spip, size_t n, uint16_t *rxbuf) {
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ /* Setting up the fields required for operation continuation.*/
+ spip->rx_ptr16 = rxbuf;
+ spip->rx_cnt = n;
+
+#else /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+ edmaChannelSetup(spip->rx_channel, /* channel. */
+ DSPI_POPR16_ADDRESS(spip), /* src. */
+ rxbuf, /* dst. */
+ 0, /* soff, do not advance. */
+ 2, /* doff, advance by two. */
+ 1, /* ssize, 16 bits transfers.*/
+ 1, /* dsize, 16 bits transfers.*/
+ 2, /* nbytes, always two. */
+ n, /* iter. */
+ 0, /* slast, no source adjust. */
+ 0, /* dlast. */
+ EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
+
+ edmaChannelStart(spip->rx_channel);
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+}
+
+/**
+ * @brief Starts transmission using DMA for frames up to 8 bits.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ *
+ * @notapi
+ */
+static void spi_start_tx_ignore(SPIDriver *spip, size_t n) {
+
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_RX_AND_TX
+ /* Preloading the TX FIFO with as much frames as possible.*/
+ spi_dspi_prefill_txfifo_idle(spip, &n);
+
+ /* This is the case where the whole operation can be satisfied using the
+ preloading alone.*/
+ if (n == 0)
+ return;
+
+ /* Setting up the fields required for operation continuation.*/
+ spip->tx_ptr = NULL;
+ spip->tx_cnt = n;
+
+ /* Enabling the TFFF interrupt source for transfer continuation.*/
+ spip->dspi->RSER.B.TFFFRE = 1;
+
+#else /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+ /* Special case when the data to be transmitted can entirely fit into the
+ TX FIFO, in this case the TX DMAs are not activated.*/
+ if (n <= SPC5_DSPI_FIFO_DEPTH) {
+ spi_dspi_prefill_txfifo_idle(spip, &n);
+ return;
+ }
+
+ /* Preparing the TX intermediate buffer with the fixed part.*/
+ spip->tx_cmd = spip->config->pushr | (uint32_t)0xFFFF;
+
+ /* The first frame is pushed by the CPU, then the DMA is activated to
+ send the following frames. This should reduce latency on the operation
+ start.*/
+ spip->dspi->PUSHR.R = spip->tx_last = spip->tx_cmd;
+
+ /* Setting up TX1 DMA TCD parameters for 32 bits transfers.*/
+ edmaChannelSetup(spip->tx1_channel, /* channel. */
+ &spip->tx_cmd, /* src. */
+ &spip->dspi->PUSHR.R, /* dst. */
+ 0, /* soff, do not advance. */
+ 0, /* doff, do not advance. */
+ 2, /* ssize, 32 bits transfers.*/
+ 2, /* dsize, 32 bits transfers.*/
+ 4, /* nbytes, always four. */
+ n - 2, /* iter. */
+ 0, /* slast, no source adjust. */
+ 0, /* dlast, no dest.adjust. */
+ EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
+
+ /* Starting TX1 DMA channel.*/
+ edmaChannelStart(spip->tx1_channel);
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+}
+
+/**
+ * @brief Starts transmission using DMA for frames up to 8 bits.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+static void spi_start_tx8(SPIDriver *spip, size_t n, const uint8_t *txbuf) {
+
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_RX_AND_TX
+ /* Preloading the TX FIFO with as much frames as possible.*/
+ spi_dspi_prefill_txfifo8(spip, &n, &txbuf);
+
+ /* This is the case where the whole operation can be satisfied using the
+ preloading alone.*/
+ if (n == 0)
+ return;
+
+ /* Setting up the fields required for operation continuation.*/
+ spip->tx_ptr8 = txbuf;
+ spip->tx_cnt = n;
+
+ /* Enabling the TFFF interrupt source for transfer continuation.*/
+ spip->dspi->RSER.B.TFFFRE = 1;
+
+#else /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+ /* Special case when the data to be transmitted can entirely fit into the
+ TX FIFO, in this case the TX DMAs are not activated.*/
+ if (n <= SPC5_DSPI_FIFO_DEPTH) {
+ spi_dspi_prefill_txfifo8(spip, &n, &txbuf);
+ return;
+ }
+
+ /* Preparing the TX intermediate buffer with the fixed part.*/
+ spip->tx_cmd = spip->config->pushr;
+
+ /* The first frame is pushed immediately, then the DMA is activated to
+ send the following frames. This should reduce latency on the operation
+ start.*/
+ spip->dspi->PUSHR.R = spip->config->pushr | (uint32_t)*txbuf;
+
+ /* The last frame is a special case, will be pushed by the TX FIFO drain
+ interrupt handler or the DMA final callback.*/
+ spip->tx_last = txbuf[n - 1];
+
+ /* At least two frames left, the DMA is enabled in order to handle the
+ long transfer, note that the final frame is not pushed by the DMA.*/
+ /* Setting up TX1 DMA TCD parameters for 8 bits transfers.*/
+ edmaChannelSetupLinked(
+ spip->tx1_channel, /* channel. */
+ spip->tx2_channel, /* linkch. */
+ txbuf + 1, /* src. */
+ ((const uint8_t *)&spip->tx_cmd) + 3, /* dst. */
+ 1, /* soff, advance by 1. */
+ 0, /* doff, do not advance. */
+ 0, /* ssize, 8 bits transfers. */
+ 0, /* dsize, 8 bits transfers. */
+ 1, /* nbytes, always one. */
+ n - 2, /* iter. */
+ 0, /* slast, no source adjust. */
+ 0, /* dlast, no dest.adjust. */
+ EDMA_TCD_MODE_DREQ); /* mode. */
+
+ /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
+ edmaChannelSetup(spip->tx2_channel, /* channel. */
+ &spip->tx_cmd, /* src. */
+ &spip->dspi->PUSHR.R, /* dst. */
+ 0, /* soff, do not advance. */
+ 0, /* doff, do not advance. */
+ 2, /* ssize, 32 bits transfers.*/
+ 2, /* dsize, 32 bits transfers.*/
+ 4, /* nbytes, always four. */
+ n - 2, /* iter. */
+ 0, /* slast, no source adjust. */
+ 0, /* dlast, no dest.adjust. */
+ EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
+
+ /* Starting TX DMA channels.*/
+ edmaChannelStart(spip->tx2_channel);
+ edmaChannelStart(spip->tx1_channel);
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+}
+
+/**
+ * @brief Starts transmission using DMA for frames up to 16 bits.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+static void spi_start_tx16(SPIDriver *spip, size_t n, const uint16_t *txbuf) {
+
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_RX_AND_TX
+ /* Preloading the TX FIFO with as much frames as possible.*/
+ spi_dspi_prefill_txfifo16(spip, &n, &txbuf);
+
+ /* This is the case where the whole operation can be satisfied using the
+ preloading alone.*/
+ if (n == 0)
+ return;
+
+ /* Setting up the fields required for operation continuation.*/
+ spip->tx_ptr16 = txbuf;
+ spip->tx_cnt = n;
+
+ /* Enabling the TFFF interrupt source for transfer continuation.*/
+ spip->dspi->RSER.B.TFFFRE = 1;
+
+#else /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+ /* Special case when the data to be transmitted can entirely fit into the
+ TX FIFO, in this case the TX DMAs are not activated.*/
+ if (n <= SPC5_DSPI_FIFO_DEPTH) {
+ spi_dspi_prefill_txfifo16(spip, &n, &txbuf);
+ return;
+ }
+
+ /* Preparing the TX intermediate buffer with the fixed part.*/
+ spip->tx_cmd = spip->config->pushr;
+
+ /* The first frame is pushed immediately, then the DMA is activated to
+ send the following frames. This should reduce latency on the operation
+ start.*/
+ spip->dspi->PUSHR.R = spip->config->pushr | (uint32_t)*txbuf;
+
+ /* The last frame is a special case, will be pushed by the TX FIFO drain
+ interrupt handler or the DMA final callback.*/
+ spip->tx_last = txbuf[n - 1];
+
+ /* At least two frames left, the DMA is enabled in order to handle the
+ long transfer, note that the final frame is not pushed by the DMA.*/
+ /* Setting up TX1 DMA TCD parameters for 16 bits transfers.*/
+ edmaChannelSetupLinked(
+ spip->tx1_channel, /* channel. */
+ spip->tx2_channel, /* linkch. */
+ txbuf + 1, /* src. */
+ ((const uint8_t *)&spip->tx_cmd) + 2, /* dst. */
+ 2, /* soff, advance by 2. */
+ 0, /* doff, do not advance. */
+ 1, /* ssize, 16 bits transfers.*/
+ 1, /* dsize, 16 bits transfers.*/
+ 2, /* nbytes, always two. */
+ n - 2, /* iter. */
+ 0, /* slast, no source adjust. */
+ 0, /* dlast, no dest.adjust. */
+ EDMA_TCD_MODE_DREQ); /* mode. */
+
+ /* Setting up TX2 DMA TCD parameters for 32 bits transfers.*/
+ edmaChannelSetup(spip->tx2_channel, /* channel. */
+ &spip->tx_cmd, /* src. */
+ &spip->dspi->PUSHR.R, /* dst. */
+ 0, /* soff, do not advance. */
+ 0, /* doff, do not advance. */
+ 2, /* ssize, 32 bits transfers.*/
+ 2, /* dsize, 32 bits transfers.*/
+ 4, /* nbytes, always four. */
+ n - 2, /* iter. */
+ 0, /* slast, no source adjust. */
+ 0, /* dlast, no dest.adjust. */
+ EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode. */
+
+ /* Starting TX DMA channels.*/
+ edmaChannelStart(spip->tx2_channel);
+ edmaChannelStart(spip->tx1_channel);
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+}
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared RX DMA events service routine.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ *
+ * @notapi
+ */
+static void spi_serve_rx_dma_irq(edma_channel_t channel, void *p) {
+ SPIDriver *spip = (SPIDriver *)p;
+
+ /* Clearing RX channel state.*/
+ edmaChannelStop(channel);
+
+ /* Stops the transfer.*/
+ spi_dspi_stop(spip);
+
+ /* Portable SPI ISR code defined in the high level driver, note, it is
+ a macro.*/
+ _spi_isr_code(spip);
+}
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+/**
+ * @brief Shared TX1/TX2 DMA events service routine.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ *
+ * @notapi
+ */
+static void spi_serve_tx_dma_irq(edma_channel_t channel, void *p) {
+ SPIDriver *spip = (SPIDriver *)p;
+
+ (void)channel;
+
+ /* Clearing TX channels state.*/
+ edmaChannelStop(spip->tx1_channel);
+ edmaChannelStop(spip->tx2_channel);
+
+ /* If the TX FIFO is full then the push of the last frame is delegated to
+ an interrupt handler else it is performed immediately. Both conditions
+ can be true depending on the SPI speed and ISR latency.*/
+ if (spip->dspi->SR.B.TFFF) {
+ spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) &
+ ~SPC5_PUSHR_CONT;
+ }
+ else {
+ spip->dspi->RSER.B.TFFFDIRS = 0;
+ }
+}
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared ISR for DMA error events.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ * @param[in] esr content of the ESR register
+ *
+ * @notapi
+ */
+static void spi_serve_dma_error_irq(edma_channel_t channel,
+ void *p,
+ uint32_t esr) {
+ SPIDriver *spip = (SPIDriver *)p;
+
+ (void)channel;
+ (void)esr;
+
+ /* Stops the transfer.*/
+ spi_dspi_stop(spip);
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+ edmaChannelStop(spip->tx1_channel);
+ edmaChannelStop(spip->tx2_channel);
+#endif
+ edmaChannelStop(spip->rx_channel);
+
+ SPC5_SPI_DMA_ERROR_HOOK(spip);
+}
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared ISR for RFDF DSPI events.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_serve_dspi_rfdf(SPIDriver *spip) {
+
+ osalSysLockFromISR();
+
+ /* Emptying the RX FIFO.*/
+ while ((spip->rx_cnt > 0) && (spip->dspi->SR.B.RXCTR > 0)) {
+ uint32_t frame = spip->dspi->POPR.R;
+ if (spip->rx_ptr != NULL) {
+ if (spip->dspi->CTAR[0].B.FMSZ < 8)
+ *spip->rx_ptr8++ = (uint8_t)frame;
+ else
+ *spip->rx_ptr16++ = (uint16_t)frame;
+ }
+ spip->rx_cnt--;
+ }
+
+ /* Interrupt served.*/
+ spip->dspi->SR.B.RFDF = 1;
+
+ if (spip->rx_cnt == 0) {
+ /* Stops the transfer.*/
+ spi_dspi_stop(spip);
+
+ /* Portable SPI ISR code defined in the high level driver, note, it is
+ a macro.*/
+ _spi_isr_code(spip);
+ }
+ else {
+ if (spip->tx_cnt > 0) {
+ /* Filling the TX FIFO.*/
+ if (spip->tx_ptr == NULL)
+ spi_dspi_prefill_txfifo_idle(spip, &spip->tx_cnt);
+ else {
+ if (spip->dspi->CTAR[0].B.FMSZ < 8)
+ spi_dspi_prefill_txfifo8(spip, &spip->tx_cnt, &spip->tx_ptr8);
+ else
+ spi_dspi_prefill_txfifo16(spip, &spip->tx_cnt, &spip->tx_ptr16);
+ }
+ }
+ }
+
+ osalSysUnlockFromISR();
+}
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+/**
+ * @brief Shared ISR for TFFF DSPI events.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_serve_dspi_tfff(SPIDriver *spip) {
+
+ osalSysLockFromISR();
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+ /* Interrupt served and back to DMA mode.*/
+ spip->dspi->RSER.B.TFFFDIRS = 1;
+ spip->dspi->SR.B.TFFF = 1;
+
+ /* Pushing last frame.*/
+ spip->dspi->PUSHR.R = (spip->config->pushr | spip->tx_last | SPC5_PUSHR_EOQ) &
+ ~SPC5_PUSHR_CONT;
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX */
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_ONLY
+ /* Pushing some more frames in the TX FIFO.*/
+ if (spip->tx_ptr == NULL)
+ spi_dspi_prefill_txfifo_idle(spip, &spip->tx_cnt);
+ else {
+ if (spip->dspi->CTAR[0].B.FMSZ < 8)
+ spi_dspi_prefill_txfifo8(spip, &spip->tx_cnt, &spip->tx_ptr8);
+ else
+ spi_dspi_prefill_txfifo16(spip, &spip->tx_cnt, &spip->tx_ptr16);
+ }
+
+ /* Interrupt served.*/
+ spip->dspi->SR.B.TFFF = 1;
+
+ /* If there are no more frames to be pushed then the TFFF interrupt source
+ is disabled.*/
+ if (spip->tx_cnt == 0)
+ spip->dspi->RSER.B.TFFFRE = 0;
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_ONLY */
+
+ osalSysUnlockFromISR();
+}
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI0_RFDF_HANDLER)
+#error "SPC5_DSPI0_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI0 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI0_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI0 */
+
+#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI1_RFDF_HANDLER)
+#error "SPC5_DSPI1_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI1 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI1_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI1 */
+
+#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI2_RFDF_HANDLER)
+#error "SPC5_DSPI2_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI2 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI2_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI2 */
+
+#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI3_RFDF_HANDLER)
+#error "SPC5_DSPI3_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI3 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI3_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI3 */
+
+#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI4_RFDF_HANDLER)
+#error "SPC5_DSPI4_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI4 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI4_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI4 */
+
+#if SPC5_SPI_USE_DSPI5 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI5_RFDF_HANDLER)
+#error "SPC5_DSPI5_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI5 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI5_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI5 */
+
+#if SPC5_SPI_USE_DSPI6 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI6_RFDF_HANDLER)
+#error "SPC5_DSPI6_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI6 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI6_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI6 */
+
+#if SPC5_SPI_USE_DSPI7 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI7_RFDF_HANDLER)
+#error "SPC5_DSPI7_RFDF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI7 RFDF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI7_RFDF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_rfdf(&SPID8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI7 */
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE */
+
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI0_TFFF_HANDLER)
+#error "SPC5_DSPI0_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI0 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI0_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI0 */
+
+#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI1_TFFF_HANDLER)
+#error "SPC5_DSPI1_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI1 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI1_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI1 */
+
+#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI2_TFFF_HANDLER)
+#error "SPC5_DSPI2_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI2 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI2_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI2 */
+
+#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI3_TFFF_HANDLER)
+#error "SPC5_DSPI3_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI3 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI3_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI3 */
+
+#if SPC5_SPI_USE_DSPI4 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI4_TFFF_HANDLER)
+#error "SPC5_DSPI4_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI4 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI4_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI4 */
+
+#if SPC5_SPI_USE_DSPI5 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI5_TFFF_HANDLER)
+#error "SPC5_DSPI5_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI5 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI5_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI5 */
+
+#if SPC5_SPI_USE_DSPI6 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI6_TFFF_HANDLER)
+#error "SPC5_DSPI6_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI6 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI6_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI6 */
+
+#if SPC5_SPI_USE_DSPI7 || defined(__DOXYGEN__)
+#if !defined(SPC5_DSPI7_TFFF_HANDLER)
+#error "SPC5_DSPI7_TFFF_HANDLER not defined"
+#endif
+/**
+ * @brief DSPI7 TFFF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_DSPI7_TFFF_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spi_serve_dspi_tfff(&SPID8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_SPI_USE_DSPI7 */
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+
+#if SPC5_SPI_USE_DSPI0
+ /* Driver initialization.*/
+ SPC5_DSPI0_ENABLE_CLOCK();
+ spiObjectInit(&SPID1);
+ spi_lld_obj_init(&SPID1, &SPC5_DSPI0);
+ SPC5_DSPI0.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI0_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI0_RFDF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI0_TFFF_NUMBER].R = SPC5_SPI_DSPI0_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI0 */
+
+#if SPC5_SPI_USE_DSPI1
+ /* Driver initialization.*/
+ SPC5_DSPI1_ENABLE_CLOCK();
+ spiObjectInit(&SPID2);
+ spi_lld_obj_init(&SPID2, &SPC5_DSPI1);
+ SPC5_DSPI1.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI1_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI1_RFDF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI1_TFFF_NUMBER].R = SPC5_SPI_DSPI1_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI1 */
+
+#if SPC5_SPI_USE_DSPI2
+ /* Driver initialization.*/
+ SPC5_DSPI2_ENABLE_CLOCK();
+ spiObjectInit(&SPID3);
+ spi_lld_obj_init(&SPID3, &SPC5_DSPI2);
+ SPC5_DSPI2.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI2_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI2_RFDF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI2_TFFF_NUMBER].R = SPC5_SPI_DSPI2_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI2 */
+
+#if SPC5_SPI_USE_DSPI3
+ /* Driver initialization.*/
+ SPC5_DSPI3_ENABLE_CLOCK();
+ spiObjectInit(&SPID4);
+ spi_lld_obj_init(&SPID4, &SPC5_DSPI3);
+ SPC5_DSPI3.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI3_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI3_RFDF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI3_TFFF_NUMBER].R = SPC5_SPI_DSPI3_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI3 */
+
+#if SPC5_SPI_USE_DSPI4
+ /* Driver initialization.*/
+ SPC5_DSPI4_ENABLE_CLOCK();
+ spiObjectInit(&SPID5);
+ spi_lld_obj_init(&SPID5, &SPC5_DSPI4);
+ SPC5_DSPI4.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI4_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI4_RFDF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI4_TFFF_NUMBER].R = SPC5_SPI_DSPI4_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI4 */
+
+#if SPC5_SPI_USE_DSPI5
+ /* Driver initialization.*/
+ SPC5_DSPI5_ENABLE_CLOCK();
+ spiObjectInit(&SPID6);
+ spi_lld_obj_init(&SPID6, &SPC5_DSPI5);
+ SPC5_DSPI5.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI5_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI5_RFDF_NUMBER].R = SPC5_SPI_DSPI5_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI5_TFFF_NUMBER].R = SPC5_SPI_DSPI5_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI5 */
+
+#if SPC5_SPI_USE_DSPI6
+ /* Driver initialization.*/
+ SPC5_DSPI6_ENABLE_CLOCK();
+ spiObjectInit(&SPID7);
+ spi_lld_obj_init(&SPID7, &SPC5_DSPI6);
+ SPC5_DSPI6.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI6_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI6_RFDF_NUMBER].R = SPC5_SPI_DSPI6_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI6_TFFF_NUMBER].R = SPC5_SPI_DSPI6_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI6 */
+
+#if SPC5_SPI_USE_DSPI7
+ /* Driver initialization.*/
+ SPC5_DSPI7_ENABLE_CLOCK();
+ spiObjectInit(&SPID8);
+ spi_lld_obj_init(&SPID8, &SPC5_DSPI7);
+ SPC5_DSPI7.MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | SPC5_MCR_MDIS |
+ SPC5_SPI_DSPI7_MCR;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ INTC.PSR[SPC5_DSPI7_RFDF_NUMBER].R = SPC5_SPI_DSPI7_IRQ_PRIO;
+#else
+ INTC.PSR[SPC5_DSPI7_TFFF_NUMBER].R = SPC5_SPI_DSPI7_IRQ_PRIO;
+#endif
+#endif /* SPC5_SPI_USE_DSPI7 */
+}
+
+/**
+ * @brief Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+
+ osalDbgAssert((spip->config->pushr & DSPI_PUSHR_EXCLUDED_BITS) == 0,
+ "invalid PUSHR bits specified");
+
+ if (spip->state == SPI_STOP) {
+ /* Enables the peripheral.*/
+
+#if SPC5_SPI_USE_DSPI0
+ if (&SPID1 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi0_tx1_dma_config,
+ spi_dspi0_tx2_dma_config,
+ spi_dspi0_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI0 */
+
+#if SPC5_SPI_USE_DSPI1
+ if (&SPID2 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi1_tx1_dma_config,
+ spi_dspi1_tx2_dma_config,
+ spi_dspi1_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI1 */
+
+#if SPC5_SPI_USE_DSPI2
+ if (&SPID3 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi2_tx1_dma_config,
+ spi_dspi2_tx2_dma_config,
+ spi_dspi2_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI2 */
+
+#if SPC5_SPI_USE_DSPI3
+ if (&SPID4 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi3_tx1_dma_config,
+ spi_dspi3_tx2_dma_config,
+ spi_dspi3_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI3 */
+
+#if SPC5_SPI_USE_DSPI4
+ if (&SPID5 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi4_tx1_dma_config,
+ spi_dspi4_tx2_dma_config,
+ spi_dspi4_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI4 */
+
+#if SPC5_SPI_USE_DSPI5
+ if (&SPID6 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi5_tx1_dma_config,
+ spi_dspi5_tx2_dma_config,
+ spi_dspi5_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI5 */
+
+#if SPC5_SPI_USE_DSPI6
+ if (&SPID7 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi6_tx1_dma_config,
+ spi_dspi6_tx2_dma_config,
+ spi_dspi6_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI6 */
+
+#if SPC5_SPI_USE_DSPI7
+ if (&SPID8 == spip) {
+ spi_lld_setdma(spip,
+ spi_dspi7_tx1_dma_config,
+ spi_dspi7_tx2_dma_config,
+ spi_dspi7_rx_dma_config)
+ }
+#endif /* SPC5_SPI_USE_DSPI7 */
+
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+ osalDbgAssert((spip->tx1_channel != EDMA_ERROR) &&
+ (spip->tx2_channel != EDMA_ERROR),
+ "TX DMA channels cannot be allocated");
+#endif
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE
+ osalDbgAssert(spip->rx_channel != EDMA_ERROR,
+ "RX DMA channels cannot be allocated");
+#endif
+ }
+
+ /* Configures the peripheral, the RSER register setting depend on the
+ chosen DMA use mode.*/
+ spip->dspi->MCR.B.MDIS = 0;
+ spip->dspi->CTAR[0].R = spip->config->ctar0;
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE
+ spip->dspi->RSER.R = SPC5_RSER_RFDF_RE;
+#endif
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_ONLY
+ spip->dspi->RSER.R = SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
+#endif
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+ spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
+ SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
+#endif
+ spip->dspi->SR.R = spip->dspi->SR.R;
+}
+
+/**
+ * @brief Deactivates the SPI peripheral.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+ if (spip->state == SPI_READY) {
+ /* Releases the allocated EDMA channels.*/
+#if SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX
+ edmaChannelRelease(spip->tx1_channel);
+ edmaChannelRelease(spip->tx2_channel);
+#endif
+#if SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE
+ edmaChannelRelease(spip->rx_channel);
+#endif
+
+ /* Resets the peripheral.*/
+ spip->dspi->CTAR[0].R = 0;
+ spip->dspi->RSER.R = 0;
+ spip->dspi->SR.R = spip->dspi->SR.R;
+ spip->dspi->MCR.R |= SPC5_MCR_HALT |
+ SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
+ spip->dspi->MCR.B.MDIS = 1;
+ }
+}
+
+/**
+ * @brief Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+ palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+ palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ * idle words on the SPI bus and ignores the received data.
+ * @post At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+ /* Starting transfer.*/
+ spi_dspi_start(spip);
+
+ /* Setting up the DMA channels.*/
+ spi_start_rx_ignore(spip, n);
+ spi_start_tx_ignore(spip, n);
+}
+
+/**
+ * @brief Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ * operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to be exchanged
+ * @param[in] txbuf the pointer to the transmit buffer
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf) {
+
+ /* Starting transfer.*/
+ spi_dspi_start(spip);
+
+ /* DMAs require a different setup depending on the frame size.*/
+ if (spip->dspi->CTAR[0].B.FMSZ < 8) {
+ spi_start_rx8(spip, n, rxbuf);
+ spi_start_tx8(spip, n, txbuf);
+ }
+ else {
+ spi_start_rx16(spip, n, rxbuf);
+ spi_start_tx16(spip, n, txbuf);
+ }
+}
+
+/**
+ * @brief Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to send
+ * @param[in] txbuf the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+ /* Starting transfer.*/
+ spi_dspi_start(spip);
+
+ /* Setting up the RX DMA channel.*/
+ spi_start_rx_ignore(spip, n);
+
+ /* DMAs require a different setup depending on the frame size.*/
+ if (spip->dspi->CTAR[0].B.FMSZ < 8)
+ spi_start_tx8(spip, n, txbuf);
+ else
+ spi_start_tx16(spip, n, txbuf);
+}
+
+/**
+ * @brief Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post At the end of the operation the configured callback is invoked.
+ * @note The buffers are organized as uint8_t arrays for data sizes below or
+ * equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] n number of words to receive
+ * @param[out] rxbuf the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+ /* Starting transfer.*/
+ spi_dspi_start(spip);
+
+ /* DMAs require a different setup depending on the frame size.*/
+ if (spip->dspi->CTAR[0].B.FMSZ < 8)
+ spi_start_rx8(spip, n, rxbuf);
+ else
+ spi_start_rx16(spip, n, rxbuf);
+
+ spi_start_tx_ignore(spip, n);
+}
+
+/**
+ * @brief Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ * synchronization method. This function is useful when exchanging
+ * small amount of data on high speed channels, usually in this
+ * situation is much more efficient just wait for completion using
+ * polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object
+ * @param[in] frame the data frame to send over the SPI bus
+ * @return The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+ uint32_t popr;
+
+ /* Starting transfer.*/
+ spi_dspi_start(spip);
+
+ /* Data exchange.*/
+ spip->dspi->PUSHR.R = (SPC5_PUSHR_EOQ | spip->config->pushr |
+ (uint32_t)frame) & ~SPC5_PUSHR_CONT;
+ while (!spip->dspi->SR.B.RFDF)
+ ;
+ popr = spip->dspi->POPR.R;
+
+ /* Stopping transfer.*/
+ spi_dspi_stop(spip);
+
+ return (uint16_t)popr;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.h b/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.h new file mode 100644 index 000000000..397f96efe --- /dev/null +++ b/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.h @@ -0,0 +1,848 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/DSPI_v1/hal_spi_lld.h
+ * @brief SPC5xx SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef HAL_SPI_LLD_H
+#define HAL_SPI_LLD_H
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+#include "spc5_dspi.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name SPI DMA modes
+ * @{
+ */
+#define SPC5_SPI_DMA_NONE 0
+#define SPC5_SPI_DMA_RX_ONLY 1
+#define SPC5_SPI_DMA_RX_AND_TX 2
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief SPID1 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI0 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI0) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI0 FALSE
+#endif
+
+/**
+ * @brief SPID2 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI1 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI1) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI1 FALSE
+#endif
+
+/**
+ * @brief SPID3 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI2 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI2) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI2 FALSE
+#endif
+
+/**
+ * @brief SPID4 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI3 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI3) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI3 FALSE
+#endif
+
+/**
+ * @brief SPID5 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI4 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI4 FALSE
+#endif
+
+/**
+ * @brief SPID6 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI5 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI5) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI5 FALSE
+#endif
+
+/**
+ * @brief SPID7 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI6 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI6) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI6 FALSE
+#endif
+
+/**
+ * @brief SPID8 driver enable switch.
+ * @details If set to @p TRUE the support for DSPI7 is included.
+ */
+#if !defined(SPC5_SPI_USE_DSPI7) || defined(__DOXYGEN__)
+#define SPC5_SPI_USE_DSPI7 FALSE
+#endif
+
+/**
+ * @brief Selects the DMA mode for the SPI driver.
+ * @details The driver is able to work using three distinct DMA modes:
+ * - SPC5_SPI_DMA_RX_AND_TX, 3 DMA channels are used for both RX
+ * and TX. Note, the transmission size is limited to 512 frames
+ * in this mode because EDMA limitations.
+ * - SPC5_SPI_DMA_RX_ONLY, 1 DMA channels is used for RX only. TX
+ * is handled using interrupts.
+ * - SPC5_SPI_DMA_NONE, the DMA is not used at all, the drivers
+ * works in a fully interrupt-driven way.
+ * .
+ * @note DMA modes are only possible on those platforms where a DMA
+ * controllers is present.
+ */
+#if !defined(SPC5_SPI_DMA_MODE) || defined(__DOXYGEN__)
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_NONE
+#endif
+
+/**
+ * @brief DSPI0 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI1 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI1_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSP2 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI2_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI3 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI3_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI4 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI5 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI5_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI5_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI6 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI6_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI6_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI7 MCR PCS defaults.
+ */
+#if !defined(SPC5_SPI_DSPI7_MCR) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI7_MCR (SPC5_MCR_PCSIS0 | \
+ SPC5_MCR_PCSIS1 | \
+ SPC5_MCR_PCSIS2 | \
+ SPC5_MCR_PCSIS3 | \
+ SPC5_MCR_PCSIS4 | \
+ SPC5_MCR_PCSIS5 | \
+ SPC5_MCR_PCSIS6 | \
+ SPC5_MCR_PCSIS7)
+#endif
+
+/**
+ * @brief DSPI0 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI1 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI1_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI2 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI3 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI3_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI4 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI5 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI5_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI6 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI6_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI6_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI7 DMA IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI7_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI7_DMA_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief SPI DMA error hook.
+ */
+#if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DSPI DMA failure")
+#endif
+
+/**
+ * @brief DSPI0 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI0_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI0_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI1 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI1_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI1_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI2 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI2_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI2_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI3 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI3_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI3_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI4 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI4_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI5 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI5_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI5_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI6 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI6_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI6_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI7 IRQ priority.
+ */
+#if !defined(SPC5_SPI_DSPI7_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI7_IRQ_PRIO 10
+#endif
+
+/**
+ * @brief DSPI0 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI0_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI0 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI0_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI1 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI1_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI1 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI1_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI2 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI2_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI2 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI2_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI3 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI3_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI3 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI3_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI4 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI4_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI4 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI4_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI5 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI5_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI5 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI5_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI6 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI6_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI6_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI6 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI6_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI6_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief DSPI7 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI7_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI7_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief DSPI7 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SPI_DSPI7_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SPI_DSPI7_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if !(SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE) && \
+ !(SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_ONLY) && \
+ !(SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX)
+#error "invalid SPC5_SPI_DMA_MODE selected"
+#endif
+
+#if !SPC5_HAS_EDMA && (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE)
+#error "SPI with DMA modes are not supported on this device, no DMA found"
+#endif
+
+#if SPC5_SPI_USE_DSPI0 && !SPC5_HAS_DSPI0
+#error "DSPI0 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI1 && !SPC5_HAS_DSPI1
+#error "DSPI1 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI2 && !SPC5_HAS_DSPI2
+#error "DSPI2 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI3 && !SPC5_HAS_DSPI3
+#error "DSPI3 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI4 && !SPC5_HAS_DSPI4
+#error "DSPI4 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI5 && !SPC5_HAS_DSPI5
+#error "DSPI5 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI6 && !SPC5_HAS_DSPI6
+#error "DSPI6 not present in the selected device"
+#endif
+
+#if SPC5_SPI_USE_DSPI7 && !SPC5_HAS_DSPI7
+#error "DSPI7 not present in the selected device"
+#endif
+
+#if !SPC5_SPI_USE_DSPI0 && !SPC5_SPI_USE_DSPI1 && \
+ !SPC5_SPI_USE_DSPI2 && !SPC5_SPI_USE_DSPI3 && \
+ !SPC5_SPI_USE_DSPI4 && !SPC5_SPI_USE_DSPI5 && \
+ !SPC5_SPI_USE_DSPI6 && !SPC5_SPI_USE_DSPI7
+#error "SPI driver activated but no DSPI peripheral assigned"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI0 && \
+ (!defined(SPC5_SPI_DSPI0_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI0_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI0_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI0, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI1 && \
+ (!defined(SPC5_SPI_DSPI1_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI1_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI1_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI1, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI2 && \
+ (!defined(SPC5_SPI_DSPI2_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI2_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI2_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI2, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI3 && \
+ (!defined(SPC5_SPI_DSPI3_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI3_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI3_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI3, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI4 && \
+ (!defined(SPC5_SPI_DSPI4_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI4_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI4_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI4, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI5 && \
+ (!defined(SPC5_SPI_DSPI5_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI5_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI5_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI5, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI6 && \
+ (!defined(SPC5_SPI_DSPI6_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI6_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI6_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI6, check mcuconf.h"
+#endif
+
+#if SPC5_HAS_EDMA && SPC5_SPI_USE_DSPI7 && \
+ (!defined(SPC5_SPI_DSPI7_TX1_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI7_TX2_DMA_CH_ID) || \
+ !defined(SPC5_SPI_DSPI7_RX_DMA_CH_ID))
+#error "DMA channels not defined for DSPI7, check mcuconf.h"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief SPI notification callback type.
+ *
+ * @param[in] spip pointer to the @p SPIDriver object triggering the
+ * callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief Driver configuration structure.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ /**
+ * @brief Operation complete callback.
+ */
+ spicallback_t end_cb;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief The chip select line port.
+ */
+ ioportid_t ssport;
+ /**
+ * @brief The chip select line pad number.
+ */
+ uint16_t sspad;
+ /**
+ * @brief DSPI CTAR0 value for this session.
+ */
+ uint32_t ctar0;
+ /**
+ * @brief DSPI PUSHR command for this session.
+ * @note Only CTAR0 can be referenced, the other CTARs are not
+ * initialized. The data part must be left to zero.
+ */
+ uint32_t pushr;
+} SPIConfig;
+
+/**
+ * @brief Structure representing an SPI driver.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+struct SPIDriver {
+ /**
+ * @brief Driver state.
+ */
+ volatile spistate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const SPIConfig *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+ /**
+ * @brief Waiting thread.
+ */
+ thread_reference_t thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+ /**
+ * @brief Mutex protecting the peripheral.
+ */
+ mutex_t mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+ SPI_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the DSPI registers block.
+ */
+ struct spc5_dspi *dspi;
+#if (SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_NONE) || defined(__DOXYGEN__)
+ /**
+ * @brief EDMA channel used for receive.
+ */
+ edma_channel_t rx_channel;
+#else /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE */
+ /**
+ * @brief Memory pointer for RX operations.
+ */
+ union {
+ void *rx_ptr;
+ uint8_t *rx_ptr8;
+ uint16_t *rx_ptr16;
+ };
+ /**
+ * @brief Remaining frames to be received.
+ */
+ size_t rx_cnt;
+#endif /* SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_NONE */
+#if (SPC5_SPI_DMA_MODE == SPC5_SPI_DMA_RX_AND_TX) || defined(__DOXYGEN__)
+ /**
+ * @brief EDMA channel used for data memory to memory copy.
+ */
+ edma_channel_t tx1_channel;
+ /**
+ * @brief EDMA channel used for transmit.
+ */
+ edma_channel_t tx2_channel;
+ /**
+ * @brief Command for the ongoing TX operation.
+ */
+ uint32_t tx_cmd;
+ /**
+ * @brief Last frame of a transmission sequence.
+ */
+ uint32_t tx_last;
+#else /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_RX_AND_TX */
+ /**
+ * @brief Memory pointer for TX operations.
+ */
+ union {
+ const void *tx_ptr;
+ const uint8_t *tx_ptr8;
+ const uint16_t *tx_ptr16;
+ };
+ /**
+ * @brief Remaining frames to be transmitted.
+ */
+ size_t tx_cnt;
+#endif /* SPC5_SPI_DMA_MODE != SPC5_SPI_DMA_RX_AND_TX */
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_SPI_USE_DSPI0 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if SPC5_SPI_USE_DSPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#if SPC5_SPI_USE_DSPI2 && !defined(__DOXYGEN__)
+extern SPIDriver SPID3;
+#endif
+
+#if SPC5_SPI_USE_DSPI3 && !defined(__DOXYGEN__)
+extern SPIDriver SPID4;
+#endif
+
+#if SPC5_SPI_USE_DSPI4 && !defined(__DOXYGEN__)
+extern SPIDriver SPID5;
+#endif
+
+#if SPC5_SPI_USE_DSPI5 && !defined(__DOXYGEN__)
+extern SPIDriver SPID6;
+#endif
+
+#if SPC5_SPI_USE_DSPI6 && !defined(__DOXYGEN__)
+extern SPIDriver SPID7;
+#endif
+
+#if SPC5_SPI_USE_DSPI7 && !defined(__DOXYGEN__)
+extern SPIDriver SPID8;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void spi_lld_init(void);
+ void spi_lld_start(SPIDriver *spip);
+ void spi_lld_stop(SPIDriver *spip);
+ void spi_lld_select(SPIDriver *spip);
+ void spi_lld_unselect(SPIDriver *spip);
+ void spi_lld_ignore(SPIDriver *spip, size_t n);
+ void spi_lld_exchange(SPIDriver *spip, size_t n,
+ const void *txbuf, void *rxbuf);
+ void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+ void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* HAL_SPI_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/DSPI_v1/spc5_dspi.h b/os/hal/ports/SPC5/LLD/DSPI_v1/spc5_dspi.h new file mode 100644 index 000000000..6f88f5edd --- /dev/null +++ b/os/hal/ports/SPC5/LLD/DSPI_v1/spc5_dspi.h @@ -0,0 +1,460 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file DSPI_v1/spc5_dspi.h
+ * @brief SPC5xx DSPI header file.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef _SPC5_DSPI_H_
+#define _SPC5_DSPI_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name MCR register definitions
+ * @{
+ */
+#define SPC5_MCR_MSTR (1U << 31)
+#define SPC5_MCR_CONT_SCKE (1U << 30)
+#define SPC5_MCR_DCONF_MASK (3U << 28)
+#define SPC5_MCR_FRZ (1U << 27)
+#define SPC5_MCR_MTFE (1U << 26)
+#define SPC5_MCR_PCSSE (1U << 25)
+#define SPC5_MCR_ROOE (1U << 24)
+#define SPC5_MCR_PCSIS7 (1U << 23)
+#define SPC5_MCR_PCSIS6 (1U << 22)
+#define SPC5_MCR_PCSIS5 (1U << 21)
+#define SPC5_MCR_PCSIS4 (1U << 20)
+#define SPC5_MCR_PCSIS3 (1U << 19)
+#define SPC5_MCR_PCSIS2 (1U << 18)
+#define SPC5_MCR_PCSIS1 (1U << 17)
+#define SPC5_MCR_PCSIS0 (1U << 16)
+#define SPC5_MCR_DOZE (1U << 15)
+#define SPC5_MCR_MDIS (1U << 14)
+#define SPC5_MCR_DIS_TXF (1U << 13)
+#define SPC5_MCR_DIS_RXF (1U << 12)
+#define SPC5_MCR_CLR_TXF (1U << 11)
+#define SPC5_MCR_CLR_RXF (1U << 10)
+#define SPC5_MCR_SMPL_PT_MASK (3U << 8)
+#define SPC5_MCR_SMPL_PT(n) ((n) << 8)
+#define SPC5_MCR_FCPCS (1U << 2)
+#define SPC5_MCR_PES (1U << 1)
+#define SPC5_MCR_HALT (1U << 0)
+/** @} */
+
+/**
+ * @name RSER register definitions
+ * @{
+ */
+#define SPC5_RSER_TCF_RE (1U << 31)
+#define SPC5_RSER_DSITCF_RE (1U << 29)
+#define SPC5_RSER_EOQF_RE (1U << 28)
+#define SPC5_RSER_TFUF_RE (1U << 27)
+#define SPC5_RSER_SPITCF_RE (1U << 26)
+#define SPC5_RSER_TFFF_RE (1U << 25)
+#define SPC5_RSER_TFFF_DIRS (1U << 24)
+#define SPC5_RSER_DPEF_RE (1U << 22)
+#define SPC5_RSER_SPEF_RE (1U << 21)
+#define SPC5_RSER_DDIF_RE (1U << 20)
+#define SPC5_RSER_RFOF_RE (1U << 19)
+#define SPC5_RSER_RFDF_RE (1U << 17)
+#define SPC5_RSER_RFDF_DIRS (1U << 16)
+/** @} */
+
+/**
+ * @name CTAR registers definitions
+ * @{
+ */
+#define SPC5_CTAR_DBR (1U << 31)
+#define SPC5_CTAR_FMSZ_MASK (15U << 27)
+#define SPC5_CTAR_FMSZ(n) (((n) - 1) << 27)
+#define SPC5_CTAR_CPOL (1U << 26)
+#define SPC5_CTAR_CPHA (1U << 25)
+#define SPC5_CTAR_LSBFE (1U << 24)
+#define SPC5_CTAR_PCSSCK_MASK (3U << 22)
+#define SPC5_CTAR_PCSSCK_PRE1 (0U << 22)
+#define SPC5_CTAR_PCSSCK_PRE3 (1U << 22)
+#define SPC5_CTAR_PCSSCK_PRE5 (2U << 22)
+#define SPC5_CTAR_PCSSCK_PRE7 (3U << 22)
+#define SPC5_CTAR_PASC_MASK (3U << 20)
+#define SPC5_CTAR_PASC_PRE1 (0U << 20)
+#define SPC5_CTAR_PASC_PRE3 (1U << 20)
+#define SPC5_CTAR_PASC_PRE5 (2U << 20)
+#define SPC5_CTAR_PASC_PRE7 (3U << 20)
+#define SPC5_CTAR_PDT_MASK (3U << 18)
+#define SPC5_CTAR_PDT_PRE1 (0U << 18)
+#define SPC5_CTAR_PDT_PRE3 (1U << 18)
+#define SPC5_CTAR_PDT_PRE5 (2U << 18)
+#define SPC5_CTAR_PDT_PRE7 (3U << 18)
+#define SPC5_CTAR_PBR_MASK (3U << 16)
+#define SPC5_CTAR_PBR_PRE2 (0U << 16)
+#define SPC5_CTAR_PBR_PRE3 (1U << 16)
+#define SPC5_CTAR_PBR_PRE5 (2U << 16)
+#define SPC5_CTAR_PBR_PRE7 (3U << 16)
+#define SPC5_CTAR_CSSCK_MASK (15U << 12)
+#define SPC5_CTAR_CSSCK_DIV2 (0U << 12)
+#define SPC5_CTAR_CSSCK_DIV4 (1U << 12)
+#define SPC5_CTAR_CSSCK_DIV8 (2U << 12)
+#define SPC5_CTAR_CSSCK_DIV16 (3U << 12)
+#define SPC5_CTAR_CSSCK_DIV32 (4U << 12)
+#define SPC5_CTAR_CSSCK_DIV64 (5U << 12)
+#define SPC5_CTAR_CSSCK_DIV128 (6U << 12)
+#define SPC5_CTAR_CSSCK_DIV256 (7U << 12)
+#define SPC5_CTAR_CSSCK_DIV512 (8U << 12)
+#define SPC5_CTAR_CSSCK_DIV1024 (9U << 12)
+#define SPC5_CTAR_CSSCK_DIV2048 (10U << 12)
+#define SPC5_CTAR_CSSCK_DIV4096 (11U << 12)
+#define SPC5_CTAR_CSSCK_DIV8192 (12U << 12)
+#define SPC5_CTAR_CSSCK_DIV16384 (13U << 12)
+#define SPC5_CTAR_CSSCK_DIV32768 (14U << 12)
+#define SPC5_CTAR_CSSCK_DIV65536 (15U << 12)
+#define SPC5_CTAR_ASC_MASK (15U << 8)
+#define SPC5_CTAR_ASC_DIV2 (0U << 8)
+#define SPC5_CTAR_ASC_DIV4 (1U << 8)
+#define SPC5_CTAR_ASC_DIV8 (2U << 8)
+#define SPC5_CTAR_ASC_DIV16 (3U << 8)
+#define SPC5_CTAR_ASC_DIV32 (4U << 8)
+#define SPC5_CTAR_ASC_DIV64 (5U << 8)
+#define SPC5_CTAR_ASC_DIV128 (6U << 8)
+#define SPC5_CTAR_ASC_DIV256 (7U << 8)
+#define SPC5_CTAR_ASC_DIV512 (8U << 8)
+#define SPC5_CTAR_ASC_DIV1024 (9U << 8)
+#define SPC5_CTAR_ASC_DIV2048 (10U << 8)
+#define SPC5_CTAR_ASC_DIV4096 (11U << 8)
+#define SPC5_CTAR_ASC_DIV8192 (12U << 8)
+#define SPC5_CTAR_ASC_DIV16384 (13U << 8)
+#define SPC5_CTAR_ASC_DIV32768 (14U << 8)
+#define SPC5_CTAR_ASC_DIV65536 (15U << 8)
+#define SPC5_CTAR_DT_MASK (15U << 4)
+#define SPC5_CTAR_DT_DIV2 (0U << 4)
+#define SPC5_CTAR_DT_DIV4 (1U << 4)
+#define SPC5_CTAR_DT_DIV8 (2U << 4)
+#define SPC5_CTAR_DT_DIV16 (3U << 4)
+#define SPC5_CTAR_DT_DIV32 (4U << 4)
+#define SPC5_CTAR_DT_DIV64 (5U << 4)
+#define SPC5_CTAR_DT_DIV128 (6U << 4)
+#define SPC5_CTAR_DT_DIV256 (7U << 4)
+#define SPC5_CTAR_DT_DIV512 (8U << 4)
+#define SPC5_CTAR_DT_DIV1024 (9U << 4)
+#define SPC5_CTAR_DT_DIV2048 (10U << 4)
+#define SPC5_CTAR_DT_DIV4096 (11U << 4)
+#define SPC5_CTAR_DT_DIV8192 (12U << 4)
+#define SPC5_CTAR_DT_DIV16384 (13U << 4)
+#define SPC5_CTAR_DT_DIV32768 (14U << 4)
+#define SPC5_CTAR_DT_DIV65536 (15U << 4)
+#define SPC5_CTAR_BR_MASK (15U << 0)
+#define SPC5_CTAR_BR_DIV2 (0U << 0)
+#define SPC5_CTAR_BR_DIV4 (1U << 0)
+#define SPC5_CTAR_BR_DIV6 (2U << 0)
+#define SPC5_CTAR_BR_DIV8 (3U << 0)
+#define SPC5_CTAR_BR_DIV16 (4U << 0)
+#define SPC5_CTAR_BR_DIV32 (5U << 0)
+#define SPC5_CTAR_BR_DIV64 (6U << 0)
+#define SPC5_CTAR_BR_DIV128 (7U << 0)
+#define SPC5_CTAR_BR_DIV256 (8U << 0)
+#define SPC5_CTAR_BR_DIV512 (9U << 0)
+#define SPC5_CTAR_BR_DIV1024 (10U << 0)
+#define SPC5_CTAR_BR_DIV2048 (11U << 0)
+#define SPC5_CTAR_BR_DIV4096 (12U << 0)
+#define SPC5_CTAR_BR_DIV8192 (13U << 0)
+#define SPC5_CTAR_BR_DIV16384 (14U << 0)
+#define SPC5_CTAR_BR_DIV32768 (15U << 0)
+/** @} */
+
+/**
+ * @name PUSHR register definitions
+ * @{
+ */
+#define SPC5_PUSHR_CONT (1U << 31)
+#define SPC5_PUSHR_CTAS_MASK (3U << 28)
+#define SPC5_PUSHR_CTAS(n) ((n) << 29)
+#define SPC5_PUSHR_EOQ (1U << 27)
+#define SPC5_PUSHR_CTCNT (1U << 26)
+#define SPC5_PUSHR_MASC (1U << 25)
+#define SPC5_PUSHR_MCSC (1U << 24)
+#define SPC5_PUSHR_PCS_MASK (255U << 16)
+#define SPC5_PUSHR_PCS(n) ((1U << (n)) << 16)
+#define SPC5_PUSHR_TXDATA_MASK (0xFFFFU << 0)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+struct spc5_dspi {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR :1;
+ vuint32_t CONT_SCKE :1;
+ vuint32_t DCONF :2;
+ vuint32_t FRZ :1;
+ vuint32_t MTFE :1;
+ vuint32_t PCSSE :1;
+ vuint32_t ROOE :1;
+ vuint32_t PCSIS7 :1;
+ vuint32_t PCSIS6 :1;
+ vuint32_t PCSIS5 :1;
+ vuint32_t PCSIS4 :1;
+ vuint32_t PCSIS3 :1;
+ vuint32_t PCSIS2 :1;
+ vuint32_t PCSIS1 :1;
+ vuint32_t PCSIS0 :1;
+ vuint32_t :1;
+ vuint32_t MDIS :1;
+ vuint32_t DIS_TXF :1;
+ vuint32_t DIS_RXF :1;
+ vuint32_t CLR_TXF :1;
+ vuint32_t CLR_RXF :1;
+ vuint32_t SMPL_PT :2;
+ vuint32_t :7;
+ vuint32_t HALT :1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ uint32_t dspi_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT :16;
+ vuint32_t :16;
+ } B;
+ } TCR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR :1;
+ vuint32_t FMSZ :4;
+ vuint32_t CPOL :1;
+ vuint32_t CPHA :1;
+ vuint32_t LSBFE :1;
+ vuint32_t PCSSCK :2;
+ vuint32_t PASC :2;
+ vuint32_t PDT :2;
+ vuint32_t PBR :2;
+ vuint32_t CSSCK :4;
+ vuint32_t ASC :4;
+ vuint32_t DT :4;
+ vuint32_t BR :4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF :1;
+ vuint32_t TXRXS :1;
+ vuint32_t :1;
+ vuint32_t EOQF :1;
+ vuint32_t TFUF :1;
+ vuint32_t :1;
+ vuint32_t TFFF :1;
+ vuint32_t :5;
+ vuint32_t RFOF :1;
+ vuint32_t :1;
+ vuint32_t RFDF :1;
+ vuint32_t :1;
+ vuint32_t TXCTR :4;
+ vuint32_t TXNXTPTR :4;
+ vuint32_t RXCTR :4;
+ vuint32_t POPNXTPTR :4;
+ } B;
+ } SR; /* Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE :1;
+ vuint32_t :2;
+ vuint32_t EOQFRE :1;
+ vuint32_t TFUFRE :1;
+ vuint32_t :1;
+ vuint32_t TFFFRE :1;
+ vuint32_t TFFFDIRS :1;
+ vuint32_t :4;
+ vuint32_t RFOFRE :1;
+ vuint32_t :1;
+ vuint32_t RFDFRE :1;
+ vuint32_t RFDFDIRS :1;
+ vuint32_t :16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT :1;
+ vuint32_t CTAS :3;
+ vuint32_t EOQ :1;
+ vuint32_t CTCNT :1;
+ vuint32_t :2;
+ vuint32_t PCS7 :1;
+ vuint32_t PCS6 :1;
+ vuint32_t PCS5 :1;
+ vuint32_t PCS4 :1;
+ vuint32_t PCS3 :1;
+ vuint32_t PCS2 :1;
+ vuint32_t PCS1 :1;
+ vuint32_t PCS0 :1;
+ vuint32_t TXDATA :16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RXDATA :16;
+ } B;
+ } POPR; /* POP RX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD :16;
+ vuint32_t TXDATA :16;
+ } B;
+ } TXFR[5]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_txf[11];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RXDATA :16;
+ } B;
+ } RXFR[5]; /* Receive FIFO Registers */
+
+ vuint32_t DSPI_reserved_rxf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE :1;
+ vuint32_t :1;
+ vuint32_t MTOCNT :6;
+ vuint32_t :4;
+ vuint32_t TXSS :1;
+ vuint32_t TPOL :1;
+ vuint32_t TRRE :1;
+ vuint32_t CID :1;
+ vuint32_t DCONT :1;
+ vuint32_t DSICTAS :3;
+ vuint32_t :6;
+ vuint32_t DPCS5 :1;
+ vuint32_t DPCS4 :1;
+ vuint32_t DPCS3 :1;
+ vuint32_t DPCS2 :1;
+ vuint32_t DPCS1 :1;
+ vuint32_t DPCS0 :1;
+ } B;
+ } DSICR; /* DSI Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SER_DATA :16;
+ } B;
+ } SDR; /* DSI Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t ASER_DATA :16;
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t COMP_DATA :16;
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t DESER_DATA :16;
+ } B;
+ } DDR; /* DSI deserialization Data Register */
+
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name DSPI units references
+ * @{
+ */
+#if SPC5_HAS_DSPI0 || defined(__DOXYGEN__)
+#define SPC5_DSPI0 (*(struct spc5_dspi *)0xFFF90000U)
+#endif
+
+#if SPC5_HAS_DSPI1 || defined(__DOXYGEN__)
+#define SPC5_DSPI1 (*(struct spc5_dspi *)0xFFF94000U)
+#endif
+
+#if SPC5_HAS_DSPI2 || defined(__DOXYGEN__)
+#define SPC5_DSPI2 (*(struct spc5_dspi *)0xFFF98000U)
+#endif
+
+#if SPC5_HAS_DSPI3 || defined(__DOXYGEN__)
+#define SPC5_DSPI3 (*(struct spc5_dspi *)0xFFF9C000U)
+#endif
+
+#if SPC5_HAS_DSPI4 || defined(__DOXYGEN__)
+#define SPC5_DSPI4 (*(struct spc5_dspi *)0xFFFA0000U)
+#endif
+
+#if SPC5_HAS_DSPI5 || defined(__DOXYGEN__)
+#define SPC5_DSPI5 (*(struct spc5_dspi *)0xFFFA4000U)
+#endif
+
+#if SPC5_HAS_DSPI6 || defined(__DOXYGEN__)
+#define SPC5_DSPI6 (*(struct spc5_dspi *)0xFFFA8000U)
+#endif
+
+#if SPC5_HAS_DSPI7 || defined(__DOXYGEN__)
+#define SPC5_DSPI7 (*(struct spc5_dspi *)0xFFFAC000U)
+#endif
+/** @} */
+
+#endif /* _SPC5_DSPI_H_ */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c new file mode 100644 index 000000000..6a50b1d26 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c @@ -0,0 +1,1397 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/spc5_edma.c
+ * @brief EDMA helper driver code.
+ *
+ * @addtogroup SPC5xx_EDMA
+ * @{
+ */
+
+#include "hal.h"
+
+#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES};
+#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
+static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES};
+#endif
+#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
+static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES};
+static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES};
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Configurations for the various EDMA channels.
+ */
+static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS];
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief EDMA (channels 0..31) error interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector10) {
+ edma_channel_t channel;
+ uint32_t erl, esr = SPC5_EDMA.ESR.R;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Scanning for errors.*/
+ channel = 0;
+ while (((erl = SPC5_EDMA.ERL.R) != 0) &&
+ (channel < (SPC5_EDMA_NCHANNELS > 32 ? 32 : SPC5_EDMA_NCHANNELS))) {
+ if ((erl & (1U << channel)) != 0) {
+ /* Error flag cleared.*/
+ SPC5_EDMA.CER.R = channel;
+
+ /* If the channel is not associated then the error is simply discarded
+ else the error callback is invoked.*/
+ if ((channels[channel] != NULL) &&
+ (channels[channel]->dma_error_func != NULL))
+ channels[channel]->dma_error_func(channel,
+ channels[channel]->dma_param,
+ esr);
+ }
+ channel++;
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 0 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector11) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[0] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 0;
+ channels[0]->dma_func(0, channels[0]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 1 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector12) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[1] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 1;
+ channels[1]->dma_func(1, channels[1]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 2 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector13) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[2] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 2;
+ channels[2]->dma_func(2, channels[2]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 3 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector14) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[3] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 3;
+ channels[3]->dma_func(3, channels[3]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 4 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector15) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[4] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 4;
+ channels[4]->dma_func(4, channels[4]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 5 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector16) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[5] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 5;
+ channels[5]->dma_func(5, channels[5]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 6 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector17) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[6] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 6;
+ channels[6]->dma_func(6, channels[6]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 7 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector18) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[7] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 7;
+ channels[7]->dma_func(7, channels[7]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 8 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector19) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[8] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 8;
+ channels[8]->dma_func(8, channels[8]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 9 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector20) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[9] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 9;
+ channels[9]->dma_func(9, channels[9]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 10 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector21) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[10] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 10;
+ channels[10]->dma_func(10, channels[10]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 11 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector22) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[11] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 11;
+ channels[11]->dma_func(11, channels[11]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 12 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector23) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[12] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 12;
+ channels[12]->dma_func(12, channels[12]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 13 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector24) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[13] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 13;
+ channels[13]->dma_func(13, channels[13]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 14 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector25) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[14] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 14;
+ channels[14]->dma_func(14, channels[14]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 15 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector26) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[15] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 15;
+ channels[15]->dma_func(15, channels[15]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)
+/**
+ * @brief EDMA channel 16 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector27) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[16] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 16;
+ channels[16]->dma_func(16, channels[16]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 17 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector28) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[17] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 17;
+ channels[17]->dma_func(17, channels[17]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 18 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector29) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[18] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 18;
+ channels[18]->dma_func(18, channels[18]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 19 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector30) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[19] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 19;
+ channels[19]->dma_func(19, channels[19]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 20 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector31) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[20] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 20;
+ channels[20]->dma_func(20, channels[20]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 21 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector32) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[21] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 21;
+ channels[21]->dma_func(21, channels[21]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 22 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector33) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[22] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 22;
+ channels[22]->dma_func(22, channels[22]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 23 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector34) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[23] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 23;
+ channels[23]->dma_func(23, channels[23]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 24 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector35) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[24] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 24;
+ channels[24]->dma_func(24, channels[24]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 25 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector36) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[25] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 25;
+ channels[25]->dma_func(25, channels[25]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 26 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector37) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[26] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 26;
+ channels[26]->dma_func(26, channels[26]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 27 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector38) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[27] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 27;
+ channels[27]->dma_func(27, channels[27]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 28 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector39) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[28] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 28;
+ channels[28]->dma_func(28, channels[28]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 29 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector40) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[29] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 29;
+ channels[29]->dma_func(29, channels[29]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 30 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector41) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[30] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 30;
+ channels[30]->dma_func(30, channels[30]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 31 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector42) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[31] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 31;
+ channels[31]->dma_func(31, channels[31]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)
+/**
+ * @brief EDMA (channels 32..64) error interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector210) {
+ edma_channel_t channel;
+ uint32_t erh, esr = SPC5_EDMA.ESR.R;
+
+ OSAL_IRQ_PROLOGUE();
+
+ /* Scanning for errors.*/
+ channel = 32;
+ while (((erh = SPC5_EDMA.ERH.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {
+
+ if ((erh & (1U << (channel - 32))) != 0) {
+ /* Error flag cleared.*/
+ SPC5_EDMA.CER.R = channel;
+
+ /* If the channel is not associated then the error is simply discarded
+ else the error callback is invoked.*/
+ if ((channels[channel] != NULL) &&
+ (channels[channel]->dma_error_func != NULL))
+ channels[channel]->dma_error_func(channel,
+ channels[channel]->dma_param,
+ esr);
+ channel++;
+ }
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 32 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector211) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[32] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 32;
+ channels[32]->dma_func(32, channels[32]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 33 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector212) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[33] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 33;
+ channels[33]->dma_func(33, channels[33]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 34 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector213) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[34] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 34;
+ channels[34]->dma_func(34, channels[34]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 35 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector214) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[35] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 35;
+ channels[35]->dma_func(35, channels[35]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 36 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector215) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[36] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 36;
+ channels[36]->dma_func(36, channels[36]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 37 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector216) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[37] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 37;
+ channels[37]->dma_func(37, channels[37]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 38 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector217) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[38] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 38;
+ channels[38]->dma_func(38, channels[38]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 39 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector218) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[39] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 39;
+ channels[39]->dma_func(39, channels[39]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 40 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector219) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[40] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 40;
+ channels[40]->dma_func(40, channels[40]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 41 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector220) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[41] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 41;
+ channels[41]->dma_func(41, channels[41]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 42 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector221) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[42] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 42;
+ channels[42]->dma_func(42, channels[42]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 43 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector222) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[43] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 43;
+ channels[43]->dma_func(43, channels[43]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 44 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector223) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[44] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 44;
+ channels[44]->dma_func(44, channels[44]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 45 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector224) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[45] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 45;
+ channels[45]->dma_func(45, channels[45]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 46 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector225) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[46] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 46;
+ channels[46]->dma_func(46, channels[46]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 47 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector226) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[47] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 47;
+ channels[47]->dma_func(47, channels[47]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 48 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector227) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[48] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 48;
+ channels[48]->dma_func(48, channels[48]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 49 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector228) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[49] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 49;
+ channels[49]->dma_func(49, channels[49]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 50 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector229) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[50] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 50;
+ channels[50]->dma_func(50, channels[50]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 51 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector230) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[51] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 51;
+ channels[51]->dma_func(51, channels[51]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 52 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector231) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[52] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 52;
+ channels[52]->dma_func(52, channels[52]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 53 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector232) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[53] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 53;
+ channels[53]->dma_func(53, channels[53]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 54 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector233) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[54] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 54;
+ channels[54]->dma_func(54, channels[54]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 55 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector234) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[55] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 55;
+ channels[55]->dma_func(55, channels[55]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 56 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector235) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[56] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 56;
+ channels[56]->dma_func(56, channels[56]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 57 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector236) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[57] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 57;
+ channels[57]->dma_func(57, channels[57]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 58 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector237) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[58] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 58;
+ channels[58]->dma_func(58, channels[58]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 59 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector238) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[59] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 59;
+ channels[59]->dma_func(59, channels[59]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 60 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector239) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[60] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 60;
+ channels[60]->dma_func(60, channels[60]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 61 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector240) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[61] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 61;
+ channels[61]->dma_func(61, channels[61]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 62 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector241) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[62] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 62;
+ channels[62]->dma_func(62, channels[62]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief EDMA channel 63 interrupt.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector242) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (channels[63] == NULL) {
+ SPC5_EDMA_ERROR_HANDLER();
+ }
+ SPC5_EDMA.CIRQR.R = 63;
+ channels[63]->dma_func(63, channels[63]->dma_param);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif /* SPC5_EDMA_NCHANNELS > 32 */
+#endif /* SPC5_EDMA_NCHANNELS > 16 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief EDMA driver initialization.
+ *
+ * @special
+ */
+void edmaInit(void) {
+ unsigned i;
+
+ SPC5_EDMA.CR.R = SPC5_EDMA_CR_SETTING;
+ SPC5_EDMA.ERQRL.R = 0x00000000;
+ SPC5_EDMA.EEIRL.R = 0x00000000;
+ SPC5_EDMA.IRQRL.R = 0xFFFFFFFF;
+ SPC5_EDMA.ERL.R = 0xFFFFFFFF;
+#if SPC5_EDMA_NCHANNELS > 32
+ SPC5_EDMA.ERQRH.R = 0x00000000;
+ SPC5_EDMA.EEIRH.R = 0x00000000;
+ SPC5_EDMA.IRQRH.R = 0xFFFFFFFF;
+ SPC5_EDMA.ERH.R = 0xFFFFFFFF;
+#endif
+ /* Initializing all the channels with a different priority withing the
+ channels group.*/
+ for (i = 0; i < 16; i++) {
+ SPC5_EDMA.CPR[i].R = g0[i];
+#if SPC5_EDMA_NCHANNELS > 16
+ SPC5_EDMA.CPR[i + 16].R = g1[i];
+#endif
+#if SPC5_EDMA_NCHANNELS > 32
+ SPC5_EDMA.CPR[i + 32].R = g2[i];
+ SPC5_EDMA.CPR[i + 48].R = g3[i];
+#endif
+ }
+
+ /* Error interrupt source.*/
+ INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;
+
+#if defined(SPC5_EDMA_MUX_PCTL)
+ /* DMA MUX PCTL setup, only if required.*/
+ halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL);
+#endif
+}
+
+/**
+ * @brief EDMA channel allocation.
+ *
+ * @param[in] ccfg channel configuration
+ * @return The channel number.
+ * @retval EDMA_ERROR if the channel cannot be allocated.
+ *
+ * @special
+ */
+edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
+
+ osalDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16));
+
+ /* If the channel is already taken then an error is returned.*/
+ if (channels[ccfg->dma_channel] != NULL)
+ return EDMA_ERROR; /* Already taken. */
+
+#if SPC5_EDMA_HAS_MUX
+ /* Programming the MUX.*/
+ SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 |
+ ccfg->dma_periph);
+#endif /* !SPC5_EDMA_HAS_MUX */
+
+ /* Associating the configuration to the channel.*/
+ channels[ccfg->dma_channel] = ccfg;
+
+ /* If an error callback is defined then the error interrupt source is
+ enabled for the channel.*/
+ if (ccfg->dma_error_func != NULL)
+ SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel;
+
+ /* Setting up IRQ priority for the selected channel.*/
+ INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio;
+
+ return ccfg->dma_channel;
+}
+
+/**
+ * @brief EDMA channel release.
+ *
+ * @param[in] channel the channel number
+ *
+ * @special
+ */
+void edmaChannelRelease(edma_channel_t channel) {
+
+ osalDbgCheck((channel >= 0) && (channel < SPC5_EDMA_NCHANNELS));
+ osalDbgAssert(channels[channel] != NULL, "not allocated");
+
+ /* Enforcing a stop.*/
+ edmaChannelStop(channel);
+
+#if SPC5_EDMA_HAS_MUX
+ /* Disabling the MUX slot.*/
+ SPC5_DMAMUX.CHCONFIG[channel].R = 0;
+#endif
+
+ /* Clearing ISR sources for the channel.*/
+ SPC5_EDMA.CIRQR.R = channel;
+ SPC5_EDMA.CEEIR.R = channel;
+ SPC5_EDMA.CER.R = channel;
+
+ /* The channels is flagged as available.*/
+ channels[channel] = NULL;
+}
+
+#endif /* SPC5_HAS_EDMA */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h new file mode 100644 index 000000000..c621baea3 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.h @@ -0,0 +1,1005 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/spc5_edma.h
+ * @brief EDMA helper driver header.
+ *
+ * @addtogroup SPC5xx_EDMA
+ * @{
+ */
+
+#ifndef _SPC5_EDMA_H_
+#define _SPC5_EDMA_H_
+
+#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief EDMA channel allocation error.
+ */
+#define EDMA_ERROR -1
+
+/**
+ * @name EDMA CR register definitions
+ * @{
+ */
+#define EDMA_CR_CX (1U << 17)
+#define EDMA_CR_ECX (1U << 16)
+#define EDMA_CR_GRP3PRI_MASK (3U << 14)
+#define EDMA_CR_GRP3PRI(n) ((n) << 14)
+#define EDMA_CR_GRP2PRI_MASK (3U << 12)
+#define EDMA_CR_GRP2PRI(n) ((n) << 12)
+#define EDMA_CR_GRP1PRI_MASK (3U << 10)
+#define EDMA_CR_GRP1PRI(n) ((n) << 10)
+#define EDMA_CR_GRP0PRI_MASK (3U << 8)
+#define EDMA_CR_GRP0PRI(n) ((n) << 8)
+#define EDMA_CR_EMLM (1U << 7)
+#define EDMA_CR_CLM (1U << 6)
+#define EDMA_CR_HALT (1U << 5)
+#define EDMA_CR_HOE (1U << 4)
+#define EDMA_CR_ERGA (1U << 3)
+#define EDMA_CR_ERCA (1U << 2)
+#define EDMA_CR_EDBG (1U << 1)
+#define EDMA_CR_EBW (1U << 0)
+/** @} */
+
+/**
+ * @name EDMA mode constants
+ * @{
+ */
+#define EDMA_TCD_MODE_START (1U << 0)
+#define EDMA_TCD_MODE_INT_END (1U << 1)
+#define EDMA_TCD_MODE_INT_HALF (1U << 2)
+#define EDMA_TCD_MODE_DREQ (1U << 3)
+#define EDMA_TCD_MODE_SG (1U << 4)
+#define EDMA_TCD_MODE_MELINK (1U << 5)
+#define EDMA_TCD_MODE_ACTIVE (1U << 6)
+#define EDMA_TCD_MODE_DONE (1U << 7)
+#define EDMA_TCD_MODE_MLINKCH_MASK (63U << 8)
+#define EDMA_TCD_MODE_MLINKCH(n) ((uint32_t)(n) << 8)
+#define EDMA_TCD_MODE_BWC_MASK (3U << 14)
+#define EDMA_TCD_MODE_BWC(n) ((uint32_t)(n) << 14)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default EDMA CR register initialization.
+ */
+#if !defined(SPC5_EDMA_CR_SETTING) || defined(__DOXYGEN__)
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#endif
+
+/**
+ * @brief Static priorities for channels group 0.
+ */
+#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP0_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief Static priorities for channels group 1.
+ */
+#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP1_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief Static priorities for channels group 2.
+ */
+#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP2_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief Static priorities for channels group 3.
+ */
+#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__)
+#define SPC5_EDMA_GROUP3_PRIORITIES \
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+#endif
+
+/**
+ * @brief EDMA error handler IRQ priority.
+ */
+#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__)
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#endif
+
+/**
+ * @brief EDMA peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_EDMA_MUX_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief EDMA critical error handler, must not return.
+ */
+#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("EDMA failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of and eDMA channel number.
+ */
+typedef int32_t edma_channel_t;
+
+/**
+ * @brief Type of an eDMA TCD.
+ */
+typedef struct {
+ union {
+ uint32_t word[8];
+ };
+} edma_tcd_t;
+
+/**
+ * @brief Type of an eDMA peripheral.
+ */
+typedef struct {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :14;
+ vuint32_t CX :1;
+ vuint32_t ECX :1;
+ vuint32_t GRP3PRI :2;
+ vuint32_t GRP2PRI :2;
+ vuint32_t GRP1PRI :2;
+ vuint32_t GRP0PRI :2;
+ vuint32_t EMLM :1;
+ vuint32_t CLM :1;
+ vuint32_t HALT :1;
+ vuint32_t HOE :1;
+ vuint32_t ERGA :1;
+ vuint32_t ERCA :1;
+ vuint32_t EDBG :1;
+ vuint32_t :1;
+ } B;
+ } CR; /* DMA Control Register @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD :1;
+ vuint32_t :14;
+ vuint32_t ECX :1;
+ vuint32_t GPE :1;
+ vuint32_t CPE :1;
+ vuint32_t ERRCHN :6;
+ vuint32_t SAE :1;
+ vuint32_t SOE :1;
+ vuint32_t DAE :1;
+ vuint32_t DOE :1;
+ vuint32_t NCE :1;
+ vuint32_t SGE :1;
+ vuint32_t SBE :1;
+ vuint32_t DBE :1;
+ } B;
+ } ESR; /* Error Status Register @baseaddress + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ63 :1;
+ vuint32_t ERQ62 :1;
+ vuint32_t ERQ61 :1;
+ vuint32_t ERQ60 :1;
+ vuint32_t ERQ59 :1;
+ vuint32_t ERQ58 :1;
+ vuint32_t ERQ57 :1;
+ vuint32_t ERQ56 :1;
+ vuint32_t ERQ55 :1;
+ vuint32_t ERQ54 :1;
+ vuint32_t ERQ53 :1;
+ vuint32_t ERQ52 :1;
+ vuint32_t ERQ51 :1;
+ vuint32_t ERQ50 :1;
+ vuint32_t ERQ49 :1;
+ vuint32_t ERQ48 :1;
+ vuint32_t ERQ47 :1;
+ vuint32_t ERQ46 :1;
+ vuint32_t ERQ45 :1;
+ vuint32_t ERQ44 :1;
+ vuint32_t ERQ43 :1;
+ vuint32_t ERQ42 :1;
+ vuint32_t ERQ41 :1;
+ vuint32_t ERQ40 :1;
+ vuint32_t ERQ39 :1;
+ vuint32_t ERQ38 :1;
+ vuint32_t ERQ37 :1;
+ vuint32_t ERQ36 :1;
+ vuint32_t ERQ35 :1;
+ vuint32_t ERQ34 :1;
+ vuint32_t ERQ33 :1;
+ vuint32_t ERQ32 :1;
+ } B;
+ } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ31 :1;
+ vuint32_t ERQ30 :1;
+ vuint32_t ERQ29 :1;
+ vuint32_t ERQ28 :1;
+ vuint32_t ERQ27 :1;
+ vuint32_t ERQ26 :1;
+ vuint32_t ERQ25 :1;
+ vuint32_t ERQ24 :1;
+ vuint32_t ERQ23 :1;
+ vuint32_t ERQ22 :1;
+ vuint32_t ERQ21 :1;
+ vuint32_t ERQ20 :1;
+ vuint32_t ERQ19 :1;
+ vuint32_t ERQ18 :1;
+ vuint32_t ERQ17 :1;
+ vuint32_t ERQ16 :1;
+ vuint32_t ERQ15 :1;
+ vuint32_t ERQ14 :1;
+ vuint32_t ERQ13 :1;
+ vuint32_t ERQ12 :1;
+ vuint32_t ERQ11 :1;
+ vuint32_t ERQ10 :1;
+ vuint32_t ERQ09 :1;
+ vuint32_t ERQ08 :1;
+ vuint32_t ERQ07 :1;
+ vuint32_t ERQ06 :1;
+ vuint32_t ERQ05 :1;
+ vuint32_t ERQ04 :1;
+ vuint32_t ERQ03 :1;
+ vuint32_t ERQ02 :1;
+ vuint32_t ERQ01 :1;
+ vuint32_t ERQ00 :1;
+ } B;
+ } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/
+
+ union {
+ vuint32_t R;
+ struct {
+
+ vuint32_t EEI63 :1;
+ vuint32_t EEI62 :1;
+ vuint32_t EEI61 :1;
+ vuint32_t EEI60 :1;
+ vuint32_t EEI59 :1;
+ vuint32_t EEI58 :1;
+ vuint32_t EEI57 :1;
+ vuint32_t EEI56 :1;
+ vuint32_t EEI55 :1;
+ vuint32_t EEI54 :1;
+ vuint32_t EEI53 :1;
+ vuint32_t EEI52 :1;
+ vuint32_t EEI51 :1;
+ vuint32_t EEI50 :1;
+ vuint32_t EEI49 :1;
+ vuint32_t EEI48 :1;
+ vuint32_t EEI47 :1;
+ vuint32_t EEI46 :1;
+ vuint32_t EEI45 :1;
+ vuint32_t EEI44 :1;
+ vuint32_t EEI43 :1;
+ vuint32_t EEI42 :1;
+ vuint32_t EEI41 :1;
+ vuint32_t EEI40 :1;
+ vuint32_t EEI39 :1;
+ vuint32_t EEI38 :1;
+ vuint32_t EEI37 :1;
+ vuint32_t EEI36 :1;
+ vuint32_t EEI35 :1;
+ vuint32_t EEI34 :1;
+ vuint32_t EEI33 :1;
+ vuint32_t EEI32 :1;
+ } B;
+ } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EEI31 :1;
+ vuint32_t EEI30 :1;
+ vuint32_t EEI29 :1;
+ vuint32_t EEI28 :1;
+ vuint32_t EEI27 :1;
+ vuint32_t EEI26 :1;
+ vuint32_t EEI25 :1;
+ vuint32_t EEI24 :1;
+ vuint32_t EEI23 :1;
+ vuint32_t EEI22 :1;
+ vuint32_t EEI21 :1;
+ vuint32_t EEI20 :1;
+ vuint32_t EEI19 :1;
+ vuint32_t EEI18 :1;
+ vuint32_t EEI17 :1;
+ vuint32_t EEI16 :1;
+ vuint32_t EEI15 :1;
+ vuint32_t EEI14 :1;
+ vuint32_t EEI13 :1;
+ vuint32_t EEI12 :1;
+ vuint32_t EEI11 :1;
+ vuint32_t EEI10 :1;
+ vuint32_t EEI09 :1;
+ vuint32_t EEI08 :1;
+ vuint32_t EEI07 :1;
+ vuint32_t EEI06 :1;
+ vuint32_t EEI05 :1;
+ vuint32_t EEI04 :1;
+ vuint32_t EEI03 :1;
+ vuint32_t EEI02 :1;
+ vuint32_t EEI01 :1;
+ vuint32_t EEI00 :1;
+ } B;
+ } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t SERQ :7;
+ } B;
+ } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CERQ :7;
+ } B;
+ } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t SEEI :7;
+ } B;
+ } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CEEI :7;
+ } B;
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CINT :7;
+ } B;
+ } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CERR :7;
+ } B;
+ } CER; /* DMA Clear error Register @baseaddress + 0x1D */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t SSB :7;
+ } B;
+ } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP :1;
+ vuint8_t CDSB :7;
+ } B;
+ } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT63 :1;
+ vuint32_t INT62 :1;
+ vuint32_t INT61 :1;
+ vuint32_t INT60 :1;
+ vuint32_t INT59 :1;
+ vuint32_t INT58 :1;
+ vuint32_t INT57 :1;
+ vuint32_t INT56 :1;
+ vuint32_t INT55 :1;
+ vuint32_t INT54 :1;
+ vuint32_t INT53 :1;
+ vuint32_t INT52 :1;
+ vuint32_t INT51 :1;
+ vuint32_t INT50 :1;
+ vuint32_t INT49 :1;
+ vuint32_t INT48 :1;
+ vuint32_t INT47 :1;
+ vuint32_t INT46 :1;
+ vuint32_t INT45 :1;
+ vuint32_t INT44 :1;
+ vuint32_t INT43 :1;
+ vuint32_t INT42 :1;
+ vuint32_t INT41 :1;
+ vuint32_t INT40 :1;
+ vuint32_t INT39 :1;
+ vuint32_t INT38 :1;
+ vuint32_t INT37 :1;
+ vuint32_t INT36 :1;
+ vuint32_t INT35 :1;
+ vuint32_t INT34 :1;
+ vuint32_t INT33 :1;
+ vuint32_t INT32 :1;
+ } B;
+ } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT31 :1;
+ vuint32_t INT30 :1;
+ vuint32_t INT29 :1;
+ vuint32_t INT28 :1;
+ vuint32_t INT27 :1;
+ vuint32_t INT26 :1;
+ vuint32_t INT25 :1;
+ vuint32_t INT24 :1;
+ vuint32_t INT23 :1;
+ vuint32_t INT22 :1;
+ vuint32_t INT21 :1;
+ vuint32_t INT20 :1;
+ vuint32_t INT19 :1;
+ vuint32_t INT18 :1;
+ vuint32_t INT17 :1;
+ vuint32_t INT16 :1;
+ vuint32_t INT15 :1;
+ vuint32_t INT14 :1;
+ vuint32_t INT13 :1;
+ vuint32_t INT12 :1;
+ vuint32_t INT11 :1;
+ vuint32_t INT10 :1;
+ vuint32_t INT09 :1;
+ vuint32_t INT08 :1;
+ vuint32_t INT07 :1;
+ vuint32_t INT06 :1;
+ vuint32_t INT05 :1;
+ vuint32_t INT04 :1;
+ vuint32_t INT03 :1;
+ vuint32_t INT02 :1;
+ vuint32_t INT01 :1;
+ vuint32_t INT00 :1;
+ } B;
+ } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR63 :1;
+ vuint32_t ERR62 :1;
+ vuint32_t ERR61 :1;
+ vuint32_t ERR60 :1;
+ vuint32_t ERR59 :1;
+ vuint32_t ERR58 :1;
+ vuint32_t ERR57 :1;
+ vuint32_t ERR56 :1;
+ vuint32_t ERR55 :1;
+ vuint32_t ERR54 :1;
+ vuint32_t ERR53 :1;
+ vuint32_t ERR52 :1;
+ vuint32_t ERR51 :1;
+ vuint32_t ERR50 :1;
+ vuint32_t ERR49 :1;
+ vuint32_t ERR48 :1;
+ vuint32_t ERR47 :1;
+ vuint32_t ERR46 :1;
+ vuint32_t ERR45 :1;
+ vuint32_t ERR44 :1;
+ vuint32_t ERR43 :1;
+ vuint32_t ERR42 :1;
+ vuint32_t ERR41 :1;
+ vuint32_t ERR40 :1;
+ vuint32_t ERR39 :1;
+ vuint32_t ERR38 :1;
+ vuint32_t ERR37 :1;
+ vuint32_t ERR36 :1;
+ vuint32_t ERR35 :1;
+ vuint32_t ERR34 :1;
+ vuint32_t ERR33 :1;
+ vuint32_t ERR32 :1;
+ } B;
+ } ERH; /* DMA Error High @baseaddress + 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR31 :1;
+ vuint32_t ERR30 :1;
+ vuint32_t ERR29 :1;
+ vuint32_t ERR28 :1;
+ vuint32_t ERR27 :1;
+ vuint32_t ERR26 :1;
+ vuint32_t ERR25 :1;
+ vuint32_t ERR24 :1;
+ vuint32_t ERR23 :1;
+ vuint32_t ERR22 :1;
+ vuint32_t ERR21 :1;
+ vuint32_t ERR20 :1;
+ vuint32_t ERR19 :1;
+ vuint32_t ERR18 :1;
+ vuint32_t ERR17 :1;
+ vuint32_t ERR16 :1;
+ vuint32_t ERR15 :1;
+ vuint32_t ERR14 :1;
+ vuint32_t ERR13 :1;
+ vuint32_t ERR12 :1;
+ vuint32_t ERR11 :1;
+ vuint32_t ERR10 :1;
+ vuint32_t ERR09 :1;
+ vuint32_t ERR08 :1;
+ vuint32_t ERR07 :1;
+ vuint32_t ERR06 :1;
+ vuint32_t ERR05 :1;
+ vuint32_t ERR04 :1;
+ vuint32_t ERR03 :1;
+ vuint32_t ERR02 :1;
+ vuint32_t ERR01 :1;
+ vuint32_t ERR00 :1;
+ } B;
+ } ERL; /* DMA Error Low @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HRS63 :1;
+ vuint32_t HRS62 :1;
+ vuint32_t HRS61 :1;
+ vuint32_t HRS60 :1;
+ vuint32_t HRS59 :1;
+ vuint32_t HRS58 :1;
+ vuint32_t HRS57 :1;
+ vuint32_t HRS56 :1;
+ vuint32_t HRS55 :1;
+ vuint32_t HRS54 :1;
+ vuint32_t HRS53 :1;
+ vuint32_t HRS52 :1;
+ vuint32_t HRS51 :1;
+ vuint32_t HRS50 :1;
+ vuint32_t HRS49 :1;
+ vuint32_t HRS48 :1;
+ vuint32_t HRS47 :1;
+ vuint32_t HRS46 :1;
+ vuint32_t HRS45 :1;
+ vuint32_t HRS44 :1;
+ vuint32_t HRS43 :1;
+ vuint32_t HRS42 :1;
+ vuint32_t HRS41 :1;
+ vuint32_t HRS40 :1;
+ vuint32_t HRS39 :1;
+ vuint32_t HRS38 :1;
+ vuint32_t HRS37 :1;
+ vuint32_t HRS36 :1;
+ vuint32_t HRS35 :1;
+ vuint32_t HRS34 :1;
+ vuint32_t HRS33 :1;
+ vuint32_t HRS32 :1;
+ } B;
+ } HRSH; /* hardware request status high @baseaddress + 0x30 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HRS31 :1;
+ vuint32_t HRS30 :1;
+ vuint32_t HRS29 :1;
+ vuint32_t HRS28 :1;
+ vuint32_t HRS27 :1;
+ vuint32_t HRS26 :1;
+ vuint32_t HRS25 :1;
+ vuint32_t HRS24 :1;
+ vuint32_t HRS23 :1;
+ vuint32_t HRS22 :1;
+ vuint32_t HRS21 :1;
+ vuint32_t HRS20 :1;
+ vuint32_t HRS19 :1;
+ vuint32_t HRS18 :1;
+ vuint32_t HRS17 :1;
+ vuint32_t HRS16 :1;
+ vuint32_t HRS15 :1;
+ vuint32_t HRS14 :1;
+ vuint32_t HRS13 :1;
+ vuint32_t HRS12 :1;
+ vuint32_t HRS11 :1;
+ vuint32_t HRS10 :1;
+ vuint32_t HRS09 :1;
+ vuint32_t HRS08 :1;
+ vuint32_t HRS07 :1;
+ vuint32_t HRS06 :1;
+ vuint32_t HRS05 :1;
+ vuint32_t HRS04 :1;
+ vuint32_t HRS03 :1;
+ vuint32_t HRS02 :1;
+ vuint32_t HRS01 :1;
+ vuint32_t HRS00 :1;
+ } B;
+ } HRSL; /* hardware request status low @baseaddress + 0x34 */
+
+ uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP :1;
+ vuint8_t DPA :1;
+ vuint8_t GRPPRI :2;
+ vuint8_t CHPRI :4;
+ } B;
+ } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */
+
+ uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */
+
+ edma_tcd_t TCD[64];
+} edma_t;
+
+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
+/**
+ * @brief Type of a DMA-MUX peripheral.
+ */
+typedef struct {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[SPC5_EDMA_NCHANNELS];
+} dma_mux_t;
+#endif /* SPC5_EDMA_HAS_MUX */
+
+/**
+ * @brief DMA callback type.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ */
+typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
+
+/**
+ * @brief DMA error callback type.
+ *
+ * @param[in] channel the channel number
+ * @param[in] p parameter for the registered function
+ * @param[in] esr content of the ESR register
+ */
+typedef void (*edma_error_callback_t)(edma_channel_t channel,
+ void *p,
+ uint32_t esr);
+
+/**
+ * @brief Type of an EDMA channel configuration structure.
+ */
+typedef struct {
+ edma_channel_t dma_channel; /**< @brief Channel to be allocated.*/
+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
+ uint8_t dma_periph; /**< @brief Peripheral to be
+ associated to the channel. */
+#endif
+ uint8_t dma_irq_prio; /**< @brief IRQ priority level for
+ this channel. */
+ edma_callback_t dma_func; /**< @brief Channel callback,
+ can be NULL if not required. */
+ edma_error_callback_t dma_error_func; /**< @brief Channel error callback,
+ can be NULL if not required. */
+ void *dma_param; /**< @brief Channel callback param. */
+} edma_channel_config_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Peripherals references
+ *
+ * @{
+ */
+#if SPC5_HAS_EDMA || defined(__DOXYGEN__)
+#define SPC5_EDMA (*(edma_t *)0xFFF44000U)
+#endif
+
+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)
+#define SPC5_DMAMUX (*(dma_mux_t *)0xFFFDC000UL)
+#endif
+/** @} */
+
+/**
+ * @brief Returns the TCD address associated to a channel.
+ *
+ * @param[in] channel the channel number
+ * @return A pointer to an @p edma_tcd_t structure.
+ *
+ * @api
+ */
+#define edmaGetTCD(channel) ((edma_tcd_t *)&SPC5_EDMA.TCD[channel])
+
+/**
+ * @brief Sets the word 0 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] src the source address
+ *
+ * @api
+ */
+#define edmaTCDSetWord0(tcdp, src) \
+ ((tcdp)->word[0] = (uint32_t)(src))
+
+/**
+ * @brief Sets the word 1 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] ssize the source width
+ * @param[in] dst the destination width
+ * @param[in] soff the source increment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord1(tcdp, ssize, dsize, soff) \
+ ((tcdp)->word[1] = (((uint32_t)(ssize) << 24) | \
+ ((uint32_t)(dsize) << 16) | \
+ ((uint32_t)(soff) << 0)))
+
+/**
+ * @brief Sets the word 2 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] nbytes the inner counter value
+ *
+ * @api
+ */
+#define edmaTCDSetWord2(tcdp, nbytes) \
+ ((tcdp)->word[2] = (uint32_t)(nbytes))
+
+/**
+ * @brief Sets the word 3 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] slast the adjustment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord3(tcdp, slast) \
+ ((tcdp)->word[3] = (uint32_t)(slast))
+
+/**
+ * @brief Sets the word 4 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] dst the destination address
+ *
+ * @api
+ */
+#define edmaTCDSetWord4(tcdp, dst) \
+ ((tcdp)->word[4] = (uint32_t)(dst))
+
+/**
+ * @brief Sets the word 5 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] citer the current outer counter value
+ * @param[in] doff the destination increment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord5(tcdp, citer, doff) \
+ ((tcdp)->word[5] = (((uint32_t)(citer) << 16) | \
+ ((uint32_t)(doff) << 0)))
+
+/**
+ * @brief Sets the word 5 fields into a TCD.
+ * @note Transfers are limited to 512 operations using this modality
+ * (citer parameter).
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] linkch channel linked on minor loop counter
+ * @param[in] citer the current outer counter value
+ * @param[in] doff the destination increment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord5Linked(tcdp, linkch, citer, doff) \
+ ((tcdp)->word[5] = (((uint32_t)0x80000000) | \
+ ((uint32_t)(linkch) << 25) | \
+ ((uint32_t)(citer) << 16) | \
+ ((uint32_t)(doff) << 0)))
+
+/**
+ * @brief Sets the word 6 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] dlast the adjustment value
+ *
+ * @api
+ */
+#define edmaTCDSetWord6(tcdp, dlast) \
+ ((tcdp)->word[6] = (uint32_t)(dlast))
+
+/**
+ * @brief Sets the word 7 fields into a TCD.
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] biter the base outer counter value
+ * @param[in] mode the mode value
+ *
+ * @api
+ */
+#define edmaTCDSetWord7(tcdp, biter, mode) \
+ ((tcdp)->word[7] = (((uint32_t)(biter) << 16) | \
+ ((uint32_t)(mode) << 0)))
+
+/**
+ * @brief Sets the word 7 fields into a TCD.
+ * @note Transfers are limited to 512 operations using this modality
+ * (biter parameter).
+ *
+ * @param[in] tcdp pointer to an @p edma_tcd_t structure
+ * @param[in] linkch channel linked on minor loop counter
+ * @param[in] biter the base outer counter value
+ * @param[in] mode the mode value
+ *
+ * @api
+ */
+#define edmaTCDSetWord7Linked(tcdp, linkch, biter, mode) \
+ ((tcdp)->word[7] = (((uint32_t)0x80000000) | \
+ ((uint32_t)(linkch) << 25) | \
+ ((uint32_t)(biter) << 16) | \
+ ((uint32_t)(mode) << 0)))
+
+/**
+ * @brief Starts or restarts an EDMA channel.
+ *
+ * @param[in] channel the channel number
+ *
+ * @api
+ */
+#define edmaChannelStart(channel) (SPC5_EDMA.SERQR.R = (channel))
+
+/**
+ * @brief Stops an EDMA channel.
+ *
+ * @param[in] channel the channel number
+ *
+ * @api
+ */
+#define edmaChannelStop(channel) { \
+ SPC5_EDMA.CERQR.R = (channel); \
+ SPC5_EDMA.CDSBR.R = (channel); \
+}
+
+/**
+ * @brief EDMA channel setup.
+ *
+ * @param[in] channel eDMA channel number
+ * @param[in] src source address
+ * @param[in] dst destination address
+ * @param[in] soff source address offset
+ * @param[in] doff destination address offset
+ * @param[in] ssize source transfer size
+ * @param[in] dsize destination transfer size
+ * @param[in] nbytes minor loop count
+ * @param[in] iter major loop count
+ * @param[in] dlast last destination address adjustment
+ * @param[in] slast last source address adjustment
+ * @param[in] mode LSW of TCD register 7
+ *
+ * @api
+ */
+#define edmaChannelSetup(channel, src, dst, soff, doff, ssize, dsize, \
+ nbytes, iter, slast, dlast, mode) { \
+ edma_tcd_t *tcdp = edmaGetTCD(channel); \
+ edmaTCDSetWord0(tcdp, src); \
+ edmaTCDSetWord1(tcdp, ssize, dsize, soff); \
+ edmaTCDSetWord2(tcdp, nbytes); \
+ edmaTCDSetWord3(tcdp, slast); \
+ edmaTCDSetWord4(tcdp, dst); \
+ edmaTCDSetWord5(tcdp, iter, doff); \
+ edmaTCDSetWord6(tcdp, dlast); \
+ edmaTCDSetWord7(tcdp, iter, mode); \
+}
+
+/**
+ * @brief EDMA channel setup with linked channel on both minor and major
+ * loop counters.
+ * @note Transfers are limited to 512 operations using this modality
+ * (iter parameter).
+ *
+ * @param[in] channel eDMA channel number
+ * @param[in] linkch channel linked on minor loop counter
+ * @param[in] src source address
+ * @param[in] dst destination address
+ * @param[in] soff source address offset
+ * @param[in] doff destination address offset
+ * @param[in] ssize source transfer size
+ * @param[in] dsize destination transfer size
+ * @param[in] nbytes minor loop count
+ * @param[in] iter major loop count
+ * @param[in] dlast last destination address adjustment
+ * @param[in] slast last source address adjustment
+ * @param[in] mode LSW of TCD register 7
+ *
+ * @api
+ */
+#define edmaChannelSetupLinked(channel, linkch, src, dst, soff, \
+ doff, ssize, dsize, nbytes, iter, \
+ slast, dlast, mode) { \
+ edma_tcd_t *tcdp = edmaGetTCD(channel); \
+ edmaTCDSetWord0(tcdp, src); \
+ edmaTCDSetWord1(tcdp, ssize, dsize, soff); \
+ edmaTCDSetWord2(tcdp, nbytes); \
+ edmaTCDSetWord3(tcdp, slast); \
+ edmaTCDSetWord4(tcdp, dst); \
+ edmaTCDSetWord5Linked(tcdp, linkch, iter, doff); \
+ edmaTCDSetWord6(tcdp, dlast); \
+ edmaTCDSetWord7Linked(tcdp, linkch, iter, (mode) | \
+ EDMA_TCD_MODE_MELINK | \
+ EDMA_TCD_MODE_MLINKCH(linkch)); \
+}
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void edmaInit(void);
+ edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg);
+ void edmaChannelRelease(edma_channel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SPC5_HAS_EDMA */
+
+#endif /* _SPC5_EDMA_H_ */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/ESCI_v1/hal_serial_lld.c b/os/hal/ports/SPC5/LLD/ESCI_v1/hal_serial_lld.c new file mode 100644 index 000000000..8f16d5a23 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/ESCI_v1/hal_serial_lld.c @@ -0,0 +1,343 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/ESCI_v1/hal_serial_lld.c
+ * @brief SPC5xx low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief eSCI-A serial driver identifier.
+ */
+#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/**
+ * @brief eSCI-B serial driver identifier.
+ */
+#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/**
+ * @brief eSCI-C serial driver identifier.
+ */
+#if SPC5_USE_ESCIC || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ SERIAL_DEFAULT_BITRATE,
+ SD_MODE_NORMAL | SD_MODE_PARITY_NONE
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief eSCI initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration
+ */
+static void esci_init(SerialDriver *sdp, const SerialConfig *config) {
+ volatile struct ESCI_tag *escip = sdp->escip;
+ uint8_t mode = config->sc_mode;
+
+ escip->CR2.R = 0; /* MDIS off. */
+ escip->CR1.R = 0;
+ escip->LCR.R = 0;
+ escip->CR1.B.SBR = SPC5_SYSCLK / (16 * config->sc_speed);
+ if (mode & SD_MODE_LOOPBACK)
+ escip->CR1.B.LOOPS = 1;
+ switch (mode & SD_MODE_PARITY_MASK) {
+ case SD_MODE_PARITY_ODD:
+ escip->CR1.B.PT = 1;
+ case SD_MODE_PARITY_EVEN:
+ escip->CR1.B.PE = 1;
+ escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */
+ default:
+ ;
+ }
+ escip->LPR.R = 0;
+ escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */
+ escip->CR2.R = 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */
+}
+
+/**
+ * @brief eSCI de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] escip pointer to an eSCI I/O block
+ */
+static void esci_deinit(volatile struct ESCI_tag *escip) {
+
+ escip->LPR.R = 0;
+ escip->SR.R = 0xFFFFFFFF;
+ escip->CR1.R = 0;
+ escip->CR2.R = 0x8000; /* MDIS on. */
+}
+
+/**
+ * @brief Error handling routine.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] sr eSCI SR register value
+ */
+static void set_error(SerialDriver *sdp, uint32_t sr) {
+ eventflags_t sts = 0;
+
+ if (sr & 0x08000000)
+ sts |= SD_OVERRUN_ERROR;
+ if (sr & 0x04000000)
+ sts |= SD_NOISE_ERROR;
+ if (sr & 0x02000000)
+ sts |= SD_FRAMING_ERROR;
+ if (sr & 0x01000000)
+ sts |= SD_PARITY_ERROR;
+/* if (sr & 0x00000000)
+ sts |= SD_BREAK_DETECTED;*/
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, sts);
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common IRQ handler.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ volatile struct ESCI_tag *escip = sdp->escip;
+
+ uint32_t sr = escip->SR.R;
+ escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/
+ if (sr & 0x0F000000) /* OR | NF | FE | PF. */
+ set_error(sdp, sr);
+ if (sr & 0x20000000) { /* RDRF. */
+ osalSysLockFromISR();
+ sdIncomingDataI(sdp, escip->DR.B.D);
+ osalSysUnlockFromISR();
+ }
+ if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */
+ msg_t b;
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ escip->CR1.B.TIE = 0;
+ }
+ else {
+ escip->SR.B.TDRE = 1;
+ escip->DR.R = (uint16_t)b;
+ }
+ osalSysUnlockFromISR();
+ }
+}
+
+#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp) {
+
+ (void)qp;
+ if (ESCI_A.SR.B.TDRE) {
+ msg_t b = sdRequestDataI(&SD1);
+ if (b != Q_EMPTY) {
+ ESCI_A.SR.B.TDRE = 1;
+ ESCI_A.CR1.B.TIE = 1;
+ ESCI_A.DR.R = (uint16_t)b;
+ }
+ }
+}
+#endif
+
+#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp) {
+
+ (void)qp;
+ if (ESCI_B.SR.B.TDRE) {
+ msg_t b = sdRequestDataI(&SD2);
+ if (b != Q_EMPTY) {
+ ESCI_B.SR.B.TDRE = 1;
+ ESCI_B.CR1.B.TIE = 1;
+ ESCI_B.DR.R = (uint16_t)b;
+ }
+ }
+}
+#endif
+
+#if SPC5_USE_ESCIC || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp) {
+
+ (void)qp;
+ if (ESCI_C.SR.B.TDRE) {
+ msg_t b = sdRequestDataI(&SD3);
+ if (b != Q_EMPTY) {
+ ESCI_C.SR.B.TDRE = 1;
+ ESCI_C.CR1.B.TIE = 1;
+ ESCI_C.DR.R = (uint16_t)b;
+ }
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_USE_ESCIA || defined(__DOXYGEN__)
+#if !defined(SPC5_ESCIA_HANDLER)
+#error "SPC5_ESCIA_HANDLER not defined"
+#endif
+/**
+ * @brief eSCI-A interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_ESCIA_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_USE_ESCIB || defined(__DOXYGEN__)
+#if !defined(SPC5_ESCIB_HANDLER)
+#error "SPC5_ESCIB_HANDLER not defined"
+#endif
+/**
+ * @brief eSCI-B interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_ESCIB_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_USE_ESCIC || defined(__DOXYGEN__)
+#if !defined(SPC5_ESCIC_HANDLER)
+#error "SPC5_ESCIC_HANDLER not defined"
+#endif
+/**
+ * @brief eSCI-C interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_ESCIC_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if SPC5_USE_ESCIA
+ sdObjectInit(&SD1, NULL, notify1);
+ SD1.escip = &ESCI_A;
+ ESCI_A.CR2.R = 0x8000; /* MDIS ON. */
+ INTC.PSR[SPC5_ESCIA_NUMBER].R = SPC5_ESCIA_PRIORITY;
+#endif
+
+#if SPC5_USE_ESCIB
+ sdObjectInit(&SD2, NULL, notify2);
+ SD2.escip = &ESCI_B;
+ ESCI_B.CR2.R = 0x8000; /* MDIS ON. */
+ INTC.PSR[SPC5_ESCIB_NUMBER].R = SPC5_ESCIB_PRIORITY;
+#endif
+
+#if SPC5_USE_ESCIC
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.escip = &ESCI_C;
+ ESCI_C.CR2.R = 0x8000; /* MDIS ON. */
+ INTC.PSR[SPC5_ESCIC_NUMBER].R = SPC5_ESCIC_PRIORITY;
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+ esci_init(sdp, config);
+}
+
+/**
+ * @brief Low level serial driver stop.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY)
+ esci_deinit(sdp->escip);
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/ESCI_v1/hal_serial_lld.h b/os/hal/ports/SPC5/LLD/ESCI_v1/hal_serial_lld.h new file mode 100644 index 000000000..041edf4cb --- /dev/null +++ b/os/hal/ports/SPC5/LLD/ESCI_v1/hal_serial_lld.h @@ -0,0 +1,195 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/ESCI_v1/hal_serial_lld.c
+ * @brief SPC5xx low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef HAL_SERIAL_LLD_H
+#define HAL_SERIAL_LLD_H
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Serial port modes
+ * @{
+ */
+#define SD_MODE_PARITY_MASK 0x03 /**< @brief Parity field mask. */
+#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */
+#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */
+#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */
+
+#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */
+#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief eSCI-A driver enable switch.
+ * @details If set to @p TRUE the support for eSCI-A is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(SPC5_USE_ESCIA) || defined(__DOXYGEN__)
+#define SPC5_USE_ESCIA FALSE
+#endif
+
+/**
+ * @brief eSCI-B driver enable switch.
+ * @details If set to @p TRUE the support for eSCI-B is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(SPC5_USE_ESCIB) || defined(__DOXYGEN__)
+#define SPC5_USE_ESCIB FALSE
+#endif
+
+/**
+ * @brief eSCI-C driver enable switch.
+ * @details If set to @p TRUE the support for eSCI-C is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(SPC5_USE_ESCIC) || defined(__DOXYGEN__)
+#define SPC5_USE_ESCIC FALSE
+#endif
+
+/**
+ * @brief eSCI-A interrupt priority level setting.
+ */
+#if !defined(SPC5_ESCIA_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_ESCIA_PRIORITY 8
+#endif
+
+/**
+ * @brief eSCI-B interrupt priority level setting.
+ */
+#if !defined(SPC5_ESCIB_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_ESCIB_PRIORITY 8
+#endif
+
+/**
+ * @brief eSCI-C interrupt priority level setting.
+ */
+#if !defined(SPC5_ESCIC_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_ESCIC_PRIORITY 8
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if SPC5_USE_ESCIA && !SPC5_HAS_ESCIA
+#error "eSCI-A not present in the selected device"
+#endif
+
+#if SPC5_USE_ESCIB && !SPC5_HAS_ESCIB
+#error "eSCI-B not present in the selected device"
+#endif
+
+#if SPC5_USE_ESCIC && !SPC5_HAS_ESCIC
+#error "eSCI-C not present in the selected device"
+#endif
+
+#if !SPC5_USE_ESCIA && !SPC5_USE_ESCIB && !SPC5_USE_ESCIC
+#error "SERIAL driver activated but no eSCI peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note This structure content is architecture dependent, each driver
+ * implementation defines its own version and the custom static
+ * initializers.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t sc_speed;
+ /**
+ * @brief Mode flags.
+ */
+ uint8_t sc_mode;
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ volatile sdstate_t state; \
+ /* Input queue.*/ \
+ input_queue_t iqueue; \
+ /* Output queue.*/ \
+ output_queue_t oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the volatile eSCI registers block.*/ \
+ volatile struct ESCI_tag *escip;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_USE_ESCIA && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#if SPC5_USE_ESCIB && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#if SPC5_USE_ESCIC && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* HAL_SERIAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.c b/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.c new file mode 100644 index 000000000..0f5faae5a --- /dev/null +++ b/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.c @@ -0,0 +1,1171 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/LINFlex_v1/hal_serial_lld.c
+ * @brief SPC5xx low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief LIINFlex-0 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/**
+ * @brief LIINFlex-1 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/**
+ * @brief LIINFlex-2 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/**
+ * @brief LIINFlex-3 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+/**
+ * @brief LIINFlex-4 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+/**
+ * @brief LIINFlex-5 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
+/**
+ * @brief LIINFlex-6 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX6 || defined(__DOXYGEN__)
+SerialDriver SD7;
+#endif
+
+/**
+ * @brief LIINFlex-7 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX7 || defined(__DOXYGEN__)
+SerialDriver SD8;
+#endif
+
+/**
+ * @brief LIINFlex-8 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX8 || defined(__DOXYGEN__)
+SerialDriver SD9;
+#endif
+
+/**
+ * @brief LIINFlex-9 serial driver identifier.
+ */
+#if SPC5_SERIAL_USE_LINFLEX9 || defined(__DOXYGEN__)
+SerialDriver SD10;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver default configuration.
+ */
+static const SerialConfig default_config = {
+ SERIAL_DEFAULT_BITRATE,
+ SD_MODE_8BITS_PARITY_NONE
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief LINFlex initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration
+ */
+static void spc5_linflex_init(SerialDriver *sdp, const SerialConfig *config) {
+ uint32_t div;
+ volatile struct spc5_linflex *linflexp = sdp->linflexp;
+
+ /* Enters the configuration mode.*/
+ linflexp->LINCR1.R = 1; /* INIT bit. */
+
+ /* Configures the LINFlex in UART mode with all the required
+ parameters.*/
+ linflexp->UARTCR.R = SPC5_UARTCR_UART; /* UART mode FIRST. */
+ linflexp->UARTCR.R = SPC5_UARTCR_UART | SPC5_UARTCR_RXEN | config->mode;
+ div = SPC5_LINFLEX0_CLK / config->speed;
+ linflexp->LINFBRR.R = (uint16_t)(div & 15); /* Fractional divider. */
+ linflexp->LINIBRR.R = (uint16_t)(div >> 4); /* Integer divider. */
+ linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/
+ linflexp->LINIER.R = SPC5_LINIER_DTIE | SPC5_LINIER_DRIE |
+ SPC5_LINIER_BOIE | SPC5_LINIER_FEIE |
+ SPC5_LINIER_SZIE; /* Interrupts enabled. */
+
+ /* Leaves the configuration mode.*/
+ linflexp->LINCR1.R = 0;
+}
+
+/**
+ * @brief LINFlex de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] linflexp pointer to a LINFlex I/O block
+ */
+static void spc5_linflex_deinit(volatile struct spc5_linflex *linflexp) {
+
+ /* Enters the configuration mode.*/
+ linflexp->LINCR1.R = 1; /* INIT bit. */
+
+ /* Resets the LINFlex registers.*/
+ linflexp->LINFBRR.R = 0; /* Fractional divider. */
+ linflexp->LINIBRR.R = 0; /* Integer divider. */
+ linflexp->UARTSR.R = 0xFFFF; /* Clearing UARTSR register.*/
+ linflexp->UARTCR.R = SPC5_UARTCR_UART;
+ linflexp->LINIER.R = 0; /* Interrupts disabled. */
+
+ /* Leaves the configuration mode.*/
+ linflexp->LINCR1.R = 0;
+}
+
+/**
+ * @brief Common RXI IRQ handler.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ */
+static void spc5xx_serve_rxi_interrupt(SerialDriver *sdp) {
+ eventflags_t sts = 0;
+ uint16_t sr = sdp->linflexp->UARTSR.R;
+
+ sdp->linflexp->UARTSR.R = SPC5_UARTSR_NF | SPC5_UARTSR_DRF |
+ SPC5_UARTSR_PE0;
+ if (sr & SPC5_UARTSR_NF)
+ sts |= SD_NOISE_ERROR;
+ if (sr & SPC5_UARTSR_PE0)
+ sts |= SD_PARITY_ERROR;
+ osalSysLockFromISR();
+ if (sts)
+ chnAddFlagsI(sdp, sts);
+ if (sr & SPC5_UARTSR_DRF) {
+ sdIncomingDataI(sdp, sdp->linflexp->BDRM.B.DATA4);
+ sdp->linflexp->UARTSR.R = SPC5_UARTSR_RMB;
+ }
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common TXI IRQ handler.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ */
+static void spc5xx_serve_txi_interrupt(SerialDriver *sdp) {
+ msg_t b;
+
+ sdp->linflexp->UARTSR.R = SPC5_UARTSR_DTF;
+ osalSysLockFromISR();
+ b = oqGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+ sdp->linflexp->UARTCR.B.TXEN = 0;
+ }
+ else
+ sdp->linflexp->BDRL.B.DATA0 = b;
+ osalSysUnlockFromISR();
+}
+
+/**
+ * @brief Common ERR IRQ handler.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ */
+static void spc5xx_serve_err_interrupt(SerialDriver *sdp) {
+ eventflags_t sts = 0;
+ uint16_t sr = sdp->linflexp->UARTSR.R;
+
+ sdp->linflexp->UARTSR.R = SPC5_UARTSR_BOF | SPC5_UARTSR_FEF |
+ SPC5_UARTSR_SZF;
+ if (sr & SPC5_UARTSR_BOF)
+ sts |= SD_OVERRUN_ERROR;
+ if (sr & SPC5_UARTSR_FEF)
+ sts |= SD_FRAMING_ERROR;
+ if (sr & SPC5_UARTSR_SZF)
+ sts |= SD_BREAK_DETECTED;
+ osalSysLockFromISR();
+ chnAddFlagsI(sdp, sts);
+ osalSysUnlockFromISR();
+}
+
+#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
+static void notify1(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD1.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD1);
+ if (b != Q_EMPTY) {
+ SD1.linflexp->UARTCR.B.TXEN = 1;
+ SD1.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
+static void notify2(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD2.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD2);
+ if (b != Q_EMPTY) {
+ SD2.linflexp->UARTCR.B.TXEN = 1;
+ SD2.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
+static void notify3(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD3.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD3);
+ if (b != Q_EMPTY) {
+ SD3.linflexp->UARTCR.B.TXEN = 1;
+ SD3.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
+static void notify4(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD4.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD4);
+ if (b != Q_EMPTY) {
+ SD4.linflexp->UARTCR.B.TXEN = 1;
+ SD4.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX4 || defined(__DOXYGEN__)
+static void notify5(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD5.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD5);
+ if (b != Q_EMPTY) {
+ SD5.linflexp->UARTCR.B.TXEN = 1;
+ SD5.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX5 || defined(__DOXYGEN__)
+static void notify6(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD6.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD6);
+ if (b != Q_EMPTY) {
+ SD6.linflexp->UARTCR.B.TXEN = 1;
+ SD6.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX6 || defined(__DOXYGEN__)
+static void notify7(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD7.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD7);
+ if (b != Q_EMPTY) {
+ SD7.linflexp->UARTCR.B.TXEN = 1;
+ SD7.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX7 || defined(__DOXYGEN__)
+static void notify8(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD8.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD8);
+ if (b != Q_EMPTY) {
+ SD8.linflexp->UARTCR.B.TXEN = 1;
+ SD8.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX8 || defined(__DOXYGEN__)
+static void notify9(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD9.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD9);
+ if (b != Q_EMPTY) {
+ SD9.linflexp->UARTCR.B.TXEN = 1;
+ SD9.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX9 || defined(__DOXYGEN__)
+static void notify10(io_queue_t *qp) {
+
+ (void)qp;
+ if (!SD10.linflexp->UARTCR.B.TXEN) {
+ msg_t b = sdRequestDataI(&SD10);
+ if (b != Q_EMPTY) {
+ SD10.linflexp->UARTCR.B.TXEN = 1;
+ SD10.linflexp->BDRL.B.DATA0 = b;
+ }
+ }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_SERIAL_USE_LINFLEX0 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX0_RXI_HANDLER)
+#error "SPC5_LINFLEX0_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-0 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX0_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX0_TXI_HANDLER)
+#error "SPC5_LINFLEX0_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-0 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX0_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX0_ERR_HANDLER)
+#error "SPC5_LINFLEX0_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-0 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX0_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD1);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX1 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX1_RXI_HANDLER)
+#error "SPC5_LINFLEX1_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-1 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX1_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX1_TXI_HANDLER)
+#error "SPC5_LINFLEX1_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-1 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX1_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX1_ERR_HANDLER)
+#error "SPC5_LINFLEX1_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-1 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX1_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD2);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX2 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX2_RXI_HANDLER)
+#error "SPC5_LINFLEX2_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-2 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX2_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX2_TXI_HANDLER)
+#error "SPC5_LINFLEX2_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-2 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX2_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX2_ERR_HANDLER)
+#error "SPC5_LINFLEX2_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-2 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX2_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD3);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX3_RXI_HANDLER)
+#error "SPC5_LINFLEX3_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-3 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX3_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX3_TXI_HANDLER)
+#error "SPC5_LINFLEX3_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-3 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX3_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX3_ERR_HANDLER)
+#error "SPC5_LINFLEX3_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-3 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX3_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD4);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX4 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX4_RXI_HANDLER)
+#error "SPC5_LINFLEX4_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-4 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX4_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX4_TXI_HANDLER)
+#error "SPC5_LINFLEX4_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-4 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX4_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX4_ERR_HANDLER)
+#error "SPC5_LINFLEX4_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-4 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX4_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD5);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX5 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX5_RXI_HANDLER)
+#error "SPC5_LINFLEX5_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-5 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX5_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX5_TXI_HANDLER)
+#error "SPC5_LINFLEX5_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-5 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX5_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX5_ERR_HANDLER)
+#error "SPC5_LINFLEX5_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-5 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX5_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD6);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX6 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX6_RXI_HANDLER)
+#error "SPC5_LINFLEX6_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-6 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX6_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX6_TXI_HANDLER)
+#error "SPC5_LINFLEX6_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-6 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX6_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX6_ERR_HANDLER)
+#error "SPC5_LINFLEX6_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-6 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX6_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD7);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX7 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX7_RXI_HANDLER)
+#error "SPC5_LINFLEX7_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-7 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX7_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX7_TXI_HANDLER)
+#error "SPC5_LINFLEX7_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-7 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX7_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX7_ERR_HANDLER)
+#error "SPC5_LINFLEX7_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-7 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX7_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD8);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX8 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX8_RXI_HANDLER)
+#error "SPC5_LINFLEX8_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-8 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX8_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX8_TXI_HANDLER)
+#error "SPC5_LINFLEX8_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-8 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX8_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX8_ERR_HANDLER)
+#error "SPC5_LINFLEX8_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-8 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX8_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD9);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX9 || defined(__DOXYGEN__)
+#if !defined(SPC5_LINFLEX9_RXI_HANDLER)
+#error "SPC5_LINFLEX9_RXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-9 RXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX9_RXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_rxi_interrupt(&SD10);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX9_TXI_HANDLER)
+#error "SPC5_LINFLEX9_TXI_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-9 TXI interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX9_TXI_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_txi_interrupt(&SD10);
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+#if !defined(SPC5_LINFLEX9_ERR_HANDLER)
+#error "SPC5_LINFLEX9_ERR_HANDLER not defined"
+#endif
+/**
+ * @brief LINFlex-9 ERR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(SPC5_LINFLEX9_ERR_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ spc5xx_serve_err_interrupt(&SD10);
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if SPC5_SERIAL_USE_LINFLEX0
+ sdObjectInit(&SD1, NULL, notify1);
+ SD1.linflexp = &SPC5_LINFLEX0;
+ INTC_PSR(SPC5_LINFLEX0_RXI_NUMBER) = SPC5_SERIAL_LINFLEX0_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX0_TXI_NUMBER) = SPC5_SERIAL_LINFLEX0_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX0_ERR_NUMBER) = SPC5_SERIAL_LINFLEX0_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX1
+ sdObjectInit(&SD2, NULL, notify2);
+ SD2.linflexp = &SPC5_LINFLEX1;
+ INTC_PSR(SPC5_LINFLEX1_RXI_NUMBER) = SPC5_SERIAL_LINFLEX1_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX1_TXI_NUMBER) = SPC5_SERIAL_LINFLEX1_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX1_ERR_NUMBER) = SPC5_SERIAL_LINFLEX1_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX2
+ sdObjectInit(&SD3, NULL, notify3);
+ SD3.linflexp = &SPC5_LINFLEX2;
+ INTC_PSR(SPC5_LINFLEX2_RXI_NUMBER) = SPC5_SERIAL_LINFLEX2_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX2_TXI_NUMBER) = SPC5_SERIAL_LINFLEX2_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX2_ERR_NUMBER) = SPC5_SERIAL_LINFLEX2_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3
+ sdObjectInit(&SD4, NULL, notify4);
+ SD4.linflexp = &SPC5_LINFLEX3;
+ INTC_PSR(SPC5_LINFLEX3_RXI_NUMBER) = SPC5_SERIAL_LINFLEX3_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX3_TXI_NUMBER) = SPC5_SERIAL_LINFLEX3_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX3_ERR_NUMBER) = SPC5_SERIAL_LINFLEX3_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX4
+ sdObjectInit(&SD5, NULL, notify5);
+ SD5.linflexp = &SPC5_LINFLEX4;
+ INTC_PSR(SPC5_LINFLEX4_RXI_NUMBER) = SPC5_SERIAL_LINFLEX4_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX4_TXI_NUMBER) = SPC5_SERIAL_LINFLEX4_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX4_ERR_NUMBER) = SPC5_SERIAL_LINFLEX4_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX5
+ sdObjectInit(&SD6, NULL, notify6);
+ SD6.linflexp = &SPC5_LINFLEX5;
+ INTC_PSR(SPC5_LINFLEX5_RXI_NUMBER) = SPC5_SERIAL_LINFLEX5_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX5_TXI_NUMBER) = SPC5_SERIAL_LINFLEX5_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX5_ERR_NUMBER) = SPC5_SERIAL_LINFLEX5_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX6
+ sdObjectInit(&SD7, NULL, notify7);
+ SD7.linflexp = &SPC5_LINFLEX6;
+ INTC_PSR(SPC5_LINFLEX6_RXI_NUMBER) = SPC5_SERIAL_LINFLEX6_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX6_TXI_NUMBER) = SPC5_SERIAL_LINFLEX6_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX6_ERR_NUMBER) = SPC5_SERIAL_LINFLEX6_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX7
+ sdObjectInit(&SD8, NULL, notify8);
+ SD8.linflexp = &SPC5_LINFLEX7;
+ INTC_PSR(SPC5_LINFLEX7_RXI_NUMBER) = SPC5_SERIAL_LINFLEX7_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX7_TXI_NUMBER) = SPC5_SERIAL_LINFLEX7_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX7_ERR_NUMBER) = SPC5_SERIAL_LINFLEX7_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX8
+ sdObjectInit(&SD9, NULL, notify9);
+ SD9.linflexp = &SPC5_LINFLEX8;
+ INTC_PSR(SPC5_LINFLEX8_RXI_NUMBER) = SPC5_SERIAL_LINFLEX8_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX8_TXI_NUMBER) = SPC5_SERIAL_LINFLEX8_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX8_ERR_NUMBER) = SPC5_SERIAL_LINFLEX8_PRIORITY;
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX9
+ sdObjectInit(&SD10, NULL, notify10);
+ SD10.linflexp = &SPC5_LINFLEX9;
+ INTC_PSR(SPC5_LINFLEX9_RXI_NUMBER) = SPC5_SERIAL_LINFLEX9_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX9_TXI_NUMBER) = SPC5_SERIAL_LINFLEX9_PRIORITY;
+ INTC_PSR(SPC5_LINFLEX9_ERR_NUMBER) = SPC5_SERIAL_LINFLEX9_PRIORITY;
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ * @param[in] config the architecture-dependent serial driver configuration.
+ * If this parameter is set to @p NULL then a default
+ * configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+ if (config == NULL)
+ config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+#if SPC5_SERIAL_USE_LINFLEX0
+ if (&SD1 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
+ SPC5_SERIAL_LINFLEX0_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX1
+ if (&SD2 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
+ SPC5_SERIAL_LINFLEX1_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX2
+ if (&SD3 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
+ SPC5_SERIAL_LINFLEX2_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX3
+ if (&SD4 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
+ SPC5_SERIAL_LINFLEX3_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX4
+ if (&SD5 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX4_PCTL,
+ SPC5_SERIAL_LINFLEX4_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX5
+ if (&SD6 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX5_PCTL,
+ SPC5_SERIAL_LINFLEX5_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX6
+ if (&SD7 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX6_PCTL,
+ SPC5_SERIAL_LINFLEX6_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX7
+ if (&SD8 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX7_PCTL,
+ SPC5_SERIAL_LINFLEX7_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX8
+ if (&SD9 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX8_PCTL,
+ SPC5_SERIAL_LINFLEX8_START_PCTL);
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX9
+ if (&SD10 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX9_PCTL,
+ SPC5_SERIAL_LINFLEX9_START_PCTL);
+ }
+#endif
+ }
+ spc5_linflex_init(sdp, config);
+}
+
+/**
+ * @brief Low level serial driver stop.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ spc5_linflex_deinit(sdp->linflexp);
+
+#if SPC5_SERIAL_USE_LINFLEX0
+ if (&SD1 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX0_PCTL,
+ SPC5_SERIAL_LINFLEX0_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX1
+ if (&SD2 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX1_PCTL,
+ SPC5_SERIAL_LINFLEX1_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX2
+ if (&SD3 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX2_PCTL,
+ SPC5_SERIAL_LINFLEX2_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX3
+ if (&SD4 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX3_PCTL,
+ SPC5_SERIAL_LINFLEX3_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX4
+ if (&SD5 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX4_PCTL,
+ SPC5_SERIAL_LINFLEX4_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX5
+ if (&SD6 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX5_PCTL,
+ SPC5_SERIAL_LINFLEX5_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX6
+ if (&SD7 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX6_PCTL,
+ SPC5_SERIAL_LINFLEX6_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX7
+ if (&SD8 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX7_PCTL,
+ SPC5_SERIAL_LINFLEX7_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX8
+ if (&SD9 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX8_PCTL,
+ SPC5_SERIAL_LINFLEX8_STOP_PCTL);
+ return;
+ }
+#endif
+#if SPC5_SERIAL_USE_LINFLEX9
+ if (&SD10 == sdp) {
+ halSPCSetPeripheralClockMode(SPC5_LINFLEX9_PCTL,
+ SPC5_SERIAL_LINFLEX9_STOP_PCTL);
+ return;
+ }
+#endif
+ }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.h b/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.h new file mode 100644 index 000000000..31eb3e002 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.h @@ -0,0 +1,574 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/LINFlex_v1/hal_serial_lld.h
+ * @brief SPC5xx low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef HAL_SERIAL_LLD_H
+#define HAL_SERIAL_LLD_H
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+#include "spc5_linflex.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name Serial driver allowable modes
+ * @{
+ */
+#define SD_MODE_8BITS_PARITY_NONE (SPC5_UARTCR_WL)
+#define SD_MODE_8BITS_PARITY_EVEN (SPC5_UARTCR_WL | \
+ SPC5_UARTCR_PCE)
+#define SD_MODE_8BITS_PARITY_ODD (SPC5_UARTCR_WL | \
+ SPC5_UARTCR_PCE | \
+ SPC5_UARTCR_OP)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief LINFlex-0 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-0 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX0) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX0 FALSE
+#endif
+
+/**
+ * @brief LINFlex-1 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-1 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX1) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX1 FALSE
+#endif
+
+/**
+ * @brief LINFlex-2 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-2 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX2) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX2 FALSE
+#endif
+
+/**
+ * @brief LINFlex-3 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-3 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX3) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX3 FALSE
+#endif
+
+/**
+ * @brief LINFlex-4 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-4 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX4) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX4 FALSE
+#endif
+
+/**
+ * @brief LINFlex-5 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-5 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX5) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX5 FALSE
+#endif
+
+/**
+ * @brief LINFlex-6 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-6 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX6) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX6 FALSE
+#endif
+
+/**
+ * @brief LINFlex-7 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-7 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX7) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX7 FALSE
+#endif
+
+/**
+ * @brief LINFlex-8 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-8 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX8) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX8 FALSE
+#endif
+
+/**
+ * @brief LINFlex-9 driver enable switch.
+ * @details If set to @p TRUE the support for LINFlex-9 is included.
+ */
+#if !defined(SPC5_SERIAL_USE_LINFLEX9) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_USE_LINFLEX9 FALSE
+#endif
+
+/**
+ * @brief LINFlex-0 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX0_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-1 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX1_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-2 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX2_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX2_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-3 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX3_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX3_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-4 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX4_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX4_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-5 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX5_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX5_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-6 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX6_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX6_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-7 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX7_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX7_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-8 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX8_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX8_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-9 interrupt priority level setting.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX9_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX9_PRIORITY 8
+#endif
+
+/**
+ * @brief LINFlex-0 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX0_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-0 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX0_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-1 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX1_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-1 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX1_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-2 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX2_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-2 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX2_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-3 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX3_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-3 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX3_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-4 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX4_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-4 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX4_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-5 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX5_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-5 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX5_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-6 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX6_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX6_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-6 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX6_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX6_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-7 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX7_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX7_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-7 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX7_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX7_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-8 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX8_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX8_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-8 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX8_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX8_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+
+/**
+ * @brief LINFlex-9 peripheral configuration when started.
+ * @note The default configuration is 1 (always run) in run mode and
+ * 2 (only halt) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX9_START_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX9_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#endif
+
+/**
+ * @brief LINFlex-9 peripheral configuration when stopped.
+ * @note The default configuration is 0 (never run) in run mode and
+ * 0 (never run) in low power mode. The defaults of the run modes
+ * are defined in @p hal_lld.h.
+ */
+#if !defined(SPC5_SERIAL_LINFLEX9_STOP_PCTL) || defined(__DOXYGEN__)
+#define SPC5_SERIAL_LINFLEX9_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if SPC5_SERIAL_USE_LINFLEX0 && !SPC5_HAS_LINFLEX0
+#error "LINFlex-0 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX1 && !SPC5_HAS_LINFLEX1
+#error "LINFlex-1 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX2 && !SPC5_HAS_LINFLEX2
+#error "LINFlex-2 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX3 && !SPC5_HAS_LINFLEX3
+#error "LINFlex-3 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX4 && !SPC5_HAS_LINFLEX4
+#error "LINFlex-4 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX5 && !SPC5_HAS_LINFLEX5
+#error "LINFlex-5 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX6 && !SPC5_HAS_LINFLEX6
+#error "LINFlex-6 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX7 && !SPC5_HAS_LINFLEX7
+#error "LINFlex-7 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX8 && !SPC5_HAS_LINFLEX8
+#error "LINFlex-8 not present in the selected device"
+#endif
+
+#if SPC5_SERIAL_USE_LINFLEX9 && !SPC5_HAS_LINFLEX9
+#error "LINFlex-9 not present in the selected device"
+#endif
+
+#if !SPC5_SERIAL_USE_LINFLEX0 && !SPC5_SERIAL_USE_LINFLEX1 && \
+ !SPC5_SERIAL_USE_LINFLEX2 && !SPC5_SERIAL_USE_LINFLEX3 && \
+ !SPC5_SERIAL_USE_LINFLEX4 && !SPC5_SERIAL_USE_LINFLEX5 && \
+ !SPC5_SERIAL_USE_LINFLEX6 && !SPC5_SERIAL_USE_LINFLEX7 && \
+ !SPC5_SERIAL_USE_LINFLEX8 && !SPC5_SERIAL_USE_LINFLEX9
+#error "SERIAL driver activated but no LINFlex peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Generic Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ * @note This structure content is architecture dependent, each driver
+ * implementation defines its own version and the custom static
+ * initializers.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t speed;
+ /**
+ * @brief Mode flags.
+ */
+ uint8_t mode;
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ volatile sdstate_t state; \
+ /* Input queue.*/ \
+ input_queue_t iqueue; \
+ /* Output queue.*/ \
+ output_queue_t oqueue; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the volatile LINFlex registers block.*/ \
+ volatile struct spc5_linflex *linflexp;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_SERIAL_USE_LINFLEX0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX1 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX2 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX6 && !defined(__DOXYGEN__)
+extern SerialDriver SD7;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX7 && !defined(__DOXYGEN__)
+extern SerialDriver SD8;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX8 && !defined(__DOXYGEN__)
+extern SerialDriver SD9;
+#endif
+#if SPC5_SERIAL_USE_LINFLEX9 && !defined(__DOXYGEN__)
+extern SerialDriver SD10;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* HAL_SERIAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/LINFlex_v1/spc5_linflex.h b/os/hal/ports/SPC5/LLD/LINFlex_v1/spc5_linflex.h new file mode 100644 index 000000000..7c668fba1 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/LINFlex_v1/spc5_linflex.h @@ -0,0 +1,637 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/spc5_linflex.h
+ * @brief LINFlex helper driver header.
+ *
+ * @addtogroup SPC5xx_LINFLEX
+ * @{
+ */
+
+#ifndef _SPC5_LINFLEX_H_
+#define _SPC5_LINFLEX_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name LINIER register bits definitions
+ * @{
+ */
+#define SPC5_LINIER_HRIE (1U << 0)
+#define SPC5_LINIER_DTIE (1U << 1)
+#define SPC5_LINIER_DRIE (1U << 2)
+#define SPC5_LINIER_DBEIE (1U << 3)
+#define SPC5_LINIER_DBFIE (1U << 4)
+#define SPC5_LINIER_WUIE (1U << 5)
+#define SPC5_LINIER_LSIE (1U << 6)
+#define SPC5_LINIER_BOIE (1U << 7)
+#define SPC5_LINIER_FEIE (1U << 8)
+#define SPC5_LINIER_HEIE (1U << 11)
+#define SPC5_LINIER_CEIE (1U << 12)
+#define SPC5_LINIER_BEIE (1U << 13)
+#define SPC5_LINIER_OCIE (1U << 14)
+#define SPC5_LINIER_SZIE (1U << 15)
+/** @} */
+
+/**
+ * @name UARTSR register bits definitions
+ * @{
+ */
+#define SPC5_UARTSR_NF (1U << 0)
+#define SPC5_UARTSR_DTF (1U << 1)
+#define SPC5_UARTSR_DRF (1U << 2)
+#define SPC5_UARTSR_WUF (1U << 5)
+#define SPC5_UARTSR_RPS (1U << 6)
+#define SPC5_UARTSR_BOF (1U << 7)
+#define SPC5_UARTSR_FEF (1U << 8)
+#define SPC5_UARTSR_RMB (1U << 9)
+#define SPC5_UARTSR_PE0 (1U << 10)
+#define SPC5_UARTSR_PE1 (1U << 11)
+#define SPC5_UARTSR_PE2 (1U << 12)
+#define SPC5_UARTSR_PE3 (1U << 13)
+#define SPC5_UARTSR_OCF (1U << 14)
+#define SPC5_UARTSR_SZF (1U << 15)
+/** @} */
+
+/**
+ * @name UARTCR register bits definitions
+ * @{
+ */
+#define SPC5_UARTCR_UART (1U << 0)
+#define SPC5_UARTCR_WL (1U << 1)
+#define SPC5_UARTCR_PCE (1U << 2)
+#define SPC5_UARTCR_OP (1U << 3)
+#define SPC5_UARTCR_TXEN (1U << 4)
+#define SPC5_UARTCR_RXEN (1U << 5)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+
+struct spc5_linflex {
+
+ int16_t LINFLEX_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CCD :1;
+ vuint16_t CFD :1;
+ vuint16_t LASE :1;
+ vuint16_t AWUM :1;
+ vuint16_t MBL :4;
+ vuint16_t BF :1;
+ vuint16_t SFTM :1;
+ vuint16_t LBKM :1;
+ vuint16_t MME :1;
+ vuint16_t SBDT :1;
+ vuint16_t RBLM :1;
+ vuint16_t SLEEP :1;
+ vuint16_t INIT :1;
+ } B;
+ } LINCR1;
+
+ int16_t LINFLEX_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZIE :1;
+ vuint16_t OCIE :1;
+ vuint16_t BEIE :1;
+ vuint16_t CEIE :1;
+ vuint16_t HEIE :1;
+ vuint16_t :2;
+ vuint16_t FEIE :1;
+ vuint16_t BOIE :1;
+ vuint16_t LSIE :1;
+ vuint16_t WUIE :1;
+ vuint16_t DBFIE :1;
+ vuint16_t DBEIE :1;
+ vuint16_t DRIE :1;
+ vuint16_t DTIE :1;
+ vuint16_t HRIE :1;
+ } B;
+ } LINIER;
+
+ int16_t LINFLEX_reserved3;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LINS :4;
+ vuint16_t :2;
+ vuint16_t RMB :1;
+ vuint16_t :1;
+ vuint16_t RBSY :1;
+ vuint16_t RPS :1;
+ vuint16_t WUF :1;
+ vuint16_t DBFF :1;
+ vuint16_t DBEF :1;
+ vuint16_t DRF :1;
+ vuint16_t DTF :1;
+ vuint16_t HRF :1;
+ } B;
+ } LINSR;
+
+ int16_t LINFLEX_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF :1;
+ vuint16_t OCF :1;
+ vuint16_t BEF :1;
+ vuint16_t CEF :1;
+ vuint16_t SFEF :1;
+ vuint16_t BDEF :1;
+ vuint16_t IDPEF :1;
+ vuint16_t FEF :1;
+ vuint16_t BOF :1;
+ vuint16_t :6;
+ vuint16_t NF :1;
+ } B;
+ } LINESR;
+
+ int16_t LINFLEX_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t TDFL :2;
+ vuint16_t :1;
+ vuint16_t RDFL :2;
+ vuint16_t :4;
+ vuint16_t RXEN :1;
+ vuint16_t TXEN :1;
+ vuint16_t OP :1;
+ vuint16_t PCE :1;
+ vuint16_t WL :1;
+ vuint16_t UART :1;
+ } B;
+ } UARTCR;
+
+ int16_t LINFLEX_reserved6;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF :1;
+ vuint16_t OCF :1;
+ vuint16_t PE :4;
+ vuint16_t RMB :1;
+ vuint16_t FEF :1;
+ vuint16_t BOF :1;
+ vuint16_t RPS :1;
+ vuint16_t WUF :1;
+ vuint16_t :2;
+ vuint16_t DRF :1;
+ vuint16_t DTF :1;
+ vuint16_t NF :1;
+ } B;
+ } UARTSR;
+
+ int16_t LINFLEX_reserved7;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :5;
+ vuint16_t LTOM :1;
+ vuint16_t IOT :1;
+ vuint16_t TOCE :1;
+ vuint16_t CNT :8;
+ } B;
+ } LINTCSR;
+
+ int16_t LINFLEX_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OC2 :8;
+ vuint16_t OC1 :8;
+ } B;
+ } LINOCR;
+
+ int16_t LINFLEX_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :4;
+ vuint16_t RTO :4;
+ vuint16_t :1;
+ vuint16_t HTO :7;
+ } B;
+ } LINTOCR;
+
+ int16_t LINFLEX_reserved10;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t DIV_F :4;
+ } B;
+ } LINFBRR;
+
+ int16_t LINFLEX_reserved11;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DIV_M :13;
+ } B;
+ } LINIBRR;
+
+ int16_t LINFLEX_reserved12;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t CF :8;
+ } B;
+ } LINCFR;
+
+ int16_t LINFLEX_reserved13;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t IOBE :1;
+ vuint16_t IOPE :1;
+ vuint16_t WURQ :1;
+ vuint16_t DDRQ :1;
+ vuint16_t DTRQ :1;
+ vuint16_t ABRQ :1;
+ vuint16_t HTRQ :1;
+ vuint16_t :8;
+ } B;
+ } LINCR2;
+
+ int16_t LINFLEX_reserved14;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DFL :6;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } BIDR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3 :8;
+ vuint32_t DATA2 :8;
+ vuint32_t DATA1 :8;
+ vuint32_t DATA0 :8;
+ } B;
+ } BDRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7 :8;
+ vuint32_t DATA6 :8;
+ vuint32_t DATA5 :8;
+ vuint32_t DATA4 :8;
+ } B;
+ } BDRM;
+
+ int16_t LINFLEX_reserved15;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t FACT :8;
+ } B;
+ } IFER;
+
+ int16_t LINFLEX_reserved16;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t IFMI :4;
+ } B;
+ } IFMI;
+
+ int16_t LINFLEX_reserved17;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :12;
+ vuint16_t IFM :4;
+ } B;
+ } IFMR;
+
+ int16_t LINFLEX_reserved18;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR0;
+
+ int16_t LINFLEX_reserved19;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR1;
+
+ int16_t LINFLEX_reserved20;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR2;
+
+ int16_t LINFLEX_reserved21;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR3;
+
+ int16_t LINFLEX_reserved22;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR4;
+
+ int16_t LINFLEX_reserved23;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR5;
+
+ int16_t LINFLEX_reserved24;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR6;
+
+ int16_t LINFLEX_reserved25;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t :3;
+ vuint16_t DFL :3;
+ vuint16_t DIR :1;
+ vuint16_t CCS :1;
+ vuint16_t :2;
+ vuint16_t ID :6;
+ } B;
+ } IFCR7;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/**
+ * @name LINFlex units references
+ * @{
+ */
+#if defined(_SPC570Sxx_)
+/* Locations for SPC570Sxx devices.*/
+#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE8C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFBE8C000UL)
+#endif
+
+#elif defined(_SPC57EMxx_)
+/* Locations for SPC57EMxx devices.*/
+#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE8C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFFE90000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xFBE8C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX14 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX14 (*(struct spc5_linflex *)0xFFEA8000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX15 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX15 (*(struct spc5_linflex *)0xFBEA8000UL)
+#endif
+
+#elif defined(_SPC58NExx_) || defined(_SPC58ECxx_)
+/* Locations for _SPC58NExx_ and _SPC58ECxx_ devices.*/
+#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xF7E8C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFBE8C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xF7E90000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX3 (*(struct spc5_linflex *)0xFBE90000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX4 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX4 (*(struct spc5_linflex *)0xF7E94000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX5 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX5 (*(struct spc5_linflex *)0xFBE94000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX6 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX6 (*(struct spc5_linflex *)0xF7E98000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX7 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX7 (*(struct spc5_linflex *)0xFBE98000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX8 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX8 (*(struct spc5_linflex *)0x0xF7E9C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX9 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX9 (*(struct spc5_linflex *)0xFBE9C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX10 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX10 (*(struct spc5_linflex *)xF7EA0000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX11 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX11 (*(struct spc5_linflex *)0xFBEA0000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX12 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX12 (*(struct spc5_linflex *)0xF7EA4000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX13 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX13 (*(struct spc5_linflex *)0xFBEA4000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX14 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX14 (*(struct spc5_linflex *)0xFFEA8000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX15 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX15 (*(struct spc5_linflex *)0xFBEA8000UL)
+#endif
+
+#else /* !defined(_SPC570Sxx_) && !defined(_SPC57EMxx_) */
+/* Default locations for SPC56x devices.*/
+#if SPC5_HAS_LINFLEX0 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX0 (*(struct spc5_linflex *)0xFFE40000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX1 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX1 (*(struct spc5_linflex *)0xFFE44000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX2 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX2 (*(struct spc5_linflex *)0xFFE48000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX3 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX3 (*(struct spc5_linflex *)0xFFE4C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX4 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX4 (*(struct spc5_linflex *)0xFFE50000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX5 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX5 (*(struct spc5_linflex *)0xFFE54000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX6 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX6 (*(struct spc5_linflex *)0xFFE58000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX7 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX7 (*(struct spc5_linflex *)0xFFE5C000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX8 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX8 (*(struct spc5_linflex *)0xFFFB0000UL)
+#endif
+
+#if SPC5_HAS_LINFLEX9 || defined(__DOXYGEN__)
+#define SPC5_LINFLEX9 (*(struct spc5_linflex *)0xFFFB4000UL)
+#endif
+
+#endif /* !defined(_SPC57EMxx_) */
+
+/** @} */
+
+#endif /* _SPC5_LINFLEX_H_ */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.c b/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.c new file mode 100644 index 000000000..07d14556f --- /dev/null +++ b/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.c @@ -0,0 +1,177 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/SIUL_v1/hal_pal_lld.c
+ * @brief SPC5xx SIUL low level driver code.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief Event records (to be implemented).
+ */
+palevent_t _pal_events[1];
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#if defined(SPC5_SIUL_SYSTEM_PINS)
+static const unsigned system_pins[] = {SPC5_SIUL_SYSTEM_PINS};
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5xx I/O ports configuration.
+ *
+ * @param[in] config the SPC5xx ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+ unsigned i;
+
+#if defined(SPC5_SIUL_PCTL)
+ /* SIUL clock gating if present.*/
+ halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+#endif
+
+ /* Initialize PCR registers for undefined pads.*/
+ for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) {
+#if defined(SPC5_SIUL_SYSTEM_PINS)
+ /* Handling the case where some SIU pins are not meant to be reprogrammed,
+ for example JTAG pins.*/
+ unsigned j;
+ for (j = 0; j < sizeof system_pins; j++) {
+ if (i == system_pins[j])
+ goto skip;
+ }
+ SIU.PCR[i].R = config->default_mode;
+skip:
+ ;
+#else
+ SIU.PCR[i].R = config->default_mode;
+#endif
+ }
+
+ /* Initialize PADSEL registers.*/
+ for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++)
+ SIU.PSMI[i].R = config->padsels[i];
+
+ /* Initialize PCR registers for defined pads.*/
+ i = 0;
+ while (config->inits[i].pcr_index != -1) {
+ SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
+ SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value;
+ i++;
+ }
+}
+
+/**
+ * @brief Reads a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+ioportmask_t _pal_lld_readgroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset) {
+
+ (void)port;
+ (void)mask;
+ (void)offset;
+ return 0;
+}
+
+/**
+ * @brief Writes a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+void _pal_lld_writegroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset,
+ ioportmask_t bits) {
+
+ (void)port;
+ (void)mask;
+ (void)offset;
+ (void)bits;
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+ unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
+ ioportmask_t m1 = 0x8000;
+ while (m1) {
+ if (mask & m1)
+ SIU.PCR[pcr_index].R = mode;
+ m1 >>= 1;
+ ++pcr_index;
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.h b/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.h new file mode 100644 index 000000000..d7871701e --- /dev/null +++ b/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.h @@ -0,0 +1,471 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/SIUL_v1/hal_pal_lld.h
+ * @brief SPC5xx SIUL low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#undef PAL_MODE_RESET
+#undef PAL_MODE_UNCONNECTED
+#undef PAL_MODE_INPUT
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_PUSHPULL
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/**
+ * @name SIUL-specific PAL modes
+ * @{
+ */
+#define PAL_SPC5_SMC (1U << 14)
+#define PAL_SPC5_APC (1U << 13)
+#define PAL_SPC5_PA_MASK (7U << 10)
+#define PAL_SPC5_PA(n) ((n) << 10)
+#define PAL_SPC5_OBE (1U << 9)
+#define PAL_SPC5_IBE (1U << 8)
+#define PAL_SPC5_ODE (1U << 5)
+#define PAL_SPC5_SRC (1U << 2)
+#define PAL_SPC5_WPE (1U << 1)
+#define PAL_SPC5_WPS (1U << 0)
+/** @} */
+
+/**
+ * @name Pads mode constants
+ * @{
+ */
+/**
+ * @brief After reset state.
+ */
+#define PAL_MODE_RESET 0
+
+/**
+ * @brief Safe state for <b>unconnected</b> pads.
+ */
+#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS)
+
+/**
+ * @brief Regular input high-Z pad.
+ */
+#define PAL_MODE_INPUT (PAL_SPC5_IBE)
+
+/**
+ * @brief Input pad with weak pull up resistor.
+ */
+#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE | PAL_SPC5_WPE | \
+ PAL_SPC5_WPS)
+
+/**
+ * @brief Input pad with weak pull down resistor.
+ */
+#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE | PAL_SPC5_WPE)
+
+/**
+ * @brief Analog input mode.
+ */
+#define PAL_MODE_INPUT_ANALOG PAL_SPC5_APC
+
+/**
+ * @brief Push-pull output pad.
+ */
+#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE)
+
+/**
+ * @brief Open-drain output pad.
+ */
+#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \
+ PAL_SPC5_ODE)
+
+/**
+ * @brief Alternate "n" output pad.
+ * @note Both the IBE and OBE bits are specified in this mask, the OBE
+ * bit is not required for some PCRs but in that case it is
+ * ignored.
+ */
+#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \
+ PAL_SPC5_PA(n))
+/** @} */
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint16_t ioportmask_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint16_t iomode_t;
+
+/**
+ * @brief Type of an I/O line.
+ */
+typedef uint32_t ioline_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef uint32_t ioportid_t;
+
+/**
+ * @brief Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
+/**
+ * @brief SIUL register initializer type.
+ */
+typedef struct {
+ int32_t pcr_index;
+ uint8_t gpdo_value;
+ iomode_t pcr_value;
+} spc_siu_init_t;
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ iomode_t default_mode;
+ const spc_siu_init_t *inits;
+ const uint8_t *padsels;
+} PALConfig;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief I/O port A identifier.
+ */
+#define PORT_A 0
+
+/**
+ * @brief I/O port B identifier.
+ */
+#define PORT_B 1
+
+/**
+ * @brief I/O port C identifier.
+ */
+#define PORT_C 2
+
+/**
+ * @brief I/O port D identifier.
+ */
+#define PORT_D 3
+
+/**
+ * @brief I/O port E identifier.
+ */
+#define PORT_E 4
+
+/**
+ * @brief I/O port F identifier.
+ */
+#define PORT_F 5
+
+/**
+ * @brief I/O port G identifier.
+ */
+#define PORT_G 6
+
+/**
+ * @brief I/O port H identifier.
+ */
+#define PORT_H 7
+
+/**
+ * @brief I/O port I identifier.
+ */
+#define PORT_I 8
+
+/**
+ * @brief I/O port J identifier.
+ */
+#define PORT_J 9
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Port bit helper macro.
+ * @note Overrides the one in @p pal.h.
+ *
+ * @param[in] n bit position within the port
+ *
+ * @return The bit mask.
+ */
+#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) \
+ (((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
+
+/**
+ * @brief Reads a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset) \
+ _pal_lld_readgroup(port, mask, offset)
+
+/**
+ * @brief Writes a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) \
+ _pal_lld_writegroup(port, mask, offset, bits)
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) \
+ (SIU.GPDI[((port) * 16) + (pad)].R)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = (bit))
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = 1)
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = 0)
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R)
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+#define pal_lld_setpadmode(port, pad, mode)
+
+/**
+ * @brief Returns a PAL event structure associated to a pad.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_get_pad_event(port, pad) \
+ &_pal_events[0]; (void)(port); (void)pad
+
+/**
+ * @brief Returns a PAL event structure associated to a line.
+ *
+ * @param[in] line line identifier
+ *
+ * @notapi
+ */
+#define pal_lld_get_line_event(line) \
+ &_pal_events[0]; (void)line
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+extern palevent_t _pal_events[1];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ ioportmask_t _pal_lld_readgroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset);
+ void _pal_lld_writegroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset,
+ ioportmask_t bits);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* HAL_PAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/SIU_v1/hal_pal_lld.c b/os/hal/ports/SPC5/LLD/SIU_v1/hal_pal_lld.c new file mode 100644 index 000000000..31412d473 --- /dev/null +++ b/os/hal/ports/SPC5/LLD/SIU_v1/hal_pal_lld.c @@ -0,0 +1,144 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/SIU_v1/hal_pal_lld.c
+ * @brief SPC5xx SIU low level driver code.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+#if defined(SPC5_SIU_SYSTEM_PINS)
+static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS};
+#endif
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5xx I/O ports configuration.
+ *
+ * @param[in] config the SPC5xx ports configuration
+ *
+ * @notapi
+ */
+void _pal_lld_init(const PALConfig *config) {
+ unsigned i;
+
+ /* Initialize PCR registers for defined pads.*/
+ i = 0;
+ while (config->inits[i].pcr_index != -1) {
+ SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
+ SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value;
+ i++;
+ }
+}
+
+/**
+ * @brief Reads a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+ioportmask_t _pal_lld_readgroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset) {
+
+ (void)port;
+ (void)mask;
+ (void)offset;
+ return 0;
+}
+
+/**
+ * @brief Writes a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+void _pal_lld_writegroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset,
+ ioportmask_t bits) {
+
+ (void)port;
+ (void)mask;
+ (void)offset;
+ (void)bits;
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @notapi
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode) {
+ unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
+ ioportmask_t m1 = 0x8000;
+ while (m1) {
+ if (mask & m1)
+ SIU.PCR[pcr_index].R = mode;
+ m1 >>= 1;
+ ++pcr_index;
+ }
+}
+
+#endif /* HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/SIU_v1/hal_pal_lld.h b/os/hal/ports/SPC5/LLD/SIU_v1/hal_pal_lld.h new file mode 100644 index 000000000..5a256e88c --- /dev/null +++ b/os/hal/ports/SPC5/LLD/SIU_v1/hal_pal_lld.h @@ -0,0 +1,448 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/SIU_v1/hal_pal_lld.h
+ * @brief SPC5xx SIU low level driver header.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#ifndef HAL_PAL_LLD_H
+#define HAL_PAL_LLD_H
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#undef PAL_MODE_RESET
+#undef PAL_MODE_UNCONNECTED
+#undef PAL_MODE_INPUT
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_PUSHPULL
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/**
+ * @name SIU-specific PAL modes
+ * @{
+ */
+#define PAL_SPC5_PA_MASK (15U << 10)
+#define PAL_SPC5_PA_GPIO (0U << 10)
+#define PAL_SPC5_PA_PRIMARY PAL_SPC5_PA(0)
+#define PAL_SPC5_PA(n) ((1U << (n)) << 10)
+#define PAL_SPC5_OBE (1U << 9)
+#define PAL_SPC5_IBE (1U << 8)
+#define PAL_SPC5_DSC_MASK (3U << 6)
+#define PAL_SPC5_DSC_10PF (0U << 6)
+#define PAL_SPC5_DSC_20PF (1U << 6)
+#define PAL_SPC5_DSC_30PF (2U << 6)
+#define PAL_SPC5_DSC_50PF (3U << 6)
+#define PAL_SPC5_ODE (1U << 5)
+#define PAL_SPC5_HYS (1U << 4)
+#define PAL_SPC5_SRC_MASK (3U << 2)
+#define PAL_SPC5_SRC_MIN (0U << 2)
+#define PAL_SPC5_SRC_MID (1U << 2)
+#define PAL_SPC5_SRC_MAX (3U << 2)
+#define PAL_SPC5_WPE (1U << 1)
+#define PAL_SPC5_WPS (1U << 0)
+/** @} */
+
+/**
+ * @name Pads mode constants
+ * @{
+ */
+/**
+ * @brief After reset state.
+ */
+#define PAL_MODE_RESET 0
+
+/**
+ * @brief Safe state for <b>unconnected</b> pads.
+ */
+#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS)
+
+/**
+ * @brief Regular input high-Z pad.
+ */
+#define PAL_MODE_INPUT (PAL_SPC5_IBE)
+
+/**
+ * @brief Input pad with weak pull up resistor.
+ */
+#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE | PAL_SPC5_WPE | \
+ PAL_SPC5_WPS)
+
+/**
+ * @brief Input pad with weak pull down resistor.
+ */
+#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE | PAL_SPC5_WPE)
+
+/**
+ * @brief Push-pull output pad.
+ */
+#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE)
+
+/**
+ * @brief Open-drain output pad.
+ */
+#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \
+ PAL_SPC5_ODE)
+
+/**
+ * @brief Primary function input pad.
+ * @note Both the IBE and OBE bits are specified in this mask.
+ */
+#define PAL_MODE_INPUT_ALTERNATE_PRIMARY \
+ PAL_MODE_INPUT_ALTERNATE(0)
+
+/**
+ * @brief Alternate function input pad.
+ * @note Both the IBE and OBE bits are specified in this mask.
+ */
+#define PAL_MODE_INPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_PA(n))
+
+/**
+ * @brief Primary function output pad.
+ * @note Both the IBE and OBE bits are specified in this mask.
+ */
+#define PAL_MODE_OUTPUT_ALTERNATE_PRIMARY \
+ PAL_MODE_OUTPUT_ALTERNATE(0)
+
+/**
+ * @brief Alternate function output pad.
+ * @note Both the IBE and OBE bits are specified in this mask.
+ */
+#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \
+ PAL_SPC5_PA(n))
+/** @} */
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 16
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint16_t ioportmask_t;
+
+/**
+ * @brief Port Identifier.
+ * @details This type can be a scalar or some kind of pointer, do not make
+ * any assumption about it, use the provided macros when populating
+ * variables of this type.
+ */
+typedef uint32_t ioportid_t;
+
+/**
+ * @brief Digital I/O modes.
+ */
+typedef uint16_t iomode_t;
+
+/**
+ * @brief SIU/SIUL register initializer type.
+ */
+typedef struct {
+ int32_t pcr_index;
+ uint8_t gpdo_value;
+ iomode_t pcr_value;
+} spc_siu_init_t;
+
+/**
+ * @brief Generic I/O ports static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note Implementations may extend this structure to contain more,
+ * architecture dependent, fields.
+ */
+typedef struct {
+ const spc_siu_init_t *inits;
+} PALConfig;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @name Port identifiers
+ * @{
+ */
+#define PORT0 0
+#define PORT1 1
+#define PORT2 2
+#define PORT3 3
+#define PORT4 4
+#define PORT5 5
+#define PORT6 6
+#define PORT7 7
+#define PORT8 8
+#define PORT9 9
+#define PORT10 10
+#define PORT11 11
+#define PORT12 12
+#define PORT13 13
+#define PORT14 14
+#define PORT15 15
+#define PORT16 16
+#define PORT17 17
+#define PORT18 18
+#define PORT19 19
+#define PORT20 20
+#define PORT21 21
+#define PORT22 22
+#define PORT23 23
+#define PORT24 24
+#define PORT25 25
+#define PORT26 26
+#define PORT27 27
+#define PORT28 28
+#define PORT29 29
+#define PORT30 30
+#define PORT31 31
+/** @} */
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Port bit helper macro.
+ * @note Overrides the one in @p pal.h.
+ *
+ * @param[in] n bit position within the port
+ *
+ * @return The bit mask.
+ */
+#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n)))
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ *
+ * @notapi
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__)
+/**
+ * @brief Reads the physical I/O port states.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ *
+ * @notapi
+ */
+#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port])
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port])
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ *
+ * @notapi
+ */
+#define pal_lld_writeport(port, bits) \
+ (((volatile uint16_t *)SIU.PGPDO)[port] = (bits))
+
+/**
+ * @brief Reads a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ *
+ * @notapi
+ */
+#define pal_lld_readgroup(port, mask, offset) \
+ _pal_lld_readgroup(port, mask, offset)
+
+/**
+ * @brief Writes a group of bits.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ *
+ * @notapi
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) \
+ _pal_lld_writegroup(port, mask, offset, bits)
+
+#endif /* SPC5_SIU_SUPPORTS_PORTS */
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] mode group mode
+ *
+ * @notapi
+ */
+#define pal_lld_setgroupmode(port, mask, offset, mode) \
+ _pal_lld_setgroupmode(port, mask << offset, mode)
+
+/**
+ * @brief Reads a logical state from an I/O pad.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @return The logical state.
+ * @retval PAL_LOW low logical state.
+ * @retval PAL_HIGH high logical state.
+ *
+ * @notapi
+ */
+#define pal_lld_readpad(port, pad) \
+ (SIU.GPDI[((port) * 16) + (pad)].R)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ *
+ * @notapi
+ */
+#define pal_lld_writepad(port, pad, bit) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = (bit))
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_setpad(port, pad) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = 1)
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_clearpad(port, pad) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = 0)
+
+/**
+ * @brief Toggles a pad logical state.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_togglepad(port, pad) \
+ (SIU.GPDO[((port) * 16) + (pad)].R = ~SIU.GPDO[((port) * 16) + (pad)].R)
+
+/**
+ * @brief Pad mode setup.
+ * @details This function programs a pad with the specified mode.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[in] mode pad mode
+ *
+ * @notapi
+ */
+#define pal_lld_setpadmode(port, pad, mode)
+
+extern const PALConfig pal_default_config;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ ioportmask_t _pal_lld_readgroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset);
+ void _pal_lld_writegroup(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t offset,
+ ioportmask_t bits);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ iomode_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PAL */
+
+#endif /* HAL_PAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.c b/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.c new file mode 100644 index 000000000..36ec49bfb --- /dev/null +++ b/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.c @@ -0,0 +1,94 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/hal_st_lld.c
+ * @brief ST Driver subsystem low level driver code.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#include "hal.h"
+
+#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if defined(SPC5_USE_STM) || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(STM_HANDLER) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ if (SPC5_STM_UNIT->CH[0].CIR.CIF != 0U) {
+ SPC5_STM_UNIT->CH[0].CIR.CIF = 1U;
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+ }
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level ST driver initialization.
+ *
+ * @notapi
+ */
+void st_lld_init(void) {
+
+#if defined(SPC5_USE_STM)
+ SPC5_STM_UNIT->CNT = 0;
+ SPC5_STM_UNIT->CH[0].CCR = 0;
+ SPC5_STM_UNIT->CH[1].CCR = 0;
+ SPC5_STM_UNIT->CH[2].CCR = 0;
+ SPC5_STM_UNIT->CH[3].CCR = 0;
+ SPC5_STM_UNIT->CR.R = STM_CR_CNT(SPC5_STM_CPL_VALUE - 1) |
+ STM_CR_FRZ | STM_CR_TEN;
+#endif
+}
+
+#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.h b/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.h new file mode 100644 index 000000000..53cd7cc8b --- /dev/null +++ b/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.h @@ -0,0 +1,200 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC5xx/STMv1/hal_st_lld.h
+ * @brief ST Driver subsystem low level driver header.
+ * @details This header is designed to be include-able without having to
+ * include other files from the HAL.
+ *
+ * @addtogroup ST
+ * @{
+ */
+
+#ifndef HAL_ST_LLD_H
+#define HAL_ST_LLD_H
+
+#include "mcuconf.h"
+#include "spc5_registry.h"
+#include "registers.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name STM CR register definitions.
+ * @{
+ */
+#define STM_CR_CNT_MASK (255U << 8U)
+#define STM_CR_CNT(n) ((n) << 8U)
+#define STM_CR_FRZ (1U << 1U)
+#define STM_CR_TEN (1U << 0U)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief STM unit to be used by the ST driver.
+ */
+#if !defined(SPC5_STM_UNIT) || defined(__DOXYGEN__)
+#define SPC5_STM_UNIT STM_2
+#endif
+
+/**
+ * @brief SysTick timer IRQ priority.
+ */
+#if !defined(SPC5_STM_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_STM_IRQ_PRIORITY 8
+#endif
+
+/**
+ * @brief Counter clock to be programmed in the STM unit.
+ */
+#if !defined(SPC5_STM_CNT_CLOCK) || defined(__DOXYGEN__)
+#define SPC5_STM_CNT_CLOCK 8000000U
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if 0
+#if !defined(STM_HANDLER)
+#error "STM_HANDLER not defined in registry"
+#endif
+
+#if !defined(SPC5_STM_CLK)
+#error "SPC5_STM_CLK not defined in registry"
+#endif
+
+/**
+ * @brief Prescaler value.
+ */
+#define SPC5_STM_CPL_VALUE (SPC5_STM_CLK / SPC5_STM_CNT_CLOCK)
+
+#if (SPC5_STM_CPL_VALUE * SPC5_STM_CNT_CLOCK) != SPC5_STM_CLK
+#error "SPC5_STM_CNT_CLOCK is invalid"
+#endif
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void st_lld_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Driver inline functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the time counter value.
+ *
+ * @return The counter value.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_counter(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Starts the alarm.
+ * @note Makes sure that no spurious alarms are triggered after
+ * this call.
+ *
+ * @param[in] time the time to be set for the first alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_start_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Stops the alarm interrupt.
+ *
+ * @notapi
+ */
+static inline void st_lld_stop_alarm(void) {
+
+}
+
+/**
+ * @brief Sets the alarm time.
+ *
+ * @param[in] time the time to be set for the next alarm
+ *
+ * @notapi
+ */
+static inline void st_lld_set_alarm(systime_t time) {
+
+ (void)time;
+}
+
+/**
+ * @brief Returns the current alarm time.
+ *
+ * @return The currently set alarm time.
+ *
+ * @notapi
+ */
+static inline systime_t st_lld_get_alarm(void) {
+
+ return (systime_t)0;
+}
+
+/**
+ * @brief Determines if the alarm is active.
+ *
+ * @return The alarm status.
+ * @retval false if the alarm is not active.
+ * @retval true is the alarm is active
+ *
+ * @notapi
+ */
+static inline bool st_lld_is_alarm_active(void) {
+
+ return false;
+}
+
+#endif /* HAL_ST_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC560BCxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..43c316aa7 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/cfg/mcuconf.h.ftl @@ -0,0 +1,236 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2014 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC560B/Cxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ */
+
+#define SPC560BCxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+#define SPC5_XOSCDIV_VALUE ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
+#define SPC5_IRCDIV_VALUE ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+#define SPC5_EMIOS0_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
+#define SPC5_EMIOS1_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios1_global_prescaler.value[0]?number}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX2 ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX3 ${(conf.instance.linflex_settings.linflex3.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+#define SPC5_SERIAL_LINFLEX2_PRIORITY ${conf.instance.irq_priority_settings.linflex2.value[0]}
+#define SPC5_SERIAL_LINFLEX3_PRIORITY ${conf.instance.irq_priority_settings.linflex3.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_NONE
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+
+/*
+ * ICU-PWM driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS0_CH0 ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH1 ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH2 ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH3 ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH4 ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH5 ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH6 ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH7 ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH24 ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS0_GROUP0 ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS0_GROUP1 ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
+
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
+
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_EMIOS1_CH24 ${conf.instance.emios_settings.emios1_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS1_GROUP0 ${conf.instance.emios_settings.emios1_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP1 ${conf.instance.emios_settings.emios1_group1.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP2 ${conf.instance.emios_settings.emios1_group2.value[0]?upper_case}
+
+#define SPC5_EMIOS1_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc0.value[0]}
+#define SPC5_EMIOS1_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc1.value[0]}
+#define SPC5_EMIOS1_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc2.value[0]}
+#define SPC5_EMIOS1_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc3.value[0]}
+#define SPC5_EMIOS1_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc4.value[0]}
+#define SPC5_EMIOS1_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc5.value[0]}
+#define SPC5_EMIOS1_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc6.value[0]}
+#define SPC5_EMIOS1_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc7.value[0]}
+#define SPC5_EMIOS1_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc8.value[0]}
+#define SPC5_EMIOS1_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc9.value[0]}
+#define SPC5_EMIOS1_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc10.value[0]}
+#define SPC5_EMIOS1_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc11.value[0]}
+#define SPC5_EMIOS1_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc12.value[0]}
+
+#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
+#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN3 ${conf.instance.flexcan_settings.flexcan3.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan3_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_PRIORITY ${conf.instance.irq_priority_settings.flexcan3.value[0]}
+#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN4 ${conf.instance.flexcan_settings.flexcan4.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan4_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_PRIORITY ${conf.instance.irq_priority_settings.flexcan4.value[0]}
+#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN5 ${conf.instance.flexcan_settings.flexcan5.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan5_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_PRIORITY ${conf.instance.irq_priority_settings.flexcan5.value[0]}
+#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
+#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
+#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
+#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/hal_lld.c b/os/hal/ports/SPC5/SPC560BCxx/hal_lld.c new file mode 100644 index 000000000..9d053ac92 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/hal_lld.c @@ -0,0 +1,276 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.c
+ * @brief SPC560B/Cxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief PIT channel 0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector59) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ /* Resets the PIT channel 0 IRQ flag.*/
+ PIT.CH[0].TFLG.R = 1;
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t reg;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
+ to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
+ modes.*/
+ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
+ halSPCSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+ reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
+ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
+ PIT.CH[0].LDVAL.R = reg;
+ PIT.CH[0].CVAL.R = reg;
+ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
+ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
+}
+
+/**
+ * @brief SPC560B/Cxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.S_FIRC)
+ ;
+
+#if !SPC5_NO_INIT
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* Oscillators dividers setup.*/
+ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
+ CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.OSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
+ CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
+ CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
+
+ /* Run modes initialization.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
+ if (ME.IS.B.I_CONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
+ CFLASH.PFCR0.B.BK0_APC = 2;
+ CFLASH.PFCR0.B.BK0_RWSC = 2;
+
+ /* CMU clock enable */
+ halSPCSetPeripheralClockMode(104,
+ SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2));
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.S_SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_DIVIRC:
+ return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_DIVXOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/hal_lld.h b/os/hal/ports/SPC5/SPC560BCxx/hal_lld.h new file mode 100644 index 000000000..874a5e050 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/hal_lld.h @@ -0,0 +1,779 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.h
+ * @brief SPC560B/Cxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC560B/Cxx Car Body and Convenience"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 16000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MAX 40000
+
+/**
+ * @brief Minimum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MIN 32000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 64000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 64000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
+ oscillator. */
+#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
+ oscillator. */
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (1U << 1)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+#define SPC5_ME_ME_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_LP (2U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+#define SPC5_ME_LP_PC_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 1
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief XOSC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Fast IRC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0 | \
+ SPC5_ME_ME_STANDBY0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STANDBY0 mode settings.
+ */
+#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0 | \
+ SPC5_ME_LP_PC_STANDBY0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief PIT channel 0 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC560BCxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on the XOSC divider.*/
+#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
+#error "invalid SPC5_XOSCDIV_VALUE value specified"
+#endif
+
+/* Check on the IRC divider.*/
+#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
+#error "invalid SPC5_IRCDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*#include "spc5_edma.h"*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/platform.mk b/os/hal/ports/SPC5/SPC560BCxx/platform.mk new file mode 100644 index 000000000..b14723d62 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/platform.mk @@ -0,0 +1,22 @@ +# List of all the SPC560BCxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560BCxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/spc5_emios.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560BCxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC560BCxx/registers.h b/os/hal/ports/SPC5/SPC560BCxx/registers.h new file mode 100644 index 000000000..7d585520c --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc560bc.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/spc5_registry.h b/os/hal/ports/SPC5/SPC560BCxx/spc5_registry.h new file mode 100644 index 000000000..4f4a8d260 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/spc5_registry.h @@ -0,0 +1,419 @@ +/*
+ SPC5 HAL - Copyright (C) 2014 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/spc5_registry.h
+ * @brief SPC560B/Cxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560B/Cxx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_DSPI_FIFO_DEPTH 4
+
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI2_RFDF_HANDLER vector118
+#define SPC5_DSPI2_RFDF_NUMBER 118
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+
+#define SPC5_HAS_DSPI3 FALSE
+#define SPC5_HAS_DSPI4 FALSE
+#define SPC5_HAS_DSPI5 FALSE
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA FALSE
+
+/* LINFlex attributes.*/
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX2 TRUE
+#define SPC5_LINFLEX2_PCTL 50
+#define SPC5_LINFLEX2_RXI_HANDLER vector119
+#define SPC5_LINFLEX2_TXI_HANDLER vector120
+#define SPC5_LINFLEX2_ERR_HANDLER vector121
+#define SPC5_LINFLEX2_RXI_NUMBER 119
+#define SPC5_LINFLEX2_TXI_NUMBER 120
+#define SPC5_LINFLEX2_ERR_NUMBER 121
+#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX3 TRUE
+#define SPC5_LINFLEX3_PCTL 51
+#define SPC5_LINFLEX3_RXI_HANDLER vector122
+#define SPC5_LINFLEX3_TXI_HANDLER vector123
+#define SPC5_LINFLEX3_ERR_HANDLER vector124
+#define SPC5_LINFLEX3_RXI_NUMBER 122
+#define SPC5_LINFLEX3_TXI_NUMBER 123
+#define SPC5_LINFLEX3_ERR_NUMBER 124
+#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX4 FALSE
+#define SPC5_HAS_LINFLEX5 FALSE
+#define SPC5_HAS_LINFLEX6 FALSE
+#define SPC5_HAS_LINFLEX7 FALSE
+#define SPC5_HAS_LINFLEX8 FALSE
+#define SPC5_HAS_LINFLEX9 FALSE
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_PCTL 68
+#define SPC5_SIUL_NUM_PORTS 8
+#define SPC5_SIUL_NUM_PCRS 123
+#define SPC5_SIUL_NUM_PADSELS 32
+#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
+
+/* eMIOS attributes.*/
+#define SPC5_HAS_EMIOS0 TRUE
+#define SPC5_EMIOS0_PCTL 72
+#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
+#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
+#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
+#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
+#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
+#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
+#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
+#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
+#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
+#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
+#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
+#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
+#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
+#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
+#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
+#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
+#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
+#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
+#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
+#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
+#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
+#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
+#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
+#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
+#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
+#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
+#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
+#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
+
+#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS0_GPRE_VALUE)
+
+#define SPC5_HAS_EMIOS1 TRUE
+#define SPC5_EMIOS1_PCTL 73
+#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
+#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
+#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
+#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
+#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
+#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
+#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
+#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
+#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
+#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
+#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
+#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
+#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
+#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
+#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
+#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
+#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
+#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
+#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
+#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
+#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
+#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
+#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
+#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
+#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
+#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
+#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
+#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
+
+#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS1_GPRE_VALUE)
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 64
+#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
+#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
+#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN2 TRUE
+#define SPC5_FLEXCAN2_PCTL 18
+#define SPC5_FLEXCAN2_MB 64
+#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
+#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+
+#define SPC5_HAS_FLEXCAN3 TRUE
+#define SPC5_FLEXCAN3_PCTL 19
+#define SPC5_FLEXCAN3_MB 64
+#define SPC5_FLEXCAN3_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
+#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
+#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN4 TRUE
+#define SPC5_FLEXCAN4_PCTL 20
+#define SPC5_FLEXCAN4_MB 64
+#define SPC5_FLEXCAN4_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
+#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
+#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN5 TRUE
+#define SPC5_FLEXCAN5_PCTL 21
+#define SPC5_FLEXCAN5_MB 64
+#define SPC5_FLEXCAN5_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
+#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
+#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC TRUE
+
+#define SPC5_HAS_ADC0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR2 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR4 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR5 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL0 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL1 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL4 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL5 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 TRUE
+#define SPC5_ADC0_PCTL 32
+#define SPC5_ADC0_EOC_HANDLER vector62
+#define SPC5_ADC0_EOC_NUMBER 62
+#define SPC5_ADC0_WD_HANDLER vector64
+#define SPC5_ADC0_WD_NUMBER 64
+
+#define SPC5_HAS_ADC1 FALSE
+/** @} */
+
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/typedefs.h b/os/hal/ports/SPC5/SPC560BCxx/typedefs.h new file mode 100644 index 000000000..40c6506b1 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC560BCxx/xpc560bc.h b/os/hal/ports/SPC5/SPC560BCxx/xpc560bc.h new file mode 100644 index 000000000..30cdcb45f --- /dev/null +++ b/os/hal/ports/SPC5/SPC560BCxx/xpc560bc.h @@ -0,0 +1,3757 @@ +/*****************************************************************
+ *
+ * FILE : MPC5604B_0M27V_0100.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for:
+ * MPC5604B, mask set = 0M27V
+ * SPC560B4, mask set = FB50X20B
+ *
+ * COPYRIGHT :(c) 2009, Freescale & STMicroelectronics
+ *
+ * VERSION : 01.02
+ * DATE : 08 MAY 2009
+ * AUTHOR : b04629
+ * HISTORY : Original source taken from jdp_0100.h.
+ * Updated to be compatable with
+ * - MPC5604B Mask ID 0M27V
+ * - MPC5604B Reference Manual Rev 3 Draft A
+ * - SPC560B4 Mask ID FB50X20B
+ * - SPC560B4 Reference Manual Rev 3 Draft A
+ *
+ ******************************************************************/
+
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
+
+/*****************************************************************
+* Example instantiation and use:
+*
+* <MODULE>.<REGISTER>.B.<BIT> = 1;
+* <MODULE>.<REGISTER>.R = 0x10000000;
+*
+******************************************************************/
+
+#ifndef _MPC5604B_H_
+#define _MPC5604B_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+
+#endif /*
+ */
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif /*
+ */
+/****************************************************************************/
+/* MODULE : ADC */
+/****************************************************************************/
+ struct ADC_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t:4;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORTCHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACK0:1;
+ vuint32_t:4;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR; /* MAIN CONFIGURATION REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACK0:1;
+ vuint32_t:2;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR; /* MAIN STATUS REGISTER */
+
+ int32_t ADC_reserved1[2]; /* (0x010 - 0x008)/4 = 0x02 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR; /* INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH31:1;
+ vuint32_t EOC_CH30:1;
+ vuint32_t EOC_CH29:1;
+ vuint32_t EOC_CH28:1;
+ vuint32_t EOC_CH27:1;
+ vuint32_t EOC_CH26:1;
+ vuint32_t EOC_CH25:1;
+ vuint32_t EOC_CH24:1;
+ vuint32_t EOC_CH23:1;
+ vuint32_t EOC_CH22:1;
+ vuint32_t EOC_CH21:1;
+ vuint32_t EOC_CH20:1;
+ vuint32_t EOC_CH19:1;
+ vuint32_t EOC_CH18:1;
+ vuint32_t EOC_CH17:1;
+ vuint32_t EOC_CH16:1;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CEOCFR[3]; /* Channel Pending Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR; /* INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1;
+ vuint32_t CIM30:1;
+ vuint32_t CIM29:1;
+ vuint32_t CIM28:1;
+ vuint32_t CIM27:1;
+ vuint32_t CIM26:1;
+ vuint32_t CIM25:1;
+ vuint32_t CIM24:1;
+ vuint32_t CIM23:1;
+ vuint32_t CIM22:1;
+ vuint32_t CIM21:1;
+ vuint32_t CIM20:1;
+ vuint32_t CIM19:1;
+ vuint32_t CIM18:1;
+ vuint32_t CIM17:1;
+ vuint32_t CIM16:1;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR[3]; /* Channel Interrupt Mask Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t WDG3H:1;
+ vuint32_t WDG2H:1;
+ vuint32_t WDG1H:1;
+ vuint32_t WDG0H:1;
+ vuint32_t WDG3L:1;
+ vuint32_t WDG2L:1;
+ vuint32_t WDG1L:1;
+ vuint32_t WDG0L:1;
+ } B;
+ } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t MSKWDG3H:1;
+ vuint32_t MSKWDG2H:1;
+ vuint32_t MSKWDG1H:1;
+ vuint32_t MSKWDG0H:1;
+ vuint32_t MSKWDG3L:1;
+ vuint32_t MSKWDG2L:1;
+ vuint32_t MSKWDG1L:1;
+ vuint32_t MSKWDG0L:1;
+ } B;
+ } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER */
+
+ int32_t ADC_reserved2[6]; /* (0x050 - 0x038)/4 = 0x06 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t THREN:1;
+ vuint32_t THRINV:1;
+ vuint32_t:7;
+ vuint32_t THRCH:7;
+ } B;
+ } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR[4]; /* THRESHOLD REGISTER */
+
+ int32_t ADC_reserved3[4]; /* (0x080 - 0x070)/4 = 0x04 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR; /* PRESAMPLING CONTROL REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1;
+ vuint32_t PRES30:1;
+ vuint32_t PRES29:1;
+ vuint32_t PRES28:1;
+ vuint32_t PRES27:1;
+ vuint32_t PRES26:1;
+ vuint32_t PRES25:1;
+ vuint32_t PRES24:1;
+ vuint32_t PRES23:1;
+ vuint32_t PRES22:1;
+ vuint32_t PRES21:1;
+ vuint32_t PRES20:1;
+ vuint32_t PRES19:1;
+ vuint32_t PRES18:1;
+ vuint32_t PRES17:1;
+ vuint32_t PRES16:1;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR[3]; /* PRESAMPLING REGISTER */
+
+ int32_t ADC_reserved4[1]; /* (0x094 - 0x090)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR[3]; /* CONVERSION TIMING REGISTER */
+
+ int32_t ADC_reserved5[1]; /* (0x0A4 - 0x0A0)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER */
+
+ int32_t ADC_reserved6[1]; /* (0x0B4 - 0x0B0)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR[3]; /* Injected CONVERSION MASK REGISTER */
+
+ int32_t ADC_reserved7[1]; /* (0x0C4 - 0x0C0)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8;
+ } B;
+ } DSDR; /* DECODE SIGNALS DELAY REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR; /* POWER DOWN DELAY REGISTER */
+
+ int32_t ADC_reserved8[13]; /* (0x100 - 0x0CC)/4 = 0x0D */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:6;
+ vuint32_t CDATA:10;
+ } B;
+ } CDR[96]; /* Channel 0-95 Data REGISTER */
+
+ }; /* end of ADC_tag */
+/****************************************************************************/
+/* MODULE : CANSP */
+/****************************************************************************/
+ struct CANSP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RX_COMPLETE:1;
+ vuint32_t BUSY:1;
+ vuint32_t ACTIVE_CK:1;
+ vuint32_t:3;
+ vuint32_t MODE:1;
+ vuint32_t CAN_RX_SEL:3;
+ vuint32_t BRP:5;
+ vuint32_t CAN_SMPLR_EN:1;
+ } B;
+ } CR; /* CANSP Control Register */
+
+ union {
+ vuint32_t R;
+ } SR[12]; /* CANSP Sample Register 0 to 11 */
+
+ }; /* end of CANSP_tag */
+/****************************************************************************/
+/* MODULE : CFLASH */
+/****************************************************************************/
+ struct CFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:23;
+ vuint32_t HBLOCK:8;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t ADD:19;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ union { /* CFLASH Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK0_APC:5;
+ vuint32_t BK0_WWSC:5;
+ vuint32_t BK0_RWSC:5;
+ vuint32_t BK0_RWWC2:1;
+ vuint32_t BK0_RWWC1:1;
+ vuint32_t B0_P1_BCFG:2;
+ vuint32_t B0_P1_DPFE:1;
+ vuint32_t B0_P1_IPFE:1;
+ vuint32_t B0_P1_PFLM:2;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK0_RWWC0:1;
+ vuint32_t B0_P0_BCFG:2;
+ vuint32_t B0_P0_DPFE:1;
+ vuint32_t B0_P0_IPFE:1;
+ vuint32_t B0_P0_PFLM:2;
+ vuint32_t B0_P0_BFE:1;
+ } B;
+ } PFCR0;
+
+ union { /* CFLASH Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK1_APC:5;
+ vuint32_t BK1_WWSC:5;
+ vuint32_t BK1_RWSC:5;
+ vuint32_t BK1_RWWC2:1;
+ vuint32_t BK1_RWWC1:1;
+ vuint32_t:6;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK1_RWWC0:1;
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1;
+ } B;
+ } PFCR1;
+
+ union { /* cflash Access Protection Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t ARBM:2;
+ vuint32_t M7PFD:1;
+ vuint32_t M6PFD:1;
+ vuint32_t M5PFD:1;
+ vuint32_t M4PFD:1;
+ vuint32_t M3PFD:1;
+ vuint32_t M2PFD:1;
+ vuint32_t M1PFD:1;
+ vuint32_t M0PFD:1;
+ vuint32_t M7AP:2;
+ vuint32_t M6AP:2;
+ vuint32_t M5AP:2;
+ vuint32_t M4AP:2;
+ vuint32_t M3AP:2;
+ vuint32_t M2AP:2;
+ vuint32_t M1AP:2;
+ vuint32_t M0AP:2;
+ } B;
+ } FAPR;
+
+ int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of CFLASH_tag */
+/****************************************************************************/
+/* MODULE : CGM */
+/****************************************************************************/
+ struct CGM_tag {
+
+ /* The CGM provides a unified register interface, enabling access to
+
+ all clock sources:
+
+ Base Address | Clock Sources
+
+ -----------------------------
+
+ 0xC3FE0000 | FXOSC_CTL
+
+ ---------- | Reserved
+
+ 0xC3FE0040 | SXOSC_CTL
+
+ 0xC3FE0060 | FIRC_CTL
+
+ 0xC3FE0080 | SIRC_CTL
+
+ 0xC3FE00A0 | FMPLL_0
+
+ ---------- | Reserved
+
+ 0xC3FE0100 | CMU_0
+
+ */
+ /************************************/
+ /* FXOSC_CTL @ CGM base address + 0x0000 */
+ /************************************/
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:7;
+ } B;
+ } FXOSC_CTL; /* Fast OSC Control Register */
+
+ /************************************/
+ /* SXOSC_CTL @ CGM base address + 0x0040 */
+ /************************************/
+ int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } SXOSC_CTL; /* Slow OSC Control Register */
+
+ /************************************/
+ /* FIRC_CTL @ CGM base address + 0x0060 */
+ /************************************/
+ int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t RCTRIM:6;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:8;
+ } B;
+ } FIRC_CTL; /* Fast IRC Control Register */
+
+ /****************************************/
+ /* SIRC_CTL @ CGM base address + 0x0080 */
+ /****************************************/
+ int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t RCTRIM:5;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:3;
+ vuint32_t S_SIRC:1;
+ vuint32_t:3;
+ vuint32_t SIRCON_STDBY:1;
+ } B;
+ } SIRC_CTL; /* Slow IRC Control Register */
+
+ /*************************************/
+ /* FMPLL @ CGM base address + 0x00A0 */
+ /*************************************/
+ int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t IDF:4;
+ vuint32_t ODF:2;
+ vuint32_t:1;
+ vuint32_t NDIV:7;
+ vuint32_t:7;
+ vuint32_t EN_PLL_SW:1;
+ vuint32_t MODE:1;
+ vuint32_t UNLOCK_ONCE:1;
+ vuint32_t:1;
+ vuint32_t I_LOCK:1;
+ vuint32_t S_LOCK:1;
+ vuint32_t PLL_FAIL_MASK:1;
+ vuint32_t PLL_FAIL_FLAG:1;
+ vuint32_t:1;
+ } B;
+ } FMPLL_CR; /* FMPLL Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1;
+ vuint32_t:1;
+ vuint32_t SPRD_SEL:1;
+ vuint32_t MOD_PERIOD:13;
+ vuint32_t FM_EN:1;
+ vuint32_t INC_STEP:15;
+ } B;
+ } FMPLL_MR; /* FMPLL Modulation Register */
+
+ /************************************/
+ /* CMU @ CGM base address + 0x0100 */
+ /************************************/
+ int32_t CGM_reserved5[22]; /* (0x100 - 0x0A8)/4 = 0x16 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SFM:1;
+ vuint32_t:13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t:5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_CSR; /* Control Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t FD:20;
+ } B;
+ } CMU_FDR; /* Frequency Display Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HFREF_A:12;
+ } B;
+ } CMU_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t LFREF_A:12;
+ } B;
+ } CMU_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t FLCI_A:1;
+ vuint32_t FHHI_A:1;
+ vuint32_t FLLI_A:1;
+ vuint32_t OLRI:1;
+ } B;
+ } CMU_ISR; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CMU_IMR; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t MD:20;
+ } B;
+ } CMU_MDR; /* Measurement Duration Register */
+
+ /************************************/
+ /* CGM General Registers @ CGM base address + 0x0370 */
+ /************************************/
+ int32_t CGM_reserved7[149]; /* (0x370 - 0x11C)/4 = 0x95 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t EN:1;
+ } B;
+ } OC_EN; /* Output Clock Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t SELDIV:2;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } OCDS_SC; /* Output Clock Division Select Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELSTAT:4;
+ vuint32_t:24;
+ } B;
+ } SC_SS; /* System Clock Select Status */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DE:1;
+ vuint8_t:3;
+ vuint8_t DIV:4;
+ } B;
+ } SC_DC[3]; /* System Clock Divider Configuration 0->2 */
+
+ }; /* end of CGM_tag */
+/****************************************************************************/
+/* MODULE : CTU */
+/****************************************************************************/
+ struct CTU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t TRGIEN:1;
+ vuint32_t TRGI:1;
+ vuint32_t:6;
+ } B;
+ } CSR; /* Control Status Register */
+
+ int32_t CTU_reserved0[11]; /* (0x030 - 0x004)/4 = 0x0B */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TM:1;
+ vuint32_t:7;
+ vuint32_t CLR_FLAG:1;
+ vuint32_t:1;
+ vuint32_t CHANNELVALUE:6;
+ } B;
+ } EVTCFGR[64]; /* Event Configuration Register */
+
+ }; /* end of CTU_tag */
+/****************************************************************************/
+/* MODULE : DFLASH */
+/****************************************************************************/
+ struct DFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:23;
+ vuint32_t HBLOCK:8;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t ADD:19;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of Dflash_tag */
+/****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+ struct DSPI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t:2;
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t DOZE:1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t:7;
+ vuint32_t HALT:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ uint32_t dspi_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t:16;
+ } B;
+ } TCR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t:1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t:1;
+ vuint32_t TFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR; /* Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t:2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t:1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t:4;
+ vuint32_t RFOFRE:1;
+ vuint32_t:1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t:16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t:4;
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR; /* POP RX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_txf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[4]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_rxf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t:1;
+ vuint32_t MTOCNT:6;
+ vuint32_t:4;
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t:6;
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR; /* DSI Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SER_DATA:16;
+ } B;
+ } SDR; /* DSI Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ASER_DATA:16;
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t COMP_DATA:16;
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DESER_DATA:16;
+ } B;
+ } DDR; /* DSI deserialization Data Register */
+
+ }; /* end of DSPI_tag */
+/****************************************************************************/
+/* MODULE : ECSM */
+/****************************************************************************/
+ struct ECSM_tag {
+
+ union {
+ vuint16_t R;
+ } PCT; /* ECSM Processor Core Type Register */
+
+ union {
+ vuint16_t R;
+ } REV; /* ECSM Revision Register */
+
+ int32_t ECSM_reserved1;
+
+ union {
+ vuint32_t R;
+ } IMC; /* ECSM IPS Module Configuration Register */
+
+ int8_t ECSM_reserved2[7];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1;
+ vuint8_t:3;
+ vuint8_t PRILVL:4;
+ } B;
+ } MWCR; /* ECSM Miscellaneous Wakeup Control Register */
+
+ int32_t ECSM_reserved3[2];
+ int8_t ECSM_reserved4[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1;
+ vuint8_t FB0SI:1;
+ vuint8_t FB1AI:1;
+ vuint8_t FB1SI:1;
+ vuint8_t:4;
+ } B;
+ } MIR; /* ECSM Miscellaneous Interrupt Register */
+
+ int32_t ECSM_reserved5;
+
+ union {
+ vuint32_t R;
+ } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */
+
+ int32_t ECSM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */
+ int8_t ECSM_reserved7[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t:2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR; /* ECSM ECC Configuration Register */
+
+ int8_t ECSM_reserved8[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t:2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR; /* ECSM ECC Status Register */
+
+ int16_t ECSM_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t:2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t:1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR; /* ECSM ECC Error Generation Register */
+
+ int32_t ECSM_reserved10;
+
+ union {
+ vuint32_t R;
+ } FEAR; /* ECSM Flash ECC Address Register */
+
+ int16_t ECSM_reserved11;
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR; /* ECSM Flash ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } FEAT; /* ECSM Flash ECC Attributes Register */
+
+ int32_t ECSM_reserved12;
+
+ union {
+ vuint32_t R;
+ } FEDR; /* ECSM Flash ECC Data Register */
+
+ union {
+ vuint32_t R;
+ } REAR; /* ECSM RAM ECC Address Register */
+
+ int8_t ECSM_reserved13;
+
+ union {
+ vuint8_t R;
+ } RESR; /* ECSM RAM ECC Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR; /* ECSM RAM ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } REAT; /* ECSM RAM ECC Attributes Register */
+
+ int32_t ECSM_reserved14;
+
+ union {
+ vuint32_t R;
+ } REDR; /* ECSM RAM ECC Data Register */
+
+ }; /* end of ECSM_tag */
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+ struct EMIOS_CHANNEL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CADR:16;
+ } B;
+ } CADR; /* Channel A Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CBDR:16;
+ } B;
+ } CBDR; /* Channel B Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CCNTR:16;
+ } B;
+ } CCNTR; /* Channel Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t ODIS:1;
+ vuint32_t ODISSL:2;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPEN:1;
+ vuint32_t DMA:1;
+ vuint32_t:1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t:3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t:1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR; /* Channel Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:15;
+ vuint32_t OVFL:1;
+ vuint32_t:12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR; /* Channel Status Register */
+
+ union {
+ vuint32_t R; /* Alternate Channel A Data Register */
+ } ALTCADR;
+
+ uint32_t emios_channel_reserved[2];
+
+ }; /* end of EMIOS_CHANNEL_tag */
+
+ struct EMIOS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t ETB:1;
+ vuint32_t GPREN:1;
+ vuint32_t:6;
+ vuint32_t SRV:4;
+ vuint32_t GPRE:8;
+ vuint32_t:8;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR; /* Global FLAG Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR; /* Output Update Disable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t CHDIS23:1;
+ vuint32_t CHDIS22:1;
+ vuint32_t CHDIS21:1;
+ vuint32_t CHDIS20:1;
+ vuint32_t CHDIS19:1;
+ vuint32_t CHDIS18:1;
+ vuint32_t CHDIS17:1;
+ vuint32_t CHDIS16:1;
+ vuint32_t CHDIS15:1;
+ vuint32_t CHDIS14:1;
+ vuint32_t CHDIS13:1;
+ vuint32_t CHDIS12:1;
+ vuint32_t CHDIS11:1;
+ vuint32_t CHDIS10:1;
+ vuint32_t CHDIS9:1;
+ vuint32_t CHDIS8:1;
+ vuint32_t CHDIS7:1;
+ vuint32_t CHDIS6:1;
+ vuint32_t CHDIS5:1;
+ vuint32_t CHDIS4:1;
+ vuint32_t CHDIS3:1;
+ vuint32_t CHDIS2:1;
+ vuint32_t CHDIS1:1;
+ vuint32_t CHDIS0:1;
+ } B;
+ } UCDIS; /* Disable Channel Register */
+
+ uint32_t emios_reserved1[4];
+
+ struct EMIOS_CHANNEL_tag CH[28];
+
+ }; /* end of EMIOS_tag */
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+ struct FLEXCAN_BUF_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } DATA;
+
+ }; /* end of FLEXCAN_BUF_t */
+
+ struct FLEXCAN_RXFIFO_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+ }; /* end of FLEXCAN_RXFIFO_t */
+
+ struct FLEXCAN_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLFWAK:1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t DOZE:1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ } TIMER; /* Free Running Timer */
+
+ uint32_t FLEXCAN_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK; /* RX Global Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK; /* RX 14 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK; /* RX 15 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t:1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAKINT:1;
+ } B;
+ } ESR; /* Error and Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH; /* Interruput Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interruput Flag Register */
+
+ uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64]; /* RX Individual Mask Registers */
+
+ }; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : i2c */
+/****************************************************************************/
+ struct I2C_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ADR:7;
+ vuint8_t:1;
+ } B;
+ } IBAD; /* Module Bus Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t IBC:8;
+ } B;
+ } IBFD; /* Module Bus Frequency Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t MDIS:1;
+ vuint8_t IBIE:1;
+ vuint8_t MS:1;
+ vuint8_t TX:1;
+ vuint8_t NOACK:1;
+ vuint8_t RSTA:1;
+ vuint8_t DMAEN:1;
+ vuint8_t IBDOZE:1;
+ } B;
+ } IBCR; /* Module Bus Control Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t TCF:1;
+ vuint8_t IAAS:1;
+ vuint8_t IBB:1;
+ vuint8_t IBAL:1;
+ vuint8_t:1;
+ vuint8_t SRW:1;
+ vuint8_t IBIF:1;
+ vuint8_t RXAK:1;
+ } B;
+ } IBSR; /* Module Status Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DATA:8;
+ } B;
+ } IBDR; /* Module Data Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t BIIE:1;
+ vuint8_t:7;
+ } B;
+ } IBIC; /* Module Interrupt Configuration Register */
+
+ }; /* end of I2C_tag */
+/****************************************************************************/
+/* MODULE : INTC */
+/****************************************************************************/
+ struct INTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t VTES:1;
+ vuint32_t:4;
+ vuint32_t HVEN:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR; /* Current Priority Register */
+
+ int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA:21;
+ vuint32_t INTVEC:9;
+ vuint32_t:2;
+ } B;
+ } IACKR; /* Interrupt Acknowledge Register */
+
+ int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } EOIR; /* End of Interrupt Register */
+
+ int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1;
+ vuint8_t CLR:1;
+ } B;
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */
+
+ uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PRI:4;
+ } B;
+ } PSR[512]; /* Software Set/Clear Interrupt Register */
+
+ }; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : LINFLEX */
+/****************************************************************************/
+
+ struct LINFLEX_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CCD:1;
+ vuint32_t CFD:1;
+ vuint32_t LASE:1;
+ vuint32_t AWUM:1;
+ vuint32_t MBL:4;
+ vuint32_t BF:1;
+ vuint32_t SLFM:1;
+ vuint32_t LBKM:1;
+ vuint32_t MME:1;
+ vuint32_t SBDT:1;
+ vuint32_t RBLM:1;
+ vuint32_t SLEEP:1;
+ vuint32_t INIT:1;
+ } B;
+ } LINCR1; /* LINFLEX LIN Control Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SZIE:1;
+ vuint32_t OCIE:1;
+ vuint32_t BEIE:1;
+ vuint32_t CEIE:1;
+ vuint32_t HEIE:1;
+ vuint32_t:2;
+ vuint32_t FEIE:1;
+ vuint32_t BOIE:1;
+ vuint32_t LSIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t DBFIE:1;
+ vuint32_t DBEIE:1;
+ vuint32_t DRIE:1;
+ vuint32_t DTIE:1;
+ vuint32_t HRIE:1;
+ } B;
+ } LINIER; /* LINFLEX LIN Interrupt Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t LINS:4;
+ vuint32_t:2;
+ vuint32_t RMB:1;
+ vuint32_t:1;
+ vuint32_t RBSY:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t DBFF:1;
+ vuint32_t DBEF:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t HRF:1;
+ } B;
+ } LINSR; /* LINFLEX LIN Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t BEF:1;
+ vuint32_t CEF:1;
+ vuint32_t SFEF:1;
+ vuint32_t SDEF:1;
+ vuint32_t IDPEF:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t:6;
+ vuint32_t NF:1;
+ } B;
+ } LINESR; /* LINFLEX LIN Error Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:1;
+ vuint32_t TDFL:2;
+ vuint32_t:1;
+ vuint32_t RDFL:2;
+ vuint32_t:4;
+ vuint32_t RXEN:1;
+ vuint32_t TXEN:1;
+ vuint32_t OP:1;
+ vuint32_t PCE:1;
+ vuint32_t WL:1;
+ vuint32_t UART:1;
+ } B;
+ } UARTCR; /* LINFLEX UART Mode Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t PE:4;
+ vuint32_t RMB:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t:2;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t NF:1;
+ } B;
+ } UARTSR; /* LINFLEX UART Mode Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:5;
+ vuint32_t LTOM:1;
+ vuint32_t IOT:1;
+ vuint32_t TOCE:1;
+ vuint32_t CNT:8;
+ } B;
+ } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t OC2:8;
+ vuint32_t OC1:8;
+ } B;
+ } LINOCR; /* LINFLEX LIN Output Compare Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:4;
+ vuint32_t RTO:4;
+ vuint32_t:1;
+ vuint32_t HTO:7;
+ } B;
+ } LINTOCR; /* LINFLEX LIN Output Compare Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:12;
+ vuint32_t DIV_F:4;
+ } B;
+ } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:3;
+ vuint32_t DIV_M:13;
+ } B;
+ } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:8;
+ vuint32_t CF:8;
+ } B;
+ } LINCFR; /* LINFLEX LIN Checksum Field Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:1;
+ vuint32_t IOBE:1;
+ vuint32_t IOPE:1;
+ vuint32_t WURQ:1;
+ vuint32_t DDRQ:1;
+ vuint32_t DTRQ:1;
+ vuint32_t ABRQ:1;
+ vuint32_t HTRQ:1;
+ vuint32_t:8;
+ } B;
+ } LINCR2; /* LINFLEX LIN Control Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } BIDR; /* LINFLEX Buffer Identifier Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL; /* LINFLEX Buffer Data Register Least Significant */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM; /* LINFLEX Buffer Data Register Most Significant */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:8;
+ vuint32_t FACT:8;
+ } B;
+ } IFER; /* LINFLEX Identifier Filter Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:12;
+ vuint32_t IFMI:4;
+ } B;
+ } IFMI; /* LINFLEX Identifier Filter Match Index Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:12;
+ vuint32_t IFM:4;
+ } B;
+ } IFMR; /* LINFLEX Identifier Filter Mode Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:3;
+ vuint32_t DFL:3;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } IFCR[16]; /* LINFLEX Identifier Filter Control Register 0-15 */
+
+ }; /* end of LINFLEX_tag */
+/****************************************************************************/
+/* MODULE : ME */
+/****************************************************************************/
+ struct ME_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t S_CURRENTMODE:4;
+ vuint32_t S_MTRANS:1;
+ vuint32_t S_DC:1;
+ vuint32_t:2;
+ vuint32_t S_PDO:1;
+ vuint32_t:2;
+ vuint32_t S_MVR:1;
+ vuint32_t S_DFLA:2;
+ vuint32_t S_CFLA:2;
+ vuint32_t:9;
+ vuint32_t S_FMPLL:1;
+ vuint32_t S_FXOSC:1;
+ vuint32_t S_FIRC:1;
+ vuint32_t S_SYSCLK:4;
+ } B;
+ } GS; /* Global Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TARGET_MODE:4;
+ vuint32_t:12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL; /* Mode Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } MER; /* Mode Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t I_CONF:1;
+ vuint32_t I_MODE:1;
+ vuint32_t I_SAFE:1;
+ vuint32_t I_MTC:1;
+ } B;
+ } IS; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t M_CONF:1;
+ vuint32_t M_MODE:1;
+ vuint32_t M_SAFE:1;
+ vuint32_t M_MTC:1;
+ } B;
+ } IM; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t S_MTI:1;
+ vuint32_t S_MRI:1;
+ vuint32_t S_DMA:1;
+ vuint32_t S_NMA:1;
+ vuint32_t S_SEA:1;
+ } B;
+ } IMTS; /* Invalid Mode Transition Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t MPH_BUSY:1;
+ vuint32_t:2;
+ vuint32_t PMC_PROG:1;
+ vuint32_t CORE_DBG:1;
+ vuint32_t:2;
+ vuint32_t SMR:1;
+ vuint32_t:1;
+ vuint32_t FMPLL_SC:1;
+ vuint32_t FXOSC_SC:1;
+ vuint32_t FIRC_SC:1;
+ vuint32_t:1;
+ vuint32_t SYSCLK_SW:1;
+ vuint32_t DFLASH_SC:1;
+ vuint32_t CFLASH_SC:1;
+ vuint32_t CDP_PRPH_0_143:1;
+ vuint32_t:3;
+ vuint32_t CDP_PRPH_96_127:1;
+ vuint32_t CDP_PRPH_64_95:1;
+ vuint32_t CDP_PRPH_32_63:1;
+ vuint32_t CDP_PRPH_0_31:1;
+ } B;
+ } DMTS; /* Invalid Mode Transition Status Register */
+
+ int32_t ME_reserved0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET; /* Reset Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST; /* Test Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE; /* Safe Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN; /* DRUN Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN[4]; /* RUN 0->4 Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT0; /* HALT0 Mode Configuration Register */
+
+ int32_t ME_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP0; /* STOP0 Mode Configuration Register */
+
+ int32_t ME_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY0; /* STANDBY0 Mode Configuration Register */
+
+ int32_t ME_reserved3[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t S_FLEXCAN5:1;
+ vuint32_t S_FLEXCAN4:1;
+ vuint32_t S_FLEXCAN3:1;
+ vuint32_t S_FLEXCAN2:1;
+ vuint32_t S_FLEXCAN1:1;
+ vuint32_t S_FLEXCAN0:1;
+ vuint32_t:9;
+ vuint32_t S_DSPI2:1;
+ vuint32_t S_DSPI1:1;
+ vuint32_t S_DSPI0:1;
+ vuint32_t:4;
+ } B;
+ } PS0; /* Peripheral Status Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t S_CANSAMPLER:1;
+ vuint32_t:2;
+ vuint32_t S_CTU:1;
+ vuint32_t:5;
+ vuint32_t S_LINFLEX3:1;
+ vuint32_t S_LINFLEX2:1;
+ vuint32_t S_LINFLEX1:1;
+ vuint32_t S_LINFLEX0:1;
+ vuint32_t:3;
+ vuint32_t S_I2C:1;
+ vuint32_t:11;
+ vuint32_t S_ADC:1;
+ } B;
+ } PS1; /* Peripheral Status Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t S_PIT_RTI:1;
+ vuint32_t S_RTC_API:1;
+ vuint32_t:18;
+ vuint32_t S_EMIOS:1;
+ vuint32_t:2;
+ vuint32_t S_WKUP:1;
+ vuint32_t S_SIU:1;
+ vuint32_t:4;
+ } B;
+ } PS2; /* Peripheral Status Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:23;
+ vuint32_t S_CMU:1;
+ vuint32_t:8;
+ } B;
+ } PS3; /* Peripheral Status Register 3 */
+
+ int32_t ME_reserved4[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t:8;
+ } B;
+ } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t DBG_F:1;
+ vuint8_t LP_CFG:3;
+ vuint8_t RUN_CFG:3;
+ } B;
+ } PCTL[144]; /* Peripheral Control 0->143 Register */
+
+ }; /* end of ME_tag */
+/****************************************************************************/
+/* MODULE : MPU */
+/****************************************************************************/
+ struct MPU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SPERR:8;
+ vuint32_t:4;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NGRD:4;
+ vuint32_t:7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR; /* Module Control/Error Status Register */
+
+ uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR3;
+
+ uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD0; /* Region Descriptor n Word 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD1; /* Region Descriptor n Word 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2; /* Region Descriptor n Word 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t:15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3; /* Region Descriptor n Word 3 */
+
+ } RGD[16];
+
+ uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
+
+ }; /* end of MPU_tag */
+/****************************************************************************/
+/* MODULE : PCU */
+/****************************************************************************/
+ struct PCU_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RST:1;
+ } B;
+ } PCONF[3]; /* Power domain 0-2 configuration register */
+
+ int32_t PCU_reserved0[13]; /* (0x040 - 0x00C)/4 = 0x0D */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t PD2:1;
+ vuint32_t PD1:1;
+ vuint32_t PD0:1;
+ } B;
+ } PSTAT; /* Power Domain Status Register */
+
+ int32_t PCU_reserved1[15]; /* {0x0080-0x0044}/0x4 = 0xF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t MASK_LVDHV5:1;
+ } B;
+ } VCTL; /* Voltage Regulator Control Register */
+
+ }; /* end of PCU_tag */
+/****************************************************************************/
+/* MODULE : pit */
+/****************************************************************************/
+ struct PIT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR;
+
+ uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+ } CH[6];
+
+ }; /* end of PIT_tag */
+/****************************************************************************/
+/* MODULE : RGM */
+/****************************************************************************/
+ struct RGM_tag {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1;
+ vuint16_t:6;
+ vuint16_t F_FLASH:1;
+ vuint16_t F_LVD45:1;
+ vuint16_t F_CMU_FHL:1;
+ vuint16_t F_CMU_OLR:1;
+ vuint16_t F_FMPLL:1;
+ vuint16_t F_CHKSTOP:1;
+ vuint16_t F_SOFT:1;
+ vuint16_t F_CORE:1;
+ vuint16_t F_JTAG:1;
+ } B;
+ } FES; /* Functional Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t F_POR:1;
+ vuint16_t:11;
+ vuint16_t F_LVD27:1;
+ vuint16_t F_SWT:1;
+ vuint16_t F_LVD12_PD1:1;
+ vuint16_t F_LVD12_PD0:1;
+ } B;
+ } DES; /* Destructive Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1;
+ vuint16_t:6;
+ vuint16_t D_FLASH:1;
+ vuint16_t D_LVD45:1;
+ vuint16_t D_CMU_FHL:1;
+ vuint16_t D_CMU_OLR:1;
+ vuint16_t D_FMPLL:1;
+ vuint16_t D_CHKSTOP:1;
+ vuint16_t D_SOFT:1;
+ vuint16_t D_CORE:1;
+ vuint16_t D_JTAG:1;
+ } B;
+ } FERD; /* Functional Event Reset Disable */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t D_POR:1;
+ vuint16_t:11;
+ vuint16_t D_LVD27:1;
+ vuint16_t D_SWT:1;
+ vuint16_t D_LVD12_PD1:1;
+ vuint16_t D_LVD12_PD0:1;
+ } B;
+ } DERD; /* Destructive Event Reset Disable */
+
+ int16_t RGM_reserved0[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t AR_EXR:1;
+ vuint16_t:6;
+ vuint16_t AR_FLASH:1;
+ vuint16_t AR_LVD45:1;
+ vuint16_t AR_CMU_FHL:1;
+ vuint16_t AR_CMU_OLR:1;
+ vuint16_t AR_FMPLL:1;
+ vuint16_t AR_CHKSTOP:1;
+ vuint16_t AR_SOFT:1;
+ vuint16_t AR_CORE:1;
+ vuint16_t AR_JTAG:1;
+ } B;
+ } FEAR; /* Functional Event Alternate Request */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t AR_LVD27:1;
+ vuint16_t AR_SWT:1;
+ vuint16_t AR_LVD12_PD1:1;
+ vuint16_t AR_LVD12_PD0:1;
+ } B;
+ } DEAR; /* Destructive Event Alternate Request */
+
+ int16_t RGM_reserved1[2];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t SS_LVD45:1;
+ vuint16_t SS_CMU_FHL:1;
+ vuint16_t SS_CMU_OLR:1;
+ vuint16_t SS_PLL:1;
+ vuint16_t SS_CHKSTOP:1;
+ vuint16_t SS_SOFT:1;
+ vuint16_t SS_CORE:1;
+ vuint16_t SS_JTAG:1;
+ } B;
+ } FESS; /* Functional Event Short Sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t BOOT_FROM_BKP_RAM:1;
+ vuint16_t:7;
+ } B;
+ } STDBY; /* STANDBY reset sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t BE_EXR:1;
+ vuint16_t:6;
+ vuint16_t BE_FLASH:1;
+ vuint16_t BE_LVD45:1;
+ vuint16_t BE_CMU_FHL:1;
+ vuint16_t BE_CMU_OLR:1;
+ vuint16_t BE_FMPLL:1;
+ vuint16_t BE_CHKSTOP:1;
+ vuint16_t BE_SOFT:1;
+ vuint16_t BE_CORE:1;
+ vuint16_t BE_JTAG:1;
+ } B;
+ } FBRE; /* Functional Bidirectional Reset Enable */
+
+ }; /* end of RGM_tag */
+/****************************************************************************/
+/* MODULE : RTC */
+/****************************************************************************/
+ struct RTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SUPV:1;
+ vuint32_t:31;
+ } B;
+ } RTCSUPV; /* RTC Supervisor Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNTEN:1;
+ vuint32_t RTCIE:1;
+ vuint32_t FRZEN:1;
+ vuint32_t ROVREN:1;
+ vuint32_t RTCVAL:12;
+ vuint32_t APIEN:1;
+ vuint32_t APIIE:1;
+ vuint32_t CLKSEL:2;
+ vuint32_t DIV512EN:1;
+ vuint32_t DIV32EN:1;
+ vuint32_t APIVAL:10;
+ } B;
+ } RTCC; /* RTC Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t RTCF:1;
+ vuint32_t:15;
+ vuint32_t APIF:1;
+ vuint32_t:2;
+ vuint32_t ROVRF:1;
+ vuint32_t:10;
+ } B;
+ } RTCS; /* RTC Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RTCCNT:32;
+ } B;
+ } RTCCNT; /* RTC Counter Register */
+
+ }; /* end of RTC_tag */
+/****************************************************************************/
+/* MODULE : SIU */
+/****************************************************************************/
+ struct SIU_tag {
+
+ int32_t SIU_reserved0; /* {0x004-0x000}/4 = 0x01 */
+
+ union { /* MCU ID Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16;
+ vuint32_t CSP:1;
+ vuint32_t PKG:5;
+ vuint32_t:2;
+ vuint32_t MAJOR_MASK:4;
+ vuint32_t MINOR_MASK:4;
+ } B;
+ } MIDR;
+
+ union { /* MCU ID Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1;
+ vuint32_t FLASH_SIZE_1:4;
+ vuint32_t FLASH_SIZE_2:4;
+ vuint32_t:7;
+ vuint32_t PARTNUM:8;
+ vuint32_t:3;
+ vuint32_t EE:1;
+ vuint32_t:4;
+ } B;
+ } MIDR2;
+
+ int32_t SIU_reserved1[2]; /* {0x014-0x00C}/4 = 0x02 */
+
+ union { /* Interrupt Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t EIF15:1;
+ vuint32_t EIF14:1;
+ vuint32_t EIF13:1;
+ vuint32_t EIF12:1;
+ vuint32_t EIF11:1;
+ vuint32_t EIF10:1;
+ vuint32_t EIF9:1;
+ vuint32_t EIF8:1;
+ vuint32_t EIF7:1;
+ vuint32_t EIF6:1;
+ vuint32_t EIF5:1;
+ vuint32_t EIF4:1;
+ vuint32_t EIF3:1;
+ vuint32_t EIF2:1;
+ vuint32_t EIF1:1;
+ vuint32_t EIF0:1;
+ } B;
+ } ISR;
+
+ union { /* Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t EIRE15:1;
+ vuint32_t EIRE14:1;
+ vuint32_t EIRE13:1;
+ vuint32_t EIRE12:1;
+ vuint32_t EIRE11:1;
+ vuint32_t EIRE10:1;
+ vuint32_t EIRE9:1;
+ vuint32_t EIRE8:1;
+ vuint32_t EIRE7:1;
+ vuint32_t EIRE6:1;
+ vuint32_t EIRE5:1;
+ vuint32_t EIRE4:1;
+ vuint32_t EIRE3:1;
+ vuint32_t EIRE2:1;
+ vuint32_t EIRE1:1;
+ vuint32_t EIRE0:1;
+ } B;
+ } IRER;
+
+ int32_t SIU_reserved2[3]; /* {0x028-0x01C}/4 = 0x03 */
+
+ union { /* Interrupt Rising-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t IREE15:1;
+ vuint32_t IREE14:1;
+ vuint32_t IREE13:1;
+ vuint32_t IREE12:1;
+ vuint32_t IREE11:1;
+ vuint32_t IREE10:1;
+ vuint32_t IREE9:1;
+ vuint32_t IREE8:1;
+ vuint32_t IREE7:1;
+ vuint32_t IREE6:1;
+ vuint32_t IREE5:1;
+ vuint32_t IREE4:1;
+ vuint32_t IREE3:1;
+ vuint32_t IREE2:1;
+ vuint32_t IREE1:1;
+ vuint32_t IREE0:1;
+ } B;
+ } IREER;
+
+ union { /* Interrupt Falling-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t IFEE15:1;
+ vuint32_t IFEE14:1;
+ vuint32_t IFEE13:1;
+ vuint32_t IFEE12:1;
+ vuint32_t IFEE11:1;
+ vuint32_t IFEE10:1;
+ vuint32_t IFEE9:1;
+ vuint32_t IFEE8:1;
+ vuint32_t IFEE7:1;
+ vuint32_t IFEE6:1;
+ vuint32_t IFEE5:1;
+ vuint32_t IFEE4:1;
+ vuint32_t IFEE3:1;
+ vuint32_t IFEE2:1;
+ vuint32_t IFEE1:1;
+ vuint32_t IFEE0:1;
+ } B;
+ } IFEER;
+
+ union { /* Interrupt Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t IFE15:1;
+ vuint32_t IFE14:1;
+ vuint32_t IFE13:1;
+ vuint32_t IFE12:1;
+ vuint32_t IFE11:1;
+ vuint32_t IFE10:1;
+ vuint32_t IFE9:1;
+ vuint32_t IFE8:1;
+ vuint32_t IFE7:1;
+ vuint32_t IFE6:1;
+ vuint32_t IFE5:1;
+ vuint32_t IFE4:1;
+ vuint32_t IFE3:1;
+ vuint32_t IFE2:1;
+ vuint32_t IFE1:1;
+ vuint32_t IFE0:1;
+ } B;
+ } IFER;
+
+ int32_t SIU_reserved3[3]; /* {0x040-0x034}/4 = 0x03 */
+
+ union { /* Pad Configuration Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SMC:1;
+ vuint16_t APC:1;
+ vuint16_t:1;
+ vuint16_t PA:2;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t:2;
+ vuint16_t ODE:1;
+ vuint16_t:2;
+ vuint16_t SRC:1;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[123];
+
+ int32_t SIU_reserved4[242]; /* {0x500-0x136}/0xF2 */
+
+ union { /* Pad Selection for Multiplexed Input Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PADSEL:4;
+ } B;
+ } PSMI[32];
+
+ int32_t SIU_reserved5[56]; /* {0x600-0x520}/4 = 0x38 */
+
+ union { /* GPIO Pin Data Output Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[124];
+
+ int32_t SIU_reserved6[97]; /* {0x800-0x67C}/4 = 0x61 */
+
+ union { /* GPIO Pin Data Input Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[124];
+
+ int32_t SIU_reserved7[225]; /* {0xC00-0x87C}/0x4 = 0xE1 */
+
+ union { /* Parallel GPIO Pin Data Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPD0:32;
+ } B;
+ } PGPDO[4];
+
+ int32_t SIU_reserved8[12]; /* {0xC40-0xC10}/0x4 = 0x0C */
+
+ union { /* Parallel GPIO Pin Data Input Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDI:32;
+ } B;
+ } PGPDI[4];
+
+ int32_t SIU_reserved9[12]; /* {0xC80-0xC50}/0x4 = 0x0C */
+
+ union { /* Masked Parallel GPIO Pin Data Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16;
+ vuint32_t MPPDO:16;
+ } B;
+ } MPGPDO[8];
+
+ int32_t SIU_reserved10[216]; /* {0x1000-0x0CA0}/4 = 0xD8 */
+
+ union { /* Interrupt Filter Maximum Counter Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t MAXCNT:4;
+ } B;
+ } IFMC[16];
+
+ int32_t SIU_reserved11[16]; /* {0x1080-0x1040}/4 = 0x10 */
+
+ union { /* Interrupt Filter Clock Prescaler Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFCP:4;
+ } B;
+ } IFCPR;
+
+ }; /* end of SIU_tag */
+/****************************************************************************/
+/* MODULE : SSCM */
+/****************************************************************************/
+ struct SSCM_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t NXEN:1;
+ vuint16_t:3;
+ vuint16_t BMODE:3;
+ vuint16_t:1;
+ vuint16_t ABD:1;
+ vuint16_t:3;
+ } B;
+ } STATUS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SRAM_SIZE:5;
+ vuint16_t PRSZ:5;
+ vuint16_t PVLB:1;
+ vuint16_t DTSZ:4;
+ vuint16_t DVLD:1;
+ } B;
+ } MEMCONFIG; /* System Memory Configuration Register */
+
+ int16_t SSCM_reserved;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:14;
+ vuint16_t PAE:1;
+ vuint16_t RAE:1;
+ } B;
+ } ERROR; /* Error Configuration Register */
+
+ int16_t SSCM_reserved1[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32;
+ } B;
+ } PWCMPH; /* Password Comparison Register High Word */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32;
+ } B;
+ } PWCMPL; /* Password Comparison Register Low Word */
+
+ }; /* end of SSCM_tag */
+/****************************************************************************/
+/* MODULE : STM */
+/****************************************************************************/
+ struct STM_CHANNEL_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR; /* STM Channel Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR; /* STM Channel Interrupt Register */
+
+ union {
+ vuint32_t R;
+ } CMP; /* STM Channel Compare Register 0 */
+
+ int32_t STM_CHANNEL_reserved;
+
+ }; /* end of STM_CHANNEL_tag */
+
+ struct STM_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8;
+ vuint32_t:6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR; /* STM Control Register */
+
+ union {
+ vuint32_t R;
+ } CNT; /* STM Count Register */
+
+ int32_t STM_reserved[2];
+
+ struct STM_CHANNEL_tag CH[4];
+
+ }; /* end of STM_tag */
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+ struct SWT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t:15;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } CR; /* SWT Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } IR; /* SWT Interrupt Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO; /* SWT Time-Out Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+ } B;
+ } WN; /* SWT Window Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16;
+ } B;
+ } SR; /* SWT Service Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO; /* SWT Counter Output Register */
+
+ }; /* end of SWT_tag */
+/****************************************************************************/
+/* MODULE : WKUP */
+/****************************************************************************/
+ struct WKUP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1;
+ vuint32_t NOVF0:1;
+ vuint32_t:30;
+ } B;
+ } NSR; /* NMI Status Register */
+
+ int32_t WKUP_reserved;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK:1;
+ vuint32_t NDSS:2;
+ vuint32_t NWRE:1;
+ vuint32_t:1;
+ vuint32_t NREE:1;
+ vuint32_t NFEE:1;
+ vuint32_t NFE:1;
+ vuint32_t:24;
+ } B;
+ } NCR; /* NMI Configuration Register */
+
+ int32_t WKUP_reserved1[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t EIF:20;
+ } B;
+ } WISR; /* Wakeup/Interrupt Status Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t EIRE:20;
+ } B;
+ } IRER; /* Interrupt Request Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t WRE:20;
+ } B;
+ } WRER; /* Wakeup Request Enable Register */
+
+ int32_t WKUP_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t IREE:20;
+ } B;
+ } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t IFEE:20;
+ } B;
+ } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t IFE:20;
+ } B;
+ } WIFER; /* Wakeup/Interrupt Filter Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t IPUE:20;
+ } B;
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
+
+ }; /* end of WKUP_tag */
+/******************************************************************
+| defines and macros (scope: module-local)
+|-----------------------------------------------------------------*/
+/* Define instances of modules */
+#define ADC (*(volatile struct ADC_tag *) 0xFFE00000UL)
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
+#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
+#define I2C (*(volatile struct I2C_tag *) 0xFFE30000UL)
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
+#define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL)
+#define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL)
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
+
+#ifdef __MWERKS__
+#pragma pop
+#endif /*
+ */
+
+#ifdef __cplusplus
+}
+#endif /*
+ */
+
+#endif /* ifdef _MPC5604B_H */
+
+/* End of file */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..9782d053f --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/cfg/mcuconf.h.ftl @@ -0,0 +1,330 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC560Bxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC560Bxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+#define SPC5_XOSCDIV_VALUE ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
+#define SPC5_IRCDIV_VALUE ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+#define SPC5_EMIOS0_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
+#define SPC5_EMIOS1_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios1_global_prescaler.value[0]?number}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX2 ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX3 ${(conf.instance.linflex_settings.linflex3.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX4 ${(conf.instance.linflex_settings.linflex4.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX5 ${(conf.instance.linflex_settings.linflex5.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX6 ${(conf.instance.linflex_settings.linflex6.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX7 ${(conf.instance.linflex_settings.linflex7.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX8 ${(conf.instance.linflex_settings.linflex8.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX9 ${(conf.instance.linflex_settings.linflex9.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+#define SPC5_SERIAL_LINFLEX2_PRIORITY ${conf.instance.irq_priority_settings.linflex2.value[0]}
+#define SPC5_SERIAL_LINFLEX3_PRIORITY ${conf.instance.irq_priority_settings.linflex3.value[0]}
+#define SPC5_SERIAL_LINFLEX4_PRIORITY ${conf.instance.irq_priority_settings.linflex4.value[0]}
+#define SPC5_SERIAL_LINFLEX5_PRIORITY ${conf.instance.irq_priority_settings.linflex5.value[0]}
+#define SPC5_SERIAL_LINFLEX6_PRIORITY ${conf.instance.irq_priority_settings.linflex6.value[0]}
+#define SPC5_SERIAL_LINFLEX7_PRIORITY ${conf.instance.irq_priority_settings.linflex7.value[0]}
+#define SPC5_SERIAL_LINFLEX8_PRIORITY ${conf.instance.irq_priority_settings.linflex8.value[0]}
+#define SPC5_SERIAL_LINFLEX9_PRIORITY ${conf.instance.irq_priority_settings.linflex9.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI3 ${conf.instance.dspi_settings.dspi_3.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI4 ${conf.instance.dspi_settings.dspi_4.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI5 ${conf.instance.dspi_settings.dspi_5.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI3_MCR (0${s0 + s1})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI4_MCR (0${s0 + s1})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI5_MCR (0${s0 + s1})
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx1.value[0]}
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx2.value[0]}
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_rx.value[0]}
+#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx1.value[0]}
+#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx2.value[0]}
+#define SPC5_SPI_DSPI4_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_rx.value[0]}
+#define SPC5_SPI_DSPI5_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx1.value[0]}
+#define SPC5_SPI_DSPI5_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx2.value[0]}
+#define SPC5_SPI_DSPI5_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_rx.value[0]}
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI5_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * ICU-PWM driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS0_CH0 ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH1 ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH2 ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH3 ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH4 ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH5 ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH6 ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH7 ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH24 ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS0_GROUP0 ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS0_GROUP1 ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
+
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
+
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_EMIOS1_CH24 ${conf.instance.emios_settings.emios1_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS1_GROUP0 ${conf.instance.emios_settings.emios1_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP1 ${conf.instance.emios_settings.emios1_group1.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP2 ${conf.instance.emios_settings.emios1_group2.value[0]?upper_case}
+
+#define SPC5_EMIOS1_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc0.value[0]}
+#define SPC5_EMIOS1_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc1.value[0]}
+#define SPC5_EMIOS1_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc2.value[0]}
+#define SPC5_EMIOS1_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc3.value[0]}
+#define SPC5_EMIOS1_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc4.value[0]}
+#define SPC5_EMIOS1_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc5.value[0]}
+#define SPC5_EMIOS1_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc6.value[0]}
+#define SPC5_EMIOS1_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc7.value[0]}
+#define SPC5_EMIOS1_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc8.value[0]}
+#define SPC5_EMIOS1_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc9.value[0]}
+#define SPC5_EMIOS1_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc10.value[0]}
+#define SPC5_EMIOS1_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc11.value[0]}
+#define SPC5_EMIOS1_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc12.value[0]}
+
+#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
+#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN3 ${conf.instance.flexcan_settings.flexcan3.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan3_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_PRIORITY ${conf.instance.irq_priority_settings.flexcan3.value[0]}
+#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN4 ${conf.instance.flexcan_settings.flexcan4.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan4_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_PRIORITY ${conf.instance.irq_priority_settings.flexcan4.value[0]}
+#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN5 ${conf.instance.flexcan_settings.flexcan5.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_PRIORITY ${conf.instance.irq_priority_settings.flexcan5.value[0]}
+#define SPC5_CAN_FLEXCAN5_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan5_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+
+#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
+#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
+#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
+#define SPC5_ADC_ADC0_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
+#define SPC5_ADC_ADC0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+
+
+[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
+#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
+#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
+#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
+#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c new file mode 100644 index 000000000..5a9481c6d --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c @@ -0,0 +1,279 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.c
+ * @brief SPC560B/Cxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief PIT channel 0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector59) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ /* Resets the PIT channel 0 IRQ flag.*/
+ PIT.CH[0].TFLG.R = 1;
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t reg;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
+ to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
+ modes.*/
+ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
+ halSPCSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+ reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
+ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
+ PIT.CH[0].LDVAL.R = reg;
+ PIT.CH[0].CVAL.R = reg;
+ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
+ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC560B/Cxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.RC)
+ ;
+
+#if !SPC5_NO_INIT
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* Oscillators dividers setup.*/
+ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
+ CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.CURRENTMODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.FXOSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC[0].R = SPC5_CGM_SC_DC0;
+ CGM.SC_DC[1].R = SPC5_CGM_SC_DC1;
+ CGM.SC_DC[2].R = SPC5_CGM_SC_DC2;
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
+
+ /* Run modes initialization.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ ME.STANDBY0.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
+ if (ME.IS.B.ICONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
+ CFLASH.PFCR0.B.BK0_APC = 2;
+ CFLASH.PFCR0.B.BK0_RWSC = 2;
+
+ /* CMU clock enable */
+ halSPCSetPeripheralClockMode(104,
+ SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2));
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGETMODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_DIVIRC:
+ return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_DIVXOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/hal_lld.h b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.h new file mode 100644 index 000000000..0e9e339bd --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/hal_lld.h @@ -0,0 +1,779 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/hal_lld.h
+ * @brief SPC560Bxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC560Bxx Car Body and Convenience"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 16000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MAX 40000
+
+/**
+ * @brief Minimum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MIN 32000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 64000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 64000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
+ oscillator. */
+#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
+ oscillator. */
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (1U << 1)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+#define SPC5_ME_ME_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_LP (2U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+#define SPC5_ME_LP_PC_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 1
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief XOSC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Fast IRC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0 | \
+ SPC5_ME_ME_STANDBY0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STANDBY0 mode settings.
+ */
+#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0 | \
+ SPC5_ME_LP_PC_STANDBY0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief PIT channel 0 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC560Bxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC560Bxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on the XOSC divider.*/
+#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
+#error "invalid SPC5_XOSCDIV_VALUE value specified"
+#endif
+
+/* Check on the IRC divider.*/
+#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
+#error "invalid SPC5_IRCDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/platform.mk b/os/hal/ports/SPC5/SPC560Bxx/platform.mk new file mode 100644 index 000000000..4621464ec --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/platform.mk @@ -0,0 +1,22 @@ +# List of all the SPC560Bxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Bxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/spc5_emios.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Bxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC560Bxx/registers.h b/os/hal/ports/SPC5/SPC560Bxx/registers.h new file mode 100644 index 000000000..0ea75e6c0 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc560b.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h b/os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h new file mode 100644 index 000000000..0f0ccc6ea --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/spc5_registry.h @@ -0,0 +1,676 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/spc560b_registry.h
+ * @brief SPC560Bxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if defined(_SPC560B54L3_)
+#define SPC5_NUM_DSPI 3
+#define SPC5_NUM_LINFLEX 4
+#define SPC5_NUM_GPIO 77
+
+#elif defined(_SPC560B54L5_)
+#define SPC5_NUM_DSPI 5
+#define SPC5_NUM_LINFLEX 6
+#define SPC5_NUM_GPIO 121
+
+#elif defined(_SPC560B60L3_)
+#define SPC5_NUM_DSPI 3
+#define SPC5_NUM_LINFLEX 6
+#define SPC5_NUM_GPIO 77
+
+#elif defined(_SPC560B60L5_)
+#define SPC5_NUM_DSPI 5
+#define SPC5_NUM_LINFLEX 6
+#define SPC5_NUM_GPIO 121
+
+#elif defined(_SPC560B60L7_)
+#define SPC5_NUM_DSPI 6
+#define SPC5_NUM_LINFLEX 8
+#define SPC5_NUM_GPIO 149
+
+#elif defined(_SPC560B64L5_)
+#define SPC5_NUM_DSPI 5
+#define SPC5_NUM_LINFLEX 8
+#define SPC5_NUM_GPIO 149
+
+#elif defined(_SPC560B64L7_)
+#define SPC5_NUM_DSPI 6
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 149
+
+#else
+#error "SPC560Bxx platform not defined"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560Bxx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_DSPI_FIFO_DEPTH 4
+
+#if SPC5_NUM_DSPI > 0
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI0 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 1
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI1 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 2
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI2_RFDF_HANDLER vector118
+#define SPC5_DSPI2_RFDF_NUMBER 118
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI2 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 3
+#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_DSPI3_PCTL 7
+#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
+#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI3_RX_DMA_DEV_ID 8
+#define SPC5_DSPI3_TFFF_HANDLER vector184
+#define SPC5_DSPI3_TFFF_NUMBER 184
+#define SPC5_DSPI3_RFDF_HANDLER vector186
+#define SPC5_DSPI3_RFDF_NUMBER 186
+#define SPC5_DSPI3_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL)
+#define SPC5_DSPI3_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI3 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 4
+#define SPC5_HAS_DSPI4 TRUE
+#define SPC5_DSPI4_PCTL 8
+#define SPC5_DSPI4_TX1_DMA_DEV_ID 9
+#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI4_RX_DMA_DEV_ID 10
+#define SPC5_DSPI4_TFFF_HANDLER vector213
+#define SPC5_DSPI4_TFFF_NUMBER 213
+#define SPC5_DSPI4_RFDF_HANDLER vector215
+#define SPC5_DSPI4_RFDF_NUMBER 215
+#define SPC5_DSPI4_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL)
+#define SPC5_DSPI4_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI4 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 5
+#define SPC5_HAS_DSPI5 TRUE
+#define SPC5_DSPI5_PCTL 9
+#define SPC5_DSPI5_TX1_DMA_DEV_ID 11
+#define SPC5_DSPI5_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI5_RX_DMA_DEV_ID 12
+#define SPC5_DSPI5_TFFF_HANDLER vector221
+#define SPC5_DSPI5_TFFF_NUMBER 221
+#define SPC5_DSPI5_RFDF_HANDLER vector223
+#define SPC5_DSPI5_RFDF_NUMBER 223
+#define SPC5_DSPI5_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI5_PCTL, SPC5_SPI_DSPI5_START_PCTL)
+#define SPC5_DSPI5_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI5_PCTL, SPC5_SPI_DSPI5_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI5 FALSE
+#endif
+
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 16
+#define SPC5_EDMA_HAS_MUX TRUE
+#define SPC5_EDMA_MUX_PCTL 23
+
+/* LINFlex attributes.*/
+#if SPC5_NUM_LINFLEX > 0
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX0 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 1
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX1 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 2
+#define SPC5_HAS_LINFLEX2 TRUE
+#define SPC5_LINFLEX2_PCTL 50
+#define SPC5_LINFLEX2_RXI_HANDLER vector119
+#define SPC5_LINFLEX2_TXI_HANDLER vector120
+#define SPC5_LINFLEX2_ERR_HANDLER vector121
+#define SPC5_LINFLEX2_RXI_NUMBER 119
+#define SPC5_LINFLEX2_TXI_NUMBER 120
+#define SPC5_LINFLEX2_ERR_NUMBER 121
+#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX2 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 3
+#define SPC5_HAS_LINFLEX3 TRUE
+#define SPC5_LINFLEX3_PCTL 51
+#define SPC5_LINFLEX3_RXI_HANDLER vector122
+#define SPC5_LINFLEX3_TXI_HANDLER vector123
+#define SPC5_LINFLEX3_ERR_HANDLER vector124
+#define SPC5_LINFLEX3_RXI_NUMBER 122
+#define SPC5_LINFLEX3_TXI_NUMBER 123
+#define SPC5_LINFLEX3_ERR_NUMBER 124
+#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX3 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 4
+#define SPC5_HAS_LINFLEX4 TRUE
+#define SPC5_LINFLEX4_PCTL 52
+#define SPC5_LINFLEX4_RXI_HANDLER vector187
+#define SPC5_LINFLEX4_TXI_HANDLER vector188
+#define SPC5_LINFLEX4_ERR_HANDLER vector189
+#define SPC5_LINFLEX4_RXI_NUMBER 187
+#define SPC5_LINFLEX4_TXI_NUMBER 188
+#define SPC5_LINFLEX4_ERR_NUMBER 189
+#define SPC5_LINFLEX4_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX4 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 5
+#define SPC5_HAS_LINFLEX5 TRUE
+#define SPC5_LINFLEX5_PCTL 53
+#define SPC5_LINFLEX5_RXI_HANDLER vector199
+#define SPC5_LINFLEX5_TXI_HANDLER vector200
+#define SPC5_LINFLEX5_ERR_HANDLER vector201
+#define SPC5_LINFLEX5_RXI_NUMBER 199
+#define SPC5_LINFLEX5_TXI_NUMBER 200
+#define SPC5_LINFLEX5_ERR_NUMBER 201
+#define SPC5_LINFLEX5_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX5 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 6
+#define SPC5_HAS_LINFLEX6 TRUE
+#define SPC5_LINFLEX6_PCTL 54
+#define SPC5_LINFLEX6_RXI_HANDLER vector216
+#define SPC5_LINFLEX6_TXI_HANDLER vector217
+#define SPC5_LINFLEX6_ERR_HANDLER vector218
+#define SPC5_LINFLEX6_RXI_NUMBER 216
+#define SPC5_LINFLEX6_TXI_NUMBER 217
+#define SPC5_LINFLEX6_ERR_NUMBER 218
+#define SPC5_LINFLEX6_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX6 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 7
+#define SPC5_HAS_LINFLEX7 TRUE
+#define SPC5_LINFLEX7_PCTL 55
+#define SPC5_LINFLEX7_RXI_HANDLER vector224
+#define SPC5_LINFLEX7_TXI_HANDLER vector225
+#define SPC5_LINFLEX7_ERR_HANDLER vector226
+#define SPC5_LINFLEX7_RXI_NUMBER 224
+#define SPC5_LINFLEX7_TXI_NUMBER 225
+#define SPC5_LINFLEX7_ERR_NUMBER 226
+#define SPC5_LINFLEX7_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX7 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 8
+#define SPC5_HAS_LINFLEX8 TRUE
+#define SPC5_LINFLEX8_PCTL 12
+#define SPC5_LINFLEX8_RXI_HANDLER vector227
+#define SPC5_LINFLEX8_TXI_HANDLER vector228
+#define SPC5_LINFLEX8_ERR_HANDLER vector229
+#define SPC5_LINFLEX8_RXI_NUMBER 227
+#define SPC5_LINFLEX8_TXI_NUMBER 228
+#define SPC5_LINFLEX8_ERR_NUMBER 229
+#define SPC5_LINFLEX8_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX8 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 9
+#define SPC5_HAS_LINFLEX9 TRUE
+#define SPC5_LINFLEX9_PCTL 13
+#define SPC5_LINFLEX9_RXI_HANDLER vector230
+#define SPC5_LINFLEX9_TXI_HANDLER vector231
+#define SPC5_LINFLEX9_ERR_HANDLER vector232
+#define SPC5_LINFLEX9_RXI_NUMBER 230
+#define SPC5_LINFLEX9_TXI_NUMBER 231
+#define SPC5_LINFLEX9_ERR_NUMBER 232
+#define SPC5_LINFLEX9_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX9 FALSE
+#endif
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_PCTL 68
+#define SPC5_SIUL_NUM_PORTS 10
+#define SPC5_SIUL_NUM_PCRS 149
+#define SPC5_SIUL_NUM_PADSELS 64
+#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
+
+/* eMIOS attributes.*/
+#define SPC5_HAS_EMIOS0 TRUE
+#define SPC5_EMIOS0_PCTL 72
+#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
+#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
+#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
+#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
+#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
+#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
+#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
+#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
+#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
+#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
+#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
+#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
+#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
+#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
+#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
+#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
+#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
+#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
+#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
+#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
+#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
+#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
+#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
+#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
+#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
+#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
+#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
+#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
+
+#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS0_GPRE_VALUE)
+
+#define SPC5_HAS_EMIOS1 TRUE
+#define SPC5_EMIOS1_PCTL 73
+#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
+#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
+#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
+#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
+#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
+#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
+#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
+#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
+#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
+#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
+#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
+#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
+#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
+#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
+#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
+#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
+#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
+#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
+#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
+#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
+#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
+#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
+#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
+#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
+#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
+#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
+#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
+#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
+
+#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS1_GPRE_VALUE)
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 64
+#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
+#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
+#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN2 TRUE
+#define SPC5_FLEXCAN2_PCTL 18
+#define SPC5_FLEXCAN2_MB 64
+#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
+#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+
+#define SPC5_HAS_FLEXCAN3 TRUE
+#define SPC5_FLEXCAN3_PCTL 19
+#define SPC5_FLEXCAN3_MB 64
+#define SPC5_FLEXCAN3_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
+#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
+#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN4 TRUE
+#define SPC5_FLEXCAN4_PCTL 20
+#define SPC5_FLEXCAN4_MB 64
+#define SPC5_FLEXCAN4_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
+#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
+#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN5 TRUE
+#define SPC5_FLEXCAN5_PCTL 21
+#define SPC5_FLEXCAN5_MB 64
+#define SPC5_FLEXCAN5_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
+#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
+#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC FALSE
+
+#define SPC5_HAS_ADC0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR2 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR4 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR5 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL5 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL6 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL7 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL8 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL9 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL10 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL11 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 TRUE
+#define SPC5_ADC0_PCTL 32
+#define SPC5_ADC0_DMA_DEV_ID 29
+#define SPC5_ADC0_EOC_HANDLER vector62
+#define SPC5_ADC0_EOC_NUMBER 62
+#define SPC5_ADC0_WD_HANDLER vector64
+#define SPC5_ADC0_WD_NUMBER 64
+
+#define SPC5_HAS_ADC1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR3 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR4 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR5 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC1_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL5 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC1_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR2 TRUE
+#define SPC5_ADC1_PCTL 33
+#define SPC5_ADC1_DMA_DEV_ID 30
+#define SPC5_ADC1_EOC_HANDLER vector82
+#define SPC5_ADC1_EOC_NUMBER 82
+#define SPC5_ADC1_WD_HANDLER vector84
+#define SPC5_ADC1_WD_NUMBER 84
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/typedefs.h b/os/hal/ports/SPC5/SPC560Bxx/typedefs.h new file mode 100644 index 000000000..b798a3b5c --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Bxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Bxx/xpc560b.h b/os/hal/ports/SPC5/SPC560Bxx/xpc560b.h new file mode 100644 index 000000000..ac637b6cf --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Bxx/xpc560b.h @@ -0,0 +1,6551 @@ +/*****************************************************************
+ * PROJECT : MPC5607B
+ *
+ * FILE : jdp.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for MPC5607B
+ *
+ * COPYRIGHT :(c) 2008, Freescale & STMicroelectronics
+ *
+ * VERSION : 01.03
+ * DATE : 1.20.2010
+ * AUTHOR : r23668
+ * HISTORY : Hand edited from previous jdp.h file
+ * Changes from rev 1.01
+ * CGM Section replaced with more accurate section from Bolero 512K
+ * eMIOS CADR, CBDR & CCNTR changed from 24 to 16 bit.
+ * CAN Sampler section corrected: 0-15 should be resrved not 16-32.
+ * Includes additions from Stefan Luellman
+* Example instantiation and use:
+*
+* <MODULE>.<REGISTER>.B.<BIT> = 1;
+* <MODULE>.<REGISTER>.R = 0x10000000;
+*
+******************************************************************/
+
+#ifndef _JDP_H_
+#define _JDP_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+
+
+/****************************************************************************/
+/* MODULE : ADC0 */
+/****************************************************************************/
+ struct ADC0_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t EDGLEV:1;
+ vuint32_t TRGEN:1;
+ vuint32_t EDGE:1;
+ vuint32_t XSTRTEN:1;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORT_CHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t:2;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR; /* MAIN CONFIGURATION REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR; /* MAIN STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t OFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t EOFFSET:1;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR; /* INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR0; /* PRECISE CHANNELS PENDING REGISTERS */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH31:1;
+ vuint32_t EOC_CH30:1;
+ vuint32_t EOC_CH29:1;
+ vuint32_t EOC_CH28:1;
+ vuint32_t EOC_CH27:1;
+ vuint32_t EOC_CH26:1;
+ vuint32_t EOC_CH25:1;
+ vuint32_t EOC_CH24:1;
+ vuint32_t EOC_CH23:1;
+ vuint32_t EOC_CH22:1;
+ vuint32_t EOC_CH21:1;
+ vuint32_t EOC_CH20:1;
+ vuint32_t EOC_CH19:1;
+ vuint32_t EOC_CH18:1;
+ vuint32_t EOC_CH17:1;
+ vuint32_t EOC_CH16:1;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR1; /* EXTENDED INTERNAL CHANNELS PENDING REGISTERS */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH31:1;
+ vuint32_t EOC_CH30:1;
+ vuint32_t EOC_CH29:1;
+ vuint32_t EOC_CH28:1;
+ vuint32_t EOC_CH27:1;
+ vuint32_t EOC_CH26:1;
+ vuint32_t EOC_CH25:1;
+ vuint32_t EOC_CH24:1;
+ vuint32_t EOC_CH23:1;
+ vuint32_t EOC_CH22:1;
+ vuint32_t EOC_CH21:1;
+ vuint32_t EOC_CH20:1;
+ vuint32_t EOC_CH19:1;
+ vuint32_t EOC_CH18:1;
+ vuint32_t EOC_CH17:1;
+ vuint32_t EOC_CH16:1;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR2; /* EXTERNAL CHANNELS PENDING REGISTERS */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t MSKOFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t MSKEOFFSET:1;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR; /* INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0; /* PRECISE CHANNELS INTERRUPT MASK 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1;
+ vuint32_t CIM30:1;
+ vuint32_t CIM29:1;
+ vuint32_t CIM28:1;
+ vuint32_t CIM27:1;
+ vuint32_t CIM26:1;
+ vuint32_t CIM25:1;
+ vuint32_t CIM24:1;
+ vuint32_t CIM23:1;
+ vuint32_t CIM22:1;
+ vuint32_t CIM21:1;
+ vuint32_t CIM20:1;
+ vuint32_t CIM19:1;
+ vuint32_t CIM18:1;
+ vuint32_t CIM17:1;
+ vuint32_t CIM16:1;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR1; /* EXTENDED INTERNAL CHANNELS INTERRUPT MASK 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1;
+ vuint32_t CIM30:1;
+ vuint32_t CIM29:1;
+ vuint32_t CIM28:1;
+ vuint32_t CIM27:1;
+ vuint32_t CIM26:1;
+ vuint32_t CIM25:1;
+ vuint32_t CIM24:1;
+ vuint32_t CIM23:1;
+ vuint32_t CIM22:1;
+ vuint32_t CIM21:1;
+ vuint32_t CIM20:1;
+ vuint32_t CIM19:1;
+ vuint32_t CIM18:1;
+ vuint32_t CIM17:1;
+ vuint32_t CIM16:1;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR2; /* EXTERNAL CHANNELS INTERRUPT MASK 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t WDG5H:1; // non validi
+ vuint32_t WDG5L:1; // non validi
+ vuint32_t WDG4H:1; // non validi
+ vuint32_t WDG4L:1; // non validi
+ vuint32_t WDG3H:1; // validi
+ vuint32_t WDG3L:1; // validi
+ vuint32_t WDG2H:1; // validi
+ vuint32_t WDG2L:1; // validi
+ vuint32_t WDG1H:1; // validi
+ vuint32_t WDG1L:1; // validi
+ vuint32_t WDG0H:1; // validi
+ vuint32_t WDG0L:1; // validi
+ } B;
+ } WTISR; /* WATCHDOG THRESHOLD INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t MSKWDG5H:1; // non validi
+ vuint32_t MSKWDG5L:1; // non validi
+ vuint32_t MSKWDG4H:1; // non validi
+ vuint32_t MSKWDG4L:1; // non validi
+ vuint32_t MSKWDG3H:1; // validi
+ vuint32_t MSKWDG2H:1; // validi
+ vuint32_t MSKWDG1H:1; // validi
+ vuint32_t MSKWDG0H:1; // validi
+ vuint32_t MSKWDG3L:1; // validi
+ vuint32_t MSKWDG2L:1; // validi
+ vuint32_t MSKWDG1L:1; // validi
+ vuint32_t MSKWDG0L:1; // validi
+ } B;
+ } WTIMR; /* WATCHDOG THRESHOLD INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE; /* DMA ENABLE REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0; /* PRECISE CHANNELS DMA REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA31:1;
+ vuint32_t DMA30:1;
+ vuint32_t DMA29:1;
+ vuint32_t DMA28:1;
+ vuint32_t DMA27:1;
+ vuint32_t DMA26:1;
+ vuint32_t DMA25:1;
+ vuint32_t DMA24:1;
+ vuint32_t DMA23:1;
+ vuint32_t DMA22:1;
+ vuint32_t DMA21:1;
+ vuint32_t DMA20:1;
+ vuint32_t DMA19:1;
+ vuint32_t DMA18:1;
+ vuint32_t DMA17:1;
+ vuint32_t DMA16:1;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR1; /* EXTENDED INTERNAL CHANNELS DMA REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA31:1;
+ vuint32_t DMA30:1;
+ vuint32_t DMA29:1;
+ vuint32_t DMA28:1;
+ vuint32_t DMA27:1;
+ vuint32_t DMA26:1;
+ vuint32_t DMA25:1;
+ vuint32_t DMA24:1;
+ vuint32_t DMA23:1;
+ vuint32_t DMA22:1;
+ vuint32_t DMA21:1;
+ vuint32_t DMA20:1;
+ vuint32_t DMA19:1;
+ vuint32_t DMA18:1;
+ vuint32_t DMA17:1;
+ vuint32_t DMA16:1;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR2; /* EXTERNAL CHANNELS DMA REGISTER 2 */
+
+ int32_t ADC0_reserved11[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR[4]; /* THRESHOLD REGISTER 0-3 */
+
+
+ int32_t ADC0_reserved12[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR; /* PRESAMPLING CONTROL REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0; /* PRECISE CHANNELS PRESAMPLING REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1;
+ vuint32_t PRES30:1;
+ vuint32_t PRES29:1;
+ vuint32_t PRES28:1;
+ vuint32_t PRES27:1;
+ vuint32_t PRES26:1;
+ vuint32_t PRES25:1;
+ vuint32_t PRES24:1;
+ vuint32_t PRES23:1;
+ vuint32_t PRES22:1;
+ vuint32_t PRES21:1;
+ vuint32_t PRES20:1;
+ vuint32_t PRES19:1;
+ vuint32_t PRES18:1;
+ vuint32_t PRES17:1;
+ vuint32_t PRES16:1;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR1; /* EXTENDED INTERNAL CHANNELS PRESAMPLING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1;
+ vuint32_t PRES30:1;
+ vuint32_t PRES29:1;
+ vuint32_t PRES28:1;
+ vuint32_t PRES27:1;
+ vuint32_t PRES26:1;
+ vuint32_t PRES25:1;
+ vuint32_t PRES24:1;
+ vuint32_t PRES23:1;
+ vuint32_t PRES22:1;
+ vuint32_t PRES21:1;
+ vuint32_t PRES20:1;
+ vuint32_t PRES19:1;
+ vuint32_t PRES18:1;
+ vuint32_t PRES17:1;
+ vuint32_t PRES16:1;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR2; /* EXTERNAL CHANNELS PRESAMPLING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved4;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0; /* PRECISE CHANNELS CONVERSION TIMING REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1; /* EXTENDED INTERNAL CHANNELS CONVERSION TIMING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR2; /* EXTERNAL CHANNELS CONVERSION TIMING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved5;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0; /* PRECISE CHANNELS NORMAL CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR1; /* EXTENDED INTERNAL CHANNELS NORMAL CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR2; /* EXTERNAL CHANNELS NORMAL CONVERSION MASK REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC0_reserved6;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0; /* PRECISE CHANNELS INJECTED CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR1; /* EXTENDED INTERNAL CHANNELS INJECTED CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1;
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR2; /* EXTERNAL CHANNELS INJECTED CONVERSION MASK REGISTER 2 */
+
+
+ int32_t ADC0_reserved_OFFWR; /* Digital offset cancellation removed from 1.5M and removed from spec of 512K */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8;
+ } B;
+ } DSDR; /* DECODE SIGNALS DELAY REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR; /* POWER DOWN EXIT DELAY REGISTER */
+
+
+
+ int32_t ADC0_reserved7[13]; /* {0x100-0x0F0}/0x4 = 4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:6;
+ vuint32_t CDATA:10;
+ } B;
+ } CDR[96]; /* CHANNEL x DATA REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR4; /* THRESHOLD REGISTER 4 */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR5; /* THRESHOLD REGISTER 5 */ /* Bolero 1.5M / ADC0 only */
+
+ int32_t ADC0_reserved8[10];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH7:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH6:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH5:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH4:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH3:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH2:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH1:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH0:3;
+ } B;
+ } CWSELR0; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH15:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH14:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH13:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH12:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH11:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH10:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH9:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH8:3;
+ } B;
+ } CWSELR1; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CWSELR2; /* reserved (16 precise channels only) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CWSELR3; /* reserved (16 precise channels only) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH39:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH38:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH37:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH36:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH35:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH34:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH33:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH32:3;
+ } B;
+ } CWSELR4; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH47:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH46:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH45:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH44:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH43:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH42:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH41:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH40:3;
+ } B;
+ } CWSELR5; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH55:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH54:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH53:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH52:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH51:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH50:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH49:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH48:3;
+ } B;
+ } CWSELR6; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH63:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH62:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH61:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH60:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH59:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH58:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH57:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH56:3;
+ } B;
+ } CWSELR7; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED INTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH71:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH70:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH69:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH68:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH67:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH66:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH65:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH64:3;
+ } B;
+ } CWSELR8; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH79:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH78:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH77:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH76:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH75:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH74:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH73:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH72:3;
+ } B;
+ } CWSELR9; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH87:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH86:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH85:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH84:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH83:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH82:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH81:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH80:3;
+ } B;
+ } CWSELR10; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH95:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH94:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH93:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH92:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH91:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH90:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH89:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH88:3;
+ } B;
+ } CWSELR11; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */ /* Bolero 1.5M / ADC0 only */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CWEN31:1;
+ vuint32_t CWEN30:1;
+ vuint32_t CWEN29:1;
+ vuint32_t CWEN28:1;
+ vuint32_t CWEN27:1;
+ vuint32_t CWEN26:1;
+ vuint32_t CWEN25:1;
+ vuint32_t CWEN24:1;
+ vuint32_t CWEN23:1;
+ vuint32_t CWEN22:1;
+ vuint32_t CWEN21:1;
+ vuint32_t CWEN20:1;
+ vuint32_t CWEN19:1;
+ vuint32_t CWEN18:1;
+ vuint32_t CWEN17:1;
+ vuint32_t CWEN16:1;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR[3]; /* CHANNEL WATCHDOG ENABLE REGISTERS 0-2 */
+
+ int32_t ADC0_reserved9;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AWORR_CH31:1;
+ vuint32_t AWORR_CH30:1;
+ vuint32_t AWORR_CH29:1;
+ vuint32_t AWORR_CH28:1;
+ vuint32_t AWORR_CH27:1;
+ vuint32_t AWORR_CH26:1;
+ vuint32_t AWORR_CH25:1;
+ vuint32_t AWORR_CH24:1;
+ vuint32_t AWORR_CH23:1;
+ vuint32_t AWORR_CH22:1;
+ vuint32_t AWORR_CH21:1;
+ vuint32_t AWORR_CH20:1;
+ vuint32_t AWORR_CH19:1;
+ vuint32_t AWORR_CH18:1;
+ vuint32_t AWORR_CH17:1;
+ vuint32_t AWORR_CH16:1;
+ vuint32_t AWORR_CH15:1;
+ vuint32_t AWORR_CH14:1;
+ vuint32_t AWORR_CH13:1;
+ vuint32_t AWORR_CH12:1;
+ vuint32_t AWORR_CH11:1;
+ vuint32_t AWORR_CH10:1;
+ vuint32_t AWORR_CH9:1;
+ vuint32_t AWORR_CH8:1;
+ vuint32_t AWORR_CH7:1;
+ vuint32_t AWORR_CH6:1;
+ vuint32_t AWORR_CH5:1;
+ vuint32_t AWORR_CH4:1;
+ vuint32_t AWORR_CH3:1;
+ vuint32_t AWORR_CH2:1;
+ vuint32_t AWORR_CH1:1;
+ vuint32_t AWORR_CH0:1;
+ } B;
+ } AWORR[3]; /* ANALOG WATCHDOG OUT OF RANGE REGISTERS 0-2 */
+
+ int32_t ADC0_reserved10;
+
+ }; /* end of ADC0_tag */
+
+
+
+/****************************************************************************/
+/* MODULE : ADC1 */
+/****************************************************************************/
+ struct ADC1_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t EDGLEV:1;
+ vuint32_t TRGEN:1;
+ vuint32_t EDGE:1;
+ vuint32_t XSTRTEN:1;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORT_CHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t:2;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR; /* MAIN CONFIGURATION REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:1; //vuint32_t OFFREFRESH:1;
+ vuint32_t:1; //vuint32_t OFFCANC:1;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR; /* MAIN STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t OFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t EOFFSET:1;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR; /* INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR0; /* PRECISE CHANNELS PENDING REGISTERS */
+
+ int32_t ADC1_reserved11[2];
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t:1; //vuint32_t MSKOFFCANCOVR:1;
+ vuint32_t:1; //vuint32_t MSKEOFFSET:1;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR; /* INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0; /* PRECISE CHANNELS INTERRUPT MASK 0 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM63:1;
+ vuint32_t CIM62:1;
+ vuint32_t CIM61:1;
+ vuint32_t CIM60:1;
+ vuint32_t CIM59:1;
+ vuint32_t CIM58:1;
+ vuint32_t CIM57:1;
+ vuint32_t CIM56:1;
+ vuint32_t CIM55:1;
+ vuint32_t CIM54:1;
+ vuint32_t CIM53:1;
+ vuint32_t CIM52:1;
+ vuint32_t CIM51:1;
+ vuint32_t CIM50:1;
+ vuint32_t CIM49:1;
+ vuint32_t CIM48:1;
+ vuint32_t CIM47:1;
+ vuint32_t CIM46:1;
+ vuint32_t CIM45:1;
+ vuint32_t CIM44:1;
+ vuint32_t CIM43:1;
+ vuint32_t CIM42:1;
+ vuint32_t CIM41:1;
+ vuint32_t CIM40:1;
+ vuint32_t CIM39:1;
+ vuint32_t CIM38:1;
+ vuint32_t CIM37:1;
+ vuint32_t CIM36:1;
+ vuint32_t CIM35:1;
+ vuint32_t CIM34:1;
+ vuint32_t CIM33:1;
+ vuint32_t CIM32:1;
+ } B;
+ } CIMR1; /* EXTENDED CHANNELS INTERRUPT MASK 1 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM95:1;
+ vuint32_t CIM94:1;
+ vuint32_t CIM93:1;
+ vuint32_t CIM92:1;
+ vuint32_t CIM91:1;
+ vuint32_t CIM90:1;
+ vuint32_t CIM89:1;
+ vuint32_t CIM88:1;
+ vuint32_t CIM87:1;
+ vuint32_t CIM86:1;
+ vuint32_t CIM85:1;
+ vuint32_t CIM84:1;
+ vuint32_t CIM83:1;
+ vuint32_t CIM82:1;
+ vuint32_t CIM81:1;
+ vuint32_t CIM80:1;
+ vuint32_t CIM79:1;
+ vuint32_t CIM78:1;
+ vuint32_t CIM77:1;
+ vuint32_t CIM76:1;
+ vuint32_t CIM75:1;
+ vuint32_t CIM74:1;
+ vuint32_t CIM73:1;
+ vuint32_t CIM72:1;
+ vuint32_t CIM71:1;
+ vuint32_t CIM70:1;
+ vuint32_t CIM69:1;
+ vuint32_t CIM68:1;
+ vuint32_t CIM67:1;
+ vuint32_t CIM66:1;
+ vuint32_t CIM65:1;
+ vuint32_t CIM64:1;
+ } B;
+ } CIMR2; /* EXTERNAL CHANNELS INTERRUPT MASK 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t WDG5H:1; // non validi
+ vuint32_t WDG5L:1; // non validi
+ vuint32_t WDG4H:1; // non validi
+ vuint32_t WDG4L:1; // non validi
+ vuint32_t WDG3H:1; // validi
+ vuint32_t WDG3L:1; // validi
+ vuint32_t WDG2H:1; // validi
+ vuint32_t WDG2L:1; // validi
+ vuint32_t WDG1H:1; // validi
+ vuint32_t WDG1L:1; // validi
+ vuint32_t WDG0H:1; // validi
+ vuint32_t WDG0L:1; // validi
+ } B;
+ } WTISR; /* WATCHDOG THRESHOLD INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t MSKWDG5H:1; // non validi
+ vuint32_t MSKWDG5L:1; // non validi
+ vuint32_t MSKWDG4H:1; // non validi
+ vuint32_t MSKWDG4L:1; // non validi
+ vuint32_t MSKWDG3H:1; // validi
+ vuint32_t MSKWDG2H:1; // validi
+ vuint32_t MSKWDG1H:1; // validi
+ vuint32_t MSKWDG0H:1; // validi
+ vuint32_t MSKWDG3L:1; // validi
+ vuint32_t MSKWDG2L:1; // validi
+ vuint32_t MSKWDG1L:1; // validi
+ vuint32_t MSKWDG0L:1; // validi
+ } B;
+ } WTIMR; /* WATCHDOG THRESHOLD INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE; /* DMA ENABLE REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0; /* PRECISE CHANNELS DMA REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA63:1;
+ vuint32_t DMA62:1;
+ vuint32_t DMA61:1;
+ vuint32_t DMA60:1;
+ vuint32_t DMA59:1;
+ vuint32_t DMA58:1;
+ vuint32_t DMA57:1;
+ vuint32_t DMA56:1;
+ vuint32_t DMA55:1;
+ vuint32_t DMA54:1;
+ vuint32_t DMA53:1;
+ vuint32_t DMA52:1;
+ vuint32_t DMA51:1;
+ vuint32_t DMA50:1;
+ vuint32_t DMA49:1;
+ vuint32_t DMA48:1;
+ vuint32_t DMA47:1;
+ vuint32_t DMA46:1;
+ vuint32_t DMA45:1;
+ vuint32_t DMA44:1;
+ vuint32_t DMA43:1;
+ vuint32_t DMA42:1;
+ vuint32_t DMA41:1;
+ vuint32_t DMA40:1;
+ vuint32_t DMA39:1;
+ vuint32_t DMA38:1;
+ vuint32_t DMA37:1;
+ vuint32_t DMA36:1;
+ vuint32_t DMA35:1;
+ vuint32_t DMA34:1;
+ vuint32_t DMA33:1;
+ vuint32_t DMA32:1;
+ } B;
+ } DMAR1; /* EXTENDED INTERNAL CHANNELS DMA REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA95:1;
+ vuint32_t DMA94:1;
+ vuint32_t DMA93:1;
+ vuint32_t DMA92:1;
+ vuint32_t DMA91:1;
+ vuint32_t DMA90:1;
+ vuint32_t DMA89:1;
+ vuint32_t DMA88:1;
+ vuint32_t DMA87:1;
+ vuint32_t DMA86:1;
+ vuint32_t DMA85:1;
+ vuint32_t DMA84:1;
+ vuint32_t DMA83:1;
+ vuint32_t DMA82:1;
+ vuint32_t DMA81:1;
+ vuint32_t DMA80:1;
+ vuint32_t DMA79:1;
+ vuint32_t DMA78:1;
+ vuint32_t DMA77:1;
+ vuint32_t DMA76:1;
+ vuint32_t DMA75:1;
+ vuint32_t DMA74:1;
+ vuint32_t DMA73:1;
+ vuint32_t DMA72:1;
+ vuint32_t DMA71:1;
+ vuint32_t DMA70:1;
+ vuint32_t DMA69:1;
+ vuint32_t DMA68:1;
+ vuint32_t DMA67:1;
+ vuint32_t DMA66:1;
+ vuint32_t DMA65:1;
+ vuint32_t DMA64:1;
+ } B;
+ } DMAR2; /* EXTERNAL CHANNELS DMA REGISTER 2 */
+
+ int32_t ADC1_reserved13[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR[3]; /* THRESHOLD REGISTER 0-2 */
+
+ int32_t ADC1_reserved14[5];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR; /* PRESAMPLING CONTROL REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0; /* PRECISE CHANNELS PRESAMPLING REGISTER 0 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES63:1;
+ vuint32_t PRES62:1;
+ vuint32_t PRES61:1;
+ vuint32_t PRES60:1;
+ vuint32_t PRES59:1;
+ vuint32_t PRES58:1;
+ vuint32_t PRES57:1;
+ vuint32_t PRES56:1;
+ vuint32_t PRES55:1;
+ vuint32_t PRES54:1;
+ vuint32_t PRES53:1;
+ vuint32_t PRES52:1;
+ vuint32_t PRES51:1;
+ vuint32_t PRES50:1;
+ vuint32_t PRES49:1;
+ vuint32_t PRES48:1;
+ vuint32_t PRES47:1;
+ vuint32_t PRES46:1;
+ vuint32_t PRES45:1;
+ vuint32_t PRES44:1;
+ vuint32_t PRES43:1;
+ vuint32_t PRES42:1;
+ vuint32_t PRES41:1;
+ vuint32_t PRES40:1;
+ vuint32_t PRES39:1;
+ vuint32_t PRES38:1;
+ vuint32_t PRES37:1;
+ vuint32_t PRES36:1;
+ vuint32_t PRES35:1;
+ vuint32_t PRES34:1;
+ vuint32_t PRES33:1;
+ vuint32_t PRES32:1;
+ } B;
+ } PSR1; /* EXTENDED CHANNELS PRESAMPLING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES95:1;
+ vuint32_t PRES94:1;
+ vuint32_t PRES93:1;
+ vuint32_t PRES92:1;
+ vuint32_t PRES91:1;
+ vuint32_t PRES90:1;
+ vuint32_t PRES89:1;
+ vuint32_t PRES88:1;
+ vuint32_t PRES87:1;
+ vuint32_t PRES86:1;
+ vuint32_t PRES85:1;
+ vuint32_t PRES84:1;
+ vuint32_t PRES83:1;
+ vuint32_t PRES82:1;
+ vuint32_t PRES81:1;
+ vuint32_t PRES80:1;
+ vuint32_t PRES79:1;
+ vuint32_t PRES78:1;
+ vuint32_t PRES77:1;
+ vuint32_t PRES76:1;
+ vuint32_t PRES75:1;
+ vuint32_t PRES74:1;
+ vuint32_t PRES73:1;
+ vuint32_t PRES72:1;
+ vuint32_t PRES71:1;
+ vuint32_t PRES70:1;
+ vuint32_t PRES69:1;
+ vuint32_t PRES68:1;
+ vuint32_t PRES67:1;
+ vuint32_t PRES66:1;
+ vuint32_t PRES65:1;
+ vuint32_t PRES64:1;
+ } B;
+ } PSR2; /* EXTERNAL CHANNELS PRESAMPLING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved4;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0; /* PRECISE CHANNELS CONVERSION TIMING REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1; /* EXTENDED CHANNELS CONVERSION TIMING REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR2; /* EXTERNAL CHANNELS CONVERSION TIMING REGISTER 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved5;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0; /* PRECISE CHANNELS NORMAL CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH63:1;
+ vuint32_t CH62:1;
+ vuint32_t CH61:1;
+ vuint32_t CH60:1;
+ vuint32_t CH59:1;
+ vuint32_t CH58:1;
+ vuint32_t CH57:1;
+ vuint32_t CH56:1;
+ vuint32_t CH55:1;
+ vuint32_t CH54:1;
+ vuint32_t CH53:1;
+ vuint32_t CH52:1;
+ vuint32_t CH51:1;
+ vuint32_t CH50:1;
+ vuint32_t CH49:1;
+ vuint32_t CH48:1;
+ vuint32_t CH47:1;
+ vuint32_t CH46:1;
+ vuint32_t CH45:1;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } NCMR1; /* EXTENDED CHANNELS NORMAL CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } NCMR2; /* EXTERNAL CHANNELS NORMAL CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } ADC1_reserved6;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0; /* PRECISE CHANNELS INJECTED CONVERSION MASK REGISTER 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH63:1;
+ vuint32_t CH62:1;
+ vuint32_t CH61:1;
+ vuint32_t CH60:1;
+ vuint32_t CH59:1;
+ vuint32_t CH58:1;
+ vuint32_t CH57:1;
+ vuint32_t CH56:1;
+ vuint32_t CH55:1;
+ vuint32_t CH54:1;
+ vuint32_t CH53:1;
+ vuint32_t CH52:1;
+ vuint32_t CH51:1;
+ vuint32_t CH50:1;
+ vuint32_t CH49:1;
+ vuint32_t CH48:1;
+ vuint32_t CH47:1;
+ vuint32_t CH46:1;
+ vuint32_t CH45:1;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } JCMR1; /* EXTENDED CHANNELS INJECTED CONVERSION MASK REGISTER 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } JCMR2; /* EXTERNAL CHANNELS INJECTED CONVERSION MASK REGISTER 2 */
+
+ int32_t ADC1_reserved18[1];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8;
+ } B;
+ } DSDR; /* DECODE SIGNALS DELAY REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR; /* POWER DOWN EXIT DELAY REGISTER */
+
+
+ int32_t ADC1_reserved7[13]; /* {0x100-0x0F0}/0x4 = 4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:4;
+ vuint32_t CDATA:12;
+ } B;
+ } CDR[95]; /* CHANNEL x DATA REGISTER */
+
+
+
+ int32_t ADC1_reserved8[13];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH7:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH6:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH5:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH4:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH3:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH2:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH1:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH0:3;
+ } B;
+ } CWSELR0; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH15:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH14:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH13:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH12:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH11:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH10:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH9:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH8:3;
+ } B;
+ } CWSELR1; /* CHANNEL WATCHDOG SELECTION REGISTERS (PRECISE CHANNELS) */
+
+ int32_t ADC1_reserved19[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH39:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH38:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH37:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH36:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH35:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH34:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH33:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH32:3;
+ } B;
+ } CWSELR4; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH47:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH46:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH45:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH44:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH43:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH42:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH41:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH40:3;
+ } B;
+ } CWSELR5; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTENDED CHANNELS) */
+
+ int32_t ADC1_reserved20[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH71:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH70:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH69:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH68:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH67:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH66:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH65:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH64:3;
+ } B;
+ } CWSELR8; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH79:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH78:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH77:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH76:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH75:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH74:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH73:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH72:3;
+ } B;
+ } CWSELR9; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH87:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH86:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH85:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH84:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH83:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH82:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH81:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH80:3;
+ } B;
+ } CWSELR10; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH95:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH94:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH93:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH92:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH91:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH90:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH89:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH88:3;
+ } B;
+ } CWSELR11; /* CHANNEL WATCHDOG SELECTION REGISTERS (EXTERNAL CHANNELS) */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CWEN31:1;
+ vuint32_t CWEN30:1;
+ vuint32_t CWEN29:1;
+ vuint32_t CWEN28:1;
+ vuint32_t CWEN27:1;
+ vuint32_t CWEN26:1;
+ vuint32_t CWEN25:1;
+ vuint32_t CWEN24:1;
+ vuint32_t CWEN23:1;
+ vuint32_t CWEN22:1;
+ vuint32_t CWEN21:1;
+ vuint32_t CWEN20:1;
+ vuint32_t CWEN19:1;
+ vuint32_t CWEN18:1;
+ vuint32_t CWEN17:1;
+ vuint32_t CWEN16:1;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR[3]; /* CHANNEL WATCHDOG ENABLE REGISTERS 0-2 */
+
+ int32_t ADC1_reserved9[1];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AWORR_CH31:1;
+ vuint32_t AWORR_CH30:1;
+ vuint32_t AWORR_CH29:1;
+ vuint32_t AWORR_CH28:1;
+ vuint32_t AWORR_CH27:1;
+ vuint32_t AWORR_CH26:1;
+ vuint32_t AWORR_CH25:1;
+ vuint32_t AWORR_CH24:1;
+ vuint32_t AWORR_CH23:1;
+ vuint32_t AWORR_CH22:1;
+ vuint32_t AWORR_CH21:1;
+ vuint32_t AWORR_CH20:1;
+ vuint32_t AWORR_CH19:1;
+ vuint32_t AWORR_CH18:1;
+ vuint32_t AWORR_CH17:1;
+ vuint32_t AWORR_CH16:1;
+ vuint32_t AWORR_CH15:1;
+ vuint32_t AWORR_CH14:1;
+ vuint32_t AWORR_CH13:1;
+ vuint32_t AWORR_CH12:1;
+ vuint32_t AWORR_CH11:1;
+ vuint32_t AWORR_CH10:1;
+ vuint32_t AWORR_CH9:1;
+ vuint32_t AWORR_CH8:1;
+ vuint32_t AWORR_CH7:1;
+ vuint32_t AWORR_CH6:1;
+ vuint32_t AWORR_CH5:1;
+ vuint32_t AWORR_CH4:1;
+ vuint32_t AWORR_CH3:1;
+ vuint32_t AWORR_CH2:1;
+ vuint32_t AWORR_CH1:1;
+ vuint32_t AWORR_CH0:1;
+ } B;
+ } AWORR[3]; /* ANALOG WATCHDOG OUT OF RANGE REGISTERS */
+
+ }; /* end of ADC1_tag */
+
+
+
+/****************************************************************************/
+/* MODULE : CANSP */
+/****************************************************************************/
+ struct CANSP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RX_COMPLETE:1;
+ vuint32_t BUSY:1;
+ vuint32_t ACTIVE_CK:1;
+ vuint32_t:3;
+ vuint32_t MODE:1;
+ vuint32_t CAN_RX_SEL:3;
+ vuint32_t BRP:5;
+ vuint32_t CAN_SMPLR_EN:1;
+ } B;
+ } CR; /* CANSP Control Register */
+
+ union {
+ vuint32_t R;
+ } SR[12]; /* CANSP Sample Register 0 to 11 */
+
+ }; /* end of CANSP_tag */
+/****************************************************************************/
+/* MODULE : MCM */
+/****************************************************************************/
+ struct ECSM_tag {
+
+ union {
+ vuint16_t R;
+ } PCT; /* MCM Processor Core Type Register */
+
+ union {
+ vuint16_t R;
+ } REV; /* MCM Revision Register */
+
+ int32_t MCM_reserved;
+
+ union {
+ vuint32_t R;
+ } MC; /* MCM Configuration Register */
+
+ int8_t MCM_reserved1[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t POR:1;
+ vuint8_t DIR:1;
+ vuint8_t:6;
+ } B;
+ } MRSR; /* MCM Miscellaneous Reset Status Register */
+
+ int8_t MCM_reserved2[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1;
+ vuint8_t:3;
+ vuint8_t PRILVL:4;
+ } B;
+ } MWCR; /* MCM Miscellaneous Wakeup Control Register */
+
+ int32_t MCM_reserved3[2];
+ int8_t MCM_reserved4[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1;
+ vuint8_t FB0SI:1;
+ vuint8_t FB1AI:1;
+ vuint8_t FB1SI:1;
+ vuint8_t:4;
+ } B;
+ } MIR; /* MCM Miscellaneous Interrupt Register */
+
+ int32_t MCM_reserved5;
+
+ union {
+ vuint32_t R;
+ } MUDCR; /* MCM Miscellaneous User-Defined Control Register */
+
+ int32_t MCM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */
+ int8_t MCM_reserved7[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t:2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR; /* MCM ECC Configuration Register */
+
+ int8_t MCM_reserved8[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t:2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR; /* MCM ECC Status Register */
+
+ int16_t MCM_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t:2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t:1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR; /* MCM ECC Error Generation Register */
+
+ int32_t MCM_reserved10;
+
+ union {
+ vuint32_t R;
+ } FEAR; /* MCM Flash ECC Address Register */
+
+ int16_t MCM_reserved11;
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR; /* MCM Flash ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } FEAT; /* MCM Flash ECC Attributes Register */
+
+ int32_t MCM_reserved12;
+
+ union {
+ vuint32_t R;
+ } FEDR; /* MCM Flash ECC Data Register */
+
+ union {
+ vuint32_t R;
+ } REAR; /* MCM RAM ECC Address Register */
+
+ int8_t MCM_reserved13;
+
+ union {
+ vuint8_t R;
+ } RESR; /* MCM RAM ECC Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR; /* MCM RAM ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } REAT; /* MCM RAM ECC Attributes Register */
+
+ int32_t MCM_reserved14;
+
+ union {
+ vuint32_t R;
+ } REDR; /* MCM RAM ECC Data Register */
+
+ }; /* end of MCM_tag */
+/****************************************************************************/
+/* MODULE : RTC */
+/****************************************************************************/
+ struct RTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SUPV:1;
+ vuint32_t:31;
+ } B;
+ } RTCSUPV; /* RTC Supervisor Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNTEN:1;
+ vuint32_t RTCIE:1;
+ vuint32_t FRZEN:1;
+ vuint32_t ROVREN:1;
+ vuint32_t RTCVAL:12;
+ vuint32_t APIEN:1;
+ vuint32_t APIE:1;
+ vuint32_t CLKSEL:2;
+ vuint32_t DIV512EN:1;
+ vuint32_t DIV32EN:1;
+ vuint32_t APIVAL:10;
+ } B;
+ } RTCC; /* RTC Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t RTCF:1;
+ vuint32_t:15;
+ vuint32_t APIF:1;
+ vuint32_t:2;
+ vuint32_t ROVRF:1;
+ vuint32_t:10;
+ } B;
+ } RTCS; /* RTC Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RTCCNT:32;
+ } B;
+ } RTCCNT; /* RTC Counter Register */
+
+ }; /* end of RTC_tag */
+/****************************************************************************/
+/* MODULE : SIU */
+/****************************************************************************/
+ struct SIU_tag {
+
+ int32_t SIU_reserved0;
+
+ union { /* MCU ID Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16;
+ vuint32_t CSP:1;
+ vuint32_t PKG:5;
+ vuint32_t:2;
+ vuint32_t MAJOR_MASK:4;
+ vuint32_t MINOR_MASK:4;
+ } B;
+ } MIDR;
+
+ union { /* MCU ID Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1;
+ vuint32_t FLASH_SIZE_1:4;
+ vuint32_t FLASH_SIZE_2:4;
+ vuint32_t:7;
+ vuint32_t PARTNUM:8;
+ vuint32_t:3;
+ vuint32_t EE:1;
+ vuint32_t:4;
+ } B;
+ } MIDR2;
+
+ int32_t SIU_reserved1[2];
+
+ union { /* Interrupt Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIF31:1;
+ vuint32_t EIF30:1;
+ vuint32_t EIF29:1;
+ vuint32_t EIF28:1;
+ vuint32_t EIF27:1;
+ vuint32_t EIF26:1;
+ vuint32_t EIF25:1;
+ vuint32_t EIF24:1;
+ vuint32_t EIF23:1;
+ vuint32_t EIF22:1;
+ vuint32_t EIF21:1;
+ vuint32_t EIF20:1;
+ vuint32_t EIF19:1;
+ vuint32_t EIF18:1;
+ vuint32_t EIF17:1;
+ vuint32_t EIF16:1;
+ vuint32_t EIF15:1;
+ vuint32_t EIF14:1;
+ vuint32_t EIF13:1;
+ vuint32_t EIF12:1;
+ vuint32_t EIF11:1;
+ vuint32_t EIF10:1;
+ vuint32_t EIF9:1;
+ vuint32_t EIF8:1;
+ vuint32_t EIF7:1;
+ vuint32_t EIF6:1;
+ vuint32_t EIF5:1;
+ vuint32_t EIF4:1;
+ vuint32_t EIF3:1;
+ vuint32_t EIF2:1;
+ vuint32_t EIF1:1;
+ vuint32_t EIF0:1;
+ } B;
+ } ISR;
+
+ union { /* Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE31:1;
+ vuint32_t EIRE30:1;
+ vuint32_t EIRE29:1;
+ vuint32_t EIRE28:1;
+ vuint32_t EIRE27:1;
+ vuint32_t EIRE26:1;
+ vuint32_t EIRE25:1;
+ vuint32_t EIRE24:1;
+ vuint32_t EIRE23:1;
+ vuint32_t EIRE22:1;
+ vuint32_t EIRE21:1;
+ vuint32_t EIRE20:1;
+ vuint32_t EIRE19:1;
+ vuint32_t EIRE18:1;
+ vuint32_t EIRE17:1;
+ vuint32_t EIRE16:1;
+ vuint32_t EIRE15:1;
+ vuint32_t EIRE14:1;
+ vuint32_t EIRE13:1;
+ vuint32_t EIRE12:1;
+ vuint32_t EIRE11:1;
+ vuint32_t EIRE10:1;
+ vuint32_t EIRE9:1;
+ vuint32_t EIRE8:1;
+ vuint32_t EIRE7:1;
+ vuint32_t EIRE6:1;
+ vuint32_t EIRE5:1;
+ vuint32_t EIRE4:1;
+ vuint32_t EIRE3:1;
+ vuint32_t EIRE2:1;
+ vuint32_t EIRE1:1;
+ vuint32_t EIRE0:1;
+ } B;
+ } IRER;
+
+ int32_t SIU_reserved2[3];
+
+ union { /* Interrupt Rising-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IREE31:1;
+ vuint32_t IREE30:1;
+ vuint32_t IREE29:1;
+ vuint32_t IREE28:1;
+ vuint32_t IREE27:1;
+ vuint32_t IREE26:1;
+ vuint32_t IREE25:1;
+ vuint32_t IREE24:1;
+ vuint32_t IREE23:1;
+ vuint32_t IREE22:1;
+ vuint32_t IREE21:1;
+ vuint32_t IREE20:1;
+ vuint32_t IREE19:1;
+ vuint32_t IREE18:1;
+ vuint32_t IREE17:1;
+ vuint32_t IREE16:1;
+ vuint32_t IREE15:1;
+ vuint32_t IREE14:1;
+ vuint32_t IREE13:1;
+ vuint32_t IREE12:1;
+ vuint32_t IREE11:1;
+ vuint32_t IREE10:1;
+ vuint32_t IREE9:1;
+ vuint32_t IREE8:1;
+ vuint32_t IREE7:1;
+ vuint32_t IREE6:1;
+ vuint32_t IREE5:1;
+ vuint32_t IREE4:1;
+ vuint32_t IREE3:1;
+ vuint32_t IREE2:1;
+ vuint32_t IREE1:1;
+ vuint32_t IREE0:1;
+ } B;
+ } IREER;
+
+ union { /* Interrupt Falling-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE31:1;
+ vuint32_t IFEE30:1;
+ vuint32_t IFEE29:1;
+ vuint32_t IFEE28:1;
+ vuint32_t IFEE27:1;
+ vuint32_t IFEE26:1;
+ vuint32_t IFEE25:1;
+ vuint32_t IFEE24:1;
+ vuint32_t IFEE23:1;
+ vuint32_t IFEE22:1;
+ vuint32_t IFEE21:1;
+ vuint32_t IFEE20:1;
+ vuint32_t IFEE19:1;
+ vuint32_t IFEE18:1;
+ vuint32_t IFEE17:1;
+ vuint32_t IFEE16:1;
+ vuint32_t IFEE15:1;
+ vuint32_t IFEE14:1;
+ vuint32_t IFEE13:1;
+ vuint32_t IFEE12:1;
+ vuint32_t IFEE11:1;
+ vuint32_t IFEE10:1;
+ vuint32_t IFEE9:1;
+ vuint32_t IFEE8:1;
+ vuint32_t IFEE7:1;
+ vuint32_t IFEE6:1;
+ vuint32_t IFEE5:1;
+ vuint32_t IFEE4:1;
+ vuint32_t IFEE3:1;
+ vuint32_t IFEE2:1;
+ vuint32_t IFEE1:1;
+ vuint32_t IFEE0:1;
+ } B;
+ } IFEER;
+
+ union { /* Interrupt Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFE31:1;
+ vuint32_t IFE30:1;
+ vuint32_t IFE29:1;
+ vuint32_t IFE28:1;
+ vuint32_t IFE27:1;
+ vuint32_t IFE26:1;
+ vuint32_t IFE25:1;
+ vuint32_t IFE24:1;
+ vuint32_t IFE23:1;
+ vuint32_t IFE22:1;
+ vuint32_t IFE21:1;
+ vuint32_t IFE20:1;
+ vuint32_t IFE19:1;
+ vuint32_t IFE18:1;
+ vuint32_t IFE17:1;
+ vuint32_t IFE16:1;
+ vuint32_t IFE15:1;
+ vuint32_t IFE14:1;
+ vuint32_t IFE13:1;
+ vuint32_t IFE12:1;
+ vuint32_t IFE11:1;
+ vuint32_t IFE10:1;
+ vuint32_t IFE9:1;
+ vuint32_t IFE8:1;
+ vuint32_t IFE7:1;
+ vuint32_t IFE6:1;
+ vuint32_t IFE5:1;
+ vuint32_t IFE4:1;
+ vuint32_t IFE3:1;
+ vuint32_t IFE2:1;
+ vuint32_t IFE1:1;
+ vuint32_t IFE0:1;
+ } B;
+ } IFER;
+
+ int32_t SIU_reserved3[3];
+
+ union { /* Pad Configuration Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SME:1;
+ vuint16_t APC:1; //modified by safdar
+ vuint16_t APC0:1; //added by safdar
+ vuint16_t PA:2;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t DCS:2;
+ vuint16_t ODE:1;
+ vuint16_t HYS:1;
+ vuint16_t SRC:2;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[149];
+
+ int16_t SIU_reserved12[363];
+ int32_t SIU_reserved4[48]; /* {0x500-0x440}/0x4 */
+
+ union { /* Pad Selection for Multiplexed Input Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PADSEL:4;
+ } B;
+ } PSMI[64];
+
+ int32_t SIU_reserved5[48]; /* {0x500-0x440}/0x4 */
+
+ union { /* GPIO Pin Data Output Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[152];
+
+ int32_t SIU_reserved6[90]; /* {0x500-0x440}/0x4 */
+
+ union { /* GPIO Pin Data Input Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[152];
+ int32_t SIU_reserved13[128];
+ int32_t SIU_reserved7[90]; /* {0xC00-0xA00}/0x4 */
+
+ union { /* Parallel GPIO Pin Data Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPD0:32;
+ } B;
+ } PGPDO[5];
+
+ int32_t SIU_reserved8[11]; /* {0xC00-0xA00}/0x4 */
+
+ union { /* Parallel GPIO Pin Data Input Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDI:32;
+ } B;
+ } PGPDI[5];
+
+ int32_t SIU_reserved9[11]; /* {0xC00-0xA00}/0x4 */
+
+
+ union { /* Masked Parallel GPIO Pin Data Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16;
+ vuint32_t MPPDO:16;
+ } B;
+ } MPGPDO[10];
+
+ int32_t SIU_reserved10[214]; /* {0x1000-0x0D00}/0x4 */
+
+ union { /* Interrupt Filter Maximum Counter Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t MAXCNT:4;
+ } B;
+ } IFMC[24];
+
+ int32_t SIU_reserved11[8]; /* {0x1000-0x0D00}/0x4 */
+
+ union { /* Interrupt Filter Clock Prescaler Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFCP:4;
+ } B;
+ } IFCPR;
+
+ }; /* end of SIU_tag */
+/****************************************************************************/
+/* MODULE : SSCM */
+/****************************************************************************/
+ struct SSCM_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t NXEN:1;
+ vuint16_t:1;
+ vuint16_t SEC:1;
+ vuint16_t:1;
+ vuint16_t BMODE:3;
+ vuint16_t DMID:1;
+ vuint16_t ABD:1;
+ vuint16_t:3;
+ } B;
+ } STATUS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SRAMSIZE:5;
+ vuint16_t IFLASHSIZE:5;
+ vuint16_t IVLD:1;
+ vuint16_t DFLASHSIZE:4;
+ vuint16_t DVLD:1;
+ } B;
+ } MEMCONFIG; /* System Memory Configuration Register */
+
+ int16_t SSCM_reserved;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:14;
+ vuint16_t PAE:1;
+ vuint16_t RAE:1;
+ } B;
+ } ERROR; /* Error Configuration Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:13;
+ vuint16_t DEBUG_MODE:3;
+ } B;
+ } DEBUGPORT; /* Debug Status Port Register */
+
+ int16_t SSCM_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32;
+ } B;
+ } PWCMPH; /* Password Comparison Register High Word */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32;
+ } B;
+ } PWCMPL; /* Password Comparison Register Low Word */
+
+ }; /* end of SSCM_tag */
+/****************************************************************************/
+/* MODULE : STM */
+/****************************************************************************/
+ struct STM_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8;
+ vuint32_t:6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR0; /* STM Control Register */
+
+ union {
+ vuint32_t R;
+ } CNT0; /* STM Count Register */
+
+ int32_t STM_reserved[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR0; /* STM Channel Control Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR0; /* STM Channel Interrupt Register 0 */
+
+ union {
+ vuint32_t R;
+ } CMP0; /* STM Channel Compare Register 0 */
+
+ int32_t STM_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR1; /* STM Channel Control Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR1; /* STM Channel Interrupt Register 1 */
+
+ union {
+ vuint32_t R;
+ } CMP1; /* STM Channel Compare Register 1 */
+
+ int32_t STM_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR2; /* STM Channel Control Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR2; /* STM Channel Interrupt Register 2 */
+
+ union {
+ vuint32_t R;
+ } CMP2; /* STM Channel Compare Register 2 */
+
+ int32_t STM_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR3; /* STM Channel Control Register 3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR3; /* STM Channel Interrupt Register 3 */
+
+ union {
+ vuint32_t R;
+ } CMP3; /* STM Channel Compare Register 3 */
+
+ }; /* end of STM_tag */
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+ struct SWT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t:15;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } CR; /* SWT Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } IR; /* SWT Interrupt Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO; /* SWT Time-Out Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+ } B;
+ } WN; /* SWT Window Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16;
+ } B;
+ } SR; /* SWT Service Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO; /* SWT Counter Output Register */
+
+ }; /* end of SWT_tag */
+/****************************************************************************/
+/* MODULE : WKUP */
+/****************************************************************************/
+ struct WKUP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1;
+ vuint32_t NOVF0:1;
+ vuint32_t:6;
+ vuint32_t NIF1:1;
+ vuint32_t NOVF1:1;
+ vuint32_t:6;
+ vuint32_t NIF2:1;
+ vuint32_t NOVF2:1;
+ vuint32_t:6;
+ vuint32_t NIF3:1;
+ vuint32_t NOVF3:1;
+ vuint32_t:6;
+ } B;
+ } NSR; /* NMI Status Register */
+
+ int32_t WKUP_reserved;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK0:1;
+ vuint32_t NDSS0:2;
+ vuint32_t NWRE0:1;
+ vuint32_t:1;
+ vuint32_t NREE0:1;
+ vuint32_t NFEE0:1;
+ vuint32_t NFE0:1;
+ vuint32_t NLOCK1:1;
+ vuint32_t NDSS1:2;
+ vuint32_t NWRE1:1;
+ vuint32_t:1;
+ vuint32_t NREE1:1;
+ vuint32_t NFEE1:1;
+ vuint32_t NFE1:1;
+ vuint32_t NLOCK2:1;
+ vuint32_t NDSS2:2;
+ vuint32_t NWRE2:1;
+ vuint32_t:1;
+ vuint32_t NREE2:1;
+ vuint32_t NFEE2:1;
+ vuint32_t NFE2:1;
+ vuint32_t NLOCK3:1;
+ vuint32_t NDSS3:2;
+ vuint32_t NWRE3:1;
+ vuint32_t:1;
+ vuint32_t NREE3:1;
+ vuint32_t NFEE3:1;
+ vuint32_t NFE3:1;
+ } B;
+ } NCR; /* NMI Configuration Register */
+
+ int32_t WKUP_reserved1[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EIF:32;
+ } B;
+ } WISR; /* Wakeup/Interrupt Status Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE:32;
+ } B;
+ } IRER; /* Interrupt Request Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WRE:32;
+ } B;
+ } WRER; /* Wakeup Request Enable Register */
+
+ int32_t WKUP_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IREE:32;
+ } B;
+ } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE:32;
+ } B;
+ } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IFE:32;
+ } B;
+ } WIFER; /* Wakeup/Interrupt Filter Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IPUE:32;
+ } B;
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
+
+ }; /* end of WKUP_tag */
+/****************************************************************************/
+/* MODULE : LINFLEX */
+/****************************************************************************/
+
+ struct LINFLEX_tag {
+
+ int16_t LINFLEX_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CCD:1;
+ vuint16_t CFD:1;
+ vuint16_t LASE:1;
+ vuint16_t AWUM:1; // LCH vuint16_t AUTOWU:1;
+ vuint16_t MBL:4;
+ vuint16_t BF:1;
+ vuint16_t SLFM:1;
+ vuint16_t LBKM:1;
+ vuint16_t MME:1;
+ vuint16_t SBDT:1; // LCH vuint16_t SSBL:1;
+ vuint16_t RBLM:1;
+ vuint16_t SLEEP:1;
+ vuint16_t INIT:1;
+ } B;
+ } LINCR1; /* LINFLEX LIN Control Register 1 */
+
+ int16_t LINFLEX_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZIE:1;
+ vuint16_t OCIE:1;
+ vuint16_t BEIE:1;
+ vuint16_t CEIE:1;
+ vuint16_t HEIE:1;
+ vuint16_t:2;
+ vuint16_t FEIE:1;
+ vuint16_t BOIE:1;
+ vuint16_t LSIE:1;
+ vuint16_t WUIE:1;
+ vuint16_t DBFIE:1;
+ vuint16_t DBEIE:1;
+ vuint16_t DRIE:1;
+ vuint16_t DTIE:1;
+ vuint16_t HRIE:1;
+ } B;
+ } LINIER; /* LINFLEX LIN Interrupt Enable Register */
+
+ int16_t LINFLEX_reserved3;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LINS:4;
+ vuint16_t:2;
+ vuint16_t RMB:1;
+ vuint16_t:1;
+ vuint16_t RBSY:1; // LCH vuint16_t RXBUSY:1;
+ vuint16_t RPS:1; // LCH vuint16_t RDI:1;
+ vuint16_t WUF:1;
+ vuint16_t DBFF:1;
+ vuint16_t DBEF:1;
+ vuint16_t DRF:1;
+ vuint16_t DTF:1;
+ vuint16_t HRF:1;
+ } B;
+ } LINSR; /* LINFLEX LIN Status Register */
+
+ int16_t LINFLEX_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF:1;
+ vuint16_t OCF:1;
+ vuint16_t BEF:1;
+ vuint16_t CEF:1;
+ vuint16_t SFEF:1;
+ vuint16_t SDEF:1;
+ vuint16_t IDPEF:1;
+ vuint16_t FEF:1;
+ vuint16_t BOF:1;
+ vuint16_t:6;
+ vuint16_t NF:1;
+ } B;
+ } LINESR; /* LINFLEX LIN Error Status Register */
+
+ int16_t LINFLEX_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t TDFL:2;
+ vuint16_t:1;
+ vuint16_t RDFL:2;
+ vuint16_t RFBM:1;
+ vuint16_t TFBM:1;
+ vuint16_t WL1:1;
+ vuint16_t OP1:1;
+ vuint16_t RXEN:1;
+ vuint16_t TXEN:1;
+ vuint16_t OP0:1; //LCH vuint16_t PARITYODD:1;
+ vuint16_t PCE:1;
+ vuint16_t WL0:1;
+ vuint16_t UART:1;
+ } B;
+ } UARTCR; /* LINFLEX UART Mode Control Register */
+
+ int16_t LINFLEX_reserved6;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF:1;
+ vuint16_t OCF:1;
+ vuint16_t PE:4;
+ vuint16_t RMB:1;
+ vuint16_t FEF:1;
+ vuint16_t BOF:1;
+ vuint16_t RPS:1; // LCH vuint16_t RDI:1;
+ vuint16_t WUF:1;
+ vuint16_t:2;
+ vuint16_t DRF:1;
+ vuint16_t DTF:1;
+ vuint16_t NF:1;
+ } B;
+ } UARTSR; /* LINFLEX UART Mode Status Register */
+
+ int16_t LINFLEX_reserved7;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t LTOM:1; //LCH vuint16_t MODE:1;
+ vuint16_t IOT:1;
+ vuint16_t TOCE:1;
+ vuint16_t CNT:8;
+ } B;
+ } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */
+
+ int16_t LINFLEX_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OC2:8;
+ vuint16_t OC1:8;
+ } B;
+ } LINOCR; /* LINFLEX LIN Output Compare Register */
+
+ int16_t LINFLEX_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t RTO:4; // LCH vuint16_t RTC:4;
+ vuint16_t:1;
+ vuint16_t HTO:7; // LCH vuint16_t HTC:7;
+ } B;
+ } LINTOCR; /* LINFLEX LIN Output Compare Register */
+
+ int16_t LINFLEX_reserved10;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t DIV_F:4; // LCH vuint16_t FBR:4;
+ } B;
+ } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */
+
+ int16_t LINFLEX_reserved11;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DIV_M:13; // LCH vuint16_t IBR:13;
+ } B;
+ } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */
+
+ int16_t LINFLEX_reserved12;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t CF:8;
+ } B;
+ } LINCFR; /* LINFLEX LIN Checksum Field Register */
+
+ int16_t LINFLEX_reserved13;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t IOBE:1;
+ vuint16_t IOPE:1;
+ vuint16_t WURQ:1;
+ vuint16_t DDRQ:1;
+ vuint16_t DTRQ:1;
+ vuint16_t ABRQ:1;
+ vuint16_t HTRQ:1;
+ vuint16_t:8;
+ } B;
+ } LINCR2; /* LINFLEX LIN Control Register 2 */
+
+ int16_t LINFLEX_reserved14;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DFL:6;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2; // LCH vuint16_t:1;
+ vuint16_t ID:6;
+ } B;
+ } BIDR; /* LINFLEX Buffer Identifier Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL; /* LINFLEX Buffer Data Register Least Significant */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM; /* LINFLEX Buffer Data Register Most Significant */
+
+ int16_t LINFLEX_reserved15;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t FACT:8;
+ } B;
+ } IFER; /* LINFLEX Identifier Filter Enable Register */
+
+ int16_t LINFLEX_reserved16;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t IFMI:4;
+ } B;
+ } IFMI; /* LINFLEX Identifier Filter Match Index Register */
+
+ int16_t LINFLEX_reserved17;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t IFM:4;
+ } B;
+ } IFMR; /* LINFLEX Identifier Filter Mode Register */
+
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:3;
+ vuint32_t DFL:3;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } IFCR[16];
+
+ int32_t LINFLEX_reserved18;//GCR egister commented
+
+
+ int16_t LINFLEX_reserved19;//UARTPTO upper 16 bits reserved
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t PTO:12;
+ } B;
+ }UARTPTO;
+
+ int32_t LINFLEX_reserved20;//UARTCTO egister commented
+
+ int16_t LINFLEX_reserved21;
+
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DTE15:1;
+ vuint16_t DTE14:1;
+ vuint16_t DTE13:1;
+ vuint16_t DTE12:1;
+ vuint16_t DTE11:1;
+ vuint16_t DTE10:1;
+ vuint16_t DTE9:1;
+ vuint16_t DTE8:1;
+ vuint16_t DTE7:1;
+ vuint16_t DTE6:1;
+ vuint16_t DTE5:1;
+ vuint16_t DTE4:1;
+ vuint16_t DTE3:1;
+ vuint16_t DTE2:1;
+ vuint16_t DTE1:1;
+ vuint16_t DTE0:1;
+ } B;
+ } DMATXE;
+ int16_t LINFLEX_reserved22;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DRE15:1;
+ vuint16_t DRE14:1;
+ vuint16_t DRE13:1;
+ vuint16_t DRE12:1;
+ vuint16_t DRE11:1;
+ vuint16_t DRE10:1;
+ vuint16_t DRE9:1;
+ vuint16_t DRE8:1;
+ vuint16_t DRE7:1;
+ vuint16_t DRE6:1;
+ vuint16_t DRE5:1;
+ vuint16_t DRE4:1;
+ vuint16_t DRE3:1;
+ vuint16_t DRE2:1;
+ vuint16_t DRE1:1;
+ vuint16_t DRE0:1;
+
+ } B;
+ } DMARXE;
+
+
+
+ }; /* end of LINFLEX_tag */
+
+/****************************************************************************/
+/* MODULE : ME */
+/****************************************************************************/
+struct ME_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CURRENTMODE:4;
+ vuint32_t MTRANS:1;
+ vuint32_t DC:1;
+ vuint32_t:2;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVR:1;
+ vuint32_t DFLA:2;
+ vuint32_t CFLA:2;
+ vuint32_t SSCLK:9;
+ vuint32_t PLL:1;
+ vuint32_t OSC:1;
+ vuint32_t RC:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } GS; /* Global Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TARGETMODE:4;
+ vuint32_t:12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL; /* Mode Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } MER; /* Mode Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IS; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IM; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MTI:1;
+ vuint32_t MRI:1;
+ vuint32_t DMA:1;
+ vuint32_t NMA:1;
+ vuint32_t SEA:1;
+ } B;
+ } IMTS; /* Invalid Mode Transition Status Register */
+
+ int32_t ME_reserved0[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET; /* Reset Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST; /* Test Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE; /* Safe Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN; /* DRUN Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN[4]; /* RUN 0->4 Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT0; /* HALT0 Mode Configuration Register */
+
+ int32_t ME_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP0; /* STOP0 Mode Configuration Register */
+
+ int32_t ME_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY0; /* STANDBY0 Mode Configuration Register */
+
+ int32_t ME_reserved3[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PERIPH:32;
+ } B;
+ } PS[5]; /* Peripheral Status 0->4 Register */
+
+ int32_t ME_reserved4[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t:8;
+ } B;
+ } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DBGP:1;
+ vuint8_t DBGF:1;
+ vuint8_t LPCFG:1;
+ vuint8_t RUNCFG:1;
+ } B;
+ } PCTL[144]; /* Peripheral Control 0->143 Register */
+
+ /************************************/
+ /* Register Protection */
+ /************************************/
+ int32_t ME_reserved5[1964]; /* {0x2000-0x0150}/0x4 = 0x7AC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CURRENTMODE:4;
+ vuint32_t MTRANS:1;
+ vuint32_t DC:1;
+ vuint32_t:2;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVR:1;
+ vuint32_t DFLA:2;
+ vuint32_t CFLA:2;
+ vuint32_t SSCLK:9;
+ vuint32_t PLL:1;
+ vuint32_t OSC:1;
+ vuint32_t RC:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } GS_LOCK; /* Global Status Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TARGETMODE:4;
+ vuint32_t:12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL_LOCK; /* Mode Control Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } ME_LOCK; /* Mode Enable Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IS_LOCK; /* Interrupt Status Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t ICONF:1;
+ vuint32_t IMODE:1;
+ vuint32_t SAFE:1;
+ vuint32_t MTC:1;
+ } B;
+ } IM_LOCK; /* Interrupt Mask Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MTI:1;
+ vuint32_t MRI:1;
+ vuint32_t DMA:1;
+ vuint32_t NMA:1;
+ vuint32_t SEA:1;
+ } B;
+ } IMTS_LOCK; /* Invalid Mode Transition Status Register Lock */
+
+ int32_t ME_reserved6[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET_LOCK; /* Reset Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST_LOCK; /* Test Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE_LOCK; /* Safe Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN_LOCK; /* DRUN Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN_LOCK[4]; /* RUN 0->4 Mode Configuration Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT0_LOCK; /* HALT0 Mode Configuration Register Lock */
+
+ int32_t ME_reserved7;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP0_LOCK; /* STOP0 Mode Configuration Register Lock */
+
+ int32_t ME_reserved8[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t SSCLKON:9;
+ vuint32_t PLLON:1;
+ vuint32_t OSCON:1;
+ vuint32_t RCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY0_LOCK; /* STANDBY0 Mode Configuration Register Lock */
+
+ int32_t ME_reserved9[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PERIPH:32;
+ } B;
+ } PS_LOCK[5]; /* Peripheral Status 0->4 Register Lock */
+
+ int32_t ME_reserved10[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC_LOCK[8]; /* RUN Peripheral Configuration 0->7 Register Lock */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t:8;
+ } B;
+ } LPPC_LOCK[8]; /* Low Power Peripheral Configuration 0->7 Register Lock */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DBGP:1;
+ vuint8_t DBGF:1;
+ vuint8_t LPCFG:1;
+ vuint8_t RUNCFG:1;
+ } B;
+ } PCTL_LOCK[144]; /* Peripheral Control 0->143 Register Lock */
+
+ int32_t ME_reserved11[1452]; /* {0x3800-0x2150}/0x4 = 0x5AC */
+
+ union { /* Soft Lock Bit Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SLB0:4;
+ vuint32_t:4;
+ vuint32_t SLB1:4;
+ vuint32_t:4;
+ vuint32_t SLB2:4;
+ vuint32_t:4;
+ vuint32_t SLB3:4;
+ } B;
+ } SLBR[384];
+
+ int32_t ME_reserved12[127]; /* {0x3FFC-0x3E00}/0x4 = 0x07F */
+
+ union { /* Global Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HLB:1;
+ vuint32_t:7;
+ vuint32_t SOB:1;
+ vuint32_t:23;
+ } B;
+ } GCR;
+
+ }; /* end of ME_tag */
+
+
+/****************************************************************************/
+/* MODULE : CGM */
+/****************************************************************************/
+ struct CGM_tag {
+
+ /* The CGM provides a unified register interface, enabling access to
+ all clock sources:
+
+ Base Address | Clock Sources
+ -----------------------------
+ 0xC3FE0000 | FXOSC_CTL
+ ---------- | Reserved
+ 0xC3FE0040 | SXOSC_CTL
+ 0xC3FE0060 | FIRC_CTL
+ 0xC3FE0080 | SIRC_CTL
+ 0xC3FE00A0 | FMPLL_0
+ ---------- | Reserved
+ 0xC3FE0100 | CMU_0
+
+ */
+
+ /************************************/
+ /* FXOSC_CTL @ CGM base address + 0x0000 */
+ /************************************/
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:7;
+ } B;
+ } FXOSC_CTL; /* Fast OSC Control Register */
+
+ /************************************/
+ /* SXOSC_CTL @ CGM base address + 0x0040 */
+ /************************************/
+ int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } SXOSC_CTL; /* Slow OSC Control Register */
+
+ /************************************/
+ /* FIRC_CTL @ CGM base address + 0x0060 */
+ /************************************/
+ int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t RCTRIM:6;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:8;
+ } B;
+ } FIRC_CTL; /* Fast IRC Control Register */
+
+ /****************************************/
+ /* SIRC_CTL @ CGM base address + 0x0080 */
+ /****************************************/
+ int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t RCTRIM:5;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:3;
+ vuint32_t S_SIRC:1;
+ vuint32_t:3;
+ vuint32_t SIRCON_STDBY:1;
+ } B;
+ } SIRC_CTL; /* Slow IRC Control Register */
+
+ /*************************************/
+ /* FMPLL @ CGM base address + 0x00A0 */
+ /*************************************/
+ int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t IDF:4;
+ vuint32_t ODF:2;
+ vuint32_t:1;
+ vuint32_t NDIV:7;
+ vuint32_t:7;
+ vuint32_t EN_PLL_SW:1;
+ vuint32_t MODE:1;
+ vuint32_t UNLOCK_ONCE:1;
+ vuint32_t:1;
+ vuint32_t I_LOCK:1;
+ vuint32_t S_LOCK:1;
+ vuint32_t PLL_FAIL_MASK:1;
+ vuint32_t PLL_FAIL_FLAG:1;
+ vuint32_t:1;
+ } B;
+ } FMPLL_CR; /* FMPLL Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1;
+ vuint32_t:1;
+ vuint32_t SPRD_SEL:1;
+ vuint32_t MOD_PERIOD:13;
+ vuint32_t FM_EN:1;
+ vuint32_t INC_STEP:15;
+ } B;
+ } FMPLL_MR; /* FMPLL Modulation Register */
+
+ /************************************/
+ /* CMU @ CGM base address + 0x0100 */
+ /************************************/
+ int32_t CGM_reserved5[22]; /* (0x100 - 0x0A8)/4 = 0x16 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SFM:1;
+ vuint32_t:13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t:5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_CSR; /* Control Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t FD:20;
+ } B;
+ } CMU_FDR; /* Frequency Display Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HFREF_A:12;
+ } B;
+ } CMU_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t LFREF_A:12;
+ } B;
+ } CMU_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t FLCI_A:1;
+ vuint32_t FHHI_A:1;
+ vuint32_t FLLI_A:1;
+ vuint32_t OLRI:1;
+ } B;
+ } CMU_ISR; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CMU_IMR; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t MD:20;
+ } B;
+ } CMU_MDR; /* Measurement Duration Register */
+
+ /************************************/
+ /* CGM General Registers @ CGM base address + 0x0370 */
+ /************************************/
+ int32_t CGM_reserved7[149]; /* (0x370 - 0x11C)/4 = 0x95 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t EN:1;
+ } B;
+ } OC_EN; /* Output Clock Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t SELDIV:2;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } OCDS_SC; /* Output Clock Division Select Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELSTAT:4;
+ vuint32_t:24;
+ } B;
+ } SC_SS; /* System Clock Select Status */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DE:1;
+ vuint8_t:3;
+ vuint8_t DIV:4;
+ } B;
+ } SC_DC[3]; /* System Clock Divider Configuration 0->2 */
+
+ }; /* end of CGM_tag */
+/****************************************************************************/
+/* MODULE : RGM */
+/****************************************************************************/
+ struct RGM_tag {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1;
+ vuint16_t:3;
+ vuint16_t F_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t F_PLL1:1;
+ vuint16_t F_FLASH:1;
+ vuint16_t F_LVD45:1;
+ vuint16_t F_CMU0_FHL:1;
+ vuint16_t F_CMU0_OLR:1;
+ vuint16_t F_PLL0:1;
+ vuint16_t F_CHKSTOP:1;
+ vuint16_t F_SOFT:1;
+ vuint16_t F_CORE:1;
+ vuint16_t F_JTAG:1;
+ } B;
+ } FES; /* Functional Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t POR:1;
+ vuint16_t:7;
+ vuint16_t F_COMP:1;
+ vuint16_t F_LVD27_IO:1;
+ vuint16_t F_LVD27_FLASH:1;
+ vuint16_t F_LVD27_VREG:1;
+ vuint16_t F_LVD27:1;
+ vuint16_t F_SWT:1;
+ vuint16_t F_LVD12_PD1:1;
+ vuint16_t F_LVD12_PD0:1;
+ } B;
+ } DES; /* Destructive Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1;
+ vuint16_t:3;
+ vuint16_t D_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t D_PLL1:1;
+ vuint16_t D_FLASH:1;
+ vuint16_t D_LVD45:1;
+ vuint16_t D_CMU0_FHL:1;
+ vuint16_t D_CMU0_OLR:1;
+ vuint16_t D_PLL0:1;
+ vuint16_t D_CHKSTOP:1;
+ vuint16_t D_SOFT:1;
+ vuint16_t D_CORE:1;
+ vuint16_t D_JTAG:1;
+ } B;
+ } FERD; /* Functional Event Reset Disable */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t D_COMP:1;
+ vuint16_t D_LVD27_IO:1;
+ vuint16_t D_LVD27_FLASH:1;
+ vuint16_t D_LVD27_VREG:1;
+ vuint16_t D_LVD27:1;
+ vuint16_t D_SWT:1;
+ vuint16_t D_LVD12_PD1:1;
+ vuint16_t D_LVD12_PD0:1;
+ } B;
+ } DERD; /* Destructive Event Reset Disable */
+
+ int16_t RGM_reserved0[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t AR_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t AR_PLL1:1;
+ vuint16_t AR_FLASH:1;
+ vuint16_t AR_LVD45:1;
+ vuint16_t AR_CMU0_FHL:1;
+ vuint16_t AR_CMU0_OLR:1;
+ vuint16_t AR_PLL0:1;
+ vuint16_t AR_CHKSTOP:1;
+ vuint16_t AR_SOFT:1;
+ vuint16_t AR_CORE:1;
+ vuint16_t AR_JTAG:1;
+ } B;
+ } FEAR; /* Functional Event Alternate Request */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t AR_COMP:1;
+ vuint16_t AR_LVD27_IO:1;
+ vuint16_t AR_LVD27_FLASH:1;
+ vuint16_t AR_LVD27_VREG:1;
+ vuint16_t AR_LVD27:1;
+ vuint16_t AR_SWT:1;
+ vuint16_t AR_LVD12_PD1:1;
+ vuint16_t AR_LVD12_PD0:1;
+ } B;
+ } DEAR; /* Destructive Event Alternate Request */
+
+ int16_t RGM_reserved1[2];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+ vuint16_t SS_FLASH:1;
+ vuint16_t SS_LVD45:1;
+ vuint16_t SS_CMU0_FHL:1;
+ vuint16_t SS_CMU0_OLR:1;
+ vuint16_t SS_PLL0:1;
+ vuint16_t SS_CHKSTOP:1;
+ vuint16_t SS_SOFT:1;
+ vuint16_t SS_CORE:1;
+ vuint16_t SS_JTAG:1;
+ } B;
+ } FESS; /* Functional Event Short Sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t BOOT:1;
+ vuint16_t:4;
+ vuint16_t DRUND_FLA:1;
+ vuint16_t:1;
+ vuint16_t DRUNC_FLA:1;
+ } B;
+ } STDBY; /* STANDBY reset sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+ vuint16_t BE_FLASH:1;
+ vuint16_t BE_LVD45:1;
+ vuint16_t BE_CMU0_FHL:1;
+ vuint16_t BE_CMU0_OLR:1;
+ vuint16_t BE_PLL0:1;
+ vuint16_t BE_CHKSTOP:1;
+ vuint16_t BE_SOFT:1;
+ vuint16_t BE_CORE:1;
+ vuint16_t BE_JTAG:1;
+ } B;
+ } FBRE; /* Functional Bidirectional Reset Enable */
+
+ }; /* end of RGM_tag */
+/****************************************************************************/
+/* MODULE : PCU */
+/****************************************************************************/
+ struct PCU_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RST:1;
+ } B;
+ } PCONF[16]; /* Power domain 0-15 configuration register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PD15:1;
+ vuint32_t PD14:1;
+ vuint32_t PD13:1;
+ vuint32_t PD12:1;
+ vuint32_t PD11:1;
+ vuint32_t PD10:1;
+ vuint32_t PD9:1;
+ vuint32_t PD8:1;
+ vuint32_t PD7:1;
+ vuint32_t PD6:1;
+ vuint32_t PD5:1;
+ vuint32_t PD4:1;
+ vuint32_t PD3:1;
+ vuint32_t PD2:1;
+ vuint32_t PD1:1;
+ vuint32_t PD0:1;
+ } B;
+ } PSTAT; /* Power Domain Status Register */
+
+ int32_t PCU_reserved0[15]; /* {0x0080-0x0044}/0x4 = 0xF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t MASK_LVDHV5:1;
+ } B;
+ } VCTL; /* Voltage Regulator Control Register */
+
+ }; /* end of PCU_tag */
+
+/****************************************************************************/
+/* MODULE : CTUL */
+/****************************************************************************/
+ struct CTUL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:8;
+ vuint32_t TRGIEN:1;
+ vuint32_t TRGI:1;
+ vuint32_t:6;
+ } B;
+ } CSR; /* Control Status Register */
+
+ int32_t CTU_reserved0[11];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TM:1;
+ vuint32_t CLR_FLAG:1;
+ vuint32_t:5;
+ vuint32_t ADC_SEL:1;
+ vuint32_t:1;
+ vuint32_t CHANNELVALUE:7;
+ } B;
+ } EVTCFGR[64]; /* Event Configuration Register */
+
+ }; /* end of CTUL_tag */
+
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+ struct EMIOS_CHANNEL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CADR:16;
+ } B;
+ } CADR; /* Channel A Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CBDR:16;
+ } B;
+ } CBDR; /* Channel B Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CCNTR:16;
+ } B;
+ } CCNTR; /* Channel Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t:3;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPEN:1;
+ vuint32_t DMA:1;
+ vuint32_t:1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t:3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t:1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR; /* Channel Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:15;
+ vuint32_t OVFL:1;
+ vuint32_t:12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR; /* Channel Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ALTA:16;
+ } B;
+ } ALTCADR; /* Alternate Channel A Data Register */
+
+ uint32_t emios_channel_reserved[2];
+
+ }; /* end of EMIOS_CHANNEL_tag */
+
+ struct EMIOS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t:1;
+ vuint32_t GPREN:1;
+ vuint32_t:10;
+ vuint32_t GPRE:8;
+ vuint32_t:8;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t F31:1;
+ vuint32_t F30:1;
+ vuint32_t F29:1;
+ vuint32_t F28:1;
+ vuint32_t F27:1;
+ vuint32_t F26:1;
+ vuint32_t F25:1;
+ vuint32_t F24:1;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR; /* Global FLAG Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OU31:1;
+ vuint32_t OU30:1;
+ vuint32_t OU29:1;
+ vuint32_t OU28:1;
+ vuint32_t OU27:1;
+ vuint32_t OU26:1;
+ vuint32_t OU25:1;
+ vuint32_t OU24:1;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR; /* Output Update Disable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CHDIS31:1;
+ vuint32_t CHDIS30:1;
+ vuint32_t CHDIS29:1;
+ vuint32_t CHDIS28:1;
+ vuint32_t CHDIS27:1;
+ vuint32_t CHDIS26:1;
+ vuint32_t CHDIS25:1;
+ vuint32_t CHDIS24:1;
+ vuint32_t CHDIS23:1;
+ vuint32_t CHDIS22:1;
+ vuint32_t CHDIS21:1;
+ vuint32_t CHDIS20:1;
+ vuint32_t CHDIS19:1;
+ vuint32_t CHDIS18:1;
+ vuint32_t CHDIS17:1;
+ vuint32_t CHDIS16:1;
+ vuint32_t CHDIS15:1;
+ vuint32_t CHDIS14:1;
+ vuint32_t CHDIS13:1;
+ vuint32_t CHDIS12:1;
+ vuint32_t CHDIS11:1;
+ vuint32_t CHDIS10:1;
+ vuint32_t CHDIS9:1;
+ vuint32_t CHDIS8:1;
+ vuint32_t CHDIS7:1;
+ vuint32_t CHDIS6:1;
+ vuint32_t CHDIS5:1;
+ vuint32_t CHDIS4:1;
+ vuint32_t CHDIS3:1;
+ vuint32_t CHDIS2:1;
+ vuint32_t CHDIS1:1;
+ vuint32_t CHDIS0:1;
+ } B;
+ } UCDIS; /* Disable Channel Register */
+
+ uint32_t emios_reserved1[4];
+
+ struct EMIOS_CHANNEL_tag CH[32];
+
+ }; /* end of EMIOS_tag */
+/****************************************************************************/
+/* MODULE : pit */
+/****************************************************************************/
+ struct PIT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR;
+
+ uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+ } CH[8];
+
+ }; /* end of PIT_tag */
+/****************************************************************************/
+/* MODULE : i2c */
+/****************************************************************************/
+ struct I2C_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ADR:7;
+ vuint8_t:1;
+ } B;
+ } IBAD; /* Module Bus Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t IBC:8;
+ } B;
+ } IBFD; /* Module Bus Frequency Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t MDIS:1;
+ vuint8_t IBIE:1;
+ vuint8_t MS:1;
+ vuint8_t TX:1;
+ vuint8_t NOACK:1;
+ vuint8_t RSTA:1;
+ vuint8_t DMAEN:1;
+ vuint8_t IBDOZE:1;
+ } B;
+ } IBCR; /* Module Bus Control Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t TCF:1;
+ vuint8_t IAAS:1;
+ vuint8_t IBB:1;
+ vuint8_t IBAL:1;
+ vuint8_t:1;
+ vuint8_t SRW:1;
+ vuint8_t IBIF:1;
+ vuint8_t RXAK:1;
+ } B;
+ } IBSR; /* Module Status Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DATA:8;
+ } B;
+ } IBDR; /* Module Data Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t BIIE:1;
+ vuint8_t:7;
+ } B;
+ } IBIC; /* Module Interrupt Configuration Register */
+
+ }; /* end of I2C_tag */
+/****************************************************************************/
+/* MODULE : MPU */
+/****************************************************************************/
+ struct MPU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MPERR:8;
+ vuint32_t:4;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NGRD:4;
+ vuint32_t:7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR; /* Module Control/Error Status Register */
+
+ uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR3;
+
+ uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD0; /* Region Descriptor n Word 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD1; /* Region Descriptor n Word 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2; /* Region Descriptor n Word 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t:15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3; /* Region Descriptor n Word 3 */
+
+ } RGD[16];
+
+ uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
+
+ }; /* end of MPU_tag */
+/****************************************************************************/
+/* MODULE : eDMA */
+/****************************************************************************/
+
+/*for standard format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0) */
+ struct EDMA_TCD_STD_tag {
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SMLOE:1;
+ vuint32_t DMLOE:1;
+ int32_t MLOFF:20;
+ vuint32_t NBYTES:10;
+ } B;
+ } NBYTESu; /* Region Descriptor Alternate Access Control n */
+
+ vint32_t SLAST; /* last destination address adjustment, or
+ scatter/gather address (if e_sg = 1) */
+
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITER:15;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning major iteration count */
+ vuint16_t BITER:15;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+
+ }; /* end of EDMA_TCD_STD_tag */
+
+/*for channel link format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1)*/
+ struct EDMA_TCD_CHLINK_tag {
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SMLOE:1;
+ vuint32_t DMLOE:1;
+ int32_t MLOFF:20;
+ vuint32_t NBYTES:10;
+ } B;
+ } NBYTESu; /* Region Descriptor Alternate Access Control n */
+ vint32_t SLAST; /* last destination address adjustment, or
+ scatter/gather address (if e_sg = 1) */
+
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITERLINKCH:6;
+ vuint16_t CITER:9;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning major iteration count */
+ vuint16_t BITERLINKCH:6;
+ vuint16_t BITER:9;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+
+ }; /* end of EDMA_TCD_CHLINK_tag */
+
+ struct EDMA_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t CX:1;
+ vuint32_t ECX:1;
+ vuint32_t GRP3PRI:2;
+ vuint32_t GRP2PRI:2;
+ vuint32_t GRP1PRI:2;
+ vuint32_t GRP0PRI:2;
+ vuint32_t EMLM:1;
+ vuint32_t CLM:1;
+ vuint32_t HALT:1;
+ vuint32_t HOE:1;
+ vuint32_t ERGA:1;
+ vuint32_t ERCA:1;
+ vuint32_t EDBG:1;
+ vuint32_t EBW:1;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1;
+ vuint32_t:15;
+ vuint32_t GPE:1;
+ vuint32_t CPE:1;
+ vuint32_t ERRCHN:6;
+ vuint32_t SAE:1;
+ vuint32_t SOE:1;
+ vuint32_t DAE:1;
+ vuint32_t DOE:1;
+ vuint32_t NCE:1;
+ vuint32_t SGE:1;
+ vuint32_t SBE:1;
+ vuint32_t DBE:1;
+ } B;
+ } ESR; /* Error Status Register */
+
+ int16_t EDMA_reserved1[3]; /* (0x0E - 0x08)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ERQ15:1;
+ vuint16_t ERQ14:1;
+ vuint16_t ERQ13:1;
+ vuint16_t ERQ12:1;
+ vuint16_t ERQ11:1;
+ vuint16_t ERQ10:1;
+ vuint16_t ERQ09:1;
+ vuint16_t ERQ08:1;
+ vuint16_t ERQ07:1;
+ vuint16_t ERQ06:1;
+ vuint16_t ERQ05:1;
+ vuint16_t ERQ04:1;
+ vuint16_t ERQ03:1;
+ vuint16_t ERQ02:1;
+ vuint16_t ERQ01:1;
+ vuint16_t ERQ00:1;
+ } B;
+ } ERQRL; /* DMA Enable Request Register Low */
+
+ int16_t EDMA_reserved2[3]; /* (0x16 - 0x10)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EEI15:1;
+ vuint16_t EEI14:1;
+ vuint16_t EEI13:1;
+ vuint16_t EEI12:1;
+ vuint16_t EEI11:1;
+ vuint16_t EEI10:1;
+ vuint16_t EEI09:1;
+ vuint16_t EEI08:1;
+ vuint16_t EEI07:1;
+ vuint16_t EEI06:1;
+ vuint16_t EEI05:1;
+ vuint16_t EEI04:1;
+ vuint16_t EEI03:1;
+ vuint16_t EEI02:1;
+ vuint16_t EEI01:1;
+ vuint16_t EEI00:1;
+ } B;
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SERQ:7;
+ } B;
+ } SERQR; /* DMA Set Enable Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CERQ:7;
+ } B;
+ } CERQR; /* DMA Clear Enable Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SEEI:7;
+ } B;
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CEEI:7;
+ } B;
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CINT:7;
+ } B;
+ } CIRQR; /* DMA Clear Interrupt Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CER:7;
+ } B;
+ } CERR; /* DMA Clear error Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SSB:7;
+ } B;
+ } SSBR; /* Set Start Bit Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CDSB:7;
+ } B;
+ } CDSBR; /* Clear Done Status Bit Register */
+
+ int16_t EDMA_reserved3[3]; /* (0x26 - 0x20)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t INT15:1;
+ vuint16_t INT14:1;
+ vuint16_t INT13:1;
+ vuint16_t INT12:1;
+ vuint16_t INT11:1;
+ vuint16_t INT10:1;
+ vuint16_t INT09:1;
+ vuint16_t INT08:1;
+ vuint16_t INT07:1;
+ vuint16_t INT06:1;
+ vuint16_t INT05:1;
+ vuint16_t INT04:1;
+ vuint16_t INT03:1;
+ vuint16_t INT02:1;
+ vuint16_t INT01:1;
+ vuint16_t INT00:1;
+ } B;
+ } IRQRL; /* DMA Interrupt Request Low */
+
+ int16_t EDMA_reserved4[3]; /* (0x2E - 0x28)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ERR15:1;
+ vuint16_t ERR14:1;
+ vuint16_t ERR13:1;
+ vuint16_t ERR12:1;
+ vuint16_t ERR11:1;
+ vuint16_t ERR10:1;
+ vuint16_t ERR09:1;
+ vuint16_t ERR08:1;
+ vuint16_t ERR07:1;
+ vuint16_t ERR06:1;
+ vuint16_t ERR05:1;
+ vuint16_t ERR04:1;
+ vuint16_t ERR03:1;
+ vuint16_t ERR02:1;
+ vuint16_t ERR01:1;
+ vuint16_t ERR00:1;
+ } B;
+ } ERL; /* DMA Error Low */
+
+ int16_t EDMA_reserved5[3]; /* (0x36 - 0x30)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t HRS15:1;
+ vuint16_t HRS14:1;
+ vuint16_t HRS13:1;
+ vuint16_t HRS12:1;
+ vuint16_t HRS11:1;
+ vuint16_t HRS10:1;
+ vuint16_t HRS09:1;
+ vuint16_t HRS08:1;
+ vuint16_t HRS07:1;
+ vuint16_t HRS06:1;
+ vuint16_t HRS05:1;
+ vuint16_t HRS04:1;
+ vuint16_t HRS03:1;
+ vuint16_t HRS02:1;
+ vuint16_t HRS01:1;
+ vuint16_t HRS00:1;
+ } B;
+ } HRSL; /* DMA Hardware Request Status Low */
+
+ uint32_t edma_reserved1[50]; /* (0x100 - 0x038)/4 = 0x32 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[16]; /* Channel n Priority */
+
+ uint32_t edma_reserved2[956]; /* (0x1000 - 0x0110)/4 = 0x3BC */
+
+ struct EDMA_TCD_STD_tag TCD[16];
+ /* struct EDMA_TCD_CHLINK_tag TCD[16]; */
+
+ }; /* end of EDMA_tag */
+/****************************************************************************/
+/* MODULE : INTC */
+/****************************************************************************/
+ struct INTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t VTES:1;
+ vuint32_t:4;
+ vuint32_t HVEN:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR; /* Current Priority Register */
+
+ int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA:21;
+ vuint32_t INTVEC:9;
+ vuint32_t:2;
+ } B;
+ } IACKR; /* Interrupt Acknowledge Register */
+
+ int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } EOIR; /* End of Interrupt Register */
+
+ int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1;
+ vuint8_t CLR:1;
+ } B;
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */
+
+ uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PRI:4;
+ } B;
+ } PSR[512]; /* Software Set/Clear Interrupt Register */
+
+ }; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+ struct DSPI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t:2;
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t DOZE:1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t:7;
+ vuint32_t HALT:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ uint32_t dspi_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t:16;
+ } B;
+ } TCR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t:1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t:1;
+ vuint32_t TFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR; /* Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t:2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t:1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t:4;
+ vuint32_t RFOFRE:1;
+ vuint32_t:1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t:16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t:4;
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR; /* POP RX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_txf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[4]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_rxf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t:1;
+ vuint32_t MTOCNT:6;
+ vuint32_t:4;
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t:6;
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR; /* DSI Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SER_DATA:16;
+ } B;
+ } SDR; /* DSI Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ASER_DATA:16;
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t COMP_DATA:16;
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DESER_DATA:16;
+ } B;
+ } DDR; /* DSI deserialization Data Register */
+
+ }; /* end of DSPI_tag */
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+ struct FLEXCAN_BUF_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ }; /* end of FLEXCAN_BUF_t */
+
+ struct FLEXCAN_RXFIFO_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+ }; /* end of FLEXCAN_RXFIFO_t */
+
+ struct FLEXCAN_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLFWAK:1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t DOZE:1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ } TIMER; /* Free Running Timer */
+
+ uint32_t FLEXCAN_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK; /* RX Global Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK; /* RX 14 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK; /* RX 15 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t:1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAKINT:1;
+ } B;
+ } ESR; /* Error and Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH; /* Interruput Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interrupt Flag Register */
+
+ uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64]; /* RX Individual Mask Registers */
+
+ }; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : DMAMUX */
+/****************************************************************************/
+ struct DMAMUX_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[16]; /* DMA Channel Configuration Register */
+
+ }; /* end of DMAMUX_tag */
+
+/****************************************************************************/
+/* MODULE : DFLASH */
+/****************************************************************************/
+ struct DFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:25;
+ vuint32_t HBLOCK:6;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of Dflash_tag */
+/****************************************************************************/
+/* MODULE : CFLASH */
+/****************************************************************************/
+ struct CFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:19;
+ vuint32_t HBLOCK:12;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HSL:12;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ union { /* CFLASH Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK0_APC:5;
+ vuint32_t BK0_WWSC:5;
+ vuint32_t BK0_RWSC:5;
+ vuint32_t BK0_RWWC2:1;
+ vuint32_t BK0_RWWC1:1;
+ vuint32_t B0_P1_BCFG:2;
+ vuint32_t B0_P1_DPFE:1;
+ vuint32_t B0_P1_IPFE:1;
+ vuint32_t B0_P1_PFLM:2;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK0_RWWC0:1;
+ vuint32_t B0_P0_BCFG:2;
+ vuint32_t B0_P0_DPFE:1;
+ vuint32_t B0_P0_IPFE:1;
+ vuint32_t B0_P0_PFLM:2;
+ vuint32_t B0_P0_BFE:1;
+ } B;
+ } PFCR0;
+
+ union { /* CFLASH Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK1_APC:5;
+ vuint32_t BK1_WWSC:5;
+ vuint32_t BK1_RWSC:5;
+ vuint32_t BK1_RWWC2:1;
+ vuint32_t BK1_RWWC1:1;
+ vuint32_t:6;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK1_RWWC0:1;
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1;
+ } B;
+ } PFCR1;
+
+ union { /* cflash Access Protection Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t ARBM:2;
+ vuint32_t M7PFD:1;
+ vuint32_t M6PFD:1;
+ vuint32_t M5PFD:1;
+ vuint32_t M4PFD:1;
+ vuint32_t M3PFD:1;
+ vuint32_t M2PFD:1;
+ vuint32_t M1PFD:1;
+ vuint32_t M0PFD:1;
+ vuint32_t M7AP:2;
+ vuint32_t M6AP:2;
+ vuint32_t M5AP:2;
+ vuint32_t M4AP:2;
+ vuint32_t M3AP:2;
+ vuint32_t M2AP:2;
+ vuint32_t M1AP:2;
+ vuint32_t M0AP:2;
+ } B;
+ } FAPR;
+
+ int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of CFLASH_tag */
+/******************************************************************
+| defines and macros (scope: module-local)
+|-----------------------------------------------------------------*/
+/* Define instances of modules */
+
+#define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)
+#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
+#define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL)
+#define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL)
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
+#define LINFLEX_4 (*(volatile struct LINFLEX_tag *) 0xFFE50000UL)
+#define LINFLEX_5 (*(volatile struct LINFLEX_tag *) 0xFFE54000UL)
+#define LINFLEX_6 (*(volatile struct LINFLEX_tag *) 0xFFE58000UL)
+#define LINFLEX_7 (*(volatile struct LINFLEX_tag *) 0xFFE5C000UL)
+#define LINFLEX_8 (*(volatile struct LINFLEX_tag *) 0xFFFB0000UL)
+#define LINFLEX_9 (*(volatile struct LINFLEX_tag *) 0xFFFB4000UL)
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ifdef _JDP_H */
+/* End of file */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC560Dxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..b5dd5f209 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/cfg/mcuconf.h.ftl @@ -0,0 +1,191 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC560B/Cxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC560Dxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+#define SPC5_XOSCDIV_VALUE ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
+#define SPC5_IRCDIV_VALUE ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+#define SPC5_EMIOS0_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_EMLM)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX2 ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+#define SPC5_SERIAL_LINFLEX2_PRIORITY ${conf.instance.irq_priority_settings.linflex2.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4})
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * ICU-PWM driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS0_CH0 ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH1 ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH2 ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH3 ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH4 ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH5 ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH6 ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH7 ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH24 ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS0_GROUP0 ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS0_GROUP1 ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
+
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
+
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+
+#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
+#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
+#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
+#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
+#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/hal_lld.c b/os/hal/ports/SPC5/SPC560Dxx/hal_lld.c new file mode 100644 index 000000000..e6bdac45f --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/hal_lld.c @@ -0,0 +1,285 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/hal_lld.c
+ * @brief SPC560Dxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief PIT channel 0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector59) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ /* Resets the PIT channel 0 IRQ flag.*/
+ PIT.CH[0].TFLG.R = 1;
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t reg;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* INTC initialization, software vector mode, 4 bytes vectors, starting
+ at priority 0.*/
+ INTC.MCR.R = 0;
+ INTC.CPR.R = 0;
+ INTC.IACKR.R = (uint32_t)_vectors;
+
+ /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
+ to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
+ modes.*/
+ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
+ halSPCSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+ reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
+ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
+ PIT.CH[0].LDVAL.R = reg;
+ PIT.CH[0].CVAL.R = reg;
+ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
+ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC560B/Cxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.S_FIRC)
+ ;
+
+#if !SPC5_NO_INIT
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* Oscillators dividers setup.*/
+ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
+ CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.FXOSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
+ CGM.SC_DC1.R = SPC5_CGM_SC_DC1;
+ CGM.SC_DC2.R = SPC5_CGM_SC_DC2;
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
+
+ /* Run modes initialization.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
+ if (ME.IS.B.I_ICONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings calculated for a maximum clock of 48MHz.*/
+ CFLASH.PFCR0.B.BK0_APC = 2;
+ CFLASH.PFCR0.B.BK0_RWSC = 2;
+
+ /* CMU clock enable */
+ halSPCSetPeripheralClockMode(104,
+ SPC5_ME_PCTL_RUN(1) | SPC5_ME_PCTL_LP(2));
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.S_SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_DIVIRC:
+ return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_DIVXOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/hal_lld.h b/os/hal/ports/SPC5/SPC560Dxx/hal_lld.h new file mode 100644 index 000000000..f820b3d7f --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/hal_lld.h @@ -0,0 +1,769 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/hal_lld.h
+ * @brief SPC560Dxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC560Dxx Car Body and Convenience"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 16000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 48000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 48000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
+ oscillator. */
+#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
+ oscillator. */
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (1U << 1)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+#define SPC5_ME_ME_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_LP (2U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+#define SPC5_ME_LP_PC_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=48MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 1
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=48MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 48
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=8MHz and PHI=48MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8
+#endif
+
+/**
+ * @brief XOSC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Fast IRC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0 | \
+ SPC5_ME_ME_STANDBY0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STANDBY0 mode settings.
+ */
+#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0 | \
+ SPC5_ME_LP_PC_STANDBY0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief PIT channel 0 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC560Dxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC560Dxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on the XOSC divider.*/
+#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
+#error "invalid SPC5_XOSCDIV_VALUE value specified"
+#endif
+
+/* Check on the IRC divider.*/
+#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
+#error "invalid SPC5_IRCDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/platform.mk b/os/hal/ports/SPC5/SPC560Dxx/platform.mk new file mode 100644 index 000000000..82ff61fad --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/platform.mk @@ -0,0 +1,22 @@ +# List of all the SPC560Dxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Dxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/spc5_emios.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Dxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC560Dxx/registers.h b/os/hal/ports/SPC5/SPC560Dxx/registers.h new file mode 100644 index 000000000..9bc9f2cf8 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc560d.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/spc5_registry.h b/os/hal/ports/SPC5/SPC560Dxx/spc5_registry.h new file mode 100644 index 000000000..0d2b65fd3 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/spc5_registry.h @@ -0,0 +1,289 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/spc5_registry.h
+ * @brief SPC560Dxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560Dxx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 FALSE
+#define SPC5_HAS_DSPI3 FALSE
+#define SPC5_HAS_DSPI4 FALSE
+#define SPC5_HAS_DSPI5 FALSE
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+#define SPC5_DSPI_FIFO_DEPTH 4
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 16
+#define SPC5_EDMA_HAS_MUX TRUE
+#define SPC5_EDMA_MUX_PCTL 23
+
+/* LINFlex attributes.*/
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX2 TRUE
+#define SPC5_LINFLEX2_PCTL 50
+#define SPC5_LINFLEX2_RXI_HANDLER vector119
+#define SPC5_LINFLEX2_TXI_HANDLER vector120
+#define SPC5_LINFLEX2_ERR_HANDLER vector121
+#define SPC5_LINFLEX2_RXI_NUMBER 119
+#define SPC5_LINFLEX2_TXI_NUMBER 120
+#define SPC5_LINFLEX2_ERR_NUMBER 121
+#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+
+#define SPC5_HAS_LINFLEX3 FALSE
+#define SPC5_HAS_LINFLEX4 FALSE
+#define SPC5_HAS_LINFLEX5 FALSE
+#define SPC5_HAS_LINFLEX6 FALSE
+#define SPC5_HAS_LINFLEX7 FALSE
+#define SPC5_HAS_LINFLEX8 FALSE
+#define SPC5_HAS_LINFLEX9 FALSE
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_PCTL 68
+#define SPC5_SIUL_NUM_PORTS 8
+#define SPC5_SIUL_NUM_PCRS 77
+#define SPC5_SIUL_NUM_PADSELS 63
+#define SPC5_SIUL_SYSTEM_PINS 32,33
+
+/* eMIOS attributes.*/
+#define SPC5_HAS_EMIOS0 TRUE
+#define SPC5_EMIOS0_PCTL 72
+#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
+#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
+#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
+#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
+#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
+#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
+#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
+#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
+#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
+#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
+#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
+#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
+#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
+#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
+#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
+#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
+#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
+#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
+#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
+#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
+#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
+#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
+#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
+#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
+#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
+#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
+#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
+#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
+
+#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS0_GPRE_VALUE)
+
+#define SPC5_HAS_EMIOS1 FALSE
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 32
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC FALSE
+
+#define SPC5_HAS_ADC0 FALSE
+#define SPC5_ADC_ADC0_HAS_CTR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CTR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR0 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR4 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR5 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL0 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL1 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL4 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL5 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 FALSE
+
+#define SPC5_HAS_ADC1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR2 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR3 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR4 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR5 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC1_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR2 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL5 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL8 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL9 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL10 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL11 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR2 TRUE
+#define SPC5_ADC1_PCTL 33
+#define SPC5_ADC1_DMA_DEV_ID 30
+#define SPC5_ADC1_EOC_HANDLER vector82
+#define SPC5_ADC1_EOC_NUMBER 82
+#define SPC5_ADC1_WD_HANDLER vector84
+#define SPC5_ADC1_WD_NUMBER 84
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/typedefs.h b/os/hal/ports/SPC5/SPC560Dxx/typedefs.h new file mode 100644 index 000000000..c93416b69 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Dxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Dxx/xpc560d.h b/os/hal/ports/SPC5/SPC560Dxx/xpc560d.h new file mode 100644 index 000000000..28455a71a --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Dxx/xpc560d.h @@ -0,0 +1,5557 @@ +/****************************************************************************
+ * PROJECT : MPC5602Dx
+ *
+ * FILE : MPC5602Dx_2.03.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for MPC560xBx family of MCUs. It supports the following devices:
+ *
+ * - MPC5602D
+ *
+ *
+ * COPYRIGHT :(c) 2012, Freescale
+ *
+ * VERSION : 2.03
+ * DATE : 06.05.2012
+ * AUTHOR : r23668
+ * HISTORY : New header Based Upon MPC5607B and MPC5606BK. Version 1.04
+ * 0.12 Oct 2011: MPC5606BK
+ * 1.0 Alpha Nov 2011 : MPC560xBx combined header file. Out for Review and comments.
+ * 1.01 Jan 2012: Checked with both MPC5607x and MPC5606Bx, no comments recieved.
+ * 1.04 Mar 2012: Supersedes MPC5607B ver 1.03 and becomes Ver 1.04.
+ * 2.01 Added missing ADC registers CIMR1, CIMR2, PSR1, NCMR1, NCMR2
+ * 2.02 Added more missing ADC registers CEOCFR2, DMAR1/2, PSR1, DSDR, CDR, CWSEL8-11, CWENR2, AWORR2, NCMR2, JCMR2
+ * 2.03 Corrected RM discrepancies.
+ *****************************************************************
+ * Copyright:
+ * Freescale Semiconductor, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Freescale
+ * Semiconductor, Inc. This software is provided on an "AS IS"
+ * basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, Freescale
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Freescale Semiconductor assumes no responsibility for the
+ * maintenance and support of this software
+ *
+ ******************************************************************/
+
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
+
+/*****************************************************************
+* Example instantiation and use:
+*
+* <MODULE>.<REGISTER>.B.<BIT> = 1;
+* <MODULE>.<REGISTER>.R = 0x10000000;
+*
+******************************************************************/
+
+#ifndef _JDP_H_
+#define _JDP_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+
+/****************************************************************************/
+/* MODULE : CFLASH (base address - 0xC3F8_8000) */
+/****************************************************************************/
+ struct CFLASH_tag {
+ union { /* Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:2;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* Low/Mid address block locking (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t:10;
+ vuint32_t LLK:6;
+ } B;
+ } LML;
+
+ union { /* High address space block locking (Base+0x0008)*/
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t :27;
+ vuint32_t HLK:4;
+ } B;
+ } HBL;
+
+ union { /* Secondary Low/Mid block lock (Base+0x000C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t:10;
+ vuint32_t SLK:6;
+ } B;
+ } SLL;
+
+ union { /* Low/Mid address space block sel (Base+0x0010)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t:10;
+ vuint32_t LSL:6;
+ } B;
+ } LMS;
+
+ union { /* High address Space block select (Base+0x0014)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t HSL:4;
+ } B;
+ } HBS;
+
+ union { /* Address Register (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ /* Note the following 3 registers, BIU[0..2] are mirrored to */
+ /* the code flash configuraiton PFCR[0..2] registers */
+ /* To make it easier to code, the BIU registers have been */
+ /* replaced with the PFCR registers in this header file! */
+ /* A commented out BIU register is shown for reference! */
+
+
+ union { /* CFLASH Configuration 0 (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t BK0_APC:5;
+ vuint32_t BK0_WWSC:5;
+ vuint32_t BK0_RWSC:5;
+ vuint32_t BK0_RWWC2:1;
+ vuint32_t BK0_RWWC1:1;
+ vuint32_t :7;
+ vuint32_t BK0_RWWC0:1;
+ vuint32_t B0_P0_BCFG:2;
+ vuint32_t B0_P0_DPFE:1;
+ vuint32_t B0_P0_IPFE:1;
+ vuint32_t B0_P0_PFLM:2;
+ vuint32_t B0_P0_BFE:1;
+ } B;
+ } PFCR0;
+
+ /* Commented out Bus Interface Unit 0 (Base+0x001C) */
+ /*union {
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t BI0:32;
+
+ } B;
+
+ } BIU0; */
+ union { /* CFLASH Configuration Register 1 (Base+0x0020)*/
+ vuint32_t R;
+ struct {
+ vuint32_t BK1_APC:5;
+ vuint32_t BK1_WWSC:5;
+ vuint32_t BK1_RWSC:5;
+ vuint32_t BK1_RWWC2:1;
+ vuint32_t BK1_RWWC1:1;
+ vuint32_t:7;
+ vuint32_t BK1_RWWC0:1;
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1;
+ } B;
+ } PFCR1;
+ /* Commented out Bus Interface Unit 1 (Base+0x0020) */
+ /*union {
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t BI1:32;
+
+ } B;
+
+ } BIU1; */
+
+
+ union { /* CFLASH Access Protection (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:13;
+ vuint32_t M2PFD:1;
+ vuint32_t:1;
+ vuint32_t M0PFD:1;
+ vuint32_t:10;
+ vuint32_t M2AP:2;
+ vuint32_t:2;
+ vuint32_t M0AP:2;
+ } B;
+ } PFAPR;
+ /* Commented out Bus Interface Unit 2 (Base+0x0024) */
+ /*union {
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t BI2:32;
+
+ } B;
+
+ } BIU2; */
+
+
+ vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */
+
+ union { /* User Test 0 (Base+0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test 1 (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test 2 (Base+0x0044) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/
+
+ }; /* end of CFLASH_tag */
+
+/****************************************************************************/
+/* MODULE : DFLASH (base address - 0xC3F8C000) */
+/****************************************************************************/
+ struct DFLASH_tag {
+ union { /* Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:2;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* Low/Mid address block locking (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:16;
+ vuint32_t LLK:4;
+ } B;
+ } LML;
+
+ vuint8_t DFLASH_reserved0[4]; /* Reserved 4 Bytes (+0x0008-0x000B) */
+
+
+ union { /* Secondary Low/mid block locking (Base+0x000C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:16;
+ vuint32_t SLK:4;
+ } B;
+ } SLL;
+
+ union { /* Low/Mid address space block sel (Base+0x0010)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t LSL:4;
+ } B;
+ } LMS;
+
+ vuint8_t DFLASH_reserved1[4]; /* Reserved 4 Bytes (+0x0014-0x0017)*/
+
+ union { /* Address Register (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ vuint8_t DFLASH_reserved2[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */
+
+ union { /* User Test 0 (Base+0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test 1 (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test 2 (Base+0x0044) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of Dflash_tag */
+
+/****************************************************************************/
+/* MODULE : SIU Lite (tagged as SIU for compatibility) */
+/****************************************************************************/
+struct SIU_tag {
+
+ vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */
+
+ union { /* MCU ID1 (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16;
+ vuint32_t CSP:1;
+ vuint32_t PKG:5;
+ vuint32_t :2;
+ vuint32_t MAJOR_MASK:4;
+ vuint32_t MINOR_MASK:4;
+ } B;
+ } MIDR1;
+
+ union { /* MCU ID2 (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1;
+ vuint32_t FLASH_SIZE_1:4;
+ vuint32_t FLASH_SIZE_2:4;
+ vuint32_t :7;
+ vuint32_t PARTNUM:8;
+ vuint32_t :3;
+ vuint32_t EE:1;
+ vuint32_t :3;
+ vuint32_t FR:1;
+ } B;
+ } MIDR2;
+
+ vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */
+
+ union { /* Interrupt Status Flag (Base+0x0014)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t EIF23:1;
+ vuint32_t EIF22:1;
+ vuint32_t EIF21:1;
+ vuint32_t EIF20:1;
+ vuint32_t EIF19:1;
+ vuint32_t EIF18:1;
+ vuint32_t EIF17:1;
+ vuint32_t EIF16:1;
+ vuint32_t EIF15:1;
+ vuint32_t EIF14:1;
+ vuint32_t EIF13:1;
+ vuint32_t EIF12:1;
+ vuint32_t EIF11:1;
+ vuint32_t EIF10:1;
+ vuint32_t EIF9:1;
+ vuint32_t EIF8:1;
+ vuint32_t EIF7:1;
+ vuint32_t EIF6:1;
+ vuint32_t EIF5:1;
+ vuint32_t EIF4:1;
+ vuint32_t EIF3:1;
+ vuint32_t EIF2:1;
+ vuint32_t EIF1:1;
+ vuint32_t EIF0:1;
+ } B;
+ } ISR;
+
+ union { /* Interrupt Request Enable (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IRE23:1;
+ vuint32_t IRE22:1;
+ vuint32_t IRE21:1;
+ vuint32_t IRE20:1;
+ vuint32_t IRE19:1;
+ vuint32_t IRE18:1;
+ vuint32_t IRE17:1;
+ vuint32_t IRE16:1;
+ vuint32_t IRE15:1;
+ vuint32_t IRE14:1;
+ vuint32_t IRE13:1;
+ vuint32_t IRE12:1;
+ vuint32_t IRE11:1;
+ vuint32_t IRE10:1;
+ vuint32_t IRE9:1;
+ vuint32_t IRE8:1;
+ vuint32_t IRE7:1;
+ vuint32_t IRE6:1;
+ vuint32_t IRE5:1;
+ vuint32_t IRE4:1;
+ vuint32_t IRE3:1;
+ vuint32_t IRE2:1;
+ vuint32_t IRE1:1;
+ vuint32_t IRE0:1;
+ } B;
+ } IRER;
+
+ vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */
+
+ union { /* Interrupt Rising-Edge Event Enable (+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IREE23:1;
+ vuint32_t IREE22:1;
+ vuint32_t IREE21:1;
+ vuint32_t IREE20:1;
+ vuint32_t IREE19:1;
+ vuint32_t IREE18:1;
+ vuint32_t IREE17:1;
+ vuint32_t IREE16:1;
+ vuint32_t IREE15:1;
+ vuint32_t IREE14:1;
+ vuint32_t IREE13:1;
+ vuint32_t IREE12:1;
+ vuint32_t IREE11:1;
+ vuint32_t IREE10:1;
+ vuint32_t IREE9:1;
+ vuint32_t IREE8:1;
+ vuint32_t IREE7:1;
+ vuint32_t IREE6:1;
+ vuint32_t IREE5:1;
+ vuint32_t IREE4:1;
+ vuint32_t IREE3:1;
+ vuint32_t IREE2:1;
+ vuint32_t IREE1:1;
+ vuint32_t IREE0:1;
+ } B;
+ } IREER;
+
+ union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IFEE23:1;
+ vuint32_t IFEE22:1;
+ vuint32_t IFEE21:1;
+ vuint32_t IFEE20:1;
+ vuint32_t IFEE19:1;
+ vuint32_t IFEE18:1;
+ vuint32_t IFEE17:1;
+ vuint32_t IFEE16:1;
+ vuint32_t IFEE15:1;
+ vuint32_t IFEE14:1;
+ vuint32_t IFEE13:1;
+ vuint32_t IFEE12:1;
+ vuint32_t IFEE11:1;
+ vuint32_t IFEE10:1;
+ vuint32_t IFEE9:1;
+ vuint32_t IFEE8:1;
+ vuint32_t IFEE7:1;
+ vuint32_t IFEE6:1;
+ vuint32_t IFEE5:1;
+ vuint32_t IFEE4:1;
+ vuint32_t IFEE3:1;
+ vuint32_t IFEE2:1;
+ vuint32_t IFEE1:1;
+ vuint32_t IFEE0:1;
+ } B;
+ } IFEER;
+
+ union { /* Interrupt Filter Enable (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IFE23:1;
+ vuint32_t IFE22:1;
+ vuint32_t IFE21:1;
+ vuint32_t IFE20:1;
+ vuint32_t IFE19:1;
+ vuint32_t IFE18:1;
+ vuint32_t IFE17:1;
+ vuint32_t IFE16:1;
+ vuint32_t IFE15:1;
+ vuint32_t IFE14:1;
+ vuint32_t IFE13:1;
+ vuint32_t IFE12:1;
+ vuint32_t IFE11:1;
+ vuint32_t IFE10:1;
+ vuint32_t IFE9:1;
+ vuint32_t IFE8:1;
+ vuint32_t IFE7:1;
+ vuint32_t IFE6:1;
+ vuint32_t IFE5:1;
+ vuint32_t IFE4:1;
+ vuint32_t IFE3:1;
+ vuint32_t IFE2:1;
+ vuint32_t IFE1:1;
+ vuint32_t IFE0:1;
+ } B;
+ } IFER;
+
+ vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */
+
+ union { /* Pad Configuration 0..148 (Base+0x0040-0x0168)*/
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SMC:1;
+ vuint16_t APC:1;
+ vuint16_t:1;
+ vuint16_t PA:2;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t:2;
+ vuint16_t ODE:1;
+ vuint16_t:2;
+ vuint16_t SRC:1;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[149];
+
+ vuint8_t SIU_reserved4[918]; /*Reserved 918 Bytes (Base+0x016A-0x04FF) */
+
+ union { /* Pad Selection for Mux Input (0x0500-0x53C) */
+ vuint8_t R;
+ struct {
+ vuint8_t :4;
+ vuint8_t PADSEL:4;
+ } B;
+ } PSMI[64];
+
+ vuint8_t SIU_reserved5[192]; /*Reserved 192 Bytes (Base+0x0540-0x05FF) */
+
+ union { /* GPIO Pad Data Output (Base+0x0600-0x06A0) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[124]; // only 124 GPD0 registers
+
+ vuint8_t SIU_reserved6[388]; /*Reserved 388 Bytes 512-124=388 */
+
+ union { /* GPIO Pad Data Input (Base+0x0800-0x08A0) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[124]; // only 152 GPD0 registers
+
+ vuint8_t SIU_reserved7[900]; /*Reserved 900 Bytes 1024-124=900 */
+
+ union { /* Parallel GPIO Pad Data Out 0-4 (0x0C00-0xC010) */
+ vuint32_t R;
+ struct {
+ vuint32_t PPD0:32;
+ } B;
+ } PGPDO[5];
+
+ vuint8_t SIU_reserved8[44]; /* Reserved 44 Bytes (Base+0x0C14-0x0C3F) */
+
+ union { /* Parallel GPIO Pad Data In 0-4 (0x0C40-0x0C50) */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDI:32;
+ } B;
+ } PGPDI[5];
+
+ vuint8_t SIU_reserved9[44]; /* Reserved 44 Bytes (Base+0x0C54-0x0C7F) */
+
+ union { /* Masked Parallel GPIO Pad Data Out 0-9 (0x0C80-0x0CA4) */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16;
+ vuint32_t MPPDO:16;
+ } B;
+ } MPGPDO[10];
+
+ vuint8_t SIU_reserved10[856]; /*Reserved 844 Bytes (Base+0x0CA8-0x0FFF)*/
+
+ union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t MAXCNT:4;
+ } B;
+ } IFMC[24];
+
+ vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F)*/
+
+ union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t IFCP:4;
+ } B;
+ } IFCPR;
+
+ vuint8_t SIU_reserved12[12156]; /* Reserved 12156 Bytes (+0x1084-0x3FFF)*/
+
+}; /* end of SIU_tag */
+
+/****************************************************************************/
+/* MODULE : WKUP */
+/****************************************************************************/
+struct WKUP_tag{
+
+ union { /* NMI Status Flag (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1;
+ vuint32_t NOVF0:1;
+ vuint32_t :30;
+ } B;
+ } NSR;
+
+ vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */
+
+ union { /* NMI Configuration (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK0:1;
+ vuint32_t NDSS0:2;
+ vuint32_t NWRE0:1;
+ vuint32_t :1;
+ vuint32_t NREE0:1;
+ vuint32_t NFEE0:1;
+ vuint32_t NFE0:1;
+ vuint32_t :24;
+ } B;
+ } NCR;
+
+ vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */
+
+ union { /* Wakeup/Interrup status flag (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t EIF:29;
+ } B;
+ } WISR;
+
+ union { /* Interrupt Request Enable (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t EIRE:29;
+ } B;
+ } IRER;
+
+ union { /* Wakeup Request Enable (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t WRE:29;
+ } B;
+ } WRER;
+
+ vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */
+
+ union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t IREE:29;
+ } B;
+ } WIREER;
+
+ union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t IFEE:29;
+ } B;
+ } WIFEER;
+
+ union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t IFE:29;
+ } B;
+ } WIFER;
+
+ union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t IPUE:29;
+ } B;
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
+
+ vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */
+
+}; /* end of WKUP_tag */
+
+/****************************************************************************/
+/* MODULE : EMIOS (base address - eMIOS0 0xC3FA_0000; eMIOS1 0xC3FA_4000) */
+/****************************************************************************/
+
+struct EMIOS_CHANNEL_tag{
+
+ union { /* Channel A Data (UCn Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t A:16;
+ } B;
+ } CADR;
+
+ union { /* Channel B Data (UCn Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t B:16;
+ } B;
+ } CBDR;
+
+ union { /* Channel Counter (UCn Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t C:16;
+ } B;
+ } CCNTR;
+
+ union { /* Channel Control (UCn Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t :3;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPEN:1;
+ vuint32_t DMA:1;
+ vuint32_t :1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t :3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t :1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR;
+
+ union { /* Channel Status (UCn Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t :15;
+ vuint32_t OVFL:1;
+ vuint32_t :12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR;
+
+ union { /* Alternate Channel A Data (UCn Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t ALTA:16;
+ } B;
+ } ALTCADR;
+
+ vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */
+
+}; /* end of EMIOS_CHANNEL_tag */
+
+
+struct EMIOS_tag{
+
+ union { /* Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t :1;
+ vuint32_t GPREN:1;
+ vuint32_t :10;
+ vuint32_t GPRE:8;
+ vuint32_t :8;
+ } B;
+ } MCR;
+
+ union { /* Global Flag (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t F31:1;
+ vuint32_t F30:1;
+ vuint32_t F29:1;
+ vuint32_t F28:1;
+ vuint32_t F27:1;
+ vuint32_t F26:1;
+ vuint32_t F25:1;
+ vuint32_t F24:1;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR;
+
+ union { /* Output Update Disable (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t OU31:1;
+ vuint32_t OU30:1;
+ vuint32_t OU29:1;
+ vuint32_t OU28:1;
+ vuint32_t OU27:1;
+ vuint32_t OU26:1;
+ vuint32_t OU25:1;
+ vuint32_t OU24:1;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR;
+
+ union { /* Disable Channel (Base+0x000F) */
+ vuint32_t R;
+ struct {
+ vuint32_t CHDIS31:1;
+ vuint32_t CHDIS30:1;
+ vuint32_t CHDIS29:1;
+ vuint32_t CHDIS28:1;
+ vuint32_t CHDIS27:1;
+ vuint32_t CHDIS26:1;
+ vuint32_t CHDIS25:1;
+ vuint32_t CHDIS24:1;
+ vuint32_t CHDIS23:1;
+ vuint32_t CHDIS22:1;
+ vuint32_t CHDIS21:1;
+ vuint32_t CHDIS20:1;
+ vuint32_t CHDIS19:1;
+ vuint32_t CHDIS18:1;
+ vuint32_t CHDIS17:1;
+ vuint32_t CHDIS16:1;
+ vuint32_t CHDIS15:1;
+ vuint32_t CHDIS14:1;
+ vuint32_t CHDIS13:1;
+ vuint32_t CHDIS12:1;
+ vuint32_t CHDIS11:1;
+ vuint32_t CHDIS10:1;
+ vuint32_t CHDIS9:1;
+ vuint32_t CHDIS8:1;
+ vuint32_t CHDIS7:1;
+ vuint32_t CHDIS6:1;
+ vuint32_t CHDIS5:1;
+ vuint32_t CHDIS4:1;
+ vuint32_t CHDIS3:1;
+ vuint32_t CHDIS2:1;
+ vuint32_t CHDIS1:1;
+ vuint32_t CHDIS0:1;
+ } B;
+ } UCDIS;
+
+ vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */
+
+ struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */
+
+ vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */
+
+}; /* end of EMIOS_tag */
+
+/****************************************************************************/
+/* MODULE : SSCM */
+/****************************************************************************/
+struct SSCM_tag{
+
+ union { /* Status (Base+0x0000) */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t PUB:1;
+ vuint16_t SEC:1;
+ vuint16_t:1;
+ vuint16_t BMODE:3;
+ vuint16_t:5;
+ } B;
+ } STATUS;
+
+ union { /* System Memory Configuration (Base+0x002) */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t PRSZ:5;
+ vuint16_t PVLB:1;
+ vuint16_t DTSZ:4;
+ vuint16_t DVLD:1;
+ } B;
+ } MEMCONFIG;
+
+ vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */
+
+ union { /* Error Configuration (Base+0x0006) */
+ vuint16_t R;
+ struct {
+ vuint16_t :14;
+ vuint16_t PAE:1;
+ vuint16_t RAE:1;
+ } B;
+ } ERROR;
+
+ union { /* Debug Status Port (Base+0x0008) */
+ vuint16_t R;
+ struct {
+ vuint16_t :13;
+ vuint16_t DEBUG_MODE:3;
+ } B;
+ } DEBUGPORT;
+
+ vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */
+
+ union { /* Password Comparison High Word (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32;
+ } B;
+ } PWCMPH;
+
+ union { /* Password Comparison Low Word (Base+0x0010)*/
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32;
+ } B;
+ } PWCMPL;
+
+}; /* end of SSCM_tag */
+
+/****************************************************************************/
+/* MODULE : ME */
+/****************************************************************************/
+struct ME_tag{
+
+ union { /* Global Status (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t S_CURRENTMODE:4;
+ vuint32_t S_MTRANS:1;
+ vuint32_t S_DC:1;
+ vuint32_t :2;
+ vuint32_t S_PDO:1;
+ vuint32_t :2;
+ vuint32_t S_MVR:1;
+ vuint32_t S_DFLA:2;
+ vuint32_t S_CFLA:2;
+ vuint32_t :9;
+ vuint32_t S_FMPLL:1;
+ vuint32_t S_FXOSC:1;
+ vuint32_t S_FIRC:1;
+ vuint32_t S_SYSCLK:4;
+ } B;
+ } GS;
+
+ union { /* Mode Control (Base+0x004) */
+ vuint32_t R;
+ struct {
+ vuint32_t TARGET_MODE:4;
+ vuint32_t :12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL;
+
+ union { /* Mode Enable (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :18;
+ vuint32_t STANDBY:1;
+ vuint32_t :2;
+ vuint32_t STOP:1;
+ vuint32_t :1;
+ vuint32_t HALT:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } MER;
+
+ union { /* Interrupt Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t I_ICONF:1;
+ vuint32_t I_IMODE:1;
+ vuint32_t I_SAFE:1;
+ vuint32_t I_MTC:1;
+ } B;
+ } IS;
+
+ union { /* Interrupt Mask (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t M_ICONF:1;
+ vuint32_t M_IMODE:1;
+ vuint32_t M_SAFE:1;
+ vuint32_t M_MTC:1;
+ } B;
+ } IM;
+
+ union { /* Invalid Mode Transition Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :27;
+ vuint32_t S_MTI:1;
+ vuint32_t S_MRI:1;
+ vuint32_t S_DMA:1;
+ vuint32_t S_NMA:1;
+ vuint32_t S_SEA:1;
+ } B;
+ } IMTS;
+
+ union { /* Debug Mode Transition Status (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t MPH_BUSY:1;
+ vuint32_t :2;
+ vuint32_t PMC_PROG:1;
+ vuint32_t CORE_DBG:1;
+ vuint32_t :2;
+ vuint32_t SMR:1;
+ vuint32_t :1;
+ vuint32_t FMPLL_SC:1;
+ vuint32_t FXOSC_SC:1;
+ vuint32_t FIRC_SC:1;
+ vuint32_t :1;
+ vuint32_t SYSCLK_SW:1;
+ vuint32_t DFLASH_SC:1;
+ vuint32_t CFLASH_SC:1;
+ vuint32_t CDP_PRPH_0_143:1;
+ vuint32_t :3;
+ vuint32_t CDP_PRPH_96_127:1;
+ vuint32_t CDP_PRPH_64_95:1;
+ vuint32_t CDP_PRPH_32_63:1;
+ vuint32_t CDP_PRPH_0_31:1;
+ } B;
+ } DMTS;
+
+ vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */
+
+ union { /* Reset Mode Configuration (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET;
+
+ union { /* Test Mode Configuration (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST;
+
+ union { /* Safe Mode Configuration (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE;
+
+ union { /* DRUN Mode Configuration (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN;
+
+ union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN[4];
+
+ union { /* HALT Mode Configuration (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT;
+
+ vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */
+
+ union { /* STOP Mode Configuration (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP;
+
+ vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */
+
+ union { /* STANDBY Mode Configuration (Base+0x0054) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSCON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY;
+
+ vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */
+
+ union {
+ vuint32_t R;
+ struct { /* Peripheral Status 0 (Base+0x0060) */
+ vuint32_t :8;
+ vuint32_t S_DMA_CH_MUX:1;
+ vuint32_t :6;
+ vuint32_t S_FLEXCAN0:1;
+ vuint32_t :10;
+ vuint32_t S_DSPI1:1;
+ vuint32_t S_DSPI0:1;
+ vuint32_t :4;
+ } B;
+ } PS0;
+
+ union { /* Peripheral Status 1 (Base+0x0064)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :6;
+ vuint32_t S_CTU:1;
+ vuint32_t :6;
+ vuint32_t S_LINFLEX2:1;
+ vuint32_t S_LINFLEX1:1;
+ vuint32_t S_LINFLEX0:1;
+ vuint32_t :14;
+ vuint32_t S_ADC1:1;
+ vuint32_t :1;
+ } B;
+ } PS1;
+
+ union { /* Peripheral Status 2 (Base+0x0068) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t S_PIT_RTI:1;
+ vuint32_t S_RTC_API:1;
+ vuint32_t :18;
+ vuint32_t S_EMIOS0:1;
+ vuint32_t :2;
+ vuint32_t S_WKPU:1;
+ vuint32_t S_SIUL:1;
+ vuint32_t :4;
+ } B;
+ } PS2;
+
+ union { /* Peripheral Status 3 (Base+0x006C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t S_CMU:1;
+ vuint32_t :8;
+ } B;
+ } PS3;
+
+ vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */
+
+ union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC[8];
+
+ union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */
+ vuint32_t R;
+ struct {
+ vuint32_t :18;
+ vuint32_t STANDBY:1;
+ vuint32_t :2;
+ vuint32_t STOP:1;
+ vuint32_t :1;
+ vuint32_t HALT:1;
+ vuint32_t :8;
+ } B;
+ } LPPC[8];
+
+
+ /* Note on PCTL registers: There are only some PCTL implemented in */
+ /* Bolero 1.5M/1M. In order to make the PCTL easily addressable, these */
+ /* are defined as an array (ie ME.PCTL[x].R). This means you have */
+ /* to be careful when addressing these registers in order not to */
+ /* access a PCTL that is not implemented. Following are available: */
+ /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 55, 53, 52, 51, 50, 49,48, */
+ /* 44, 33, 32, 23, 21-16, 9-4 */
+
+ union { /* Peripheral Control 0..143 (+0x00C0-0x014F) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t DBG_F:1;
+ vuint8_t LP_CFG:3;
+ vuint8_t RUN_CFG:3;
+ } B;
+ } PCTL[105];
+
+}; /* end of ME_tag */
+
+/****************************************************************************/
+/* MODULE : CGM */
+/****************************************************************************/
+struct CGM_tag{
+ /*
+ The "CGM" has fairly wide coverage and essentially includes everything in
+
+ chapter 6/7 of the Bolero Reference Manual:
+
+ Base Address | Clock Sources
+
+ -----------------------------
+
+ 0xC3FE0000 | FXOSC_CTL
+
+ 0xC3FE0040 | SXOSC_CTL
+
+ 0xC3FE0060 | FIRC_CTL
+
+ 0xC3FE0080 | SIRC_CTL
+
+ 0xC3FE00A0 | FMPLL
+
+ 0xC3FE00C0 | CGM Block 1
+
+ 0xC3FE0100 | CMU
+
+ 0xC3FE0120 | CGM Block 2
+
+
+
+ In this header file, "Base" referrs to the 1st address, 0xC3FE_0000
+
+ */
+ /* FXOSC - 0xC3FE_0000*/
+ union { /* Fast OSC Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t :7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t :2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:7;
+ } B;
+ } FXOSC_CTL;
+
+
+ /* Reserved Space between end of FXOSC and start SXOSC */
+ vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */
+
+
+ /* SXOSC - 0xC3FE_0040*/
+ union { /* Slow Osc Control (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t :7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t :2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t :5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } SXOSC_CTL;
+
+
+ /* Reserved space between end of SXOSC and start of FIRC */
+ vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */
+
+
+ /* FIRC - 0xC3FE_0060 */
+ union { /* Fast IRC Control (Base+0x0060) */
+ vuint32_t R;
+ struct {
+ vuint32_t :10;
+ vuint32_t RCTRIM:6;
+ vuint32_t :3;
+ vuint32_t RCDIV:5;
+ vuint32_t :2;
+ vuint32_t FIRCON_STDBY:1;
+ vuint32_t :5;
+ } B;
+ } FIRC_CTL;
+
+
+ /* Reserved space between end of FIRC and start of SIRC */
+ vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */
+
+
+ /* SIRC - 0xC3FE_0080 */
+ union { /* Slow IRC Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :11;
+ vuint32_t SIRCTRIM:5;
+ vuint32_t :3;
+ vuint32_t SIRCDIV:5;
+ vuint32_t :3;
+ vuint32_t S_SIRC:1;
+ vuint32_t :3;
+ vuint32_t SIRCON_STDBY:1;
+ } B;
+ } SIRC_CTL;
+
+
+ /* Reserved space between end of SIRC and start of FMPLL */
+ vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */
+
+
+ /* FMPLL - 0xC3FE_00A0 */
+ union { /* FMPLL Control (Base+0x00A0) */
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t IDF:4;
+ vuint32_t ODF:2;
+ vuint32_t:1;
+ vuint32_t NDIV:7;
+ vuint32_t:7;
+ vuint32_t EN_PLL_SW:1;
+ vuint32_t MODE:1;
+ vuint32_t UNLOCK_ONCE:1;
+ vuint32_t:1;
+ vuint32_t I_LOCK:1;
+ vuint32_t S_LOCK:1;
+ vuint32_t PLL_FAIL_MASK:1;
+ vuint32_t PLL_FAIL_FLAG:1;
+ vuint32_t:1;
+ } B;
+ } FMPLL_CR;
+
+ union { /* FMPLL Modulation (Base+0x00A4) */
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1;
+ vuint32_t :1;
+ vuint32_t SPRD_SEL:1;
+ vuint32_t MOD_PERIOD:13;
+ vuint32_t FM_EN:1;
+ vuint32_t INC_STEP:15;
+ } B;
+ } FMPLL_MR;
+
+
+ /* Reserved space between end of FMPLL and start of CGM Block 1 */
+ vuint8_t CGM_reserved4[88]; /*Reserved 88 bytes (Base+0x00A8-0x00FF) */
+
+ /* CMU - 0xC3FE_0100 */
+ union { /* CMU Control Status (Base+0x0100) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t SFM:1;
+ vuint32_t :13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t :5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_CSR;
+
+ union { /* CMU Frequency Display (Base+0x0104) */
+ vuint32_t R;
+ struct {
+ vuint32_t :12;
+ vuint32_t FD:20;
+ } B;
+ } CMU_FDR;
+
+ union { /* CMU High Freq Reference FMPLL (Base+0x0108) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t HFREF:12;
+ } B;
+ } CMU_HFREFR;
+
+ union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t LFREF:12;
+ } B;
+ } CMU_LFREFR;
+
+ union { /* CMU Interrupt Status (Base+0x0110) */
+ vuint32_t R;
+ struct {
+ vuint32_t :29;
+ vuint32_t FHHI:1; // *_A not present in RM
+ vuint32_t FLLI:1; // *_A not present in RM
+ vuint32_t OLRI:1;
+ } B;
+ } CMU_ISR;
+
+ /* Reserved space where IMR was previously positioned */
+ vuint8_t CGM_reserved5[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */
+
+ union { /* CMU Measurement Duration (Base+0x0118) */
+ vuint32_t R;
+ struct {
+ vuint32_t :12;
+ vuint32_t MD:20;
+ } B;
+ } CMU_MDR;
+
+
+ /* Reserved space between end of CMU and start of CGM Block 2 */
+ vuint8_t CGM_reserved6[596]; /*Reserved 596 bytes (Base+0x011C-0x036F) */
+
+ union { /* GCM Output Clock Enable (Base+0x0370) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t EN:1;
+ } B;
+ } OC_EN;
+
+ union { /* CGM Output Clock Division Sel (Base+0x0374) */
+ vuint32_t R;
+ struct {
+ vuint32_t :2;
+ vuint32_t SELDIV:2;
+ vuint32_t SELCTL:4;
+ vuint32_t :24;
+ } B;
+ } OCDS_SC;
+
+ union { /* CGM System Clock Select Status (Base+0x0378) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t SELSTAT:4;
+ vuint32_t :24;
+ } B;
+ } SC_SS;
+
+ union { /* CGM Sys Clk Div Config0 (Base+0x037C) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE0:1;
+ vuint8_t :3;
+ vuint8_t DIV0:4;
+ } B;
+ } SC_DC0;
+
+ union { /* CGM Sys Clk Div Config1 (Base+0x037D) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE1:1;
+ vuint8_t :3;
+ vuint8_t DIV1:4;
+ } B;
+ } SC_DC1;
+
+ union { /* CGM Sys Clk Div Config1 (Base+0x037E) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE2:1;
+ vuint8_t :3;
+ vuint8_t DIV2:4;
+ } B;
+ } SC_DC2;
+
+ vuint8_t CGM_reserved7[1]; /*Reserved 1 byte (Base+0x037F) */
+
+ union { /* CGM Aux clock select control register (Base+0x0380) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t SELCTL:4;
+ vuint32_t :24;
+ } B;
+ } AC0_SC;
+
+
+
+}; /* end of CGM_tag */
+
+/****************************************************************************/
+/* MODULE : RGM base address - 0xC3FE_4000 */
+/****************************************************************************/
+struct RGM_tag{
+
+ union { /* Functional Event Status (Base+0x0000) */
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1;
+ vuint16_t :6;
+ vuint16_t F_FLASH:1;
+ vuint16_t F_LVD45:1;
+ vuint16_t F_CMU_FHL:1;
+ vuint16_t F_CMU_OLR:1;
+ vuint16_t F_FMPLL:1;
+ vuint16_t F_CHKSTOP:1;
+ vuint16_t F_SOFT_FUNC :1;
+ vuint16_t F_CORE:1;
+ vuint16_t F_JTAG:1;
+ } B;
+ } FES;
+
+ union { /* Destructive Event Status (Base+0x0002) */
+ vuint16_t R;
+ struct {
+ vuint16_t F_POR:1;
+ vuint16_t :10;
+ vuint16_t F_LVD27_VREG:1;
+ vuint16_t F_LVD27:1;
+ vuint16_t F_SWT:1;
+ vuint16_t F_LVD12_PD1:1;
+ vuint16_t F_LVD12_PD0:1;
+ } B;
+ } DES;
+
+ union { /* Functional Event Reset Disable (+0x0004) */
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1;
+ vuint16_t :6;
+ vuint16_t D_FLASH:1;
+ vuint16_t D_LVD45:1;
+ vuint16_t D_CMU_FHL:1;
+ vuint16_t D_CMU_OLR:1;
+ vuint16_t D_FMPLL:1;
+ vuint16_t D_CHKSTOP:1;
+ vuint16_t D_SOFT_FUNC:1;
+ vuint16_t D_CORE:1;
+ vuint16_t D_JTAG:1;
+ } B;
+ } FERD;
+
+ union { /* Destructive Event Reset Disable (Base+0x0006)*/
+ vuint16_t R;
+ struct {
+ vuint16_t :11;
+ vuint16_t D_LVD27_VREG:1;
+ vuint16_t D_LVD27:1;
+ vuint16_t D_SWT:1;
+ vuint16_t D_LVD12_PD1:1;
+ vuint16_t D_LVD12_PD0:1;
+ } B;
+ } DERD;
+
+ vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */
+
+ union { /* Functional Event Alt Request (Base+0x0010) */
+ vuint16_t R;
+ struct {
+ vuint16_t AR_EXR:1;
+ vuint16_t:6;
+ vuint16_t AR_FLASH:1;
+ vuint16_t AR_LVD45:1;
+ vuint16_t AR_CMU_FHL:1;
+ vuint16_t AR_CMU_OLR:1;
+ vuint16_t AR_FMPLL:1;
+ vuint16_t AR_CHKSTOP:1;
+ vuint16_t AR_SOFT_FUNC:1;
+ vuint16_t AR_CORE:1;
+ vuint16_t AR_JTAG:1;
+ } B;
+ } FEAR;
+
+ union { /* Destructive Event Alt Request (Base+0x0012) */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t AR_LVD27_VREG:1;
+ vuint16_t AR_LVD27:1;
+ vuint16_t AR_SWT:1;
+ vuint16_t AR_LVD12_PD1:1;
+ vuint16_t AR_LVD12_PD0:1;
+ } B;
+ } DEAR; /* Destructive Event Alternate Request */
+
+ vuint8_t RGM_reserved1[4]; /*Reserved 4 bytes (Base+0x0014-0x0017) */
+
+ union { /* Functional Event Short Sequence (+0x0018) */
+ vuint16_t R;
+ struct {
+ vuint16_t SS_EXR:1;
+ vuint16_t :6;
+ vuint16_t SS_FLASH:1;
+ vuint16_t SS_LVD45:1;
+ vuint16_t SS_CMU_FHL:1;
+ vuint16_t SS_CMU_OLR:1;
+ vuint16_t SS_FMPLL:1;
+ vuint16_t SS_CHKSTOP:1;
+ vuint16_t SS_SOFT_FUNC:1;
+ vuint16_t SS_CORE:1;
+ vuint16_t SS_JTAG:1;
+ } B;
+ } FESS;
+
+ union { /* STANDBY reset sequence (Base+0x001A) */
+ vuint16_t R;
+ struct {
+ vuint16_t :8;
+ vuint16_t BOOT_FROM_BKP_RAM:1;
+ vuint16_t :7;
+ } B;
+ } STDBY;
+
+ union { /* Functional Bidirectional Reset En (+0x001C) */
+ vuint16_t R;
+ struct {
+ vuint16_t BE_EXR:1;
+ vuint16_t :6;
+ vuint16_t BE_FLASH:1;
+ vuint16_t BE_LVD45:1;
+ vuint16_t BE_CMU_FHL:1;
+ vuint16_t BE_CMU_OLR:1;
+ vuint16_t BE_FMPLL:1;
+ vuint16_t BE_CHKSTOP:1;
+ vuint16_t BE_SOFT_FUNC:1;
+ vuint16_t BE_CORE:1;
+ vuint16_t BE_JTAG:1;
+ } B;
+ } FBRE;
+
+}; /* end of RGM_tag */
+/****************************************************************************/
+/* MODULE : PCU (base address 0xC3FE_8000) */
+/****************************************************************************/
+struct PCU_tag{
+
+ union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :18;
+ vuint32_t STBY:1;
+ vuint32_t :2;
+ vuint32_t STOP:1;
+ vuint32_t :1;
+ vuint32_t HALT:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RST:1;
+ } B;
+ } PCONF[4];
+
+ vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */
+
+ union { /* PCU Power Domain Status (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t PD3:1;
+ vuint32_t PD2:1;
+ vuint32_t PD1:1;
+ vuint32_t PD0:1;
+ } B;
+ } PSTAT;
+
+ vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */
+
+
+ /* Following register is from Voltage Regulators chapter of RM */
+
+ union { /* PCU Voltage Regulator Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t MASK_LVDHV5:1;
+ } B;
+ } VREG_CTL; /* Changed from VCTL for consistency with other regs here */
+
+ }; /* end of PCU_tag */
+/****************************************************************************/
+/* MODULE : RTC/API */
+/****************************************************************************/
+struct RTC_tag{
+
+ union { /* RTC Supervisor Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t SUPV:1;
+ vuint32_t :31;
+ } B;
+ } RTCSUPV ;
+
+ union { /* RTC Control (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t CNTEN:1;
+ vuint32_t RTCIE:1;
+ vuint32_t FRZEN:1;
+ vuint32_t ROVREN:1;
+ vuint32_t RTCVAL:12;
+ vuint32_t APIEN:1;
+ vuint32_t APIIE:1;
+ vuint32_t CLKSEL:2;
+ vuint32_t DIV512EN:1;
+ vuint32_t DIV32EN:1;
+ vuint32_t APIVAL:10;
+ } B;
+ } RTCC;
+
+ union { /* RTC Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :2;
+ vuint32_t RTCF:1;
+ vuint32_t :15;
+ vuint32_t APIF:1;
+ vuint32_t :2;
+ vuint32_t ROVRF:1;
+ vuint32_t :10;
+ } B;
+ } RTCS;
+
+ union { /* RTC Counter (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t RTCCNT:32;
+ } B;
+ } RTCCNT;
+
+}; /* end of RTC_tag */
+
+/****************************************************************************/
+/* MODULE : PIT (base address - 0xC3FF_FFFF) */
+/****************************************************************************/
+ struct PIT_tag {
+
+ union { /* PIT Module Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR;
+
+ vuint8_t PIT_reserved0[252]; /* Reserved 252 Bytes (Base+0x0004-0x00FF) */
+
+ /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */
+ struct {
+
+ union { /* PIT Timer Load Value (Offset+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union { /* PIT Current Timer Value (Offset+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union { /* PIT Timer Control (Offset+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union { /* PIT Timer Control (Offset+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+
+ }CH[8]; /* End of PIT Timer Channels */
+
+}; /* end of PIT_tag */
+
+/****************************************************************************/
+/* MODULE : ADC1 (12 Bit) */
+/****************************************************************************/
+struct ADC1_tag {
+
+ union { /* ADC1 Main Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t:4;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORTCHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:4;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR;
+
+ union { /* ADC1 Main Status (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:2;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR;
+
+ vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
+
+ union { /* ADC1 Interrupt Status (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR;
+
+ union { /* ADC1 Channel Pending 0 (Base+0x0014) */
+ vuint32_t R; /* (For precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CEOCFR0;
+
+ union { /* ADC1 Channel Pending 1 (Base+0x0018) */
+ vuint32_t R; /* (For standard Channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t EOC_CH44:1;
+ vuint32_t EOC_CH43:1;
+ vuint32_t EOC_CH42:1;
+ vuint32_t EOC_CH41:1;
+ vuint32_t EOC_CH40:1;
+ vuint32_t EOC_CH39:1;
+ vuint32_t EOC_CH38:1;
+ vuint32_t EOC_CH37:1;
+ vuint32_t EOC_CH36:1;
+ vuint32_t EOC_CH35:1;
+ vuint32_t EOC_CH34:1;
+ vuint32_t EOC_CH33:1;
+ vuint32_t EOC_CH32:1;
+ } B;
+ } CEOCFR1;
+
+ union { /* ADC1 Channel Pending 2 (Base+0x001C) */
+ vuint32_t R; /* (For External Channels) */
+ struct {
+ vuint32_t EOC_CH95:1;
+ vuint32_t EOC_CH94:1;
+ vuint32_t EOC_CH93:1;
+ vuint32_t EOC_CH92:1;
+ vuint32_t EOC_CH91:1;
+ vuint32_t EOC_CH90:1;
+ vuint32_t EOC_CH89:1;
+ vuint32_t EOC_CH88:1;
+ vuint32_t EOC_CH87:1;
+ vuint32_t EOC_CH86:1;
+ vuint32_t EOC_CH85:1;
+ vuint32_t EOC_CH84:1;
+ vuint32_t EOC_CH83:1;
+ vuint32_t EOC_CH82:1;
+ vuint32_t EOC_CH81:1;
+ vuint32_t EOC_CH80:1;
+ vuint32_t EOC_CH79:1;
+ vuint32_t EOC_CH78:1;
+ vuint32_t EOC_CH77:1;
+ vuint32_t EOC_CH76:1;
+ vuint32_t EOC_CH75:1;
+ vuint32_t EOC_CH74:1;
+ vuint32_t EOC_CH73:1;
+ vuint32_t EOC_CH72:1;
+ vuint32_t EOC_CH71:1;
+ vuint32_t EOC_CH70:1;
+ vuint32_t EOC_CH69:1;
+ vuint32_t EOC_CH68:1;
+ vuint32_t EOC_CH67:1;
+ vuint32_t EOC_CH66:1;
+ vuint32_t EOC_CH65:1;
+ vuint32_t EOC_CH64:1;
+ } B;
+ } CEOCFR2;
+
+
+ union { /* ADC1 Interrupt Mask (Base+0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR;
+
+ union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */
+ vuint32_t R; /* (For Precision Channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0;
+
+ union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */
+ vuint32_t R; /* (For Standard Channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t CIM44:1;
+ vuint32_t CIM43:1;
+ vuint32_t CIM42:1;
+ vuint32_t CIM41:1;
+ vuint32_t CIM40:1;
+ vuint32_t CIM39:1;
+ vuint32_t CIM38:1;
+ vuint32_t CIM37:1;
+ vuint32_t CIM36:1;
+ vuint32_t CIM35:1;
+ vuint32_t CIM34:1;
+ vuint32_t CIM33:1;
+ vuint32_t CIM32:1;
+ } B;
+ } CIMR1;
+
+ union { /* ADC1 Channel Interrupt Mask 2 (Base+0x002C) */
+ vuint32_t R; /* (For External Mux'd Channels) */
+ struct {
+ vuint32_t CIM95:1;
+ vuint32_t CIM94:1;
+ vuint32_t CIM93:1;
+ vuint32_t CIM92:1;
+ vuint32_t CIM91:1;
+ vuint32_t CIM90:1;
+ vuint32_t CIM89:1;
+ vuint32_t CIM88:1;
+ vuint32_t CIM87:1;
+ vuint32_t CIM86:1;
+ vuint32_t CIM85:1;
+ vuint32_t CIM84:1;
+ vuint32_t CIM83:1;
+ vuint32_t CIM82:1;
+ vuint32_t CIM81:1;
+ vuint32_t CIM80:1;
+ vuint32_t CIM79:1;
+ vuint32_t CIM78:1;
+ vuint32_t CIM77:1;
+ vuint32_t CIM76:1;
+ vuint32_t CIM75:1;
+ vuint32_t CIM74:1;
+ vuint32_t CIM73:1;
+ vuint32_t CIM72:1;
+ vuint32_t CIM71:1;
+ vuint32_t CIM70:1;
+ vuint32_t CIM69:1;
+ vuint32_t CIM68:1;
+ vuint32_t CIM67:1;
+ vuint32_t CIM66:1;
+ vuint32_t CIM65:1;
+ vuint32_t CIM64:1;
+ } B;
+ } CIMR2;
+
+
+ union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t WDG2H:1;
+ vuint32_t WDG2L:1;
+ vuint32_t WDG1H:1;
+ vuint32_t WDG1L:1;
+ vuint32_t WDG0H:1;
+ vuint32_t WDG0L:1;
+ } B;
+ } WTISR;
+
+ union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t MSKWDG2H:1;
+ vuint32_t MSKWDG2L:1;
+ vuint32_t MSKWDG1H:1;
+ vuint32_t MSKWDG1L:1;
+ vuint32_t MSKWDG0H:1;
+ vuint32_t MSKWDG0L:1;
+ } B;
+ } WTIMR;
+
+ vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
+
+ union { /* ADC1 DMA Enable (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE;
+
+ union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */
+ vuint32_t R; /* (for precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0;
+
+ union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */
+ vuint32_t R; /* (for precision channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t DMA44:1;
+ vuint32_t DMA43:1;
+ vuint32_t DMA42:1;
+ vuint32_t DMA41:1;
+ vuint32_t DMA40:1;
+ vuint32_t DMA39:1;
+ vuint32_t DMA38:1;
+ vuint32_t DMA37:1;
+ vuint32_t DMA36:1;
+ vuint32_t DMA35:1;
+ vuint32_t DMA34:1;
+ vuint32_t DMA33:1;
+ vuint32_t DMA32:1;
+ } B;
+ } DMAR1;
+
+ union { /* ADC1 DMA Channel Select 2 (Base+0x004C) */
+ vuint32_t R; /* (for External channels) */
+ struct {
+ vuint32_t DMA95:1;
+ vuint32_t DMA94:1;
+ vuint32_t DMA93:1;
+ vuint32_t DMA92:1;
+ vuint32_t DMA91:1;
+ vuint32_t DMA90:1;
+ vuint32_t DMA89:1;
+ vuint32_t DMA88:1;
+ vuint32_t DMA87:1;
+ vuint32_t DMA86:1;
+ vuint32_t DMA85:1;
+ vuint32_t DMA84:1;
+ vuint32_t DMA83:1;
+ vuint32_t DMA82:1;
+ vuint32_t DMA81:1;
+ vuint32_t DMA80:1;
+ vuint32_t DMA79:1;
+ vuint32_t DMA78:1;
+ vuint32_t DMA77:1;
+ vuint32_t DMA76:1;
+ vuint32_t DMA75:1;
+ vuint32_t DMA74:1;
+ vuint32_t DMA73:1;
+ vuint32_t DMA72:1;
+ vuint32_t DMA71:1;
+ vuint32_t DMA70:1;
+ vuint32_t DMA69:1;
+ vuint32_t DMA68:1;
+ vuint32_t DMA67:1;
+ vuint32_t DMA66:1;
+ vuint32_t DMA65:1;
+ vuint32_t DMA64:1;
+ } B;
+ } DMAR2;
+
+ vuint8_t ADC1_reserved4[16]; /* Reserved 16 bytes (Base+0x0048-0x005F) */
+
+ /* Note the threshold registers are not implemented as an array for */
+ /* concistency with ADC0 header section */
+
+ union { /* ADC1 Threshold 0 (Base+0x0060) */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR0;
+
+ union { /* ADC1 Threshold 1 (Base+0x0064) */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR1;
+
+ union { /* ADC1 Threshold 2 (Base+0x0068) */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR2;
+
+ vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */
+
+ union { /* ADC1 Presampling Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR;
+
+ union { /* ADC1 Presampling 0 (Base+0x0084) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0;
+
+ union { /* ADC1 Presampling 1 (Base+0x0088) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t PRES44:1;
+ vuint32_t PRES43:1;
+ vuint32_t PRES42:1;
+ vuint32_t PRES41:1;
+ vuint32_t PRES40:1;
+ vuint32_t PRES39:1;
+ vuint32_t PRES38:1;
+ vuint32_t PRES37:1;
+ vuint32_t PRES36:1;
+ vuint32_t PRES35:1;
+ vuint32_t PRES34:1;
+ vuint32_t PRES33:1;
+ vuint32_t PRES32:1;
+ } B;
+ } PSR1;
+
+
+ union { /* ADC1 Presampling 2 (Base+0x008C) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t PRES95:1;
+ vuint32_t PRES94:1;
+ vuint32_t PRES93:1;
+ vuint32_t PRES92:1;
+ vuint32_t PRES91:1;
+ vuint32_t PRES90:1;
+ vuint32_t PRES89:1;
+ vuint32_t PRES88:1;
+ vuint32_t PRES87:1;
+ vuint32_t PRES86:1;
+ vuint32_t PRES85:1;
+ vuint32_t PRES84:1;
+ vuint32_t PRES83:1;
+ vuint32_t PRES82:1;
+ vuint32_t PRES81:1;
+ vuint32_t PRES80:1;
+ vuint32_t PRES79:1;
+ vuint32_t PRES78:1;
+ vuint32_t PRES77:1;
+ vuint32_t PRES76:1;
+ vuint32_t PRES75:1;
+ vuint32_t PRES74:1;
+ vuint32_t PRES73:1;
+ vuint32_t PRES72:1;
+ vuint32_t PRES71:1;
+ vuint32_t PRES70:1;
+ vuint32_t PRES69:1;
+ vuint32_t PRES68:1;
+ vuint32_t PRES67:1;
+ vuint32_t PRES66:1;
+ vuint32_t PRES65:1;
+ vuint32_t PRES64:1;
+ } B;
+ } PSR2;
+
+
+ vuint8_t ADC1_reserved6[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */
+
+ /* Note the following CTR registers are NOT implemented as an array to */
+ /* try and maintain some concistency through the header file */
+ /* (The registers are however identical) */
+
+ union { /* ADC1 Conversion Timing 0 (Base+0x0094) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2;
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0;
+
+ union { /* ADC1 Conversion Timing 1 (Base+0x0098) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1;
+
+
+ union { /* ADC1 Conversion Timing 2 (Base+0x009C) */
+ vuint32_t R; /* (External channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:4;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR2;
+
+ vuint8_t ADC1_reserved7[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */
+
+ union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0;
+
+ union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } NCMR1;
+
+
+ union { /* ADC1 Normal Conversion Mask 2 (Base+0x00AC) */
+ vuint32_t R; /* (External channels) */
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } NCMR2;
+
+ vuint8_t ADC1_reserved8[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B4) */
+
+ union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0;
+
+ union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t :19;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } JCMR1;
+
+
+ union { /* ADC1 Injected Conversion Mask 2 (Base+0x00BC) */
+ vuint32_t R; /* (External channels) */
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } JCMR2;
+
+ vuint8_t ADC1_reserved9[4]; /* Reserved 4 bytes (Base+0x00C0=0x00C4) */
+
+ union { /* Decode Signals Delay Register (base+0x00C4)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t DSD:12;
+ } B;
+ } DSDR;
+
+
+ union { /* Power Down Exit Delay Register (base+0x00C8)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR;
+
+ vuint8_t ADC1_reserved10[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */
+
+ union { /* ADC1 Channel 0-39 Data (Base+0x0100-0x019C) */
+ vuint32_t R; /* Note CDR[16..31] and [44..63] are reserved 0x0140-0x017F */
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:4;
+ vuint32_t CDATA:12;
+ } B;
+ } CDR[96];
+
+ vuint8_t ADC1_reserved11[48]; /* Reserved 48 bytes (Base+0x0280-0x002B0) */
+
+ union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t WSEL_CH7:4;
+ vuint32_t WSEL_CH6:4;
+ vuint32_t WSEL_CH5:4;
+ vuint32_t WSEL_CH4:4;
+ vuint32_t WSEL_CH3:4;
+ vuint32_t WSEL_CH2:4;
+ vuint32_t WSEL_CH1:4;
+ vuint32_t WSEL_CH0:4;
+ } B;
+ } CWSELR0;
+
+ union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t WSEL_CH15:4;
+ vuint32_t WSEL_CH14:4;
+ vuint32_t WSEL_CH13:4;
+ vuint32_t WSEL_CH12:4;
+ vuint32_t WSEL_CH11:4;
+ vuint32_t WSEL_CH10:4;
+ vuint32_t WSEL_CH9:4;
+ vuint32_t WSEL_CH8:4;
+ } B;
+ } CWSELR1;
+
+ vuint8_t ADC1_reserved12[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
+
+ union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t WSEL_CH39:4;
+ vuint32_t WSEL_CH38:4;
+ vuint32_t WSEL_CH37:4;
+ vuint32_t WSEL_CH36:4;
+ vuint32_t WSEL_CH35:4;
+ vuint32_t WSEL_CH34:4;
+ vuint32_t WSEL_CH33:4;
+ vuint32_t WSEL_CH32:4;
+ } B;
+ } CWSELR4;
+
+ union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:12;
+ vuint32_t WSEL_CH44:4;
+ vuint32_t WSEL_CH43:4;
+ vuint32_t WSEL_CH42:4;
+ vuint32_t WSEL_CH41:4;
+ vuint32_t WSEL_CH40:4;
+ } B;
+ } CWSELR5;
+
+ vuint8_t ADC1_reserved42[8]; /* Reserved 8 bytes (Base+0x02C8-0x02D0) */
+
+ union { /* ADC1 Channel Watchdog Select 8 (Base+0x02D0) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t WSEL_CH71:4;
+ vuint32_t WSEL_CH70:4;
+ vuint32_t WSEL_CH69:4;
+ vuint32_t WSEL_CH68:4;
+ vuint32_t WSEL_CH67:4;
+ vuint32_t WSEL_CH66:4;
+ vuint32_t WSEL_CH65:4;
+ vuint32_t WSEL_CH64:4;
+ } B;
+ } CWSELR8;
+
+ union { /* ADC1 Channel Watchdog Select 9 (Base+0x02D4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t WSEL_CH79:4;
+ vuint32_t WSEL_CH78:4;
+ vuint32_t WSEL_CH77:4;
+ vuint32_t WSEL_CH76:4;
+ vuint32_t WSEL_CH75:4;
+ vuint32_t WSEL_CH74:4;
+ vuint32_t WSEL_CH73:4;
+ vuint32_t WSEL_CH72:4;
+ } B;
+ } CWSELR9;
+
+ union { /* ADC1 Channel Watchdog Select 10 (Base+0x02D8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t WSEL_CH87:4;
+ vuint32_t WSEL_CH86:4;
+ vuint32_t WSEL_CH85:4;
+ vuint32_t WSEL_CH84:4;
+ vuint32_t WSEL_CH83:4;
+ vuint32_t WSEL_CH82:4;
+ vuint32_t WSEL_CH81:4;
+ vuint32_t WSEL_CH80:4;
+ } B;
+ } CWSELR10;
+
+ union { /* ADC1 Channel Watchdog Select 11 (Base+0x02DC) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t WSEL_CH95:4;
+ vuint32_t WSEL_CH94:4;
+ vuint32_t WSEL_CH93:4;
+ vuint32_t WSEL_CH92:4;
+ vuint32_t WSEL_CH91:4;
+ vuint32_t WSEL_CH90:4;
+ vuint32_t WSEL_CH89:4;
+ vuint32_t WSEL_CH88:4;
+ } B;
+ } CWSELR11;
+
+
+ union { /* ADC1 Channel Watchdog Enable0 (Base+0x02E0) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR0;
+
+ union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t :19;
+ vuint32_t CWEN44:1;
+ vuint32_t CWEN43:1;
+ vuint32_t CWEN42:1;
+ vuint32_t CWEN41:1;
+ vuint32_t CWEN40:1;
+ vuint32_t CWEN39:1;
+ vuint32_t CWEN38:1;
+ vuint32_t CWEN37:1;
+ vuint32_t CWEN36:1;
+ vuint32_t CWEN35:1;
+ vuint32_t CWEN34:1;
+ vuint32_t CWEN33:1;
+ vuint32_t CWEN32:1;
+ } B;
+ } CWENR1;
+
+ union { /* ADC1 Channel Watchdog Enable2 (Base++0x02E8) */
+ vuint32_t R; /* (External channels) */
+ struct {
+ vuint32_t CWEN95:1;
+ vuint32_t CWEN94:1;
+ vuint32_t CWEN93:1;
+ vuint32_t CWEN92:1;
+ vuint32_t CWEN91:1;
+ vuint32_t CWEN90:1;
+ vuint32_t CWEN89:1;
+ vuint32_t CWEN88:1;
+ vuint32_t CWEN87:1;
+ vuint32_t CWEN86:1;
+ vuint32_t CWEN85:1;
+ vuint32_t CWEN84:1;
+ vuint32_t CWEN83:1;
+ vuint32_t CWEN82:1;
+ vuint32_t CWEN81:1;
+ vuint32_t CWEN80:1;
+ vuint32_t CWEN79:1;
+ vuint32_t CWEN78:1;
+ vuint32_t CWEN77:1;
+ vuint32_t CWEN76:1;
+ vuint32_t CWEN75:1;
+ vuint32_t CWEN74:1;
+ vuint32_t CWEN73:1;
+ vuint32_t CWEN72:1;
+ vuint32_t CWEN71:1;
+ vuint32_t CWEN70:1;
+ vuint32_t CWEN69:1;
+ vuint32_t CWEN68:1;
+ vuint32_t CWEN67:1;
+ vuint32_t CWEN66:1;
+ vuint32_t CWEN65:1;
+ vuint32_t CWEN64:1;
+ } B;
+ } CWENR2;
+
+ vuint8_t ADC1_reserved14[4]; /* Reserved 4 bytes (Base+0x02EC-0x02F0) */
+
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t AWORR_CH15:1;
+ vuint32_t AWORR_CH14:1;
+ vuint32_t AWORR_CH13:1;
+ vuint32_t AWORR_CH12:1;
+ vuint32_t AWORR_CH11:1;
+ vuint32_t AWORR_CH10:1;
+ vuint32_t AWORR_CH9:1;
+ vuint32_t AWORR_CH8:1;
+ vuint32_t AWORR_CH7:1;
+ vuint32_t AWORR_CH6:1;
+ vuint32_t AWORR_CH5:1;
+ vuint32_t AWORR_CH4:1;
+ vuint32_t AWORR_CH3:1;
+ vuint32_t AWORR_CH2:1;
+ vuint32_t AWORR_CH1:1;
+ vuint32_t AWORR_CH0:1;
+ } B;
+ } AWORR0;
+
+ union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */
+ vuint32_t R;
+ struct {
+ vuint32_t :19;
+ vuint32_t AWORR_CH44:1;
+ vuint32_t AWORR_CH43:1;
+ vuint32_t AWORR_CH42:1;
+ vuint32_t AWORR_CH41:1;
+ vuint32_t AWORR_CH40:1;
+ vuint32_t AWORR_CH39:1;
+ vuint32_t AWORR_CH38:1;
+ vuint32_t AWORR_CH37:1;
+ vuint32_t AWORR_CH36:1;
+ vuint32_t AWORR_CH35:1;
+ vuint32_t AWORR_CH34:1;
+ vuint32_t AWORR_CH33:1;
+ vuint32_t AWORR_CH32:1;
+ } B;
+ } AWORR1;
+
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
+ vuint32_t R;
+ struct {
+ vuint32_t AWORR_CH95:1;
+ vuint32_t AWORR_CH94:1;
+ vuint32_t AWORR_CH93:1;
+ vuint32_t AWORR_CH92:1;
+ vuint32_t AWORR_CH91:1;
+ vuint32_t AWORR_CH90:1;
+ vuint32_t AWORR_CH89:1;
+ vuint32_t AWORR_CH88:1;
+ vuint32_t AWORR_CH87:1;
+ vuint32_t AWORR_CH86:1;
+ vuint32_t AWORR_CH85:1;
+ vuint32_t AWORR_CH84:1;
+ vuint32_t AWORR_CH83:1;
+ vuint32_t AWORR_CH82:1;
+ vuint32_t AWORR_CH81:1;
+ vuint32_t AWORR_CH80:1;
+ vuint32_t AWORR_CH79:1;
+ vuint32_t AWORR_CH78:1;
+ vuint32_t AWORR_CH77:1;
+ vuint32_t AWORR_CH76:1;
+ vuint32_t AWORR_CH75:1;
+ vuint32_t AWORR_CH74:1;
+ vuint32_t AWORR_CH73:1;
+ vuint32_t AWORR_CH72:1;
+ vuint32_t AWORR_CH71:1;
+ vuint32_t AWORR_CH70:1;
+ vuint32_t AWORR_CH69:1;
+ vuint32_t AWORR_CH68:1;
+ vuint32_t AWORR_CH67:1;
+ vuint32_t AWORR_CH66:1;
+ vuint32_t AWORR_CH65:1;
+ vuint32_t AWORR_CH64:1;
+ } B;
+ } AWORR2;
+
+ vuint8_t ADC1_reserved15[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */
+
+}; /* end of ADC1_tag */
+
+/****************************************************************************/
+/* MODULE : LINFLEX - non DMA master only */
+/****************************************************************************/
+struct LINFLEX_tag {
+
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CCD:1;
+ vuint32_t CFD:1;
+ vuint32_t LASE:1;
+ vuint32_t AWUM:1;
+ vuint32_t MBL:4;
+ vuint32_t BF:1;
+ vuint32_t SFTM:1;
+ vuint32_t LBKM:1;
+ vuint32_t MME:1;
+ vuint32_t SBDT:1;
+ vuint32_t RBLM:1;
+ vuint32_t SLEEP:1;
+ vuint32_t INIT:1;
+ } B;
+ } LINCR1;
+
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZIE:1;
+ vuint32_t OCIE:1;
+ vuint32_t BEIE:1;
+ vuint32_t CEIE:1;
+ vuint32_t HEIE:1;
+ vuint32_t :2;
+ vuint32_t FEIE:1;
+ vuint32_t BOIE:1;
+ vuint32_t LSIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t DBFIE:1;
+ vuint32_t DBEIE:1;
+ vuint32_t DRIE:1;
+ vuint32_t DTIE:1;
+ vuint32_t HRIE:1;
+ } B;
+ } LINIER;
+
+ union { /* LINFLEX LIN Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t LINS:4;
+ vuint32_t:2;
+ vuint32_t RMB:1;
+ vuint32_t:1;
+ vuint32_t RBSY:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t DBFF:1;
+ vuint32_t DBEF:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t HRF:1;
+ } B;
+ } LINSR;
+
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t BEF:1;
+ vuint32_t CEF:1;
+ vuint32_t SFEF:1;
+ vuint32_t BDEF:1;
+ vuint32_t IDPEF:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t:6;
+ vuint32_t NF:1;
+ } B;
+ } LINESR;
+
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t:1;
+ vuint32_t TDFL:2;
+ vuint32_t:1;
+ vuint32_t RDFL:2;
+ vuint32_t:4;
+ vuint32_t RXEN:1;
+ vuint32_t TXEN:1;
+ vuint32_t OP:1;
+ vuint32_t PCE:1;
+ vuint32_t WL:1;
+ vuint32_t UART:1;
+ } B;
+ } UARTCR;
+
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
+ vuint32_t RMB:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t :1;
+ vuint32_t TO:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t NF:1;
+ } B;
+ } UARTSR;
+
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t:5;
+ vuint32_t LTOM:1;
+ vuint32_t IOT:1;
+ vuint32_t TOCE:1;
+ vuint32_t CNT:8;
+ } B;
+ } LINTCSR;
+
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t OC2:8;
+ vuint32_t OC1:8;
+ } B;
+ } LINOCR;
+
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t RTO:4;
+ vuint32_t:1;
+ vuint32_t HTO:7;
+ } B;
+ } LINTOCR;
+
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DIV_F:4;
+ } B;
+ } LINFBRR;
+
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t DIV_M:20;
+ } B;
+ } LINIBRR;
+
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t CF:8;
+ } B;
+ } LINCFR;
+
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t IOBE:1;
+ vuint32_t IOPE:1;
+ vuint32_t WURQ:1;
+ vuint32_t DDRQ:1;
+ vuint32_t DTRQ:1;
+ vuint32_t ABRQ:1;
+ vuint32_t HTRQ:1;
+ vuint32_t:8;
+ } B;
+ } LINCR2;
+
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } BIDR;
+
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL;
+
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM;
+
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FACT:8;
+ } B;
+ } IFER;
+
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFMI:4;
+ } B;
+ } IFMI;
+
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t IFM:5;
+ } B;
+ } IFMR;
+
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t:3; /* for LINflexD no reseve here*/
+ vuint32_t DFL:3; /* Linflex D - this field is 6 bits (0 and 1), Linflex - this field is 3 bits (2-9 B1.5M) (2-7 B1M) */
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } IFCR[16];
+
+
+}; /* end of LINFLEX_tag */
+
+
+/****************************************************************************/
+/* MODULE : LINFLEXD0 Master/Slave DMA Enabled */
+/****************************************************************************/
+struct LINFLEXD0_tag {
+
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CCD:1;
+ vuint32_t CFD:1;
+ vuint32_t LASE:1;
+ vuint32_t AWUM:1;
+ vuint32_t MBL:4;
+ vuint32_t BF:1;
+ vuint32_t SFTM:1;
+ vuint32_t LBKM:1;
+ vuint32_t MME:1;
+ vuint32_t SBDT:1;
+ vuint32_t RBLM:1;
+ vuint32_t SLEEP:1;
+ vuint32_t INIT:1;
+ } B;
+ } LINCR1;
+
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZIE:1;
+ vuint32_t OCIE:1;
+ vuint32_t BEIE:1;
+ vuint32_t CEIE:1;
+ vuint32_t HEIE:1;
+ vuint32_t :2;
+ vuint32_t FEIE:1;
+ vuint32_t BOIE:1;
+ vuint32_t LSIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t DBFIE:1;
+ vuint32_t DBEIE:1;
+ vuint32_t DRIE:1;
+ vuint32_t DTIE:1;
+ vuint32_t HRIE:1;
+ } B;
+ } LINIER;
+
+ union { /* LINFLEX LIN Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t LINS:4;
+ vuint32_t:2;
+ vuint32_t RMB:1;
+ vuint32_t:1;
+ vuint32_t RBSY:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t DBFF:1;
+ vuint32_t DBEF:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t HRF:1;
+ } B;
+ } LINSR;
+
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t BEF:1;
+ vuint32_t CEF:1;
+ vuint32_t SFEF:1;
+ vuint32_t BDEF:1;
+ vuint32_t IDPEF:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t:6;
+ vuint32_t NF:1;
+ } B;
+ } LINESR;
+
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TDFLTFC:3;
+ vuint32_t RDFLTFC:3;
+ vuint32_t RFBM:1;
+ vuint32_t TFBM:1;
+ vuint32_t WL1:1;
+ vuint32_t PC1:1;
+ vuint32_t RXEN:1;
+ vuint32_t TXEN:1;
+ vuint32_t PC0:1;
+ vuint32_t PCE:1;
+ vuint32_t WL0:1;
+ vuint32_t UART:1;
+ } B;
+ } UARTCR;
+
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
+ vuint32_t RMB:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t :1;
+ vuint32_t TO:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t NF:1;
+ } B;
+ } UARTSR;
+
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t:5;
+ vuint32_t LTOM:1;
+ vuint32_t IOT:1;
+ vuint32_t TOCE:1;
+ vuint32_t CNT:8;
+ } B;
+ } LINTCSR;
+
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t OC2:8;
+ vuint32_t OC1:8;
+ } B;
+ } LINOCR;
+
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t RTO:4;
+ vuint32_t:1;
+ vuint32_t HTO:7;
+ } B;
+ } LINTOCR;
+
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DIV_F:4;
+ } B;
+ } LINFBRR;
+
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t DIV_M:20;
+ } B;
+ } LINIBRR;
+
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t CF:8;
+ } B;
+ } LINCFR;
+
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t IOBE:1;
+ vuint32_t IOPE:1;
+ vuint32_t WURQ:1;
+ vuint32_t DDRQ:1;
+ vuint32_t DTRQ:1;
+ vuint32_t ABRQ:1;
+ vuint32_t HTRQ:1;
+ vuint32_t:8;
+ } B;
+ } LINCR2;
+
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } BIDR;
+
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL;
+
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM;
+
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FACT:8;
+ } B;
+ } IFER;
+
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t IFMI:5;
+ } B;
+ } IFMI;
+
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t IFM:8;
+ } B;
+ } IFMR;
+
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } IFCR[16];
+
+ union { /* LINFLEX Global Counter (+0x008C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t TDFBM:1;
+ vuint32_t RDFBM:1;
+ vuint32_t TDLIS:1;
+ vuint32_t RDLIS:1;
+ vuint32_t STOP:1;
+ vuint32_t SR:1;
+ } B;
+ } GCR;
+
+ union { /* LINFLEX UART preset timeout (+0x0090) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t PTO:12;
+ } B;
+ } UARTPTO;
+
+ union { /* LINFLEX UART current timeout (+0x0094) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t CTO:12;
+ } B;
+ } UARTCTO;
+
+ union { /* LINFLEX DMA Tx Enable (+0x0098) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DTE15:1;
+ vuint32_t DTE14:1;
+ vuint32_t DTE13:1;
+ vuint32_t DTE12:1;
+ vuint32_t DTE11:1;
+ vuint32_t DTE10:1;
+ vuint32_t DTE9:1;
+ vuint32_t DTE8:1;
+ vuint32_t DTE7:1;
+ vuint32_t DTE6:1;
+ vuint32_t DTE5:1;
+ vuint32_t DTE4:1;
+ vuint32_t DTE3:1;
+ vuint32_t DTE2:1;
+ vuint32_t DTE1:1;
+ vuint32_t DTE0:1;
+ } B;
+ } DMATXE;
+
+ union { /* LINFLEX DMA RX Enable (+0x009C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DRE15:1;
+ vuint32_t DRE14:1;
+ vuint32_t DRE13:1;
+ vuint32_t DRE12:1;
+ vuint32_t DRE11:1;
+ vuint32_t DRE10:1;
+ vuint32_t DRE9:1;
+ vuint32_t DRE8:1;
+ vuint32_t DRE7:1;
+ vuint32_t DRE6:1;
+ vuint32_t DRE5:1;
+ vuint32_t DRE4:1;
+ vuint32_t DRE3:1;
+ vuint32_t DRE2:1;
+ vuint32_t DRE1:1;
+ vuint32_t DRE0:1;
+ } B;
+ } DMARXE;
+}; /* end of LINFLEXD0_tag */
+/****************************************************************************/
+/* MODULE : LINFLEXD1 Master only DMA enable */
+/****************************************************************************/
+struct LINFLEXD1_tag {
+
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CCD:1;
+ vuint32_t CFD:1;
+ vuint32_t LASE:1;
+ vuint32_t AWUM:1;
+ vuint32_t MBL:4;
+ vuint32_t BF:1;
+ vuint32_t SFTM:1;
+ vuint32_t LBKM:1;
+ vuint32_t MME:1;
+ vuint32_t SBDT:1;
+ vuint32_t RBLM:1;
+ vuint32_t SLEEP:1;
+ vuint32_t INIT:1;
+ } B;
+ } LINCR1;
+
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZIE:1;
+ vuint32_t OCIE:1;
+ vuint32_t BEIE:1;
+ vuint32_t CEIE:1;
+ vuint32_t HEIE:1;
+ vuint32_t :2;
+ vuint32_t FEIE:1;
+ vuint32_t BOIE:1;
+ vuint32_t LSIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t DBFIE:1;
+ vuint32_t DBEIE:1;
+ vuint32_t DRIE:1;
+ vuint32_t DTIE:1;
+ vuint32_t HRIE:1;
+ } B;
+ } LINIER;
+
+ union { /* LINFLEX LIN Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t LINS:4;
+ vuint32_t:2;
+ vuint32_t RMB:1;
+ vuint32_t:1;
+ vuint32_t RBSY:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t DBFF:1;
+ vuint32_t DBEF:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t HRF:1;
+ } B;
+ } LINSR;
+
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t BEF:1;
+ vuint32_t CEF:1;
+ vuint32_t SFEF:1;
+ vuint32_t BDEF:1;
+ vuint32_t IDPEF:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t:6;
+ vuint32_t NF:1;
+ } B;
+ } LINESR;
+
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TDFLTFC:3;
+ vuint32_t RDFLTFC:3;
+ vuint32_t RFBM:1;
+ vuint32_t TFBM:1;
+ vuint32_t WL1:1;
+ vuint32_t PC1:1;
+ vuint32_t RXEN:1;
+ vuint32_t TXEN:1;
+ vuint32_t PC0:1;
+ vuint32_t PCE:1;
+ vuint32_t WL0:1;
+ vuint32_t UART:1;
+ } B;
+ } UARTCR;
+
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
+ vuint32_t RMB:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t:2;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t NF:1;
+ } B;
+ } UARTSR;
+
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t:5;
+ vuint32_t LTOM:1;
+ vuint32_t IOT:1;
+ vuint32_t TOCE:1;
+ vuint32_t CNT:8;
+ } B;
+ } LINTCSR;
+
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t OC2:8;
+ vuint32_t OC1:8;
+ } B;
+ } LINOCR;
+
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t RTO:4;
+ vuint32_t:1;
+ vuint32_t HTO:7;
+ } B;
+ } LINTOCR;
+
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DIV_F:4;
+ } B;
+ } LINFBRR;
+
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t DIV_M:20;
+ } B;
+ } LINIBRR;
+
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t CF:8;
+ } B;
+ } LINCFR;
+
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t IOBE:1;
+ vuint32_t IOPE:1;
+ vuint32_t WURQ:1;
+ vuint32_t DDRQ:1;
+ vuint32_t DTRQ:1;
+ vuint32_t ABRQ:1;
+ vuint32_t HTRQ:1;
+ vuint32_t:8;
+ } B;
+ } LINCR2;
+
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } BIDR;
+
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL;
+
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM;
+
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FACT:8;
+ } B;
+ } IFER;
+
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t IFMI:5;
+ } B;
+ } IFMI;
+
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t IFM:8;
+ } B;
+ } IFMR;
+
+/* No IFCR registers on LinFlexD_1 */
+
+ union { /* LINFLEX Global Counter (+0x004C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t TDFBM:1;
+ vuint32_t RDFBM:1;
+ vuint32_t TDLIS:1;
+ vuint32_t RDLIS:1;
+ vuint32_t STOP:1;
+ vuint32_t SR:1;
+ } B;
+ } GCR;
+
+ union { /* LINFLEX UART preset timeout (+0x0050) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t PTO:12;
+ } B;
+ } UARTPTO;
+
+ union { /* LINFLEX UART current timeout (+0x0054) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t CTO:12;
+ } B;
+ } UARTCTO;
+
+ union { /* LINFLEX DMA Tx Enable (+0x0058) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DTE15:1;
+ vuint32_t DTE14:1;
+ vuint32_t DTE13:1;
+ vuint32_t DTE12:1;
+ vuint32_t DTE11:1;
+ vuint32_t DTE10:1;
+ vuint32_t DTE9:1;
+ vuint32_t DTE8:1;
+ vuint32_t DTE7:1;
+ vuint32_t DTE6:1;
+ vuint32_t DTE5:1;
+ vuint32_t DTE4:1;
+ vuint32_t DTE3:1;
+ vuint32_t DTE2:1;
+ vuint32_t DTE1:1;
+ vuint32_t DTE0:1;
+ } B;
+ } DMATXE;
+
+ union { /* LINFLEX DMA RX Enable (+0x005C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DRE15:1;
+ vuint32_t DRE14:1;
+ vuint32_t DRE13:1;
+ vuint32_t DRE12:1;
+ vuint32_t DRE11:1;
+ vuint32_t DRE10:1;
+ vuint32_t DRE9:1;
+ vuint32_t DRE8:1;
+ vuint32_t DRE7:1;
+ vuint32_t DRE6:1;
+ vuint32_t DRE5:1;
+ vuint32_t DRE4:1;
+ vuint32_t DRE3:1;
+ vuint32_t DRE2:1;
+ vuint32_t DRE1:1;
+ vuint32_t DRE0:1;
+ } B;
+ } DMARXE;
+}; /* end of LINFLEXD1_tag */
+ /****************************************************************************/
+/* MODULE : CTU Lite(base address - 0xFFE6_4000) */
+/****************************************************************************/
+struct CTU_tag{
+
+ vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */
+
+ union { /* Event Config 0..63 (Base+0x0030-0x012C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TM:1;
+ vuint32_t CLR_FLAG:1;
+ vuint32_t :5;
+ vuint32_t ADC_SEL:1;
+ vuint32_t :1;
+ vuint32_t CHANNEL_VALUE:7;
+ } B;
+ } EVTCFGR[64];
+
+
+}; /* end of CTU_tag */
+
+
+/****************************************************************************/
+/* MODULE : MPU (base address - 0xFFF1_0000) */
+/****************************************************************************/
+ struct MPU_tag {
+
+ union { /* Control/Error Status (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t SPERR:3;
+ vuint32_t:9;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NGRD:4;
+ vuint32_t :7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR;
+
+ vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */
+
+
+ union { /* Error Address Slave Port0 (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR0;
+
+ union { /* Error Detail Slave Port0 (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:8;
+ vuint32_t:8;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR0;
+
+
+ union { /* Error Address Slave Port1 (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR1;
+
+ union { /* Error Detail Slave Port1 (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:8;
+ vuint32_t:8;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR1;
+
+
+ union { /* Error Address Slave Port2 (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR2;
+
+ union { /* Error Detail Slave Port2 (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:8;
+ vuint32_t:8;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR2;
+
+ vuint8_t MPU_reserved1[984]; /* Reserved 984 Bytes (Base+0x0028-0x03FF) */
+
+ struct { /* Region Descriptor 0..15 (Base+0x0400-0x0470) */
+
+ union { /* - Word 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t :5;
+ } B;
+ } WORD0;
+
+ union { /* - Word 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t :5;
+ } B;
+ } WORD1;
+
+ union { /* - Word 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:2;
+ vuint32_t :7;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2;
+
+ union { /* - Word 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t :15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3;
+
+ }RGD[8]; /* End of Region Descriptor Structure) */
+
+ vuint8_t MPU_reserved2[896]; /* Reserved 896 Bytes (Base+0x0480-0x07FF) */
+
+ union { /* Region Descriptor Alt 0..15 (0x0800-0x081C) */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:2;
+ vuint32_t :7;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[8];
+
+ vuint8_t MPU_reserved3[14304]; /* Reserved 14304 Bytes (+0x0820-0x03FFF) */
+
+}; /* end of MPU_tag */
+
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+struct SWT_tag{
+
+ union { /* SWT Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t :14;
+ vuint32_t KEY:1;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } CR;
+
+ union { /* SWT Interrupt (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t TIF:1;
+ } B;
+ } IR;
+
+ union { /* SWT Time-Out (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO;
+
+ union { /* SWT Window (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+ } B;
+ } WN;
+
+ union { /* SWT Service (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t WSC:16;
+ } B;
+ } SR;
+
+ union { /* SWT Counter Output (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO;
+
+}; /* end of SWT_tag */
+
+/****************************************************************************/
+/* MODULE : STM */
+/****************************************************************************/
+ struct STM_CHANNEL_tag{
+
+ union { /* STM Channel Control 0..3 */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR;
+
+ union { /* STM Channel Interrupt 0..3 */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR;
+
+ union { /* STM Channel Compare 0..3 */
+ vuint32_t R;
+ struct {
+ vuint32_t CMP:32;
+ } B;
+ } CMP;
+
+ vuint8_t STM_CHANNEL_reserved0[4]; /* Reserved 4 bytes between ch reg's */
+
+ }; /* end of STM_CHANNEL_tag */
+
+
+struct STM_tag{
+
+ union { /* STM Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CPS:8;
+ vuint32_t :6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR;
+
+ union { /* STM Count (Base+0x0004) */
+ vuint32_t R;
+ } CNT;
+
+ vuint8_t STM_reserved1[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
+
+ struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */
+
+}; /* end of STM_tag */
+
+/****************************************************************************/
+/* MODULE : ECSM */
+/****************************************************************************/
+struct ECSM_tag{
+
+ union { /* ECSM Processor Core Type (Base+0x0000) */
+ vuint16_t R;
+ } PCT;
+
+ union { /* ECSM Revision (Base+0x0002) */
+ vuint16_t R;
+ } REV;
+
+ vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* ECSM IPS Module Configuration (Base+0x0008) */
+ vuint32_t R;
+ } IMC;
+
+ vuint8_t ECSM_reserved1[7]; /* Reserved 7 bytes (Base+0x000C-0x0012) */
+
+ union { /* ECSM Miscellaneous Wakeup Control (+0x0013) */
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1;
+ vuint8_t :3;
+ vuint8_t PRILVL:4;
+ } B;
+ } MWCR;
+
+ vuint8_t ECSM_reserved2[11]; /* Reserved 11 bytes (Base+0x0014-0x001E) */
+
+ union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1;
+ vuint8_t FB0SI:1;
+ vuint8_t FB1AI:1;
+ vuint8_t FB1SI:1;
+ vuint8_t :4;
+ } B;
+ } MIR;
+
+ vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
+
+ union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/
+ vuint32_t R;
+ } MUDCR; /* ECSM Miscellaneous User-Defined Control Register */
+
+ vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */
+
+ union { /* ECSM ECC Configuration (Base+0x0043) */
+ vuint8_t R;
+ struct {
+ vuint8_t :2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t :2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR;
+
+ vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */
+
+ union { /* ECSM ECC Status (Base+0x0047) */
+ vuint8_t R;
+ struct {
+ vuint8_t :2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t :2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR;
+
+ vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */
+
+ union { /* ECSM ECC Error Generation (Base+0x004A) */
+ vuint16_t R;
+ struct {
+ vuint16_t :2;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t :2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t :1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR;
+
+ vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */
+
+ union { /* ECSM Flash ECC Address(Base+0x0050) */
+ vuint32_t R;
+ } FEAR;
+
+ vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */
+
+ union { /* ECSM Flash ECC Master Number (Base+0x0056) */
+ vuint8_t R;
+ struct {
+ vuint8_t :4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR;
+
+ union { /* ECSM Flash ECC Attributes (Base+0x0057) */
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } FEAT;
+
+ vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */
+
+ union { /* ECSM Flash ECC Data (Base+0x005C) */
+ vuint32_t R;
+ } FEDR;
+
+ union { /* ECSM RAM ECC Address (Base+0x0060) */
+ vuint32_t R;
+ } REAR;
+
+ vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */
+
+ union { /* ECSM RAM ECC Address (Base+0x0065) */
+ vuint8_t R;
+ } RESR;
+
+ union { /* ECSM RAM ECC Master Number (Base+0x0066) */
+ vuint8_t R;
+ struct {
+ vuint8_t :4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR;
+
+ union { /* ECSM RAM ECC Attributes (Base+0x0067) */
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } REAT;
+
+ vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */
+
+ union { /* ECSM RAM ECC Data (Base+0x006C) */
+ vuint32_t R;
+ } REDR;
+
+}; /* end of ECSM_tag */
+
+/****************************************************************************/
+/* MODULE : eDMA (base address - 0xFFF4_4000) */
+/****************************************************************************/
+
+ /* There are 4 different TCD structures which should be used based on */
+ /* how the DMA is configured as below. CAUTION - Do not mix TCD's */
+ /* */
+ /* Channel Linking Minor Loop Mapping Addressing TCD */
+ /* OFF OFF XBAR.TCD[x] */
+ /* OFF ON XBAR.ML_TCD[x] */
+ /* ON OFF XBAR.CL_TCD[X] */
+ /* ON ON XBAR.MLCL_TCD[X] */
+ /* */
+
+ /*for "standard" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=0) */
+ /* (1) - Standard TCD (Channel Linking OFF, Minor Loop mapping OFF */
+ struct EDMA_TCD_STD_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t NBYTES; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITER:15; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITER:15; /* Starting major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* End of Standard TCD tag */
+
+
+ /* (2) - ML_TCD (Channel Linking OFF, Minor Loop mapping Enabled */
+ /* (EMLM = 1) */
+ struct EDMA_TCD_MLMIRROR_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t SMLOE:1; /* Source minor loop offset enabled */
+ vuint32_t DMLOE:1; /* Destination minor loop offset enable */
+ vuint32_t MLOFF:20; /* Minor loop offset */
+ vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITER:15; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITER:15; /* Starting major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* End of EDMA_TCD_MLMIRROR_tag */
+
+ /*for "channel link" format TCD (when EDMA.TCD[x].CITERE_LINK==BITERE_LINK=1)*/
+ /* (3) - CL_TCD (Channel Linking Enabled, Minor Loop mapping OFF */
+ /* (CITERE_LINK = BITERE_LINK = 1) */
+ struct EDMA_TCD_CHLINK_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t NBYTES; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITERLINKCH:6; /* Link channel number */
+ vuint16_t CITER:9; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITERLINKCH:6; /* Link channel number */
+ vuint16_t BITER:9; /* Starting Major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* end of EDMA_TCD_CHLINK_tag */
+
+ /* (4) - CL_TCD (Channel Linking Enabled, Minor Loop mapping Enabled */
+ /* (CITERE_LINK = BITERE_LINK = 1, EMLM = 1) */
+ struct EDMA_TCD_MLMIRROR_CHLINK_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t SMLOE:1; /* Source minor loop offset enabled */
+ vuint32_t DMLOE:1; /* Destination minor loop offset enable */
+ vuint32_t MLOFF:20; /* Minor loop offset */
+ vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITERLINKCH:6; /* Link channel number */
+ vuint16_t CITER:9; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITERLINKCH:6; /* Link channel number */
+ vuint16_t BITER:9; /* Starting Major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* end of EDMA_TCD_MLMIRROR_CHLINK_tag */
+
+struct EDMA_tag {
+
+ union { /* Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :14;
+ vuint32_t CX:1;
+ vuint32_t ECX:1;
+ vuint32_t :6;
+ vuint32_t GRP0PRI:2;
+ vuint32_t EMLM:1;
+ vuint32_t CLM:1;
+ vuint32_t HALT:1;
+ vuint32_t HOE:1;
+ vuint32_t ERGA:1;
+ vuint32_t ERCA:1;
+ vuint32_t EDBG:1;
+ vuint32_t EBW:1;
+ } B;
+ } CR;
+
+ union { /* Error Status (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1;
+ vuint32_t :16;
+ vuint32_t CPE:1;
+ vuint32_t ERRCHN:6;
+ vuint32_t SAE:1;
+ vuint32_t SOE:1;
+ vuint32_t DAE:1;
+ vuint32_t DOE:1;
+ vuint32_t NCE:1;
+ vuint32_t SGE:1;
+ vuint32_t SBE:1;
+ vuint32_t DBE:1;
+ } B;
+ } ESR;
+
+ vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B)*/
+
+ union { /* Enable Request Low Ch15..0 (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t ERQ15:1;
+ vuint32_t ERQ14:1;
+ vuint32_t ERQ13:1;
+ vuint32_t ERQ12:1;
+ vuint32_t ERQ11:1;
+ vuint32_t ERQ10:1;
+ vuint32_t ERQ09:1;
+ vuint32_t ERQ08:1;
+ vuint32_t ERQ07:1;
+ vuint32_t ERQ06:1;
+ vuint32_t ERQ05:1;
+ vuint32_t ERQ04:1;
+ vuint32_t ERQ03:1;
+ vuint32_t ERQ02:1;
+ vuint32_t ERQ01:1;
+ vuint32_t ERQ00:1;
+ } B;
+ } ERQRL;
+
+ vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013)*/
+
+ union { /* Enable Error Interrupt Low (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t EEI15:1;
+ vuint32_t EEI14:1;
+ vuint32_t EEI13:1;
+ vuint32_t EEI12:1;
+ vuint32_t EEI11:1;
+ vuint32_t EEI10:1;
+ vuint32_t EEI09:1;
+ vuint32_t EEI08:1;
+ vuint32_t EEI07:1;
+ vuint32_t EEI06:1;
+ vuint32_t EEI05:1;
+ vuint32_t EEI04:1;
+ vuint32_t EEI03:1;
+ vuint32_t EEI02:1;
+ vuint32_t EEI01:1;
+ vuint32_t EEI00:1;
+ } B;
+ } EEIRL;
+
+ union { /* DMA Set Enable Request (Base+0x0018) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t SERQ:7;
+ } B;
+ } SERQR;
+
+ union { /* DMA Clear Enable Request (Base+0x0019) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t CERQ:7;
+ } B;
+ } CERQR;
+
+ union { /* DMA Set Enable Error Interrupt (Base+0x001A) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t SEEI:7;
+ } B;
+ } SEEIR;
+
+ union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CEEI:7;
+ } B;
+ } CEEIR;
+
+ union { /* DMA Clear Interrupt Request (Base+0x001C) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t CINT:7;
+ } B;
+ } CIRQR;
+
+ union { /* DMA Clear error (Base+0x001D) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t CERR:7;
+ } B;
+ } CER;
+
+ union { /* DMA Set Start Bit (Base+0x001E) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t SSB:7;
+ } B;
+ } SSBR;
+
+ union { /* DMA Clear Done Status Bit (Base+0x001F) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t CDSB:7;
+ } B;
+ } CDSBR;
+
+ vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023)*/
+
+ union { /* DMA Interrupt Req Low Ch15..0 (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t INT15:1;
+ vuint32_t INT14:1;
+ vuint32_t INT13:1;
+ vuint32_t INT12:1;
+ vuint32_t INT11:1;
+ vuint32_t INT10:1;
+ vuint32_t INT09:1;
+ vuint32_t INT08:1;
+ vuint32_t INT07:1;
+ vuint32_t INT06:1;
+ vuint32_t INT05:1;
+ vuint32_t INT04:1;
+ vuint32_t INT03:1;
+ vuint32_t INT02:1;
+ vuint32_t INT01:1;
+ vuint32_t INT00:1;
+ } B;
+ } IRQRL;
+
+ vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B)*/
+
+ union { /* DMA Error Low Ch15..0 (Base+0x002C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t ERR15:1;
+ vuint32_t ERR14:1;
+ vuint32_t ERR13:1;
+ vuint32_t ERR12:1;
+ vuint32_t ERR11:1;
+ vuint32_t ERR10:1;
+ vuint32_t ERR09:1;
+ vuint32_t ERR08:1;
+ vuint32_t ERR07:1;
+ vuint32_t ERR06:1;
+ vuint32_t ERR05:1;
+ vuint32_t ERR04:1;
+ vuint32_t ERR03:1;
+ vuint32_t ERR02:1;
+ vuint32_t ERR01:1;
+ vuint32_t ERR00:1;
+ } B;
+ } ERL;
+
+ vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033)*/
+
+ union { /* DMA Hardware Request Stat Low (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t HRS15:1;
+ vuint32_t HRS14:1;
+ vuint32_t HRS13:1;
+ vuint32_t HRS12:1;
+ vuint32_t HRS11:1;
+ vuint32_t HRS10:1;
+ vuint32_t HRS09:1;
+ vuint32_t HRS08:1;
+ vuint32_t HRS07:1;
+ vuint32_t HRS06:1;
+ vuint32_t HRS05:1;
+ vuint32_t HRS04:1;
+ vuint32_t HRS03:1;
+ vuint32_t HRS02:1;
+ vuint32_t HRS01:1;
+ vuint32_t HRS00:1;
+ } B;
+ } HRSL;
+
+ vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/
+
+ union { /* Channel n Priority (Base+0x0100-0x010F)*/
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[16];
+
+ vuint8_t eDMA_reserved6[3824]; /* Reserved 3808 bytes (+0x0110-0x0FFF) */
+
+
+union { /* 4 different TCD definitions depending on operating mode */
+
+ /* Default TCD (Channel Linking and Minor Loop Maping disabled) */
+ struct EDMA_TCD_STD_tag TCD[16];
+
+ /* ML_TCD (Channel Linking disabled, Minor Loop Mapping enabled) */
+ struct EDMA_TCD_MLMIRROR_tag ML_TCD[16];
+
+ /* CL_TCD (Channel Linking enabled, Minor Loop Mapping disabled) */
+ struct EDMA_TCD_CHLINK_tag CL_TCD[16];
+
+ /* MLCL_TCD (Channel Linking enabled, Minor Loop Mapping enabled) */
+ struct EDMA_TCD_MLMIRROR_CHLINK_tag MLCL_TCD[16];
+ };
+
+
+ vuint8_t eDMA_reserved7[28160]; /* Reserved 28160 bytes (+0x1200-0x7FFF) */
+
+}; /* end of EDMA_tag */
+/*************************************************************************/
+/* MODULE : INTC (base address - 0xFFF4_8000) */
+/*************************************************************************/
+struct INTC_tag {
+
+ union { /* INTC Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t VTES:1;
+ vuint32_t:4;
+ vuint32_t HVEN:1;
+ } B;
+ } MCR;
+
+ vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* INTC Current Priority (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR;
+
+ vuint8_t INTC_reserved1[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
+
+ union { /* INTC Interrupt Acknowledge (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA_PRC0:21;
+ vuint32_t INTVEC_PRC0:9;
+ vuint32_t:2;
+ } B;
+ } IACKR;
+
+ vuint8_t INTC_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */
+
+ union { /* INTC End Of Interrupt (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } EOIR;
+
+ vuint8_t INTC_reserved3[4]; /* reserved 4 bytes (Base+0x001C-0x0019) */
+
+ union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1;
+ vuint8_t CLR:1;
+ } B;
+ } SSCIR[8];
+
+ vuint8_t INTC_reserved4[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */
+
+ union { /* INTC Priority Select (Base+0x0040-0x0128) */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PRI:4;
+ } B;
+ } PSR[234];
+
+}; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : DSPI */
+/* Base Addresses: */
+/* DSPI_0 - 0xFFF9_0000 */
+/* DSPI_1 - 0xFFF9_4000 */
+/* DSPI_2 - 0xFFF9_8000 */
+/* DSPI_3 - 0xFFF9_C000 */
+/* DSPI_4 - 0xFFFA_0000 */
+/* DSPI_5 - 0xFFFA_4000 */
+/****************************************************************************/
+struct DSPI_tag{
+
+ union { /* DSPI Module Configuraiton (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t :2;
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t :1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t :7;
+ vuint32_t HALT:1;
+ } B;
+ } MCR;
+
+ vuint8_t DSPI_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* DSPI Transfer Count (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t :16;
+ } B;
+ } TCR;
+
+ union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[6];
+
+ vuint8_t DSPI_reserved1[8]; /* Reserved 4 bytes (Base+0x0024-0x002B) */
+
+ union { /* DSPI Status (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t :1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t :1;
+ vuint32_t TFFF:1;
+ vuint32_t :5;
+ vuint32_t RFOF:1;
+ vuint32_t :1;
+ vuint32_t RFDF:1;
+ vuint32_t :1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR;
+
+ union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t :2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t :1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t :4;
+ vuint32_t RFOFRE:1;
+ vuint32_t :1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t :16;
+ } B;
+ } RSER;
+
+ union { /* DSPI Push TX FIFO (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t :4;
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR;
+
+ union { /* DSPI Pop RX FIFO (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR;
+
+ union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4];
+
+ vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */
+
+ union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[4];
+ }; /* end of DSPI_tag */
+ /****************************************************************************/
+/* MODULE : FlexCAN */
+/* Base Addresses: */
+/* FlexCAN_0 - 0xFFFC_0000 */
+/****************************************************************************/
+struct FLEXCAN_BUF_t{
+
+ union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t CODE:4;
+ vuint32_t :1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union { /* FLEXCAN MBx Identifier (Offset+0x0084) */
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } DATA;
+
+}; /* end of FLEXCAN_BUF_t */
+
+
+struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */
+
+ union { /* RxFIFO Control & Status (Offset+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union { /* RxFIFO Identifier (Offset+0x0084) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union { /* RxFIFO Data 0..7 (Offset+0x0088) */
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } DATA;
+
+ vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/
+
+ union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */
+ vuint32_t R;
+ } IDTABLE[8];
+
+}; /* end of FLEXCAN_RXFIFO_t */
+
+
+struct FLEXCAN_tag{
+
+ union { /* FLEXCAN Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t :1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t :1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR;
+
+ union { /* FLEXCAN Control (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t :2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR;
+
+ union { /* FLEXCAN Free Running Timer (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TIMER:16;
+ } B;
+ } TIMER;
+
+ vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
+
+ union { /* FLEXCAN RX Global Mask (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK;
+
+ /* --- Following 2 registers are included for legacy purposes only --- */
+
+ union { /* FLEXCAN RX 14 Mask (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK;
+
+ union { /* FLEXCAN RX 15 Mask (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK;
+
+ /* --- */
+
+ union { /* FLEXCAN Error Counter (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR;
+
+ union { /* FLEXCAN Error & Status (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t :1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t :1;
+ } B;
+ } ESR;
+
+ union { /* FLEXCAN Interruput Masks H (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH;
+
+ union { /* FLEXCAN Interruput Masks L (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL;
+
+ union { /* FLEXCAN Interruput Flag H (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH;
+
+ union { /* FLEXCAN Interruput Flag l (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interruput Flag Register */
+
+ vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/
+
+ union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64];
+
+}; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : DMAMUX (base address - 0xFFFD_C000) */
+/****************************************************************************/
+ struct DMAMUX_tag {
+ union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[16];
+
+ }; /* end of DMAMUX_tag */
+
+/******************************************************************
+| defines and macros (scope: module-local)
+|-----------------------------------------------------------------*/
+/* Define instances of modules */
+
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
+#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
+#define LINFLEX_0 (*(volatile struct LINFLEXD0_tag *) 0xFFE40000UL)
+#define LINFLEX_1 (*(volatile struct LINFLEXD1_tag *) 0xFFE44000UL)
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
+#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
+
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+/* End of file */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC560Pxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..3643678bd --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/cfg/mcuconf.h.ftl @@ -0,0 +1,452 @@ +[#ftl]
+
+<#--
+ -- Decodes a ME_xxx_MC register description node.
+ -->
+[#function decode_mc node]
+ [#assign s = "" /]
+ [#if node.pdo.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_MC_PDO" /]
+ [/#if]
+ [#if node.mvron.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_MC_MVRON" /]
+ [/#if]
+ [#assign n = node.dflaon.@index[0]?trim?number /]
+ [#if n == 0]
+ [#assign s = s + " | SPC5_ME_MC_DFLAON_NORMAL" /]
+ [#elseif n == 1]
+ [#assign s = s + " | SPC5_ME_MC_DFLAON_LP" /]
+ [#else]
+ [#assign s = s + " | SPC5_ME_MC_DFLAON_PD" /]
+ [/#if]
+ [#assign n = node.cflaon.@index[0]?trim?number /]
+ [#if n == 0]
+ [#assign s = s + " | SPC5_ME_MC_CFLAON_NORMAL" /]
+ [#elseif n == 1]
+ [#assign s = s + " | SPC5_ME_MC_CFLAON_LP" /]
+ [#else]
+ [#assign s = s + " | SPC5_ME_MC_CFLAON_PD" /]
+ [/#if]
+ [#if node.pll1on.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_MC_PLL1ON" /]
+ [/#if]
+ [#if node.pll0on.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_MC_PLL0ON" /]
+ [/#if]
+ [#if node.xosc0on.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_MC_XOSC0ON" /]
+ [/#if]
+ [#if node.ircon.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_MC_IRCON" /]
+ [/#if]
+ [#assign n = node.sysclk.@index[0]?trim?number /]
+ [#if n == 0]
+ [#assign s = s + " | SPC5_ME_MC_SYSCLK_IRC" /]
+ [#elseif n == 1]
+ [#assign s = s + " | SPC5_ME_MC_SYSCLK_XOSC" /]
+ [#elseif n == 2]
+ [#assign s = s + " | SPC5_ME_MC_SYSCLK_FMPLL0" /]
+ [#elseif n == 3]
+ [#assign s = s + " | SPC5_ME_MC_SYSCLK_FMPLL1" /]
+ [#else]
+ [#assign s = s + " | SPC5_ME_MC_SYSCLK_DISABLED" /]
+ [/#if]
+ [#return s]
+[/#function]
+
+<#--
+ -- Decodes a ME_RUN_PCx register description node.
+ -->
+[#function decode_runpc node]
+ [#assign s = "" /]
+ [#if node.safe.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_RUN_PC_SAFE" /]
+ [/#if]
+ [#if node.drun.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_RUN_PC_DRUN" /]
+ [/#if]
+ [#if node.run0.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_RUN_PC_RUN0" /]
+ [/#if]
+ [#if node.run1.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_RUN_PC_RUN1" /]
+ [/#if]
+ [#if node.run2.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_RUN_PC_RUN2" /]
+ [/#if]
+ [#if node.run3.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_RUN_PC_RUN3" /]
+ [/#if]
+ [#return s]
+[/#function]
+
+<#--
+ -- Decodes a ME_LP_PCx register description node.
+ -->
+[#function decode_lppc node]
+ [#assign s = "" /]
+ [#if node.halt0.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_LP_PC_HALT0" /]
+ [/#if]
+ [#if node.stop0.value[0]?lower_case == "true"]
+ [#assign s = s + " | SPC5_ME_LP_PC_STOP0" /]
+ [/#if]
+ [#return s]
+[/#function]
+
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC560Pxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC560Pxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+[#assign options = "" /]
+[#if conf.instance.initialization_settings.fmpll0_settings.progressive_clock_switching.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_FMPLL_EN_PLL_SW" /]
+[/#if]
+[#if conf.instance.initialization_settings.fmpll0_settings.mask_fail_output.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_FMPLL_PLL_FAIL_MASK" /]
+[/#if]
+#define SPC5_FMPLL0_OPTIONS (0${options})
+[#assign options = "" /]
+[#if conf.instance.initialization_settings.fmpll0_settings.fm_enable.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_FMPLL_FM_EN" /]
+ [#if conf.instance.initialization_settings.fmpll0_settings.spread_type.@index[0]?trim?number != 0]
+ [#assign options = options + " | SPC5_FMPLL_SPRD_SEL" /]
+ [/#if]
+ [#assign options = options + " | SPC5_FMPLL_MOD_PERIOD(" + conf.instance.initialization_settings.fmpll0_settings.modulation_period.value[0]?trim + ")" /]
+ [#assign options = options + " | SPC5_FMPLL_INC_STEP(" + conf.instance.initialization_settings.fmpll0_settings.increment_step.value[0]?trim + ")" /]
+[/#if]
+#define SPC5_FMPLL0_MR_INIT (0${options})
+#define SPC5_FMPLL1_IDF_VALUE ${conf.instance.initialization_settings.fmpll1_settings.idf_value.value[0]}
+#define SPC5_FMPLL1_NDIV_VALUE ${conf.instance.initialization_settings.fmpll1_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL1_ODF ${conf.instance.initialization_settings.fmpll1_settings.odf_value.value[0]}
+[#assign options = "" /]
+[#if conf.instance.initialization_settings.fmpll1_settings.progressive_clock_switching.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_FMPLL_EN_PLL_SW" /]
+[/#if]
+[#if conf.instance.initialization_settings.fmpll1_settings.mask_fail_output[0].value?lower_case == "true"]
+ [#assign options = options + " | SPC5_FMPLL_PLL_FAIL_MASK" /]
+[/#if]
+#define SPC5_FMPLL1_OPTIONS (0${options})
+[#assign options = "" /]
+[#if conf.instance.initialization_settings.fmpll1_settings.fm_enable.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_FMPLL_FM_EN" /]
+ [#if conf.instance.initialization_settings.fmpll1_settings.spread_type.@index[0]?trim?number != 0]
+ [#assign options = options + " | SPC5_FMPLL_SPRD_SEL" /]
+ [/#if]
+ [#assign options = options + " | SPC5_FMPLL_MOD_PERIOD(" + conf.instance.initialization_settings.fmpll1_settings.modulation_period.value[0]?trim + ")" /]
+ [#assign options = options + " | SPC5_FMPLL_INC_STEP(" + conf.instance.initialization_settings.fmpll1_settings.increment_step.value[0]?trim + ")" /]
+[/#if]
+#define SPC5_FMPLL1_MR_INIT (0${options})
+#define SPC5_CLKOUT_SRC SPC5_CGM_OCDS_SELCTL_${conf.instance.initialization_settings.clocks.clkout_clock_source.value[0]}
+#define SPC5_CLKOUT_DIV_VALUE ${conf.instance.initialization_settings.clocks.clkout_clock_divider.value[0]}
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux0_clock_source.value[0]}
+#define SPC5_MCONTROL_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.motor_control_clock_divider.value[0]}
+#define SPC5_FMPLL1_CLK_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.fmpll1_div_clock_divider.value[0]}
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux2_clock_source.value[0]}
+#define SPC5_SP_CLK_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.sp_clock_divider.value[0]}
+#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux3_clock_source.value[0]}
+#define SPC5_FR_CLK_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.fr_clock_divider.value[0]}
+[#assign options = "SPC5_CMU_CSR_RCDIV(" + conf.instance.initialization_settings.cmu0_settings.rcdiv.@index[0]?trim + ")" /]
+[#if conf.instance.initialization_settings.cmu0_settings.cme0.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_CMU_CSR_CME" /]
+[/#if]
+#define SPC5_CMU0_CSR_INIT (${options})
+#define SPC5_CMU0_HFREFR_INIT ${conf.instance.initialization_settings.cmu0_settings.hfref.value[0]?trim}
+#define SPC5_CMU0_LFREFR_INIT ${conf.instance.initialization_settings.cmu0_settings.lfref.value[0]?trim}
+#define SPC5_CMU0_MDR_INIT ${conf.instance.initialization_settings.cmu0_settings.md.value[0]?trim}
+[#assign options = "" /]
+[#if conf.instance.initialization_settings.cmu1_settings.cme1.value[0]?lower_case == "true"]
+ [#assign options = options + "SPC5_CMU_CSR_CME" /]
+[#else]
+ [#assign options = "0" /]
+[/#if]
+#define SPC5_CMU1_CSR_INIT (${options})
+#define SPC5_CMU1_HFREFR_INIT ${conf.instance.initialization_settings.cmu1_settings.hfref.value[0]?trim}
+#define SPC5_CMU1_LFREFR_INIT ${conf.instance.initialization_settings.cmu1_settings.lfref.value[0]?trim}
+[#assign options = "" /]
+[#if conf.instance.initialization_settings.module_entry.run_modes.reset.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_RESET" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.safe.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_SAFE" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.drun.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_DRUN" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.run0.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_RUN0" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.run1.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_RUN1" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.run2.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_RUN2" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.run3.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_RUN3" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.halt0.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_HALT0" /]
+[/#if]
+[#if conf.instance.initialization_settings.module_entry.run_modes.stop0.value[0]?lower_case == "true"]
+ [#assign options = options + " | SPC5_ME_ME_STOP0" /]
+[/#if]
+#define SPC5_ME_ME_BITS (0${options})
+#define SPC5_ME_SAFE_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.safe_state_settings)})
+#define SPC5_ME_DRUN_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.drun_state_settings)})
+#define SPC5_ME_RUN0_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run0_state_settings)})
+#define SPC5_ME_RUN1_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run1_state_settings)})
+#define SPC5_ME_RUN2_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run2_state_settings)})
+#define SPC5_ME_RUN3_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run3_state_settings)})
+#define SPC5_ME_HALT0_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.halt0_state_settings)})
+#define SPC5_ME_STOP0_MC_BITS (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.stop0_state_settings)})
+#define SPC5_ME_RUN_PC3_BITS (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc3)})
+#define SPC5_ME_RUN_PC4_BITS (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc4)})
+#define SPC5_ME_RUN_PC5_BITS (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc5)})
+#define SPC5_ME_RUN_PC6_BITS (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc6)})
+#define SPC5_ME_RUN_PC7_BITS (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc7)})
+#define SPC5_ME_LP_PC4_BITS (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc4)})
+#define SPC5_ME_LP_PC5_BITS (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc5)})
+#define SPC5_ME_LP_PC6_BITS (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc6)})
+#define SPC5_ME_LP_PC7_BITS (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc7)})
+#define SPC5_FINAL_RUNMODE SPC5_RUNMODE_${conf.instance.initialization_settings.module_entry.final_run_mode.value[0]?trim}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * PWM driver system settings.
+ */
+[#assign pwm0_all_sm = conf.instance.flexpwm_settings.synchronized_flexpwm0.value[0]?upper_case /]
+#define SPC5_PWM0_USE_SYNC_SMOD ${pwm0_all_sm}
+#define SPC5_PWM1_USE_SYNC_SMOD FALSE
+#define SPC5_PWM_USE_SMOD0 ${conf.instance.flexpwm_settings.flexpwm0_sm0.value[0]?upper_case}
+[#if pwm0_all_sm == "FALSE"]
+#define SPC5_PWM_USE_SMOD1 ${conf.instance.flexpwm_settings.flexpwm0_sm1.value[0]?upper_case}
+#define SPC5_PWM_USE_SMOD2 ${conf.instance.flexpwm_settings.flexpwm0_sm2.value[0]?upper_case}
+#define SPC5_PWM_USE_SMOD3 ${conf.instance.flexpwm_settings.flexpwm0_sm3.value[0]?upper_case}
+[#else]
+#define SPC5_PWM_USE_SMOD1 TRUE
+#define SPC5_PWM_USE_SMOD2 TRUE
+#define SPC5_PWM_USE_SMOD3 TRUE
+[/#if]
+#define SPC5_PWM_SMOD0_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm0.value[0]}
+#define SPC5_PWM_SMOD1_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm1.value[0]}
+#define SPC5_PWM_SMOD2_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm2.value[0]}
+#define SPC5_PWM_SMOD3_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm3.value[0]}
+
+/*
+ * ICU driver system settings.
+ */
+#define SPC5_ICU_USE_SMOD0 ${conf.instance.etimer_settings.etimer0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD1 ${conf.instance.etimer_settings.etimer0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD2 ${conf.instance.etimer_settings.etimer0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD3 ${conf.instance.etimer_settings.etimer0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD4 ${conf.instance.etimer_settings.etimer0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD5 ${conf.instance.etimer_settings.etimer0_ch5.value[0]?upper_case}
+#define SPC5_ICU_ETIMER0_PRIORITY ${conf.instance.irq_priority_settings.etimer0.value[0]}
+
+#define SPC5_ICU_USE_SMOD6 ${conf.instance.etimer_settings.etimer1_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD7 ${conf.instance.etimer_settings.etimer1_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD8 ${conf.instance.etimer_settings.etimer1_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD9 ${conf.instance.etimer_settings.etimer1_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD10 ${conf.instance.etimer_settings.etimer1_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD11 ${conf.instance.etimer_settings.etimer1_ch5.value[0]?upper_case}
+#define SPC5_ICU_ETIMER1_PRIORITY ${conf.instance.irq_priority_settings.etimer1.value[0]}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI3 ${conf.instance.dspi_settings.dspi_3.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI4 ${conf.instance.dspi_settings.dspi_4.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+[#assign s6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs6[0].@index[0]?trim?number] /]
+[#assign s7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs7[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5 + s6 + s7})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs5[0].@index[0]?trim?number] /]
+[#assign s6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs6[0].@index[0]?trim?number] /]
+[#assign s7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs7[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4 + s5 + s6 + s7})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI3_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI4_MCR (0${s0 + s1 + s2 + s3})
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx1.value[0]}
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx2.value[0]}
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_rx.value[0]}
+#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx1.value[0]}
+#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx2.value[0]}
+#define SPC5_SPI_DSPI4_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_rx.value[0]}
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+
+#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
+#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
+#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
+#define SPC5_ADC_ADC0_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
+#define SPC5_ADC_ADC0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
+#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
+#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
+#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
+#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/hal_lld.c b/os/hal/ports/SPC5/SPC560Pxx/hal_lld.c new file mode 100644 index 000000000..fb5c51c8f --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/hal_lld.c @@ -0,0 +1,314 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/hal_lld.c
+ * @brief SPC560Pxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief PIT channel 0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(vector59) {
+
+ OSAL_IRQ_PROLOGUE();
+
+ osalSysLockFromISR();
+ osalOsTimerHandlerI();
+ osalSysUnlockFromISR();
+
+ /* Resets the PIT channel 0 IRQ flag.*/
+ PIT.CH[0].TFLG.R = 1;
+
+ OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t reg;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_FINAL_RUNMODE) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
+ to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
+ modes.*/
+ INTC.PSR[59].R = SPC5_PIT0_IRQ_PRIORITY;
+ halSPCSetPeripheralClockMode(92,
+ SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+ reg = halSPCGetSystemClock() / OSAL_ST_FREQUENCY - 1;
+ PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */
+ PIT.CH[0].LDVAL.R = reg;
+ PIT.CH[0].CVAL.R = reg;
+ PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */
+ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC560Pxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.S_RC)
+ ;
+
+#if !SPC5_NO_INIT
+
+ /* CMUs initialization.*/
+ CGM.CMU_0_HFREFR_A.R = SPC5_CMU0_HFREFR_INIT;
+ CGM.CMU_0_LFREFR_A.R = SPC5_CMU0_LFREFR_INIT;
+ CGM.CMU_0_MDR.R = SPC5_CMU0_MDR_INIT;
+ CGM.CMU_0_CSR.R = SPC5_CMU0_CSR_INIT;
+#if SPC5_HAS_CMU1
+ CGM.CMU_1_HFREFR_A.R = SPC5_CMU1_HFREFR_INIT;
+ CGM.CMU_1_LFREFR_A.R = SPC5_CMU1_LFREFR_INIT;
+ CGM.CMU_1_CSR.R = SPC5_CMU1_CSR_INIT;
+#endif
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.OSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+#if SPC5_HAS_AC0
+ CGM.AC0DC.R = SPC5_CGM_AC0_DC0;
+ CGM.AC0SC.R = SPC5_AUX0CLK_SRC;
+#endif
+#if SPC5_HAS_AC1
+ CGM.AC1DC.R = SPC5_CGM_AC1_DC0;
+ CGM.AC1SC.R = SPC5_AUX1CLK_SRC;
+#endif
+#if SPC5_HAS_AC2
+ CGM.AC2DC.R = SPC5_CGM_AC2_DC0;
+ CGM.AC2SC.R = SPC5_AUX2CLK_SRC;
+#endif
+#if SPC5_HAS_AC3
+ CGM.AC3DC.R = SPC5_CGM_AC3_DC0;
+ CGM.AC3SC.R = SPC5_AUX3CLK_SRC;
+#endif
+
+ /* Enables the XOSC in order to check its functionality before proceeding
+ with the initialization.*/
+ ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | SPC5_ME_MC_MVRON;
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
+ SPC5_FMPLL_IDF(SPC5_FMPLL0_IDF_VALUE) |
+ SPC5_FMPLL_NDIV(SPC5_FMPLL0_NDIV_VALUE) |
+ SPC5_FMPLL0_OPTIONS;
+ CGM.FMPLL[0].MR.R = SPC5_FMPLL0_MR_INIT;
+#if SPC5_HAS_FMPLL1
+ CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
+ SPC5_FMPLL_IDF(SPC5_FMPLL1_IDF_VALUE) |
+ SPC5_FMPLL_NDIV(SPC5_FMPLL1_NDIV_VALUE) |
+ SPC5_FMPLL1_OPTIONS;
+ CGM.FMPLL[1].MR.R = SPC5_FMPLL1_MR_INIT;
+#endif
+
+ /* Run modes initialization.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ if (ME.IS.B.I_CONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings calculated for a maximum clock of 64MHz.*/
+ CFLASH.PFCR0.B.BK0_APC = 2;
+ CFLASH.PFCR0.B.BK0_RWSC = 2;
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Clock Out selection after all the other configurations.*/
+ CGM.OCDSSC.R = SPC5_CLKOUT_SRC | SPC5_CGM_OCDS_SELDIV;
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.S_SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+#if SPC5_HAS_FMPLL1
+ case SPC5_ME_GS_SYSCLK_FMPLL1:
+ return SPC5_FMPLL1_CLK;
+#endif
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/hal_lld.h b/os/hal/ports/SPC5/SPC560Pxx/hal_lld.h new file mode 100644 index 000000000..867a89a85 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/hal_lld.h @@ -0,0 +1,1179 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/hal_lld.h
+ * @brief SPC560Pxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#if defined(_SPC560PXX_LARGE_) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "SPC56APxx Chassis and Safety"
+#else
+#define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
+#endif
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 40000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 16000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 64000000
+
+/**
+ * @brief Maximum FMPLL1 output clock frequency.
+ * @note FMPLL1 is not present on all devices.
+ */
+#define SPC5_FMPLL1_CLK_MAX 120000000
+
+/**
+ * @brief Maximum FMPLL1 D1 output clock frequency.
+ * @note FMPLL1 is not present on all devices.
+ */
+#define SPC5_FMPLL1_D1_CLK_MAX 80000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/
+/** @} */
+
+/**
+ * @name FMPLL registers bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_IDF_MASK (15U << 26)
+#define SPC5_FMPLL_IDF(n) (((n) - 1) << 26)
+#define SPC5_FMPLL_ODF_MASK (3U << 24)
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+#define SPC5_FMPLL_NDIV_MASK (127U << 16)
+#define SPC5_FMPLL_NDIV(n) ((n) << 16)
+#define SPC5_FMPLL_EN_PLL_SW (1U << 8)
+#define SPC5_FMPLL_PLL_FAIL_MASK (1U << 2)
+
+#define SPC5_FMPLL_STRB_BYPASS (1U << 31)
+#define SPC5_FMPLL_SPRD_SEL (1U << 29)
+#define SPC5_FMPLL_MOD_PERIOD_MASK (0x1FFFU << 16)
+#define SPC5_FMPLL_MOD_PERIOD(n) ((n) << 16)
+#define SPC5_FMPLL_FM_EN (1U << 15)
+#define SPC5_FMPLL_INC_STEP_MASK (0x7FFFU << 0)
+#define SPC5_FMPLL_INC_STEP(n) ((n) << 0)
+/** @} */
+
+/**
+ * @name CMU registers bits definitions
+ * @{
+ */
+#define SPC5_CMU_CSR_SFM (1U << 23)
+#define SPC5_CMU_CSR_RCDIV_MASK (3U << 1)
+#define SPC5_CMU_CSR_RCDIV(n) ((n) << 1)
+#define SPC5_CMU_CSR_RCDIV_NODIV (0U << 1)
+#define SPC5_CMU_CSR_RCDIV_DIV2 (1U << 1)
+#define SPC5_CMU_CSR_RCDIV_DIV4 (2U << 1)
+#define SPC5_CMU_CSR_RCDIV_DIV8 (3U << 1)
+#define SPC5_CMU_CSR_CME (1U << 0)
+#define SPC5_CMU_ISR_FLCI (1U << 3)
+#define SPC5_CMU_ISR_FHHI (1U << 2)
+#define SPC5_CMU_ISR_FLLI (1U << 1)
+#define SPC5_CMU_ISR_OLRI (1U << 0)
+/** @} */
+
+/**
+ * @name Clock selectors used in the various GCM SC registers
+ * @{
+ */
+#define SPC5_CGM_SS_MASK (15U << 24)
+#define SPC5_CGM_SS_IRC (0U << 24)
+#define SPC5_CGM_SS_XOSC (2U << 24)
+#define SPC5_CGM_SS_FMPLL0 (4U << 24)
+#define SPC5_CGM_SS_FMPLL1 (5U << 24)
+#define SPC5_CGM_SS_FMPLL1_D1 (8U << 24)
+/** @} */
+
+/**
+ * @name Clock selectors used in the CGM_OCDS_SC register
+ * @{
+ */
+#define SPC5_CGM_OCDS_SELCTL_MASK (15U << 24)
+#define SPC5_CGM_OCDS_SELCTL_IRC (0U << 24)
+#define SPC5_CGM_OCDS_SELCTL_XOSC (1U << 24)
+#define SPC5_CGM_OCDS_SELCTL_FMPLL0 (2U << 24)
+#define SPC5_CGM_OCDS_SELCTL_FMPLL1 (3U << 24)
+/** @} */
+
+/**
+ * @name Clock dividers used in the CGM_OCDS_SC register
+ * @{
+ */
+#define SPC5_CGM_OCDS_SELDIV_MASK (3U << 28)
+#define SPC5_CGM_OCDS_SELDIV_DIV1 (0U << 28)
+#define SPC5_CGM_OCDS_SELDIV_DIV2 (1U << 28)
+#define SPC5_CGM_OCDS_SELDIV_DIV4 (2U << 28)
+#define SPC5_CGM_OCDS_SELDIV_DIV8 (3U << 28)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL1 (5U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (1U << 1)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_PLL1ON (1U << 7)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_LP (2U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 32
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief FMPLL0 CR register extra options.
+ */
+#if !defined(SPC5_FMPLL0_OPTIONS) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_OPTIONS 0
+#endif
+
+/**
+ * @brief FMPLL0 MR register initialization.
+ */
+#if !defined(SPC5_FMPLL0_MR_INIT) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_MR_INIT 0
+#endif
+
+/**
+ * @brief FMPLL1 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL1 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_NDIV_VALUE 60
+#endif
+
+/**
+ * @brief FMPLL1 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief FMPLL1 CR register extra options.
+ */
+#if !defined(SPC5_FMPLL1_OPTIONS) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_OPTIONS 0
+#endif
+
+/**
+ * @brief FMPLL1 MR register initialization.
+ */
+#if !defined(SPC5_FMPLL1_MR_INIT) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_MR_INIT 0
+#endif
+
+/**
+ * @brief Clock Out clock source.
+ */
+#if !defined(SPC5_CLKOUT_SRC) || defined(__DOXYGEN__)
+#define SPC5_CLKOUT_SRC SPC5_CGM_OCDS_SELCTL_IRC
+#endif
+
+/**
+ * @brief Clock Out clock divider value.
+ * @note Possible values are 1, 2, 4 and 8.
+ */
+#if !defined(SPC5_CLKOUT_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_CLKOUT_DIV_VALUE 2
+#endif
+
+/**
+ * @brief AUX0 clock source.
+ */
+#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief Motor Control clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_MCONTROL_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX1 clock source.
+ * @note Not configurable, always selects FMPLL1.
+ */
+#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX1CLK_SRC 0
+#endif
+
+/**
+ * @brief FMPLL1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_FMPLL1_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX2 clock source.
+ */
+#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief SP clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_SP_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_SP_CLK_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX3 clock source.
+ */
+#if !defined(SPC5_AUX3CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief FR clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_FR_CLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FR_CLK_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief CMU0 CSR register initialization.
+ */
+#if !defined(SPC5_CMU0_CSR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU0_CSR_INIT 0
+#endif
+
+/**
+ * @brief CMU0 HFREF register initialization.
+ */
+#if !defined(SPC5_CMU0_HFREFR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU0_HFREFR_INIT 4095
+#endif
+
+/**
+ * @brief CMU0 LFREF register initialization.
+ */
+#if !defined(SPC5_CMU0_LFREFR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU0_LFREFR_INIT 0
+#endif
+
+/**
+ * @brief CMU0 MDR register initialization.
+ */
+#if !defined(SPC5_CMU0_MDR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU0_MDR_INIT 0
+#endif
+
+/**
+ * @brief CMU1 CSR register initialization.
+ */
+#if !defined(SPC5_CMU1_CSR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU1_CSR_INIT 0
+#endif
+
+/**
+ * @brief CMU1 HFREF register initialization.
+ */
+#if !defined(SPC5_CMU1_HFREFR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU1_HFREFR_INIT 4095
+#endif
+
+/**
+ * @brief CMU1 LFREF register initialization.
+ */
+#if !defined(SPC5_CMU1_LFREFR_INIT) || defined(__DOXYGEN__)
+#define SPC5_CMU1_LFREFR_INIT 0
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Final run mode after initialization.
+ * @note It can be selected between DRUN, RUN0...RUN3.
+ */
+#if !defined(SPC5_FINAL_RUNMODE) || defined(__DOXYGEN__)
+#define SPC5_FINAL_RUNMODE SPC5_RUNMODE_RUN0
+#endif
+
+/**
+ * @brief PIT channel 0 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC560Pxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC560Pxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+#if SPC5_HAS_FMPLL1
+/* Check on SPC5_FMPLL1_IDF_VALUE.*/
+#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_NDIV_VALUE.*/
+#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_ODF.*/
+#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL1_ODF_VALUE 2
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL1_ODF_VALUE 4
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL1_ODF_VALUE 8
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL1_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL1_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL1_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
+
+/* Check on FMPLL1 VCO output.*/
+#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL1_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_CLK clock point.
+ */
+#define SPC5_FMPLL1_CLK \
+ (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE)
+
+/* Check on SPC5_FMPLL1_CLK.*/
+#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_D1_CLK clock point.
+ */
+#define SPC5_FMPLL1_D1_CLK \
+ (SPC5_FMPLL1_VCO_CLK / 6)
+
+/* Check on SPC5_FMPLL1_D1_CLK.*/
+#if (SPC5_FMPLL1_D1_CLK > SPC5_FMPLL1_D1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_D1_CLK_MAX)"
+#endif
+#endif /* SPC5_HAS_FMPLL1 */
+
+/**
+ * @brief CLKOUT clock point.
+ */
+#if (SPC5_CLKOUT_SRC == SPC5_CGM_OCDS_SELCTL_IRC) || defined(__DOXYGEN__)
+#define SPC5_CLKOUT_CLK SPC5_IRC_CLK
+#elif SPC5_CLKOUT_SRC == SPC5_CGM_OCDS_SELCTL_XOSC
+#define SPC5_CLKOUT_CLK SPC5_XOSC_CLK
+#elif SPC5_CLKOUT_SRC == SPC5_CGM_OCDS_SELCTL_FMPLL0
+#define SPC5_CLKOUT_CLK SPC5_FMPLL0_CLK
+#elif SPC5_CLKOUT_SRC == SPC5_CGM_OCDS_SELCTL_FMPLL1
+#define SPC5_CLKOUT_CLK SPC5_FMPLL1_CLK
+#else
+#error "invalid SPC5_CLKOUT_SRC value specified"
+#endif
+
+/* Check on the CLKOUT divider settings.*/
+#if SPC5_CLKOUT_DIV_VALUE == 1
+#define SPC5_CGM_OCDS_SELDIV SPC5_CGM_OCDS_SELDIV_DIV1
+#elif SPC5_CLKOUT_DIV_VALUE == 2
+#define SPC5_CGM_OCDS_SELDIV SPC5_CGM_OCDS_SELDIV_DIV2
+#elif SPC5_CLKOUT_DIV_VALUE == 4
+#define SPC5_CGM_OCDS_SELDIV SPC5_CGM_OCDS_SELDIV_DIV4
+#elif SPC5_CLKOUT_DIV_VALUE == 8
+#define SPC5_CGM_OCDS_SELDIV SPC5_CGM_OCDS_SELDIV_DIV8
+#else
+#error "invalid SPC5_CLKOUT_DIV_VALUE value specified"
+#endif
+
+#if SPC5_HAS_AC0 || defined(__DOXYGEN__)
+/**
+ * @brief AUX0 clock point.
+ */
+#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX0_CLK SPC5_IRC_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX0_CLK SPC5_XOSC_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX0_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX0_CLK SPC5_FMPLL1_CLK
+#else
+#error "invalid SPC5_AUX0CLK_SRC value specified"
+#endif
+
+#if !SPC5_HAS_FMPLL1 && (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1)
+#error "SPC5_AUX0CLK_SRC, FMPLL1 not present"
+#endif
+
+/* Check on the AUX0 divider 0 settings.*/
+#if SPC5_MCONTROL_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC0_DC0 0
+#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC0_DC0 ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief Motor Control clock point.
+ */
+#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_MCONTROL_CLK (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE)
+#else
+#define SPC5_MCONTROL_CLK 0
+#endif
+#endif /* #if SPC5_HAS_AC0 */
+
+#if SPC5_HAS_AC1 || defined(__DOXYGEN__)
+/**
+ * @brief AUX1 clock point.
+ */
+#if (SPC5_AUX1CLK_SRC == 0) || defined(__DOXYGEN__)
+#define SPC5_AUX1_CLK SPC5_FMPLL1_CLK
+#else
+#error "invalid SPC5_AUX1CLK_SRC value specified"
+#endif
+
+#if !SPC5_HAS_FMPLL1
+#error "SPC5_AUX1_CLK, FMPLL1 not present"
+#endif
+
+/* Check on the AUX1 divider 0 settings.*/
+#if SPC5_FMPLL1_CLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC1_DC0 0
+#elif (SPC5_FMPLL1_CLK_DIVIDER_VALUE >= 1) && (SPC5_FMPLL1_CLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC1_DC0 ((0x80U | (SPC5_FMPLL1_CLK_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_FMPLL1_CLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief FMPLL1 clock point.
+ */
+#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_FMPLL1_DIV_CLK (SPC5_AUX1_CLK / SPC5_FMPLL1_CLK_DIVIDER_VALUE)
+#else
+#define SPC5_FMPLL1_DIV_CLK 0
+#endif
+#endif /* SPC5_HAS_AC1 */
+
+#if SPC5_HAS_AC2 || defined(__DOXYGEN__)
+/**
+ * @brief AUX2 clock point.
+ */
+#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX2_CLK SPC5_IRC_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX2_CLK SPC5_XOSC_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX2_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX2_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_D1
+#define SPC5_AUX2_CLK SPC5_FMPLL1_D1_CLK
+#else
+#error "invalid SPC5_AUX2CLK_SRC value specified"
+#endif
+
+#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1) || \
+ (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_D1))
+#error "SPC5_AUX2_CLK, FMPLL1 not present"
+#endif
+
+/* Check on the AUX2 divider 0 settings.*/
+#if SPC5_SP_CLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC2_DC0 0
+#elif (SPC5_SP_CLK_DIVIDER_VALUE >= 1) && (SPC5_SP_CLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC2_DC0 ((0x80U | (SPC5_SP_CLK_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_SP_CLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief SP clock point.
+ */
+#if (SPC5_SP_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_SP_CLK (SPC5_AUX2_CLK / SPC5_SP_CLK_DIVIDER_VALUE)
+#else
+#define SPC5_SP_CLK 0
+#endif
+#endif /* SPC5_HAS_AC2 */
+
+#if SPC5_HAS_AC3 || defined(__DOXYGEN__)
+/**
+ * @brief AUX3 clock point.
+ */
+#if (SPC5_AUX3CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX3_CLK SPC5_IRC_CLK
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX3_CLK SPC5_XOSC_CLK
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX3_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX3_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1_D1
+#define SPC5_AUX3_CLK SPC5_FMPLL1_D1_CLK
+#else
+#error "invalid SPC5_AUX3CLK_SRC value specified"
+#endif
+
+#if !SPC5_HAS_FMPLL1 && ((SPC5_AUX2_CLK == SPC5_AUX3_CLK) || \
+ (SPC5_AUX3CLK_SRC == SPC5_CGM_SS_FMPLL1_D1))
+#error "SPC5_AUX3_CLK, FMPLL1 not present"
+#endif
+
+/* Check on the AUX3 divider 0 settings.*/
+#if SPC5_FR_CLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC3_DC0 0
+#elif (SPC5_FR_CLK_DIVIDER_VALUE >= 1) && (SPC5_FR_CLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC3_DC0 ((0x80U | (SPC5_FR_CLK_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_FR_CLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief FR clock point.
+ */
+#if (SPC5_FR_CLK_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_FR_CLK (SPC5_AUX3_CLK / SPC5_FR_CLK_DIVIDER_VALUE)
+#else
+#define SPC5_FR_CLK 0
+#endif
+#endif /* SPC5_HAS_AC3 */
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/platform.mk b/os/hal/ports/SPC5/SPC560Pxx/platform.mk new file mode 100644 index 000000000..f89086f74 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/platform.mk @@ -0,0 +1,23 @@ +# List of all the SPC560Pxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Pxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eTimer_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexPWM_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC560Pxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ADC_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eTimer_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexPWM_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC560Pxx/registers.h b/os/hal/ports/SPC5/SPC560Pxx/registers.h new file mode 100644 index 000000000..b51363a28 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc560p.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/spc5_registry.h b/os/hal/ports/SPC5/SPC560Pxx/spc5_registry.h new file mode 100644 index 000000000..2c46430b9 --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/spc5_registry.h @@ -0,0 +1,389 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/spc5_registry.h
+ * @brief SPC560Pxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if defined(_SPC560P34L1_) || defined(_SPC560P34L3_)
+#define _SPC560P34_
+#define _SPC560PXX_SMALL_
+#elif defined(_SPC560P40L1_) || defined(_SPC560P40L3_)
+#define _SPC560P40_
+#define _SPC560PXX_SMALL_
+#elif defined(_SPC560P44L3_) || defined(_SPC560P44L5_)
+#define _SPC560P44_
+#define _SPC560PXX_MEDIUM_
+#elif defined(_SPC560P50L3_) || defined(_SPC560P50L5_)
+#define _SPC560P50_
+#define _SPC560PXX_MEDIUM_
+#elif defined(_SPC560P54L3_) || defined(_SPC560P54L5_) || \
+ defined(_SPC56AP54L3_) || defined(_SPC56AP54L5_)
+#define _SPC560P54_
+#define _SPC560PXX_LARGE_
+#elif defined(_SPC560P60L3_) || defined(_SPC560P60L5_) || \
+ defined(_SPC56AP60L3_) || defined(_SPC56AP60L5_)
+#define _SPC560P60_
+#define _SPC560PXX_LARGE_
+#else
+#error "SPC56xPxx platform not defined"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560Pxx capabilities
+ * @{
+ */
+/* Clock attributes.*/
+#if defined(_SPC560PXX_SMALL_)
+#define SPC5_HAS_FMPLL1 FALSE
+#define SPC5_HAS_CLOCKOUT TRUE
+#define SPC5_HAS_AC0 FALSE
+#define SPC5_HAS_AC1 FALSE
+#define SPC5_HAS_AC2 FALSE
+#define SPC5_HAS_AC3 FALSE
+#define SPC5_HAS_CMU0 TRUE
+#define SPC5_HAS_CMU1 FALSE
+
+#elif defined(_SPC560PXX_MEDIUM_)
+#define SPC5_HAS_FMPLL1 TRUE
+#define SPC5_HAS_CLOCKOUT TRUE
+#define SPC5_HAS_AC0 TRUE
+#define SPC5_HAS_AC1 TRUE
+#define SPC5_HAS_AC2 TRUE
+#define SPC5_HAS_AC3 TRUE
+#define SPC5_HAS_CMU0 TRUE
+#define SPC5_HAS_CMU1 TRUE
+
+#else /* defined(_SPC560PXX_LARGE_) */
+#define SPC5_HAS_FMPLL1 FALSE
+#define SPC5_HAS_CLOCKOUT TRUE
+#define SPC5_HAS_AC0 FALSE
+#define SPC5_HAS_AC1 FALSE
+#define SPC5_HAS_AC2 FALSE
+#define SPC5_HAS_AC3 TRUE
+#define SPC5_HAS_CMU0 TRUE
+#define SPC5_HAS_CMU1 TRUE
+#endif
+
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_DSPI_FIFO_DEPTH 5
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI2_RFDF_HANDLER vector118
+#define SPC5_DSPI2_RFDF_NUMBER 118
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+
+#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
+#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_DSPI3_PCTL 7
+#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
+#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI3_RX_DMA_DEV_ID 8
+#define SPC5_DSPI3_TFFF_HANDLER vector219
+#define SPC5_DSPI3_TFFF_NUMBER 219
+#define SPC5_DSPI3_RFDF_HANDLER vector221
+#define SPC5_DSPI3_RFDF_NUMBER 221
+#define SPC5_DSPI3_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL)
+#define SPC5_DSPI3_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI3 FALSE
+#endif
+
+#if defined(_SPC560PXX_LARGE_)
+#define SPC5_HAS_DSPI4 TRUE
+#define SPC5_DSPI4_PCTL 8
+#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
+#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI4_RX_DMA_DEV_ID 21
+#define SPC5_DSPI4_TFFF_HANDLER vector258
+#define SPC5_DSPI4_TFFF_NUMBER 258
+#define SPC5_DSPI4_RFDF_HANDLER vector260
+#define SPC5_DSPI4_RFDF_NUMBER 260
+#define SPC5_DSPI4_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL)
+#define SPC5_DSPI4_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI4_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI4 FALSE
+#endif
+
+#define SPC5_HAS_DSPI5 FALSE
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 16
+#define SPC5_EDMA_HAS_MUX TRUE
+
+/* LINFlex attributes.*/
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / 1)
+
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / 1)
+
+#define SPC5_HAS_LINFLEX2 FALSE
+#define SPC5_HAS_LINFLEX3 FALSE
+#define SPC5_HAS_LINFLEX4 FALSE
+#define SPC5_HAS_LINFLEX5 FALSE
+#define SPC5_HAS_LINFLEX6 FALSE
+#define SPC5_HAS_LINFLEX7 FALSE
+#define SPC5_HAS_LINFLEX8 FALSE
+#define SPC5_HAS_LINFLEX9 FALSE
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_NUM_PORTS 8
+#if defined(_SPC560PXX_SMALL_)
+#define SPC5_SIUL_NUM_PCRS 72
+#else
+#define SPC5_SIUL_NUM_PCRS 108
+#endif
+#define SPC5_SIUL_NUM_PADSELS 36
+
+/* FlexPWM attributes.*/
+#if defined(_SPC560PXX_SMALL_) || defined(_SPC560PXX_MEDIUM_)
+#define SPC5_HAS_FLEXPWM0 TRUE
+#define SPC5_FLEXPWM0_PCTL 41
+#define SPC5_FLEXPWM0_RF0_HANDLER vector179
+#define SPC5_FLEXPWM0_COF0_HANDLER vector180
+#define SPC5_FLEXPWM0_CAF0_HANDLER vector181
+#define SPC5_FLEXPWM0_RF1_HANDLER vector182
+#define SPC5_FLEXPWM0_COF1_HANDLER vector183
+#define SPC5_FLEXPWM0_CAF1_HANDLER vector184
+#define SPC5_FLEXPWM0_RF2_HANDLER vector185
+#define SPC5_FLEXPWM0_COF2_HANDLER vector186
+#define SPC5_FLEXPWM0_CAF2_HANDLER vector187
+#define SPC5_FLEXPWM0_RF3_HANDLER vector188
+#define SPC5_FLEXPWM0_COF3_HANDLER vector189
+#define SPC5_FLEXPWM0_CAF3_HANDLER vector190
+#define SPC5_FLEXPWM0_FFLAG_HANDLER vector191
+#define SPC5_FLEXPWM0_REF_HANDLER vector192
+#define SPC5_FLEXPWM0_RF0_NUMBER 179
+#define SPC5_FLEXPWM0_COF0_NUMBER 180
+#define SPC5_FLEXPWM0_CAF0_NUMBER 181
+#define SPC5_FLEXPWM0_RF1_NUMBER 182
+#define SPC5_FLEXPWM0_COF1_NUMBER 183
+#define SPC5_FLEXPWM0_CAF1_NUMBER 184
+#define SPC5_FLEXPWM0_RF2_NUMBER 185
+#define SPC5_FLEXPWM0_COF2_NUMBER 186
+#define SPC5_FLEXPWM0_CAF2_NUMBER 187
+#define SPC5_FLEXPWM0_RF3_NUMBER 188
+#define SPC5_FLEXPWM0_COF3_NUMBER 189
+#define SPC5_FLEXPWM0_CAF3_NUMBER 190
+#define SPC5_FLEXPWM0_FFLAG_NUMBER 191
+#define SPC5_FLEXPWM0_REF_NUMBER 192
+#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK
+#else /* defined(_SPC560PXX_LARGE_) */
+#define SPC5_HAS_FLEXPWM0 FALSE
+#endif /* defined(_SPC560PXX_LARGE_) */
+
+#define SPC5_HAS_FLEXPWM1 FALSE
+
+/* eTimer attributes.*/
+#define SPC5_HAS_ETIMER0 TRUE
+#define SPC5_ETIMER0_PCTL 38
+#define SPC5_ETIMER0_TC0IR_HANDLER vector157
+#define SPC5_ETIMER0_TC1IR_HANDLER vector158
+#define SPC5_ETIMER0_TC2IR_HANDLER vector159
+#define SPC5_ETIMER0_TC3IR_HANDLER vector160
+#define SPC5_ETIMER0_TC4IR_HANDLER vector161
+#define SPC5_ETIMER0_TC5IR_HANDLER vector162
+#define SPC5_ETIMER0_WTIF_HANDLER vector165
+#define SPC5_ETIMER0_RCF_HANDLER vector167
+#define SPC5_ETIMER0_TC0IR_NUMBER 157
+#define SPC5_ETIMER0_TC1IR_NUMBER 158
+#define SPC5_ETIMER0_TC2IR_NUMBER 159
+#define SPC5_ETIMER0_TC3IR_NUMBER 160
+#define SPC5_ETIMER0_TC4IR_NUMBER 161
+#define SPC5_ETIMER0_TC5IR_NUMBER 162
+#define SPC5_ETIMER0_WTIF_NUMBER 165
+#define SPC5_ETIMER0_RCF_NUMBER 167
+#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK
+
+#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
+#define SPC5_HAS_ETIMER1 TRUE
+#define SPC5_ETIMER1_PCTL 39
+#define SPC5_ETIMER1_TC0IR_HANDLER vector168
+#define SPC5_ETIMER1_TC1IR_HANDLER vector169
+#define SPC5_ETIMER1_TC2IR_HANDLER vector170
+#define SPC5_ETIMER1_TC3IR_HANDLER vector171
+#define SPC5_ETIMER1_TC4IR_HANDLER vector172
+#define SPC5_ETIMER1_TC5IR_HANDLER vector173
+#define SPC5_ETIMER1_RCF_HANDLER vector178
+#define SPC5_ETIMER1_TC0IR_NUMBER 168
+#define SPC5_ETIMER1_TC1IR_NUMBER 169
+#define SPC5_ETIMER1_TC2IR_NUMBER 170
+#define SPC5_ETIMER1_TC3IR_NUMBER 171
+#define SPC5_ETIMER1_TC4IR_NUMBER 172
+#define SPC5_ETIMER1_TC5IR_NUMBER 173
+#define SPC5_ETIMER1_RCF_NUMBER 178
+#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
+
+#else /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
+#define SPC5_HAS_ETIMER1 FALSE
+#endif /* !(defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)) */
+
+#define SPC5_HAS_ETIMER2 FALSE
+#define SPC5_HAS_ETIMER3 FALSE
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 32
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL)
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL)
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC TRUE
+
+#define SPC5_HAS_ADC0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 FALSE
+#define SPC5_ADC0_PCTL 32
+#define SPC5_ADC0_DMA_DEV_ID 20
+#define SPC5_ADC0_EOC_HANDLER vector62
+#define SPC5_ADC0_EOC_NUMBER 62
+#define SPC5_ADC0_WD_HANDLER vector64
+#define SPC5_ADC0_WD_NUMBER 64
+
+#define SPC5_HAS_ADC1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR1 FALSE
+#define SPC5_ADC_ADC1_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR1 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 FALSE
+#define SPC5_ADC1_PCTL 33
+#define SPC5_ADC1_DMA_DEV_ID 21
+#define SPC5_ADC1_EOC_HANDLER vector82
+#define SPC5_ADC1_EOC_NUMBER 82
+#define SPC5_ADC1_WD_HANDLER vector84
+#define SPC5_ADC1_WD_NUMBER 84
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/typedefs.h b/os/hal/ports/SPC5/SPC560Pxx/typedefs.h new file mode 100644 index 000000000..d14c7dd6a --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560Pxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC560Pxx/xpc560p.h b/os/hal/ports/SPC5/SPC560Pxx/xpc560p.h new file mode 100644 index 000000000..76ea503ca --- /dev/null +++ b/os/hal/ports/SPC5/SPC560Pxx/xpc560p.h @@ -0,0 +1,7801 @@ +/*****************************************************************
+ * PROJECT : MPC5604P
+ * FILE : 5604P_Header_v1_10.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for the named projects.
+ *
+ * COPYRIGHT :(c) 2012, Freescale
+ *
+ * VERSION : 01.10
+ * DATE : 12.06.2012
+ * AUTHOR : B16991
+ * HISTORY : Changes: typo fixed in PSR1 register:SCP -> CSP, MCR: PRESCALE->BITRATE (b16991)
+ * HISTORY : Changes: typo fixed in ME register MTC bit, SSCM fix, CMU changes(b16991)
+ * HISTORY : Changes to CTU Module: CR register (LC->FC), CLR changed to 24 bits (b16991)
+ * HISTORY : Modified to add reserved space in CTU (b16991)
+ * HISTORY : Modified to support ADC on Pictus cut 2 - do not distribute! (ttz778)
+ * HISTORY : Modified to support CRC on Pictus cut 2 - do not distribute! (r60321)
+ * HISTORY : Modified to support DSPI0 CS7&8 and new FlexPWM naming on Pictus cut 2 (r60321)
+ * HISTORY : Modified to update MIDR1&2 registers and LINCR1-SFTM and LINESR-BDEF bit on Pictus (r60321)
+ * HISTORY : Modified to update RGM, CFLASH & DFLASH registers and FlexCAN & CTU Registers on Pictus (r60321)
+ * HISTORY : Modified to update DSPI Registers (FIFO deep) on Pictus (b16991)
+ *
+ *****************************************************************
+ * Copyright:
+ * Freescale Semiconductor, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Freescale
+ * Semiconductor, Inc. This software is provided on an "AS IS"
+ * basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, Freescale
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Freescale Semiconductor assumes no responsibility for the
+ * maintenance and support of this software
+ *
+ ******************************************************************/
+/*****************************************************************
+* Example instantiation and use:
+*
+* <MODULE>.<REGISTER>.B.<BIT> = 1;
+* <MODULE>.<REGISTER>.R = 0x10000000;
+*
+******************************************************************/
+
+#ifndef _JDP_H_
+#define _JDP_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+/****************************************************************************/
+/* MODULE : ADC */
+/****************************************************************************/
+ struct ADC_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t EDGLEV:1;
+ vuint32_t TRGEN:1;
+ vuint32_t EDGE:1;
+ vuint32_t XSTRTEN:1;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1;
+ vuint32_t ABORTCHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACK0:1;
+ vuint32_t OFFREFRESH:1;
+ vuint32_t OFFCANC:1;
+ vuint32_t:2;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR; /* MAIN CONFIGURATION REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACK0:1;
+ vuint32_t OFFREFRESH:1;
+ vuint32_t OFFCANC:1;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR; /* MAIN STATUS REGISTER */
+
+ int32_t ADC_reserved1[2]; /* (0x008 - 0x00F)/4 = 0x02 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t OFFCANCOVR:1;
+ vuint32_t EOFFSET:1;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR; /* INTERRUPT STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EOC31:1;
+ vuint32_t EOC30:1;
+ vuint32_t EOC29:1;
+ vuint32_t EOC28:1;
+ vuint32_t EOC27:1;
+ vuint32_t EOC26:1;
+ vuint32_t EOC25:1;
+ vuint32_t EOC24:1;
+ vuint32_t EOC23:1;
+ vuint32_t EOC22:1;
+ vuint32_t EOC21:1;
+ vuint32_t EOC20:1;
+ vuint32_t EOC19:1;
+ vuint32_t EOC18:1;
+ vuint32_t EOC17:1;
+ vuint32_t EOC16:1;
+ vuint32_t EOC15:1;
+ vuint32_t EOC14:1;
+ vuint32_t EOC13:1;
+ vuint32_t EOC12:1;
+ vuint32_t EOC11:1;
+ vuint32_t EOC10:1;
+ vuint32_t EOC9:1;
+ vuint32_t EOC8:1;
+ vuint32_t EOC7:1;
+ vuint32_t EOC6:1;
+ vuint32_t EOC5:1;
+ vuint32_t EOC4:1;
+ vuint32_t EOC3:1;
+ vuint32_t EOC2:1;
+ vuint32_t EOC1:1;
+ vuint32_t EOC0:1;
+ } B;
+ } CEOCFR[3]; /* Channel Pending Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25; //One bit added
+ vuint32_t MSKOFFCANCOVR:1; //Moved up
+ vuint32_t MSKEOFFSET:1; //Moved up
+ vuint32_t MSKEOCTU:1; //New for cut 2
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR; /* INTERRUPT MASK REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1;
+ vuint32_t CIM30:1;
+ vuint32_t CIM29:1;
+ vuint32_t CIM28:1;
+ vuint32_t CIM27:1;
+ vuint32_t CIM26:1;
+ vuint32_t CIM25:1;
+ vuint32_t CIM24:1;
+ vuint32_t CIM23:1;
+ vuint32_t CIM22:1;
+ vuint32_t CIM21:1;
+ vuint32_t CIM20:1;
+ vuint32_t CIM19:1;
+ vuint32_t CIM18:1;
+ vuint32_t CIM17:1;
+ vuint32_t CIM16:1;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR[3]; /* Channel Interrupt Mask Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t WDG3H:1;
+ vuint32_t WDG2H:1;
+ vuint32_t WDG1H:1;
+ vuint32_t WDG0H:1;
+ vuint32_t WDG3L:1;
+ vuint32_t WDG2L:1;
+ vuint32_t WDG1L:1;
+ vuint32_t WDG0L:1;
+ } B;
+ } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER was WDGTHR */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t MSKWDG3H:1;
+ vuint32_t MSKWDG2H:1;
+ vuint32_t MSKWDG1H:1;
+ vuint32_t MSKWDG0H:1;
+ vuint32_t MSKWDG3L:1;
+ vuint32_t MSKWDG2L:1;
+ vuint32_t MSKWDG1L:1;
+ vuint32_t MSKWDG0L:1;
+ } B;
+ } WTIMR; /* WATCHDOG INTERRUPT MASK REGISTER was IMWDGTHR */
+
+ int32_t ADC_reserved2[2]; /* (0x038 - 0x03F)/4 = 0x02 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30; //was 16
+ vuint32_t DCLR:1; //moved
+ vuint32_t DMAEN:1; //moved
+ } B;
+ } DMAE; /* DMAE REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DMA31:1; //was unused [16]
+ vuint32_t DMA30:1;
+ vuint32_t DMA29:1;
+ vuint32_t DMA28:1;
+ vuint32_t DMA27:1;
+ vuint32_t DMA26:1;
+ vuint32_t DMA25:1;
+ vuint32_t DMA24:1;
+ vuint32_t DMA23:1;
+ vuint32_t DMA22:1;
+ vuint32_t DMA21:1;
+ vuint32_t DMA20:1;
+ vuint32_t DMA19:1;
+ vuint32_t DMA18:1;
+ vuint32_t DMA17:1;
+ vuint32_t DMA16:1;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR[3]; /* DMA REGISTER was [6] */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t THREN:1;
+ vuint32_t THRINV:1;
+ vuint32_t THROP:1;
+ vuint32_t:6;
+ vuint32_t THRCH:7;
+ } B;
+ } TRC[4]; /* ADC THRESHOLD REGISTER REGISTER */
+
+ union {
+ vuint32_t R;
+ struct { //were in TRA & TRB
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR[4]; /* THRESHOLD REGISTER */
+
+ union {
+ vuint32_t R;
+ struct { //were in TRAALT & TRBALT
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRALT[4]; /* ADC THRESHOLD REGISTER REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:25; //was 26
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PREONCE:1;
+ } B;
+ } PSCR; /* PRESAMPLING CONTROL REGISTER was PREREG */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1; //was reserved 16
+ vuint32_t PRES30:1;
+ vuint32_t PRES29:1;
+ vuint32_t PRES28:1;
+ vuint32_t PRES27:1;
+ vuint32_t PRES26:1;
+ vuint32_t PRES25:1;
+ vuint32_t PRES24:1;
+ vuint32_t PRES23:1;
+ vuint32_t PRES22:1;
+ vuint32_t PRES21:1;
+ vuint32_t PRES20:1;
+ vuint32_t PRES19:1;
+ vuint32_t PRES18:1;
+ vuint32_t PRES17:1;
+ vuint32_t PRES16:1;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR[3]; /* PRESAMPLING REGISTER was PRER[6]*/
+
+ int32_t ADC_reserved3[1]; /* (0x090 - 0x093)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2; //!!! This field only in CTR[0]
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR[3]; /* CONVERSION TIMING REGISTER was CT[3] */
+
+ int32_t ADC_reserved4[1]; /* (0x0A0 - 0x0A3)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1; //was reserved 16
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR[3]; /* NORMAL CONVERSION MASK REGISTER was [6] */
+
+ int32_t ADC_reserved5[1]; /* (0x0B0 - 0x0B3)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1; //was reserved 16
+ vuint32_t CH30:1;
+ vuint32_t CH29:1;
+ vuint32_t CH28:1;
+ vuint32_t CH27:1;
+ vuint32_t CH26:1;
+ vuint32_t CH25:1;
+ vuint32_t CH24:1;
+ vuint32_t CH23:1;
+ vuint32_t CH22:1;
+ vuint32_t CH21:1;
+ vuint32_t CH20:1;
+ vuint32_t CH19:1;
+ vuint32_t CH18:1;
+ vuint32_t CH17:1;
+ vuint32_t CH16:1;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR[3]; /* Injected CONVERSION MASK REGISTER was ICMR[6] */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t OFFSETLOAD:1; //new
+ vuint32_t:8;
+ vuint32_t OFFSETWORD:8;
+ } B;
+ } OFFWR; /* OFFSET WORD REGISTER was OFFREG*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8;
+ } B;
+ } DSDR; /* DECODE SIGNALS DELAY REGISTER was DSD */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8; //was PDD
+ } B;
+ } PDEDR; /* POWER DOWN DELAY REGISTER was PDD */
+
+ int32_t ADC_reserved6[9]; /* (0x0CC - 0x0EF)/4 = 0x09 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TEST_CTL:32;
+ } B;
+ } TCTLR; /* Test control REGISTER */
+
+ int32_t ADC_reserved7[3]; /* (0x0F4 - 0x0FF)/4 = 0x03 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:4;
+ vuint32_t CDATA:12;
+ } B;
+ } CDR[96]; /* Channel 0-95 Data REGISTER */
+
+ }; /* end of ADC_tag */
+/****************************************************************************/
+/* MODULE : CANSP */
+/****************************************************************************/
+ struct CANSP_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t RX_COMPLETE:1;
+ vuint16_t BUSY:1;
+ vuint16_t ACTIVE_CK:1;
+ vuint16_t:3;
+ vuint16_t MODE:1;
+ vuint16_t CAN_RX_SEL:3;
+ vuint16_t BRP:5;
+ vuint16_t CAN_SMPLR_EN:1;
+ } B;
+ } CR; /* CANSP Control Register */
+
+ int16_t CANSP_reserved;
+
+ union {
+ vuint32_t R;
+ } SR[12]; /* CANSP Sample Register 0 to 11 */
+
+ }; /* end of CANSP_tag */
+/****************************************************************************/
+/* MODULE : MCM */
+/****************************************************************************/
+ struct MCM_tag {
+
+ union {
+ vuint16_t R;
+ } PCT; /* MCM Processor Core Type Register */
+
+ union {
+ vuint16_t R;
+ } REV; /* MCM Revision Register */
+
+ int32_t MCM_reserved;
+
+ union {
+ vuint32_t R;
+ } MC; /* MCM Configuration Register */
+
+ int8_t MCM_reserved1[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t POR:1;
+ vuint8_t DIR:1;
+ vuint8_t:6;
+ } B;
+ } MRSR; /* MCM Miscellaneous Reset Status Register */
+
+ int8_t MCM_reserved2[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1;
+ vuint8_t:3;
+ vuint8_t PRILVL:4;
+ } B;
+ } MWCR; /* MCM Miscellaneous Wakeup Control Register */
+
+ int32_t MCM_reserved3[2];
+ int8_t MCM_reserved4[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1;
+ vuint8_t FB0SI:1;
+ vuint8_t FB1AI:1;
+ vuint8_t FB1SI:1;
+ vuint8_t:4;
+ } B;
+ } MIR; /* MCM Miscellaneous Interrupt Register */
+
+ int32_t MCM_reserved5;
+
+ union {
+ vuint32_t R;
+ } MUDCR; /* MCM Miscellaneous User-Defined Control Register */
+
+ int32_t MCM_reserved6[6]; /* (0x040- 0x028)/4 = 0x06 */
+ int8_t MCM_reserved7[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t:2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR; /* MCM ECC Configuration Register */
+
+ int8_t MCM_reserved8[3];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t:2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR; /* MCM ECC Status Register */
+
+ int16_t MCM_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t:2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t:1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR; /* MCM ECC Error Generation Register */
+
+ int32_t MCM_reserved10;
+
+ union {
+ vuint32_t R;
+ } FEAR; /* MCM Flash ECC Address Register */
+
+ int16_t MCM_reserved11;
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR; /* MCM Flash ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } FEAT; /* MCM Flash ECC Attributes Register */
+
+ int32_t MCM_reserved12;
+
+ union {
+ vuint32_t R;
+ } FEDR; /* MCM Flash ECC Data Register */
+
+ union {
+ vuint32_t R;
+ } REAR; /* MCM RAM ECC Address Register */
+
+ int8_t MCM_reserved13;
+
+ union {
+ vuint8_t R;
+ } RESR; /* MCM RAM ECC Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR; /* MCM RAM ECC Master Number Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } REAT; /* MCM RAM ECC Attributes Register */
+
+ int32_t MCM_reserved14;
+
+ union {
+ vuint32_t R;
+ } REDR; /* MCM RAM ECC Data Register */
+
+ }; /* end of MCM_tag */
+/****************************************************************************/
+/* MODULE : RTC */
+/****************************************************************************/
+ struct RTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SUPV:1;
+ vuint32_t:31;
+ } B;
+ } RTCSUPV; /* RTC Supervisor Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNTEN:1;
+ vuint32_t RTCIE:1;
+ vuint32_t FRZEN:1;
+ vuint32_t ROVREN:1;
+ vuint32_t RTCVAL:12;
+ vuint32_t APIEN:1;
+ vuint32_t APIE:1;
+ vuint32_t CLKSEL:2;
+ vuint32_t DIV512EN:1;
+ vuint32_t DIV32EN:1;
+ vuint32_t APIVAL:10;
+ } B;
+ } RTCC; /* RTC Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t RTCF:1;
+ vuint32_t:15;
+ vuint32_t APIF:1;
+ vuint32_t:2;
+ vuint32_t ROVRF:1;
+ vuint32_t:10;
+ } B;
+ } RTCS; /* RTC Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RTCCNT:32;
+ } B;
+ } RTCCNT; /* RTC Counter Register */
+
+ }; /* end of RTC_tag */
+/****************************************************************************/
+/* MODULE : SIU */
+/****************************************************************************/
+ struct SIU_tag {
+
+ int32_t SIU_reserved0;
+
+ union { /* MCU ID Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16;
+ vuint32_t CSP:1;
+ vuint32_t PKG:5;
+ vuint32_t:2;
+ vuint32_t MAJORMASK:4;
+ vuint32_t MINORMASK:4;
+ } B;
+ } MIDR;
+
+ union { /* MCU ID Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1;
+ vuint32_t FLASH_SIZE_1:4;
+ vuint32_t FLASH_SIZE_2:4;
+ vuint32_t:7;
+ vuint32_t PARTNUM:8;
+ vuint32_t:3;
+ vuint32_t EE:1;
+ vuint32_t:3;
+ vuint32_t FR:1;
+ } B;
+ } MIDR2;
+
+ int32_t SIU_reserved1[2];
+
+ union { /* Interrupt Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIF31:1;
+ vuint32_t EIF30:1;
+ vuint32_t EIF29:1;
+ vuint32_t EIF28:1;
+ vuint32_t EIF27:1;
+ vuint32_t EIF26:1;
+ vuint32_t EIF25:1;
+ vuint32_t EIF24:1;
+ vuint32_t EIF23:1;
+ vuint32_t EIF22:1;
+ vuint32_t EIF21:1;
+ vuint32_t EIF20:1;
+ vuint32_t EIF19:1;
+ vuint32_t EIF18:1;
+ vuint32_t EIF17:1;
+ vuint32_t EIF16:1;
+ vuint32_t EIF15:1;
+ vuint32_t EIF14:1;
+ vuint32_t EIF13:1;
+ vuint32_t EIF12:1;
+ vuint32_t EIF11:1;
+ vuint32_t EIF10:1;
+ vuint32_t EIF9:1;
+ vuint32_t EIF8:1;
+ vuint32_t EIF7:1;
+ vuint32_t EIF6:1;
+ vuint32_t EIF5:1;
+ vuint32_t EIF4:1;
+ vuint32_t EIF3:1;
+ vuint32_t EIF2:1;
+ vuint32_t EIF1:1;
+ vuint32_t EIF0:1;
+ } B;
+ } ISR;
+
+ union { /* Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE31:1;
+ vuint32_t EIRE30:1;
+ vuint32_t EIRE29:1;
+ vuint32_t EIRE28:1;
+ vuint32_t EIRE27:1;
+ vuint32_t EIRE26:1;
+ vuint32_t EIRE25:1;
+ vuint32_t EIRE24:1;
+ vuint32_t EIRE23:1;
+ vuint32_t EIRE22:1;
+ vuint32_t EIRE21:1;
+ vuint32_t EIRE20:1;
+ vuint32_t EIRE19:1;
+ vuint32_t EIRE18:1;
+ vuint32_t EIRE17:1;
+ vuint32_t EIRE16:1;
+ vuint32_t EIRE15:1;
+ vuint32_t EIRE14:1;
+ vuint32_t EIRE13:1;
+ vuint32_t EIRE12:1;
+ vuint32_t EIRE11:1;
+ vuint32_t EIRE10:1;
+ vuint32_t EIRE9:1;
+ vuint32_t EIRE8:1;
+ vuint32_t EIRE7:1;
+ vuint32_t EIRE6:1;
+ vuint32_t EIRE5:1;
+ vuint32_t EIRE4:1;
+ vuint32_t EIRE3:1;
+ vuint32_t EIRE2:1;
+ vuint32_t EIRE1:1;
+ vuint32_t EIRE0:1;
+ } B;
+ } IRER;
+
+ int32_t SIU_reserved2[3];
+
+ union { /* Interrupt Rising-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IREE31:1;
+ vuint32_t IREE30:1;
+ vuint32_t IREE29:1;
+ vuint32_t IREE28:1;
+ vuint32_t IREE27:1;
+ vuint32_t IREE26:1;
+ vuint32_t IREE25:1;
+ vuint32_t IREE24:1;
+ vuint32_t IREE23:1;
+ vuint32_t IREE22:1;
+ vuint32_t IREE21:1;
+ vuint32_t IREE20:1;
+ vuint32_t IREE19:1;
+ vuint32_t IREE18:1;
+ vuint32_t IREE17:1;
+ vuint32_t IREE16:1;
+ vuint32_t IREE15:1;
+ vuint32_t IREE14:1;
+ vuint32_t IREE13:1;
+ vuint32_t IREE12:1;
+ vuint32_t IREE11:1;
+ vuint32_t IREE10:1;
+ vuint32_t IREE9:1;
+ vuint32_t IREE8:1;
+ vuint32_t IREE7:1;
+ vuint32_t IREE6:1;
+ vuint32_t IREE5:1;
+ vuint32_t IREE4:1;
+ vuint32_t IREE3:1;
+ vuint32_t IREE2:1;
+ vuint32_t IREE1:1;
+ vuint32_t IREE0:1;
+ } B;
+ } IREER;
+
+ union { /* Interrupt Falling-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE31:1;
+ vuint32_t IFEE30:1;
+ vuint32_t IFEE29:1;
+ vuint32_t IFEE28:1;
+ vuint32_t IFEE27:1;
+ vuint32_t IFEE26:1;
+ vuint32_t IFEE25:1;
+ vuint32_t IFEE24:1;
+ vuint32_t IFEE23:1;
+ vuint32_t IFEE22:1;
+ vuint32_t IFEE21:1;
+ vuint32_t IFEE20:1;
+ vuint32_t IFEE19:1;
+ vuint32_t IFEE18:1;
+ vuint32_t IFEE17:1;
+ vuint32_t IFEE16:1;
+ vuint32_t IFEE15:1;
+ vuint32_t IFEE14:1;
+ vuint32_t IFEE13:1;
+ vuint32_t IFEE12:1;
+ vuint32_t IFEE11:1;
+ vuint32_t IFEE10:1;
+ vuint32_t IFEE9:1;
+ vuint32_t IFEE8:1;
+ vuint32_t IFEE7:1;
+ vuint32_t IFEE6:1;
+ vuint32_t IFEE5:1;
+ vuint32_t IFEE4:1;
+ vuint32_t IFEE3:1;
+ vuint32_t IFEE2:1;
+ vuint32_t IFEE1:1;
+ vuint32_t IFEE0:1;
+ } B;
+ } IFEER;
+
+ union { /* Interrupt Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFE31:1;
+ vuint32_t IFE30:1;
+ vuint32_t IFE29:1;
+ vuint32_t IFE28:1;
+ vuint32_t IFE27:1;
+ vuint32_t IFE26:1;
+ vuint32_t IFE25:1;
+ vuint32_t IFE24:1;
+ vuint32_t IFE23:1;
+ vuint32_t IFE22:1;
+ vuint32_t IFE21:1;
+ vuint32_t IFE20:1;
+ vuint32_t IFE19:1;
+ vuint32_t IFE18:1;
+ vuint32_t IFE17:1;
+ vuint32_t IFE16:1;
+ vuint32_t IFE15:1;
+ vuint32_t IFE14:1;
+ vuint32_t IFE13:1;
+ vuint32_t IFE12:1;
+ vuint32_t IFE11:1;
+ vuint32_t IFE10:1;
+ vuint32_t IFE9:1;
+ vuint32_t IFE8:1;
+ vuint32_t IFE7:1;
+ vuint32_t IFE6:1;
+ vuint32_t IFE5:1;
+ vuint32_t IFE4:1;
+ vuint32_t IFE3:1;
+ vuint32_t IFE2:1;
+ vuint32_t IFE1:1;
+ vuint32_t IFE0:1;
+ } B;
+ } IFER;
+
+ int32_t SIU_reserved3[3];
+
+ union { /* Pad Configuration Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SME:1;
+ vuint16_t APC:1;
+ vuint16_t:1;
+ vuint16_t PA:2;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t DCS:2;
+ vuint16_t ODE:1;
+ vuint16_t HYS:1;
+ vuint16_t SRC:2;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[512];
+
+ int32_t SIU_reserved4[48]; /* {0x500-0x440}/0x4 */
+
+ union { /* Pad Selection for Multiplexed Input Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PADSEL:4;
+ } B;
+ } PSMI[256];
+
+ union { /* GPIO Pin Data Output Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[512];
+
+ union { /* GPIO Pin Data Input Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[512];
+
+ int32_t SIU_reserved5[128]; /* {0xC00-0xA00}/0x4 */
+
+ union { /* Parallel GPIO Pin Data Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPD0:32;
+ } B;
+ } PGPDO[16];
+
+ union { /* Parallel GPIO Pin Data Input Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDI:32;
+ } B;
+ } PGPDI[16];
+
+ union { /* Masked Parallel GPIO Pin Data Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16;
+ vuint32_t MPPDO:16;
+ } B;
+ } MPGPDO[32];
+
+ int32_t SIU_reserved6[192]; /* {0x1000-0x0D00}/0x4 */
+
+ union { /* Interrupt Filter Maximum Counter Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t MAXCNT:4;
+ } B;
+ } IFMC[32];
+
+ union { /* Interrupt Filter Clock Prescaler Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFCP:4;
+ } B;
+ } IFCPR;
+
+ }; /* end of SIU_tag */
+/****************************************************************************/
+/* MODULE : SSCM */
+/****************************************************************************/
+ struct SSCM_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t NXEN:1;
+ vuint16_t PUB:1;
+ vuint16_t SEC:1;
+ vuint16_t:1;
+ vuint16_t BMODE:3;
+ vuint16_t:1;
+ vuint16_t ABD:1;
+ vuint16_t:3;
+ } B;
+ } STATUS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SRAMSIZE:5;
+ vuint16_t IFLASHSIZE:5;
+ vuint16_t IVLD:1;
+ vuint16_t DFLASHSIZE:4;
+ vuint16_t DVLD:1;
+ } B;
+ } MEMCONFIG; /* System Memory Configuration Register */
+
+ int16_t SSCM_reserved;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:14;
+ vuint16_t PAE:1;
+ vuint16_t RAE:1;
+ } B;
+ } ERROR; /* Error Configuration Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:13;
+ vuint16_t DEBUG_MODE:3;
+ } B;
+ } DEBUGPORT; /* Debug Status Port Register */
+
+ int16_t SSCM_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32;
+ } B;
+ } PWCMPH; /* Password Comparison Register High Word */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32;
+ } B;
+ } PWCMPL; /* Password Comparison Register Low Word */
+
+ }; /* end of SSCM_tag */
+/****************************************************************************/
+/* MODULE : STM */
+/****************************************************************************/
+ struct STM_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8;
+ vuint32_t:6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR0; /* STM Control Register */
+
+ union {
+ vuint32_t R;
+ } CNT0; /* STM Count Register */
+
+ int32_t STM_reserved[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR0; /* STM Channel Control Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR0; /* STM Channel Interrupt Register 0 */
+
+ union {
+ vuint32_t R;
+ } CMP0; /* STM Channel Compare Register 0 */
+
+ int32_t STM_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR1; /* STM Channel Control Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR1; /* STM Channel Interrupt Register 1 */
+
+ union {
+ vuint32_t R;
+ } CMP1; /* STM Channel Compare Register 1 */
+
+ int32_t STM_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR2; /* STM Channel Control Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR2; /* STM Channel Interrupt Register 2 */
+
+ union {
+ vuint32_t R;
+ } CMP2; /* STM Channel Compare Register 2 */
+
+ int32_t STM_reserved3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR3; /* STM Channel Control Register 3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR3; /* STM Channel Interrupt Register 3 */
+
+ union {
+ vuint32_t R;
+ } CMP3; /* STM Channel Compare Register 3 */
+
+ }; /* end of STM_tag */
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+ struct SWT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t:15;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } CR; /* SWT Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } IR; /* SWT Interrupt Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO; /* SWT Time-Out Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+ } B;
+ } WN; /* SWT Window Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16;
+ } B;
+ } SR; /* SWT Service Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO; /* SWT Counter Output Register */
+
+ }; /* end of SWT_tag */
+/****************************************************************************/
+/* MODULE : WKUP */
+/****************************************************************************/
+ struct WKUP_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1;
+ vuint32_t NOVF0:1;
+ vuint32_t:6;
+ vuint32_t NIF1:1;
+ vuint32_t NOVF1:1;
+ vuint32_t:6;
+ vuint32_t NIF2:1;
+ vuint32_t NOVF2:1;
+ vuint32_t:6;
+ vuint32_t NIF3:1;
+ vuint32_t NOVF3:1;
+ vuint32_t:6;
+ } B;
+ } NSR; /* NMI Status Register */
+
+ int32_t WKUP_reserved;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK0:1;
+ vuint32_t NDSS0:2;
+ vuint32_t NWRE0:1;
+ vuint32_t:1;
+ vuint32_t NREE0:1;
+ vuint32_t NFEE0:1;
+ vuint32_t NFE0:1;
+ vuint32_t NLOCK1:1;
+ vuint32_t NDSS1:2;
+ vuint32_t NWRE1:1;
+ vuint32_t:1;
+ vuint32_t NREE1:1;
+ vuint32_t NFEE1:1;
+ vuint32_t NFE1:1;
+ vuint32_t NLOCK2:1;
+ vuint32_t NDSS2:2;
+ vuint32_t NWRE2:1;
+ vuint32_t:1;
+ vuint32_t NREE2:1;
+ vuint32_t NFEE2:1;
+ vuint32_t NFE2:1;
+ vuint32_t NLOCK3:1;
+ vuint32_t NDSS3:2;
+ vuint32_t NWRE3:1;
+ vuint32_t:1;
+ vuint32_t NREE3:1;
+ vuint32_t NFEE3:1;
+ vuint32_t NFE3:1;
+ } B;
+ } NCR; /* NMI Configuration Register */
+
+ int32_t WKUP_reserved1[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EIF:32;
+ } B;
+ } WISR; /* Wakeup/Interrupt Status Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE:32;
+ } B;
+ } IRER; /* Interrupt Request Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WRE:32;
+ } B;
+ } WRER; /* Wakeup Request Enable Register */
+
+ int32_t WKUP_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IREE:32;
+ } B;
+ } WIREER; /* Wakeup/Interrupt Rising-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE:32;
+ } B;
+ } WIFEER; /* Wakeup/Interrupt Falling-Edge Event Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IFE:32;
+ } B;
+ } WIFER; /* Wakeup/Interrupt Filter Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IPUE:32;
+ } B;
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
+
+ }; /* end of WKUP_tag */
+/****************************************************************************/
+/* MODULE : LINFLEX */
+/****************************************************************************/
+
+ struct LINFLEX_tag {
+
+ int16_t LINFLEX_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CCD:1;
+ vuint16_t CFD:1;
+ vuint16_t LASE:1;
+ vuint16_t AWUM:1; // LCH vuint16_t AUTOWU:1;
+ vuint16_t MBL:4;
+ vuint16_t BF:1;
+ vuint16_t SFTM:1;
+ vuint16_t LBKM:1;
+ vuint16_t MME:1;
+ vuint16_t SBDT:1; // LCH vuint16_t SSBL:1;
+ vuint16_t RBLM:1;
+ vuint16_t SLEEP:1;
+ vuint16_t INIT:1;
+ } B;
+ } LINCR1; /* LINFLEX LIN Control Register 1 */
+
+ int16_t LINFLEX_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZIE:1;
+ vuint16_t OCIE:1;
+ vuint16_t BEIE:1;
+ vuint16_t CEIE:1;
+ vuint16_t HEIE:1;
+ vuint16_t:2;
+ vuint16_t FEIE:1;
+ vuint16_t BOIE:1;
+ vuint16_t LSIE:1;
+ vuint16_t WUIE:1;
+ vuint16_t DBFIE:1;
+ vuint16_t DBEIE:1;
+ vuint16_t DRIE:1;
+ vuint16_t DTIE:1;
+ vuint16_t HRIE:1;
+ } B;
+ } LINIER; /* LINFLEX LIN Interrupt Enable Register */
+
+ int16_t LINFLEX_reserved3;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LINS:4;
+ vuint16_t:2;
+ vuint16_t RMB:1;
+ vuint16_t:1;
+ vuint16_t RBSY:1; // LCH vuint16_t RXBUSY:1;
+ vuint16_t RPS:1; // LCH vuint16_t RDI:1;
+ vuint16_t WUF:1;
+ vuint16_t DBFF:1;
+ vuint16_t DBEF:1;
+ vuint16_t DRF:1;
+ vuint16_t DTF:1;
+ vuint16_t HRF:1;
+ } B;
+ } LINSR; /* LINFLEX LIN Status Register */
+
+ int16_t LINFLEX_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF:1;
+ vuint16_t OCF:1;
+ vuint16_t BEF:1;
+ vuint16_t CEF:1;
+ vuint16_t SFEF:1;
+ vuint16_t BDEF:1;
+ vuint16_t IDPEF:1;
+ vuint16_t FEF:1;
+ vuint16_t BOF:1;
+ vuint16_t:6;
+ vuint16_t NF:1;
+ } B;
+ } LINESR; /* LINFLEX LIN Error Status Register */
+
+ int16_t LINFLEX_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t TDFL:2;
+ vuint16_t:1;
+ vuint16_t RDFL:2;
+ vuint16_t:4;
+ vuint16_t RXEN:1;
+ vuint16_t TXEN:1;
+ vuint16_t OP:1; //LCH vuint16_t PARITYODD:1;
+ vuint16_t PCE:1;
+ vuint16_t WL:1;
+ vuint16_t UART:1;
+ } B;
+ } UARTCR; /* LINFLEX UART Mode Control Register */
+
+ int16_t LINFLEX_reserved6;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SZF:1;
+ vuint16_t OCF:1;
+ vuint16_t PE:4;
+ vuint16_t RMB:1;
+ vuint16_t FEF:1;
+ vuint16_t BOF:1;
+ vuint16_t RPS:1; // LCH vuint16_t RDI:1;
+ vuint16_t WUF:1;
+ vuint16_t:2;
+ vuint16_t DRF:1;
+ vuint16_t DTF:1;
+ vuint16_t NF:1;
+ } B;
+ } UARTSR; /* LINFLEX UART Mode Status Register */
+
+ int16_t LINFLEX_reserved7;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t LTOM:1; //LCH vuint16_t MODE:1;
+ vuint16_t IOT:1;
+ vuint16_t TOCE:1;
+ vuint16_t CNT:8;
+ } B;
+ } LINTCSR; /* LINFLEX LIN Time-Out Control Status Register */
+
+ int16_t LINFLEX_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OC2:8;
+ vuint16_t OC1:8;
+ } B;
+ } LINOCR; /* LINFLEX LIN Output Compare Register */
+
+ int16_t LINFLEX_reserved9;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t RTO:4; // LCH vuint16_t RTC:4;
+ vuint16_t:1;
+ vuint16_t HTO:7; // LCH vuint16_t HTC:7;
+ } B;
+ } LINTOCR; /* LINFLEX LIN Output Compare Register */
+
+ int16_t LINFLEX_reserved10;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t DIV_F:4; // LCH vuint16_t FBR:4;
+ } B;
+ } LINFBRR; /* LINFLEX LIN Fractional Baud Rate Register */
+
+ int16_t LINFLEX_reserved11;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DIV_M:13; // LCH vuint16_t IBR:13;
+ } B;
+ } LINIBRR; /* LINFLEX LIN Integer Baud Rate Register */
+
+ int16_t LINFLEX_reserved12;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t CF:8;
+ } B;
+ } LINCFR; /* LINFLEX LIN Checksum Field Register */
+
+ int16_t LINFLEX_reserved13;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t IOBE:1;
+ vuint16_t IOPE:1;
+ vuint16_t WURQ:1;
+ vuint16_t DDRQ:1;
+ vuint16_t DTRQ:1;
+ vuint16_t ABRQ:1;
+ vuint16_t HTRQ:1;
+ vuint16_t:8;
+ } B;
+ } LINCR2; /* LINFLEX LIN Control Register 2 */
+
+ int16_t LINFLEX_reserved14;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DFL:6;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2; // LCH vuint16_t:1;
+ vuint16_t ID:6;
+ } B;
+ } BIDR; /* LINFLEX Buffer Identifier Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL; /* LINFLEX Buffer Data Register Least Significant */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM; /* LINFLEX Buffer Data Register Most Significant */
+
+ int16_t LINFLEX_reserved15;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t FACT:8;
+ } B;
+ } IFER; /* LINFLEX Identifier Filter Enable Register */
+
+ int16_t LINFLEX_reserved16;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t IFMI:4;
+ } B;
+ } IFMI; /* LINFLEX Identifier Filter Match Index Register */
+
+ int16_t LINFLEX_reserved17;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t IFM:4;
+ } B;
+ } IFMR; /* LINFLEX Identifier Filter Mode Register */
+
+ int16_t LINFLEX_reserved18;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR0; /* LINFLEX Identifier Filter Control Register 0 */
+
+ int16_t LINFLEX_reserved19;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR1; /* LINFLEX Identifier Filter Control Register 1 */
+
+ int16_t LINFLEX_reserved20;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR2; /* LINFLEX Identifier Filter Control Register 2 */
+
+ int16_t LINFLEX_reserved21;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR3; /* LINFLEX Identifier Filter Control Register 3 */
+
+ int16_t LINFLEX_reserved22;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR4; /* LINFLEX Identifier Filter Control Register 4 */
+
+ int16_t LINFLEX_reserved23;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR5; /* LINFLEX Identifier Filter Control Register 5 */
+
+ int16_t LINFLEX_reserved24;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR6; /* LINFLEX Identifier Filter Control Register 6 */
+
+ int16_t LINFLEX_reserved25;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t DFL:3;
+ vuint16_t DIR:1;
+ vuint16_t CCS:1;
+ vuint16_t:2;
+ vuint16_t ID:6;
+ } B;
+ } IFCR7; /* LINFLEX Identifier Filter Control Register 7 */
+
+ }; /* end of LINFLEX_tag */
+/****************************************************************************/
+/* MODULE : ME */
+/****************************************************************************/
+ struct ME_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t S_CURRENTMODE:4;
+ vuint32_t S_MTRANS:1;
+ vuint32_t S_DC:1;
+ vuint32_t:2;
+ vuint32_t S_PDO:1;
+ vuint32_t:2;
+ vuint32_t S_MVR:1;
+ vuint32_t S_DFLA:2;
+ vuint32_t S_CFLA:2;
+ vuint32_t:8;
+ vuint32_t S_PLL1:1;
+ vuint32_t S_PLL0:1;
+ vuint32_t S_OSC:1;
+ vuint32_t S_RC:1;
+ vuint32_t S_SYSCLK:4;
+ } B;
+ } GS; /* Global Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TARGET_MODE:4;
+ vuint32_t:12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL; /* Mode Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } MER; /* Mode Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t I_CONF:1;
+ vuint32_t I_MODE:1;
+ vuint32_t I_SAFE:1;
+ vuint32_t I_MTC:1;
+ } B;
+ } IS; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t M_CONF:1;
+ vuint32_t M_MODE:1;
+ vuint32_t M_SAFE:1;
+ vuint32_t M_TC:1;
+ } B;
+ } IM; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t S_MTI:1;
+ vuint32_t S_MRI:1;
+ vuint32_t S_DMA:1;
+ vuint32_t S_NMA:1;
+ vuint32_t S_SEA:1;
+ } B;
+ } IMTS; /* Invalid Mode Transition Status Register */
+
+ int32_t ME_reserved0[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET; /* Reset Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST; /* Test Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE; /* Safe Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN; /* DRUN Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN[4]; /* RUN 0->4 Mode Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT0; /* HALT0 Mode Configuration Register */
+
+ int32_t ME_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP0; /* STOP0 Mode Configuration Register */
+
+ int32_t ME_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1;
+ vuint32_t:2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t:8;
+ vuint32_t PLL2ON:1;
+ vuint32_t PLL1ON:1;
+ vuint32_t XOSC0ON:1;
+ vuint32_t IRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY0; /* STANDBY0 Mode Configuration Register */
+
+ int32_t ME_reserved3[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PERIPH:32;
+ } B;
+ } PS[4]; /* Peripheral Status 0->4 Register */
+
+ int32_t ME_reserved4[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC[8]; /* RUN Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STANDBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t:8;
+ } B;
+ } LPPC[8]; /* Low Power Peripheral Configuration 0->7 Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t DBG_F:1;
+ vuint8_t LP_CFG:3;
+ vuint8_t RUN_CFG:3;
+ } B;
+ } PCTL[144]; /* Peripheral Control 0->143 Register */
+
+ }; /* end of ME_tag */
+/****************************************************************************/
+/* MODULE : CGM */
+/****************************************************************************/
+ struct CGM_tag {
+
+ /* The CGM provides a unified register interface, enabling access to
+ all clock sources:
+
+ Clock Type | Starting Address Map | Associated Clock Sources
+ ------------------------------------------------------------
+ System | C3FE0000 | OSC_CTL
+ " | - | Reserved
+ " | C3FE0040 | LPOSC_CTL
+ " | C3FE0060 | RC_CTL
+ " | C3FE0080 | LPRC_CTL
+ " | C3FE00A0 | FMPLL_0
+ " | C3FE00C0 | FMPLL_1
+ " | - | Reserved
+ MISC | C3FE0100 | CMU_0 & CMU_1
+
+ */
+
+ /************************************/
+ /* OSC_CTL @ CGM base address + 0x0000 */
+ /************************************/
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } OSC_CTL; /* Main OSC Control Register */
+
+ /************************************/
+ /* LPOSC_CTL @ CGM base address + 0x0040 */
+ /************************************/
+ int32_t CGM_reserved0[15]; /* (0x040 - 0x004)/4 = 0x0F */
+ /*int32_t $RESERVED[15]; */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t:7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t:2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } LPOSC_CTL; /* Low Power OSC Control Register */
+
+ /************************************/
+ /* RC_CTL @ CGM base address + 0x0060 */
+ /************************************/
+ int32_t CGM_reserved1[7]; /* (0x060 - 0x044)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t RCTRIM:6;
+ vuint32_t:3;
+ vuint32_t RCDIV:5;
+ vuint32_t:2;
+ vuint32_t S_RC_STDBY:1;
+ vuint32_t:5;
+ } B;
+ } RC_CTL; /* RC OSC Control Register */
+
+ /*************************************/
+ /* LPRC_CTL @ CGM base address + 0x0080 */
+ /*************************************/
+ int32_t CGM_reserved2[7]; /* (0x080 - 0x064)/4 = 0x07 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t LRCTRIM:5;
+ vuint32_t:3;
+ vuint32_t LPRCDIV:5;
+ vuint32_t:3;
+ vuint32_t S_LPRC:1;
+ vuint32_t:3;
+ vuint32_t LPRCON_STDBY:1;
+ } B;
+ } LPRC_CTL; /* Low Power RC OSC Control Register */
+
+ /************************************/
+ /* FMPLL_0 @ CGM base address + 0x00A0 */
+ /* FMPLL_1 @ CGM base address + 0x0100 */
+ /************************************/
+ int32_t CGM_reserved3[7]; /* (0x0A0 - 0x084)/4 = 0x07 */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t IDF:4;
+ vuint32_t ODF:2;
+ vuint32_t:1;
+ vuint32_t NDIV:7;
+ vuint32_t:7;
+ vuint32_t EN_PLL_SW:1;
+ vuint32_t MODE:1;
+ vuint32_t UNLOCK_ONCE:1;
+ vuint32_t:1;
+ vuint32_t I_LOCK:1;
+ vuint32_t S_LOCK:1;
+ vuint32_t PLL_FAIL_MASK:1;
+ vuint32_t PLL_FAIL_FLAG:1;
+ vuint32_t:1;
+ } B;
+ } CR; /* FMPLL Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1;
+ vuint32_t:1;
+ vuint32_t SPRD_SEL:1;
+ vuint32_t MOD_PERIOD:13;
+ vuint32_t FM_EN:1;
+ vuint32_t INC_STEP:15;
+ } B;
+ } MR; /* FMPLL Modulation Register */
+
+ int32_t CGM_reserved4[6]; /* (0x0C0 - 0x0A8)/4 = 0x06 */
+ /* (0x0E0 - 0x0C8)/4 = 0x06 */
+
+ } FMPLL[2];
+
+ /************************************/
+ /* CMU @ CGM base address + 0x0100 */
+ /************************************/
+ int32_t CGM_reserved5[8]; /* (0x100 - 0x0E0)/4 = 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SFM:1;
+ vuint32_t:13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t:5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_0_CSR; /* Control Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t FD:20;
+ } B;
+ } CMU_0_FDR; /* Frequency Display Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HFREF_A:12;
+ } B;
+ } CMU_0_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t LFREF_A:12;
+ } B;
+ } CMU_0_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t FLCI_0:1;
+ vuint32_t FHHI_0:1;
+ vuint32_t FLLI_0:1;
+ vuint32_t OLRI:1;
+ } B;
+ } CMU_0_ISR; /* Interrupt Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } CMU_0_IMR; /* Interrupt Mask Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t MD:20;
+ } B;
+ } CMU_0_MDR; /* Measurement Duration Register */
+
+ int32_t CGM_reserved5A; /* (0x020 - 0x01C)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SFM:1;
+ vuint32_t:13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t:5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_1_CSR; /* Control Status Register */
+
+ int32_t CGM_reserved6; /* (0x028 - 0x024)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HFREF_A:12;
+ } B;
+ } CMU_1_HFREFR_A; /* High Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t LFREF_A:12;
+ } B;
+ } CMU_1_LFREFR_A; /* Low Frequency Reference Register PLL_A Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t FLCI_1:1;
+ vuint32_t FHHI_1:1;
+ vuint32_t FLLI_1:1;
+ vuint32_t:1;
+ } B;
+ } CMU_1_ISR; /* Interrupt Status Register */
+
+ /************************************/
+ /* CGM General Registers @ CGM base address + 0x0370 */
+ /************************************/
+ int32_t CGM_reserved7[143]; /* (0x370 - 0x134)/4 = 0x8F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t EN:1;
+ } B;
+ } OCEN; /* Output Clock Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t SELDIV:2;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } OCDSSC; /* Output Clock Division Select Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELSTAT:4;
+ vuint32_t:24;
+ } B;
+ } SCSS; /* System Clock Select Status */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } SCDC; /* GSystem Clock Divider Configuration 0->4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC0SC; /* Aux Clock 0 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC0DC; /* Aux Clock 0 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC1SC; /* Aux Clock 1 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC1DC; /* Aux Clock 1 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC2SC; /* Aux Clock 2 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC2DC; /* Aux Clock 2 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC3SC; /* Aux Clock 3 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC3DC; /* Aux Clock 3 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC4SC; /* Aux Clock 4 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC4DC; /* Aux Clock 4 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC5SC; /* Aux Clock 5 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC5DC; /* Aux Clock 5 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC6SC; /* Aux Clock 6 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC6DC; /* Aux Clock 6 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC7SC; /* Aux Clock 7 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC7DC; /* Aux Clock 7 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC8SC; /* Aux Clock 8 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC8DC; /* Aux Clock 8 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC9SC; /* Aux Clock 9 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC9DC; /* Aux Clock 9 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC10SC; /* Aux Clock 10 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC10DC; /* Aux Clock 10 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC11SC; /* Aux Clock 11 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC11DC; /* Aux Clock 11 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC12SC; /* Aux Clock 12 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC12DC; /* Aux Clock 12 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC13SC; /* Aux Clock 13 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC13DC; /* Aux Clock 13 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC14SC; /* Aux Clock 14 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC14DC; /* Aux Clock 14 Divider Configuration 0->3 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4;
+ vuint32_t:24;
+ } B;
+ } AC15SC; /* Aux Clock 15 Select Control */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1;
+ vuint32_t:3;
+ vuint32_t DIV0:4;
+ vuint32_t DE1:1;
+ vuint32_t:3;
+ vuint32_t DIV1:4;
+ vuint32_t DE2:1;
+ vuint32_t:3;
+ vuint32_t DIV2:4;
+ vuint32_t DE3:1;
+ vuint32_t:3;
+ vuint32_t DIV3:4;
+ } B;
+ } AC15DC; /* Aux Clock 15 Divider Configuration 0->3 */
+
+ }; /* end of CGM_tag */
+/****************************************************************************/
+/* MODULE : RGM */
+/****************************************************************************/
+ struct RGM_tag {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1;
+ vuint16_t:3;
+ vuint16_t F_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t F_PLL1:1;
+ vuint16_t F_FLASH:1;
+ vuint16_t F_LVD45:1;
+ vuint16_t F_CMU0_FHL:1;
+ vuint16_t F_CMU0_OLR:1;
+ vuint16_t F_PLL0:1;
+ vuint16_t F_CHKSTOP:1;
+ vuint16_t F_SOFT:1;
+ vuint16_t F_CORE:1;
+ vuint16_t F_JTAG:1;
+ } B;
+ } FES; /* Functional Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t POR:1;
+ vuint16_t:7;
+ vuint16_t F_COMP:1;
+ vuint16_t F_LVD27_IO:1;
+ vuint16_t F_LVD27_FLASH:1;
+ vuint16_t F_LVD27_VREG:1;
+ vuint16_t F_LVD27:1;
+ vuint16_t F_SWT:1;
+ vuint16_t F_LVD12_PD1:1;
+ vuint16_t F_LVD12_PD0:1;
+ } B;
+ } DES; /* Destructive Event Status */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1;
+ vuint16_t:3;
+ vuint16_t D_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t D_PLL1:1;
+ vuint16_t D_FLASH:1;
+ vuint16_t D_LVD45:1;
+ vuint16_t D_CMU0_FHL:1;
+ vuint16_t D_CMU0_OLR:1;
+ vuint16_t D_PLL0:1;
+ vuint16_t D_CHKSTOP:1;
+ vuint16_t D_SOFT:1;
+ vuint16_t D_CORE:1;
+ vuint16_t D_JTAG:1;
+ } B;
+ } FERD; /* Functional Event Reset Disable */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t D_COMP:1;
+ vuint16_t D_LVD27_IO:1;
+ vuint16_t D_LVD27_FLASH:1;
+ vuint16_t D_LVD27_VREG:1;
+ vuint16_t D_LVD27:1;
+ vuint16_t D_SWT:1;
+ vuint16_t D_LVD12_PD1:1;
+ vuint16_t D_LVD12_PD0:1;
+ } B;
+ } DERD; /* Destructive Event Reset Disable */
+
+ int16_t RGM_reserved0[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t AR_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t AR_PLL1:1;
+ vuint16_t AR_FLASH:1;
+ vuint16_t AR_LVD45:1;
+ vuint16_t AR_CMU0_FHL:1;
+ vuint16_t AR_CMU0_OLR:1;
+ vuint16_t AR_PLL0:1;
+ vuint16_t AR_CHKSTOP:1;
+ vuint16_t AR_SOFT:1;
+ vuint16_t AR_CORE:1;
+ vuint16_t AR_JTAG:1;
+ } B;
+ } FEAR; /* Functional Event Alternate Request */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t AR_COMP:1;
+ vuint16_t AR_LVD27_IO:1;
+ vuint16_t AR_LVD27_FLASH:1;
+ vuint16_t AR_LVD27_VREG:1;
+ vuint16_t AR_LVD27:1;
+ vuint16_t AR_SWT:1;
+ vuint16_t AR_LVD12_PD1:1;
+ vuint16_t AR_LVD12_PD0:1;
+ } B;
+ } DEAR; /* Destructive Event Alternate Request */
+
+ int16_t RGM_reserved1[2];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t SS_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t SS_PLL1:1;
+ vuint16_t SS_FLASH:1;
+ vuint16_t SS_LVD45:1;
+ vuint16_t SS_CMU0_FHL:1;
+ vuint16_t SS_CMU0_OLR:1;
+ vuint16_t SS_PLL0:1;
+ vuint16_t SS_CHKSTOP:1;
+ vuint16_t SS_SOFT:1;
+ vuint16_t SS_CORE:1;
+ vuint16_t SS_JTAG:1;
+ } B;
+ } FESS; /* Functional Event Short Sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t BOOT:1;
+ vuint16_t:4;
+ vuint16_t DRUND_FLA:1;
+ vuint16_t:1;
+ vuint16_t DRUNC_FLA:1;
+ } B;
+ } STDBY; /* STANDBY reset sequence */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t BE_CMU1_FHL:1;
+ vuint16_t:1;
+ vuint16_t BE_PLL1:1;
+ vuint16_t BE_FLASH:1;
+ vuint16_t BE_LVD45:1;
+ vuint16_t BE_CMU0_FHL:1;
+ vuint16_t BE_CMU0_OLR:1;
+ vuint16_t BE_PLL0:1;
+ vuint16_t BE_CHKSTOP:1;
+ vuint16_t BE_SOFT:1;
+ vuint16_t BE_CORE:1;
+ vuint16_t BE_JTAG:1;
+ } B;
+ } FBRE; /* Functional Bidirectional Reset Enable */
+
+ }; /* end of RGM_tag */
+/****************************************************************************/
+/* MODULE : PCU */
+/****************************************************************************/
+ struct PCU_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STBY0:1;
+ vuint32_t:2;
+ vuint32_t STOP0:1;
+ vuint32_t:1;
+ vuint32_t HALT0:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RST:1;
+ } B;
+ } PCONF[16]; /* Power domain 0-15 configuration register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PD15:1;
+ vuint32_t PD14:1;
+ vuint32_t PD13:1;
+ vuint32_t PD12:1;
+ vuint32_t PD11:1;
+ vuint32_t PD10:1;
+ vuint32_t PD9:1;
+ vuint32_t PD8:1;
+ vuint32_t PD7:1;
+ vuint32_t PD6:1;
+ vuint32_t PD5:1;
+ vuint32_t PD4:1;
+ vuint32_t PD3:1;
+ vuint32_t PD2:1;
+ vuint32_t PD1:1;
+ vuint32_t PD0:1;
+ } B;
+ } PSTAT; /* Power Domain Status Register */
+
+ int32_t PCU_reserved0[15]; /* {0x0080-0x0044}/0x4 = 0xF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t MASK_LVDHV5:1;
+ } B;
+ } VCTL; /* Voltage Regulator Control Register */
+
+ }; /* end of PCU_tag */
+/****************************************************************************/
+/* MODULE : FLEXPWM */
+/****************************************************************************/
+ struct FLEXPWM_SUB_tag {
+
+ union {
+ vuint16_t R;
+ } CNT; /* Counter Register */
+
+ union {
+ vuint16_t R;
+ } INIT; /* Initial Count Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DBGEN:1;
+ vuint16_t WAITEN:1;
+ vuint16_t INDEP:1;
+ vuint16_t PWMA_INIT:1;
+ vuint16_t PWMB_INIT:1;
+ vuint16_t PWMX_INIT:1;
+ vuint16_t INIT_SEL:2;
+ vuint16_t FRCEN:1;
+ vuint16_t FORCE:1;
+ vuint16_t FORCE_SEL:3;
+ vuint16_t RELOAD_SEL:1;
+ vuint16_t CLK_SEL:2;
+ } B;
+ } CTRL2; /* Control 2 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LDFQ:4;
+ vuint16_t HALF:1;
+ vuint16_t FULL:1;
+ vuint16_t DT:2;
+ vuint16_t:1;
+ vuint16_t PRSC:3;
+ vuint16_t:3;
+ vuint16_t DBLEN:1;
+ } B;
+ } CTRL; /* Control Register */
+
+ union {
+ vuint16_t R;
+ } VAL[6]; /* Value Register 0->5 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRACAEN:1;
+ vuint16_t:10;
+ vuint16_t FRACADLY:5;
+ } B;
+ } FRACA; /* Fractional Delay Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRACBEN:1;
+ vuint16_t:10;
+ vuint16_t FRACBDLY:5;
+ } B;
+ } FRACB; /* Fractional Delay Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t PWMA_IN:1;
+ vuint16_t PWMB_IN:1;
+ vuint16_t PWMX_IN:1;
+ vuint16_t:2;
+ vuint16_t POLA:1;
+ vuint16_t POLB:1;
+ vuint16_t POLX:1;
+ vuint16_t:2;
+ vuint16_t PWMAFS:2;
+ vuint16_t PWMBFS:2;
+ vuint16_t PWMXFS:2;
+ } B;
+ } OCTRL; /* Output Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t RUF:1;
+ vuint16_t REF:1;
+ vuint16_t RF:1;
+ vuint16_t CFA1:1;
+ vuint16_t CFA0:1;
+ vuint16_t CFB1:1;
+ vuint16_t CFB0:1;
+ vuint16_t CFX1:1;
+ vuint16_t CFX0:1;
+ vuint16_t CMPF:6;
+ } B;
+ } STS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t REIE:1;
+ vuint16_t RIE:1;
+ vuint16_t:4;
+ vuint16_t CX1IE:1;
+ vuint16_t CX0IE:1;
+ vuint16_t CMPIE:6;
+ } B;
+ } INTEN; /* Interrupt Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t VALDE:1;
+ vuint16_t FAND:1;
+ vuint16_t CAPTDE:2;
+ vuint16_t CA1DE:1;
+ vuint16_t CA0DE:1;
+ vuint16_t CB1DE:1;
+ vuint16_t CB0DE:1;
+ vuint16_t CX1DE:1;
+ vuint16_t CX0DE:1;
+ } B;
+ } DMAEN; /* DMA Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:10;
+ vuint16_t OUT_TRIG_EN:6;
+ } B;
+ } TCTRL; /* Output Trigger Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t DISX:4;
+ vuint16_t DISB:4;
+ vuint16_t DISA:4;
+ } B;
+ } DISMAP; /* Fault Disable Mapping Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t DTCNT0:11;
+ } B;
+ } DTCNT0; /* Deadtime Count Register 0 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t DTCNT1:11;
+ } B;
+ } DTCNT1; /* Deadtime Count Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CA1CNT:3;
+ vuint16_t CA0CNT:3;
+ vuint16_t CFAWM:2;
+ vuint16_t EDGCNTAEN:1;
+ vuint16_t INPSELA:1;
+ vuint16_t EDGA1:2;
+ vuint16_t EDGA0:2;
+ vuint16_t ONESHOTA:1;
+ vuint16_t ARMA:1;
+ } B;
+ } CAPTCTRLA; /* Capture Control Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTA:8;
+ vuint16_t EDGCMPA:8;
+ } B;
+ } CAPTCOMPA; /* Capture Compare Register A */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CB1CNT:3;
+ vuint16_t CB0CNT:3;
+ vuint16_t CFBWM:2;
+ vuint16_t EDGCNTBEN:1;
+ vuint16_t INPSELB:1;
+ vuint16_t EDGB1:2;
+ vuint16_t EDGB0:2;
+ vuint16_t ONESHOTB:1;
+ vuint16_t ARMB:1;
+ } B;
+ } CAPTCTRLB; /* Capture Control Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTB:8;
+ vuint16_t EDGCMPB:8;
+ } B;
+ } CAPTCOMPB; /* Capture Compare Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CX1CNT:3;
+ vuint16_t CX0CNT:3;
+ vuint16_t CFXWM:2;
+ vuint16_t EDGCNTX_EN:1;
+ vuint16_t INP_SELX:1;
+ vuint16_t EDGX1:2;
+ vuint16_t EDGX0:2;
+ vuint16_t ONESHOTX:1;
+ vuint16_t ARMX:1;
+ } B;
+ } CAPTCTRLX; /* Capture Control Register B */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTX:8;
+ vuint16_t EDGCMPX:8;
+ } B;
+ } CAPTCOMPX; /* Capture Compare Register X */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL0:16;
+ } B;
+ } CVAL0; /* Capture Value 0 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL0CYC:4;
+ } B;
+ } CVAL0C; /* Capture Value 0 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL1:16;
+ } B;
+ } CVAL1; /* Capture Value 1 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL1CYC:4;
+ } B;
+ } CVAL1C; /* Capture Value 1 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL2:16;
+ } B;
+ } CVAL2; /* Capture Value 2 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL2CYC:4;
+ } B;
+ } CVAL2C; /* Capture Value 2 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL3:16;
+ } B;
+ } CVAL3; /* Capture Value 3 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL3CYC:4;
+ } B;
+ } CVAL3C; /* Capture Value 3 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL4:16;
+ } B;
+ } CVAL4; /* Capture Value 4 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL4CYC:4;
+ } B;
+ } CVAL4C; /* Capture Value 4 Cycle Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL5:16;
+ } B;
+ } CVAL5; /* Capture Value 5 Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL5CYC:4;
+ } B;
+ } CVAL5C; /* Capture Value 5 Cycle Register */
+
+ uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
+
+ }; /* end of FLEXPWM_SUB_tag */
+
+ struct FLEXPWM_tag {
+
+ /* eg. FLEXPWM.SUB<[x]>.CNT.R {x = 0->3} */
+ struct FLEXPWM_SUB_tag SUB[4];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t PWMA_EN:4;
+ vuint16_t PWMB_EN:4;
+ vuint16_t PWMX_EN:4;
+ } B;
+ } OUTEN; /* Output Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t MASKA:4;
+ vuint16_t MASKB:4;
+ vuint16_t MASKX:4;
+ } B;
+ } MASK; /* Output Mask Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t OUTA_3:1;
+ vuint16_t OUTB_3:1;
+ vuint16_t OUTA_2:1;
+ vuint16_t OUTB_2:1;
+ vuint16_t OUTA_1:1;
+ vuint16_t OUTB_1:1;
+ vuint16_t OUTA_0:1;
+ vuint16_t OUTB_0:1;
+ } B;
+ } SWCOUT; /* Software Controlled Output Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t SELA_3:2;
+ vuint16_t SELB_3:2;
+ vuint16_t SELA_2:2;
+ vuint16_t SELB_2:2;
+ vuint16_t SELA_1:2;
+ vuint16_t SELB_1:2;
+ vuint16_t SELA_0:2;
+ vuint16_t SELB_0:2;
+ } B;
+ } DTSRCSEL; /* Deadtime Source Select Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t IPOL:4;
+ vuint16_t RUN:4;
+ vuint16_t CLDOK:4;
+ vuint16_t LDOK:4;
+ } B;
+ } MCTRL; /* Master Control Register */
+
+ int16_t FLEXPWM_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FLVL:4;
+ vuint16_t FAUTO:4;
+ vuint16_t FSAFE:4;
+ vuint16_t FIE:4;
+ } B;
+ } FCTRL; /* Fault Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t FTEST:1;
+ vuint16_t FFPIN:4;
+ vuint16_t:4;
+ vuint16_t FFLAG:4;
+ } B;
+ } FSTS; /* Fault Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FILT_CNT:3;
+ vuint16_t FILT_PER:8;
+ } B;
+ } FFILT; /* Fault FilterRegister */
+
+ }; /* end of FLEXPWM_tag */
+/****************************************************************************/
+/* MODULE : ETIMER */
+/****************************************************************************/
+ struct ETIMER_CHANNEL_tag {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t COMP1:16;
+ } B;
+ } COMP1; /* Compare Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t COMP2:16;
+ } B;
+ } COMP2; /* Compare Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT1:16;
+ } B;
+ } CAPT1; /* Capture Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT2:16;
+ } B;
+ } CAPT2; /* Capture Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t LOAD:16;
+ } B;
+ } LOAD; /* Load Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t HOLD:16;
+ } B;
+ } HOLD; /* Hold Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CNTR:16;
+ } B;
+ } CNTR; /* Counter Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CNTMODE:3;
+ vuint16_t PRISRC:5;
+ vuint16_t ONCE:1;
+ vuint16_t LENGTH:1;
+ vuint16_t DIR:1;
+ vuint16_t SECSRC:5;
+ } B;
+ } CTRL; /* Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t OEN:1;
+ vuint16_t RDNT:1;
+ vuint16_t INPUT:1;
+ vuint16_t VAL:1;
+ vuint16_t FORCE:1;
+ vuint16_t COFRC:1;
+ vuint16_t COINIT:2;
+ vuint16_t SIPS:1;
+ vuint16_t PIPS:1;
+ vuint16_t OPS:1;
+ vuint16_t MSTR:1;
+ vuint16_t OUTMODE:4;
+ } B;
+ } CTRL2; /* Control Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t STPEN:1;
+ vuint16_t ROC:2;
+ vuint16_t FMODE:1;
+ vuint16_t FDIS:4;
+ vuint16_t C2FCNT:3;
+ vuint16_t C1FCNT:3;
+ vuint16_t DBGEN:2;
+ } B;
+ } CTRL3; /* Control Register 3 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t WDF:1;
+ vuint16_t RCF:1;
+ vuint16_t ICF2:1;
+ vuint16_t ICF1:1;
+ vuint16_t IEHF:1;
+ vuint16_t IELF:1;
+ vuint16_t TOF:1;
+ vuint16_t TCF2:1;
+ vuint16_t TCF1:1;
+ vuint16_t TCF:1;
+ } B;
+ } STS; /* Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ICF2DE:1;
+ vuint16_t ICF1DE:1;
+ vuint16_t CMPLD2DE:1;
+ vuint16_t CMPLD1DE:1;
+ vuint16_t:2;
+ vuint16_t WDFIE:1;
+ vuint16_t RCFIE:1;
+ vuint16_t ICF2IE:1;
+ vuint16_t ICF1IE:1;
+ vuint16_t IEHFIE:1;
+ vuint16_t IELFIE:1;
+ vuint16_t TOFIE:1;
+ vuint16_t TCF2IE:1;
+ vuint16_t TCF1IE:1;
+ vuint16_t TCFIE:1;
+ } B;
+ } INTDMA; /* Interrupt and DMA Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD1:16;
+ } B;
+ } CMPLD1; /* Compare Load Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD2:16;
+ } B;
+ } CMPLD2; /* Compare Load Register 2 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CLC2:3;
+ vuint16_t CLC1:3;
+ vuint16_t CMPMODE:2;
+ vuint16_t CPT2MODE:2;
+ vuint16_t CPT1MODE:2;
+ vuint16_t CFWM:2;
+ vuint16_t ONESHOT:1;
+ vuint16_t ARM:1;
+ } B;
+ } CCCTRL; /* Compare and Capture Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FILTCNT:3;
+ vuint16_t FILTPER:8;
+ } B;
+ } FILT; /* Input Filter Register */
+
+ }; /* end of ETIMER_CHANNEL_tag */
+
+ struct ETIMER_tag {
+
+ struct ETIMER_CHANNEL_tag CHANNEL[8];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOL:16;
+ } B;
+ } WDTOL; /* Watchdog Time-out Low Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOH:16;
+ } B;
+ } WDTOH; /* Watchdog Time-out High Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t FTEST:1;
+ vuint16_t FIE:4;
+ vuint16_t:4;
+ vuint16_t FLVL:4;
+ } B;
+ } FCTRL; /* Fault Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t FFPIN:4;
+ vuint16_t:4;
+ vuint16_t FFLAG:4;
+ } B;
+ } FSTS; /* Fault Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FFILTCNT:3;
+ vuint16_t FFILTPER:8;
+ } B;
+ } FFILT; /* Fault Filter Register */
+
+ int16_t ETIMER_reserved1;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t ENBL:8;
+ } B;
+ } ENBL; /* Channel Enable Register */
+
+ int16_t ETIMER_reserved2;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t DREQ:5;
+ } B;
+ } DREQ[4]; /* DMA Request 0->3 Select Register */
+
+ }; /* end of ETIMER_tag */
+
+/****************************************************************************/
+/* MODULE : CTUL */
+/****************************************************************************/
+ struct CTUL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PRESC_CONF:4;
+ vuint32_t:4;
+ vuint32_t TRGIEN:1;
+ vuint32_t TRGI:1;
+ vuint32_t:2;
+ vuint32_t CNT3_EN:1;
+ vuint32_t CNT2_EN:1;
+ vuint32_t CNT1_EN:1;
+ vuint32_t CNT0_EN:1;
+ } B;
+ } CSR; /* Control Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:23;
+ vuint32_t SV:9;
+ } B;
+ } SVR[7]; /* Start Value Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:23;
+ vuint32_t CV:9;
+ } B;
+ } CVR[4]; /* Current Value Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TM:1;
+ vuint32_t CNT:2;
+ vuint32_t DELAY:3;
+ vuint32_t:4;
+ vuint32_t CHANNELVALUE:6;
+ } B;
+ } EVTCFGR[64]; /* Event Configuration Register */
+
+ }; /* end of CTUL_tag */
+/****************************************************************************/
+/* MODULE : CTU */
+/****************************************************************************/
+ struct CTU_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t I15_FE:1;
+ vuint32_t I15_RE:1;
+ vuint32_t I14_FE:1;
+ vuint32_t I14_RE:1;
+ vuint32_t I13_FE:1;
+ vuint32_t I13_RE:1;
+ vuint32_t I12_FE:1;
+ vuint32_t I12_RE:1;
+ vuint32_t I11_FE:1;
+ vuint32_t I11_RE:1;
+ vuint32_t I10_FE:1;
+ vuint32_t I10_RE:1;
+ vuint32_t I9_FE:1;
+ vuint32_t I9_RE:1;
+ vuint32_t I8_FE:1;
+ vuint32_t I8_RE:1;
+ vuint32_t I7_FE:1;
+ vuint32_t I7_RE:1;
+ vuint32_t I6_FE:1;
+ vuint32_t I6_RE:1;
+ vuint32_t I5_FE:1;
+ vuint32_t I5_RE:1;
+ vuint32_t I4_FE:1;
+ vuint32_t I4_RE:1;
+ vuint32_t I3_FE:1;
+ vuint32_t I3_RE:1;
+ vuint32_t I2_FE:1;
+ vuint32_t I2_RE:1;
+ vuint32_t I1_FE:1;
+ vuint32_t I1_RE:1;
+ vuint32_t I0_FE:1;
+ vuint32_t I0_RE:1;
+ } B;
+ } TGSISR; /* -Trigger Generator Subunit Input Selection Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+ vuint16_t ETTM:1;
+ vuint16_t PRES:2;
+ vuint16_t MRSSM:5;
+ vuint16_t TGSM:1;
+ } B;
+ } TGSCR; /* Trigger Generator Subunit Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t TCRV:16;
+ } B;
+ } TCR[8]; /* Trigger 0->7 Compare Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t TGSCCV:16;
+ } B;
+ } TGSCCR; /* TGS Counter Compare Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t TGSCRV:16;
+ } B;
+ } TGSCRR; /* TGS Counter Reload Register */
+
+ uint16_t CTU_reserved0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t T3INDEX:5;
+ vuint32_t:3;
+ vuint32_t T2INDEX:5;
+ vuint32_t:3;
+ vuint32_t T1INDEX:5;
+ vuint32_t:3;
+ vuint32_t T0INDEX:5;
+ } B;
+ } CLCR1; /* Command List Control Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t T7INDEX:5;
+ vuint32_t:3;
+ vuint32_t T6INDEX:5;
+ vuint32_t:3;
+ vuint32_t T5INDEX:5;
+ vuint32_t:3;
+ vuint32_t T4INDEX:5;
+ } B;
+ } CLCR2; /* Command List Control Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t T3E:1;
+ vuint32_t T3ETE:1;
+ vuint32_t T3T1E:1;
+ vuint32_t T3T0E:1;
+ vuint32_t T3ADCE:1;
+ vuint32_t:3;
+ vuint32_t T2E:1;
+ vuint32_t T2ETE:1;
+ vuint32_t T2T1E:1;
+ vuint32_t T2T0E:1;
+ vuint32_t T2ADCE:1;
+ vuint32_t:3;
+ vuint32_t T1E:1;
+ vuint32_t T1ETE:1;
+ vuint32_t T1T1E:1;
+ vuint32_t T1T0E:1;
+ vuint32_t T1ADCE:1;
+ vuint32_t:3;
+ vuint32_t T0E:1;
+ vuint32_t T0ETE:1;
+ vuint32_t T0T1E:1;
+ vuint32_t T0T0E:1;
+ vuint32_t T0ADCE:1;
+ } B;
+ } THCR1; /* Trigger Handler Control Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t T7E:1;
+ vuint32_t T7ETE:1;
+ vuint32_t T7T1E:1;
+ vuint32_t T7T0E:1;
+ vuint32_t T7ADCE:1;
+ vuint32_t:3;
+ vuint32_t T6E:1;
+ vuint32_t T6ETE:1;
+ vuint32_t T6T1E:1;
+ vuint32_t T6T0E:1;
+ vuint32_t T6ADCE:1;
+ vuint32_t:3;
+ vuint32_t T5E:1;
+ vuint32_t T5ETE:1;
+ vuint32_t T5T1E:1;
+ vuint32_t T5T0E:1;
+ vuint32_t T5ADCE:1;
+ vuint32_t:3;
+ vuint32_t T4E:1;
+ vuint32_t T4ETE:1;
+ vuint32_t T4T1E:1;
+ vuint32_t T4T0E:1;
+ vuint32_t T4ADCE:1;
+ } B;
+ } THCR2; /* Trigger Handler Control Register 2 */
+
+ /* Single Conversion Mode - Comment for Dual Conversion Mode */
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t CIR:1;
+ vuint16_t FC:1;
+ vuint16_t CMS:1;
+ vuint16_t:1;
+ vuint16_t FIFO:2;
+ vuint16_t:4;
+ vuint16_t SU:1;
+ vuint16_t:1;
+ vuint16_t CH:4;
+ } B;
+ } CLR[24]; /* Commands List Register x (double-buffered) (x = 1,...,24) */
+
+ /* Uncomment for Dual Conversion Mode */
+ /*union {
+ vuint16_t R;
+ struct {
+ vuint16_t CIR:1;
+ vuint16_t FC:1;
+ vuint16_t CMS:1;
+ vuint16_t:1;
+ vuint16_t FIFO:2;
+ vuint16_t:1;
+ vuint16_t CHB:4;
+ vuint16_t :1;
+ vuint16_t CHA:4;
+ } B;
+ } CLR[24]; */
+ /* Commands List Register x (double-buffered) (x = 1,...,24) */
+
+ uint16_t CTU_reserved1[8];
+
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t DMAEN3:1;
+ vuint16_t DMAEN2:1;
+ vuint16_t DMAEN1:1;
+ vuint16_t DMAEN0:1;
+ } B;
+ } CR; /* Control Register */
+
+ uint16_t CTU_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FIFO_OVERRUN_EN7:1;
+ vuint32_t FIFO_OVERFLOW_EN7:1;
+ vuint32_t FIFO_EMPTY_EN7:1;
+ vuint32_t FIFO_FULL_EN7:1;
+ vuint32_t FIFO_OVERRUN_EN6:1;
+ vuint32_t FIFO_OVERFLOW_EN6:1;
+ vuint32_t FIFO_EMPTY_EN6:1;
+ vuint32_t FIFO_FULL_EN6:1;
+ vuint32_t FIFO_OVERRUN_EN5:1;
+ vuint32_t FIFO_OVERFLOW_EN5:1;
+ vuint32_t FIFO_EMPTY_EN5:1;
+ vuint32_t FIFO_FULL_EN5:1;
+ vuint32_t FIFO_OVERRUN_EN4:1;
+ vuint32_t FIFO_OVERFLOW_EN4:1;
+ vuint32_t FIFO_EMPTY_EN4:1;
+ vuint32_t FIFO_FULL_EN4:1;
+ vuint32_t FIFO_OVERRUN_EN3:1;
+ vuint32_t FIFO_OVERFLOW_EN3:1;
+ vuint32_t FIFO_EMPTY_EN3:1;
+ vuint32_t FIFO_FULL_EN3:1;
+ vuint32_t FIFO_OVERRUN_EN2:1;
+ vuint32_t FIFO_OVERFLOW_EN2:1;
+ vuint32_t FIFO_EMPTY_EN2:1;
+ vuint32_t FIFO_FULL_EN2:1;
+ vuint32_t FIFO_OVERRUN_EN1:1;
+ vuint32_t FIFO_OVERFLOW_EN1:1;
+ vuint32_t FIFO_EMPTY_EN1:1;
+ vuint32_t FIFO_FULL_EN1:1;
+ vuint32_t FIFO_OVERRUN_EN0:1;
+ vuint32_t FIFO_OVERFLOW_EN0:1;
+ vuint32_t FIFO_EMPTY_EN0:1;
+ vuint32_t FIFO_FULL_EN0:1;
+ } B;
+ } FCR; /* CONTROL REGISTER FIFO */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t THRESHOLD3:8;
+ vuint32_t THRESHOLD2:8;
+ vuint32_t THRESHOLD1:8;
+ vuint32_t THRESHOLD0:8;
+ } B;
+ } TH1; /* Threshold Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t THRESHOLD7:8;
+ vuint32_t THRESHOLD6:8;
+ vuint32_t THRESHOLD5:8;
+ vuint32_t THRESHOLD4:8;
+ } B;
+ } TH2; /* Threshold Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FIFO_OVERRUN7:1;
+ vuint32_t FIFO_OVERFLOW7:1;
+ vuint32_t FIFO_EMPTY7:1;
+ vuint32_t FIFO_FULL7:1;
+ vuint32_t FIFO_OVERRUN6:1;
+ vuint32_t FIFO_OVERFLOW6:1;
+ vuint32_t FIFO_EMPTY6:1;
+ vuint32_t FIFO_FULL6:1;
+ vuint32_t FIFO_OVERRUN5:1;
+ vuint32_t FIFO_OVERFLOW5:1;
+ vuint32_t FIFO_EMPTY5:1;
+ vuint32_t FIFO_FULL5:1;
+ vuint32_t FIFO_OVERRUN4:1;
+ vuint32_t FIFO_OVERFLOW4:1;
+ vuint32_t FIFO_EMPTY4:1;
+ vuint32_t FIFO_FULL4:1;
+ vuint32_t FIFO_OVERRUN3:1;
+ vuint32_t FIFO_OVERFLOW3:1;
+ vuint32_t FIFO_EMPTY3:1;
+ vuint32_t FIFO_FULL3:1;
+ vuint32_t FIFO_OVERRUN2:1;
+ vuint32_t FIFO_OVERFLOW2:1;
+ vuint32_t FIFO_EMPTY2:1;
+ vuint32_t FIFO_FULL2:1;
+ vuint32_t FIFO_OVERRUN1:1;
+ vuint32_t FIFO_OVERFLOW1:1;
+ vuint32_t FIFO_EMPTY1:1;
+ vuint32_t FIFO_FULL1:1;
+ vuint32_t FIFO_OVERRUN0:1;
+ vuint32_t FIFO_OVERFLOW0:1;
+ vuint32_t FIFO_EMPTY0:1;
+ vuint32_t FIFO_FULL0:1;
+ } B;
+ } STATUS; /* STATUS REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t NCH:5;
+ vuint32_t:6;
+ vuint32_t DATA:10;
+ } B;
+ } FRA[8]; /* FIFO RIGHT aligned REGISTER */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t NCH:5;
+ vuint32_t DATA:10;
+ vuint32_t:6;
+ } B;
+ } FLA[8]; /* FIFO LEFT aligned REGISTER */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+ vuint16_t ETOE:1;
+ vuint16_t T1OE:1;
+ vuint16_t T0OE:1;
+ vuint16_t ADCOE:1;
+ vuint16_t TGSOSM:1;
+ vuint16_t MRSO:1;
+ vuint16_t ICE:1;
+ vuint16_t SMTO:1;
+ vuint16_t MRSRE:1;
+ } B;
+ } CTUEFR; /* Cross Triggering Unit Error Flag Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t ADC:1;
+ vuint16_t T7:1;
+ vuint16_t T6:1;
+ vuint16_t T5:1;
+ vuint16_t T4:1;
+ vuint16_t T3:1;
+ vuint16_t T2:1;
+ vuint16_t T1:1;
+ vuint16_t T0:1;
+ vuint16_t MRS:1;
+ } B;
+ } CTUIFR; /* Cross Triggering Unit Interrupt Flag Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t T7IE:1;
+ vuint16_t T6IE:1;
+ vuint16_t T5IE:1;
+ vuint16_t T4IE:1;
+ vuint16_t T3IE:1;
+ vuint16_t T2IE:1;
+ vuint16_t T1IE:1;
+ vuint16_t T0IE:1;
+ vuint16_t:5;
+ vuint16_t MRSDMAE:1;
+ vuint16_t MRSIE:1;
+ vuint16_t IEE:1;
+ } B;
+ } CTUIR; /* Cross Triggering Unit Interrupt/DMA Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t COTR:8;
+ } B;
+ } COTR; /* Control On-Time Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t T7SG:1;
+ vuint16_t T6SG:1;
+ vuint16_t T5SG:1;
+ vuint16_t T4SG:1;
+ vuint16_t T3SG:1;
+ vuint16_t T2SG:1;
+ vuint16_t T1SG:1;
+ vuint16_t T0SG:1;
+ vuint16_t CTUADCRESET:1;
+ vuint16_t CTUODIS:1;
+ vuint16_t FILTERENABLE:1;
+ vuint16_t CGRE:1;
+ vuint16_t FGRE:1;
+ vuint16_t MRSSG:1;
+ vuint16_t GRE:1;
+ vuint16_t TGSISRRE:1;
+ } B;
+ } CTUCR; /* Cross Triggering Unit Control Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t FILTERVALUE:8;
+ } B;
+ } CTUFILTER; /* Cross Triggering Unit Digital Filter */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:15;
+ vuint16_t MDIS:1;
+ } B;
+ } CTUPCR; /* Cross Triggering Unit Power Control */
+
+ }; /* end of CTU_tag */
+/****************************************************************************/
+/* MODULE : FCU */
+/****************************************************************************/
+ struct FCU_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MCL:1;
+ vuint32_t TM:2;
+ vuint32_t:19;
+ vuint32_t PS:2;
+ vuint32_t FOM:2;
+ vuint32_t FOP:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SRF0:1;
+ vuint32_t SRF1:1;
+ vuint32_t SRF2:1;
+ vuint32_t SRF3:1;
+ vuint32_t SRF4:1;
+ vuint32_t SRF5:1;
+ vuint32_t SRF6:1;
+ vuint32_t SRF7:1;
+ vuint32_t SRF8:1;
+ vuint32_t SRF9:1;
+ vuint32_t SRF10:1;
+ vuint32_t SRF11:1;
+ vuint32_t SRF12:1;
+ vuint32_t SRF13:1;
+ vuint32_t SRF14:1;
+ vuint32_t SRF15:1;
+ vuint32_t HRF15:1;
+ vuint32_t HRF14:1;
+ vuint32_t HRF13:1;
+ vuint32_t HRF12:1;
+ vuint32_t HRF11:1;
+ vuint32_t HRF10:1;
+ vuint32_t HRF9:1;
+ vuint32_t HRF8:1;
+ vuint32_t HRF7:1;
+ vuint32_t HRF6:1;
+ vuint32_t HRF5:1;
+ vuint32_t HRF4:1;
+ vuint32_t HRF3:1;
+ vuint32_t HRF2:1;
+ vuint32_t HRF1:1;
+ vuint32_t HRF0:1;
+ } B;
+ } FFR; /* Fault Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FRSRF0:1;
+ vuint32_t FRSRF1:1;
+ vuint32_t FRSRF2:1;
+ vuint32_t FRSRF3:1;
+ vuint32_t FRSRF4:1;
+ vuint32_t FRSRF5:1;
+ vuint32_t FRSRF6:1;
+ vuint32_t FRSRF7:1;
+ vuint32_t FRSRF8:1;
+ vuint32_t FRSRF9:1;
+ vuint32_t FRSRF10:1;
+ vuint32_t FRSRF11:1;
+ vuint32_t FRSRF12:1;
+ vuint32_t FRSRF13:1;
+ vuint32_t FRSRF14:1;
+ vuint32_t FRSRF15:1;
+ vuint32_t FRHRF15:1;
+ vuint32_t FRHRF14:1;
+ vuint32_t FRHRF13:1;
+ vuint32_t FRHRF12:1;
+ vuint32_t FRHRF11:1;
+ vuint32_t FRHRF10:1;
+ vuint32_t FRHRF9:1;
+ vuint32_t FRHRF8:1;
+ vuint32_t FRHRF7:1;
+ vuint32_t FRHRF6:1;
+ vuint32_t FRHRF5:1;
+ vuint32_t FRHRF4:1;
+ vuint32_t FRHRF3:1;
+ vuint32_t FRHRF2:1;
+ vuint32_t FRHRF1:1;
+ vuint32_t FRHRF0:1;
+ } B;
+ } FFFR; /* Frozen Fault Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t FSRF2:1;
+ vuint32_t FSRF3:1;
+ vuint32_t FSRF4:1;
+ vuint32_t FSRF5:1;
+ vuint32_t FSRF6:1;
+ vuint32_t FSRF7:1;
+ vuint32_t FSRF8:1;
+ vuint32_t FSRF9:1;
+ vuint32_t FSRF10:1;
+ vuint32_t FSRF11:1;
+ vuint32_t FSRF12:1;
+ vuint32_t FSRF13:1;
+ vuint32_t FSRF14:1;
+ vuint32_t FSRF15:1;
+ vuint32_t FHRF15:1;
+ vuint32_t FHRF14:1;
+ vuint32_t FHRF13:1;
+ vuint32_t FHRF12:1;
+ vuint32_t FHRF11:1;
+ vuint32_t FHRF10:1;
+ vuint32_t FHRF9:1;
+ vuint32_t FHRF8:1;
+ vuint32_t FHRF7:1;
+ vuint32_t FHRF6:1;
+ vuint32_t FHRF5:1;
+ vuint32_t FHRF4:1;
+ vuint32_t FHRF3:1;
+ vuint32_t FHRF2:1;
+ vuint32_t FHRF1:1;
+ vuint32_t FHRF0:1;
+ } B;
+ } FFGR; /* Fake Fault Generation Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ESF0:1;
+ vuint32_t ESF1:1;
+ vuint32_t ESF2:1;
+ vuint32_t ESF3:1;
+ vuint32_t ESF4:1;
+ vuint32_t ESF5:1;
+ vuint32_t ESF6:1;
+ vuint32_t ESF7:1;
+ vuint32_t ESF8:1;
+ vuint32_t ESF9:1;
+ vuint32_t ESF10:1;
+ vuint32_t ESF11:1;
+ vuint32_t ESF12:1;
+ vuint32_t ESF13:1;
+ vuint32_t ESF14:1;
+ vuint32_t ESF15:1;
+ vuint32_t EHF15:1;
+ vuint32_t EHF14:1;
+ vuint32_t EHF13:1;
+ vuint32_t EHF12:1;
+ vuint32_t EHF11:1;
+ vuint32_t EHF10:1;
+ vuint32_t EHF9:1;
+ vuint32_t EHF8:1;
+ vuint32_t EHF7:1;
+ vuint32_t EHF6:1;
+ vuint32_t EHF5:1;
+ vuint32_t EHF4:1;
+ vuint32_t EHF3:1;
+ vuint32_t EHF2:1;
+ vuint32_t EHF1:1;
+ vuint32_t EHF0:1;
+ } B;
+ } FER; /* Fault Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t KR:32;
+ } B;
+ } KR; /* Fault Collection Unit Key Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TR:32;
+ } B;
+ } TR; /* Fault Collection Unit Timeout Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TESF0:1;
+ vuint32_t TESF1:1;
+ vuint32_t TESF2:1;
+ vuint32_t TESF3:1;
+ vuint32_t TESF4:1;
+ vuint32_t TESF5:1;
+ vuint32_t TESF6:1;
+ vuint32_t TESF7:1;
+ vuint32_t TESF8:1;
+ vuint32_t TESF9:1;
+ vuint32_t TESF10:1;
+ vuint32_t TESF11:1;
+ vuint32_t TESF12:1;
+ vuint32_t TESF13:1;
+ vuint32_t TESF14:1;
+ vuint32_t TESF15:1;
+ vuint32_t TEHF15:1;
+ vuint32_t TEHF14:1;
+ vuint32_t TEHF13:1;
+ vuint32_t TEHF12:1;
+ vuint32_t TEHF11:1;
+ vuint32_t TEHF10:1;
+ vuint32_t TEHF9:1;
+ vuint32_t TEHF8:1;
+ vuint32_t TEHF7:1;
+ vuint32_t TEHF6:1;
+ vuint32_t TEHF5:1;
+ vuint32_t TEHF4:1;
+ vuint32_t TEHF3:1;
+ vuint32_t TEHF2:1;
+ vuint32_t TEHF1:1;
+ vuint32_t TEHF0:1;
+ } B;
+ } TER; /* Fault Collection Unit Timeout Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t S0:1;
+ vuint32_t S1:1;
+ vuint32_t S2:1;
+ vuint32_t S3:1;
+ } B;
+ } MSR; /* Module state register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t MCPS:4;
+ vuint32_t:12;
+ vuint32_t MCAS:4;
+ } B;
+ } MCSR; /* MC state register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t FRMCPS:4;
+ vuint32_t:12;
+ vuint32_t FRMCAS:4;
+ } B;
+ } FMCSR; /* Frozen MC State Register */
+
+ }; /* end of FCU_tag */
+/****************************************************************************/
+/* MODULE : SMC - Stepper Motor Control */
+/****************************************************************************/
+ struct SMC_tag {
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t MCPRE:2;
+ vuint8_t MCSWAI:1;
+ vuint8_t:1;
+ vuint8_t DITH:1;
+ vuint8_t:1;
+ vuint8_t MCTOIF:1;
+ } B;
+ } CTL0; /* Motor Controller Control Register 0 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t RECIRC:1;
+ vuint8_t:6;
+ vuint8_t MCTOIE:1;
+ } B;
+ } CTL1; /* Motor Controller Control Register 1 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t P:11;
+ } B;
+ } PER; /* Motor Controller Period Register */
+
+ int32_t SMC_reserved0[3]; /* (0x010 - 0x004)/4 = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t MCOM:2;
+ vuint8_t MCAM:2;
+ vuint8_t:2;
+ vuint8_t CD:2;
+ } B;
+ } CC[12]; /* Motor Controller Channel Control Register 0->11 */
+
+ int32_t SMC_reserved1; /* (0x020 - 0x01C)/4 = 0x01 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t S:5;
+ vuint16_t D:11;
+ } B;
+ } DC[12]; /* Motor Controller Duty Cycle Register 0->11 */
+
+ int8_t SMC_reserved2[8]; /* (0x040 - 0x038) = 0x08 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t TOUT:8;
+ } B;
+ } SDTO; /* Shortcut detector time-out register */
+
+ int8_t SMC_reserved3[3]; /* (0x044 - 0x041) = 0x03 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t EN:8;
+ } B;
+ } SDE[3]; /* Shortcut detector enable register 0->2 */
+
+ int8_t SMC_reserved4; /* (0x048 - 0x047) = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t IRQ_EN:8;
+ } B;
+ } SDIEN[3]; /* Shortcut detector interrupt enable register 0->2 */
+
+ int8_t SMC_reserved5; /* (0x04C - 0x04B) = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t IRQ:8;
+ } B;
+ } SDI[3]; /* Shortcut detector interrupt register 0->2 */
+
+ }; /* end of SMC_tag */
+/****************************************************************************/
+/* MODULE : SSD - Stepper Stall Detect */
+/****************************************************************************/
+ struct SSD_tag {
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t TRIG:1;
+ vuint16_t STEP:2;
+ vuint16_t RCIR:1;
+ vuint16_t ITGDIR:1;
+ vuint16_t BLNDCL:1;
+ vuint16_t ITGDCL:1;
+ vuint16_t RTZE:1;
+ vuint16_t:1;
+ vuint16_t BLNST:1;
+ vuint16_t ITGST:1;
+ vuint16_t:3;
+ vuint16_t SDCPU:1;
+ vuint16_t DZDIS:1;
+ } B;
+ } CONTROL; /* Control & Status Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t BLNIF:1;
+ vuint16_t ITGIF:1;
+ vuint16_t:5;
+ vuint16_t ACOVIF:1;
+ vuint16_t BLNIE:1;
+ vuint16_t ITGIE:1;
+ vuint16_t:5;
+ vuint16_t ACOVIE:1;
+ } B;
+ } IRQ; /* Interrupt Flag and Enable Register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ITGACC:16;
+ } B;
+ } ITGACC; /* Integrator Accumulator register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t DCNT:16;
+ } B;
+ } DCNT; /* Down Counter Count register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t BLNCNTLD:16;
+ } B;
+ } BLNCNTLD; /* Blanking Counter Load register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ITGCNTLD:16;
+ } B;
+ } ITGCNTLD; /* Integration Counter Load register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t BLNDIV:3;
+ vuint16_t:1;
+ vuint16_t ITSSDIV:3;
+ vuint16_t:2;
+ vuint16_t OFFCNC:2;
+ vuint16_t:1;
+ vuint16_t ACDIV:3;
+ } B;
+ } PRESCALE; /* Prescaler register */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t TMST:1;
+ vuint16_t ANLOUT:1;
+ vuint16_t ANLIN:1;
+ vuint16_t SSDEN:1;
+ vuint16_t STEP1:1;
+ vuint16_t POL:1;
+ vuint16_t ITG:1;
+ vuint16_t DACHIZ:1;
+ vuint16_t BUFHIZ:1;
+ vuint16_t AMPHIZ:1;
+ vuint16_t RESSHORT:1;
+ vuint16_t ITSSDRV:1;
+ vuint16_t ITSSDRVEN:1;
+ vuint16_t REFDRV:1;
+ vuint16_t REFDRVEN:1;
+ } B;
+ } FNTEST; /* Functional Test Mode register */
+
+ }; /* end of SSD_tag */
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+ struct EMIOS_CHANNEL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t CADR:24;
+ } B;
+ } CADR; /* Channel A Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t CBDR:24;
+ } B;
+ } CBDR; /* Channel B Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t CCNTR:24;
+ } B;
+ } CCNTR; /* Channel Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t ODIS:1;
+ vuint32_t ODISSL:2;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPEN:1;
+ vuint32_t DMA:1;
+ vuint32_t:1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t:3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t:1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR; /* Channel Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:15;
+ vuint32_t OVFL:1;
+ vuint32_t:12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR; /* Channel Status Register */
+
+ union {
+ vuint32_t R; /* Alternate Channel A Data Register */
+ } ALTCADR;
+
+ uint32_t emios_channel_reserved[2];
+
+ }; /* end of EMIOS_CHANNEL_tag */
+
+ struct EMIOS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t ETB:1;
+ vuint32_t GPREN:1;
+ vuint32_t:6;
+ vuint32_t SRV:4;
+ vuint32_t GPRE:8;
+ vuint32_t:8;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR; /* Global FLAG Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR; /* Output Update Disable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t CHDIS23:1;
+ vuint32_t CHDIS22:1;
+ vuint32_t CHDIS21:1;
+ vuint32_t CHDIS20:1;
+ vuint32_t CHDIS19:1;
+ vuint32_t CHDIS18:1;
+ vuint32_t CHDIS17:1;
+ vuint32_t CHDIS16:1;
+ vuint32_t CHDIS15:1;
+ vuint32_t CHDIS14:1;
+ vuint32_t CHDIS13:1;
+ vuint32_t CHDIS12:1;
+ vuint32_t CHDIS11:1;
+ vuint32_t CHDIS10:1;
+ vuint32_t CHDIS9:1;
+ vuint32_t CHDIS8:1;
+ vuint32_t CHDIS7:1;
+ vuint32_t CHDIS6:1;
+ vuint32_t CHDIS5:1;
+ vuint32_t CHDIS4:1;
+ vuint32_t CHDIS3:1;
+ vuint32_t CHDIS2:1;
+ vuint32_t CHDIS1:1;
+ vuint32_t CHDIS0:1;
+ } B;
+ } UCDIS; /* Disable Channel Register */
+
+ uint32_t emios_reserved1[4];
+
+ struct EMIOS_CHANNEL_tag CH[28];
+
+ }; /* end of EMIOS_tag */
+/****************************************************************************/
+/* MODULE : pit */
+/****************************************************************************/
+ struct PIT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR;
+
+ uint32_t pit_reserved1[63]; /* (0x0100 - 0x0004)/4 = 0x3F */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+ } CH[6];
+
+ }; /* end of PIT_tag */
+/****************************************************************************/
+/* MODULE : i2c */
+/****************************************************************************/
+ struct I2C_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ADR:7;
+ vuint8_t:1;
+ } B;
+ } IBAD; /* Module Bus Address Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t IBC:8;
+ } B;
+ } IBFD; /* Module Bus Frequency Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t MDIS:1;
+ vuint8_t IBIE:1;
+ vuint8_t MS:1;
+ vuint8_t TX:1;
+ vuint8_t NOACK:1;
+ vuint8_t RSTA:1;
+ vuint8_t DMAEN:1;
+ vuint8_t IBDOZE:1;
+ } B;
+ } IBCR; /* Module Bus Control Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t TCF:1;
+ vuint8_t IAAS:1;
+ vuint8_t IBB:1;
+ vuint8_t IBAL:1;
+ vuint8_t:1;
+ vuint8_t SRW:1;
+ vuint8_t IBIF:1;
+ vuint8_t RXAK:1;
+ } B;
+ } IBSR; /* Module Status Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t DATA:8;
+ } B;
+ } IBDR; /* Module Data Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t BIIE:1;
+ vuint8_t:7;
+ } B;
+ } IBIC; /* Module Interrupt Configuration Register */
+
+ }; /* end of I2C_tag */
+/****************************************************************************/
+/* MODULE : MPU */
+/****************************************************************************/
+ struct MPU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SPERR:8;
+ vuint32_t:4;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NGRD:4;
+ vuint32_t:7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR; /* Module Control/Error Status Register */
+
+ uint32_t mpu_reserved1[3]; /* (0x010 - 0x004)/4 = 0x03 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR0;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR3;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR3;
+
+ uint32_t mpu_reserved2[244]; /* (0x0400 - 0x0030)/4 = 0x0F4 */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD0; /* Region Descriptor n Word 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD1; /* Region Descriptor n Word 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2; /* Region Descriptor n Word 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t:15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3; /* Region Descriptor n Word 3 */
+
+ } RGD[16];
+
+ uint32_t mpu_reserved3[192]; /* (0x0800 - 0x0500)/4 = 0x0C0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
+
+ }; /* end of MPU_tag */
+/****************************************************************************/
+/* MODULE : eDMA */
+/****************************************************************************/
+
+/*for "standard" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0) */
+ struct EDMA_TCD_STD_tag {
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ vuint32_t NBYTES; /* inner (“minor”) byte count */
+
+ vint32_t SLAST; /* last destination address adjustment, or
+ scatter/gather address (if e_sg = 1) */
+
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITER:15;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */
+ vuint16_t BITER:15;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+
+ }; /* end of EDMA_TCD_STD_tag */
+
+/*for "channel link" format TCD (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1)*/
+ struct EDMA_TCD_CHLINK_tag {
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ vuint32_t NBYTES; /* inner (“minor”) byte count */
+
+ vint32_t SLAST; /* last destination address adjustment, or
+ scatter/gather address (if e_sg = 1) */
+
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITERLINKCH:6;
+ vuint16_t CITER:9;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */
+ vuint16_t BITERLINKCH:6;
+ vuint16_t BITER:9;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+
+ }; /* end of EDMA_TCD_CHLINK_tag */
+
+ struct EDMA_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t ERCA:1;
+ vuint32_t EDBG:1;
+ vuint32_t:1;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1;
+ vuint32_t:15;
+ vuint32_t GPE:1;
+ vuint32_t CPE:1;
+ vuint32_t ERRCHN:6;
+ vuint32_t SAE:1;
+ vuint32_t SOE:1;
+ vuint32_t DAE:1;
+ vuint32_t DOE:1;
+ vuint32_t NCE:1;
+ vuint32_t SGE:1;
+ vuint32_t SBE:1;
+ vuint32_t DBE:1;
+ } B;
+ } ESR; /* Error Status Register */
+
+ int16_t EDMA_reserved1[3]; /* (0x0E - 0x08)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ERQ15:1;
+ vuint16_t ERQ14:1;
+ vuint16_t ERQ13:1;
+ vuint16_t ERQ12:1;
+ vuint16_t ERQ11:1;
+ vuint16_t ERQ10:1;
+ vuint16_t ERQ09:1;
+ vuint16_t ERQ08:1;
+ vuint16_t ERQ07:1;
+ vuint16_t ERQ06:1;
+ vuint16_t ERQ05:1;
+ vuint16_t ERQ04:1;
+ vuint16_t ERQ03:1;
+ vuint16_t ERQ02:1;
+ vuint16_t ERQ01:1;
+ vuint16_t ERQ00:1;
+ } B;
+ } ERQRL; /* DMA Enable Request Register Low */
+
+ int16_t EDMA_reserved2[3]; /* (0x16 - 0x10)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t EEI15:1;
+ vuint16_t EEI14:1;
+ vuint16_t EEI13:1;
+ vuint16_t EEI12:1;
+ vuint16_t EEI11:1;
+ vuint16_t EEI10:1;
+ vuint16_t EEI09:1;
+ vuint16_t EEI08:1;
+ vuint16_t EEI07:1;
+ vuint16_t EEI06:1;
+ vuint16_t EEI05:1;
+ vuint16_t EEI04:1;
+ vuint16_t EEI03:1;
+ vuint16_t EEI02:1;
+ vuint16_t EEI01:1;
+ vuint16_t EEI00:1;
+ } B;
+ } EEIRL; /* DMA Enable Error Interrupt Register Low */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SERQ:7;
+ } B;
+ } SERQR; /* DMA Set Enable Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CERQ:7;
+ } B;
+ } CERQR; /* DMA Clear Enable Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SEEI:7;
+ } B;
+ } SEEIR; /* DMA Set Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CEEI:7;
+ } B;
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CINT:7;
+ } B;
+ } CIRQR; /* DMA Clear Interrupt Request Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CER:7;
+ } B;
+ } CERR; /* DMA Clear error Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SSB:7;
+ } B;
+ } SSBR; /* Set Start Bit Register */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CDSB:7;
+ } B;
+ } CDSBR; /* Clear Done Status Bit Register */
+
+ int16_t EDMA_reserved3[3]; /* (0x26 - 0x20)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t INT15:1;
+ vuint16_t INT14:1;
+ vuint16_t INT13:1;
+ vuint16_t INT12:1;
+ vuint16_t INT11:1;
+ vuint16_t INT10:1;
+ vuint16_t INT09:1;
+ vuint16_t INT08:1;
+ vuint16_t INT07:1;
+ vuint16_t INT06:1;
+ vuint16_t INT05:1;
+ vuint16_t INT04:1;
+ vuint16_t INT03:1;
+ vuint16_t INT02:1;
+ vuint16_t INT01:1;
+ vuint16_t INT00:1;
+ } B;
+ } IRQRL; /* DMA Interrupt Request Low */
+
+ int16_t EDMA_reserved4[3]; /* (0x2E - 0x28)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t ERR15:1;
+ vuint16_t ERR14:1;
+ vuint16_t ERR13:1;
+ vuint16_t ERR12:1;
+ vuint16_t ERR11:1;
+ vuint16_t ERR10:1;
+ vuint16_t ERR09:1;
+ vuint16_t ERR08:1;
+ vuint16_t ERR07:1;
+ vuint16_t ERR06:1;
+ vuint16_t ERR05:1;
+ vuint16_t ERR04:1;
+ vuint16_t ERR03:1;
+ vuint16_t ERR02:1;
+ vuint16_t ERR01:1;
+ vuint16_t ERR00:1;
+ } B;
+ } ERL; /* DMA Error Low */
+
+ int16_t EDMA_reserved5[3]; /* (0x36 - 0x30)/2 = 0x03 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t HRS15:1;
+ vuint16_t HRS14:1;
+ vuint16_t HRS13:1;
+ vuint16_t HRS12:1;
+ vuint16_t HRS11:1;
+ vuint16_t HRS10:1;
+ vuint16_t HRS09:1;
+ vuint16_t HRS08:1;
+ vuint16_t HRS07:1;
+ vuint16_t HRS06:1;
+ vuint16_t HRS05:1;
+ vuint16_t HRS04:1;
+ vuint16_t HRS03:1;
+ vuint16_t HRS02:1;
+ vuint16_t HRS01:1;
+ vuint16_t HRS00:1;
+ } B;
+ } HRSL; /* DMA Hardware Request Status Low */
+
+ uint32_t edma_reserved1[50]; /* (0x100 - 0x038)/4 = 0x32 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[16]; /* Channel n Priority */
+
+ uint32_t edma_reserved2[956]; /* (0x1000 - 0x0110)/4 = 0x3BC */
+
+ struct EDMA_TCD_STD_tag TCD[16];
+ /* struct EDMA_TCD_CHLINK_tag TCD[16]; */
+
+ }; /* end of EDMA_tag */
+/****************************************************************************/
+/* MODULE : INTC */
+/****************************************************************************/
+ struct INTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t VTES:1;
+ vuint32_t:4;
+ vuint32_t HVEN:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ int32_t INTC_reserved1; /* (0x008 - 0x004)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR; /* Current Priority Register */
+
+ int32_t INTC_reserved2; /* (0x010 - 0x00C)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA:21;
+ vuint32_t INTVEC:9;
+ vuint32_t:2;
+ } B;
+ } IACKR; /* Interrupt Acknowledge Register */
+
+ int32_t INTC_reserved3; /* (0x018 - 0x014)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } EOIR; /* End of Interrupt Register */
+
+ int32_t INTC_reserved4; /* (0x020 - 0x01C)/4 = 0x01 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1;
+ vuint8_t CLR:1;
+ } B;
+ } SSCIR[8]; /* Software Set/Clear Interruput Register */
+
+ uint32_t intc_reserved5[6]; /* (0x040 - 0x028)/4 = 0x06 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PRI:4;
+ } B;
+ } PSR[512]; /* Software Set/Clear Interrupt Register */
+
+ }; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+ struct DSPI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t PCSIS7:1;
+ vuint32_t PCSIS6:1;
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t:1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t:7;
+ vuint32_t HALT:1;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ uint32_t dspi_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t:16;
+ } B;
+ } TCR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t:1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t:1;
+ vuint32_t TFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR; /* Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t:2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t:1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t:4;
+ vuint32_t RFOFRE:1;
+ vuint32_t:1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t:16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t:2;
+ vuint32_t PCS7:1;
+ vuint32_t PCS6:1;
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR; /* POP RX FIFO Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[5]; /* Transmit FIFO Registers */
+
+ vuint32_t DSPI_reserved_txf[11];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[5]; /* Receive FIFO Registers */
+
+ vuint32_t DSPI_reserved_rxf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t:1;
+ vuint32_t MTOCNT:6;
+ vuint32_t:4;
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t:6;
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR; /* DSI Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SER_DATA:16;
+ } B;
+ } SDR; /* DSI Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ASER_DATA:16;
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t COMP_DATA:16;
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DESER_DATA:16;
+ } B;
+ } DDR; /* DSI deserialization Data Register */
+
+ }; /* end of DSPI_tag */
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+ struct FLEXCAN_BUF_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ }; /* end of FLEXCAN_BUF_t */
+
+ struct FLEXCAN_RXFIFO_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+ }; /* end of FLEXCAN_RXFIFO_t */
+
+ struct FLEXCAN_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLFWAK:1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t:1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ } TIMER; /* Free Running Timer */
+
+ uint32_t FLEXCAN_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK; /* RX Global Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK; /* RX 14 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK; /* RX 15 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t:1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAKINT:1;
+ } B;
+ } ESR; /* Error and Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH; /* Interruput Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interruput Flag Register */
+
+ uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64]; /* RX Individual Mask Registers */
+
+ }; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : DMAMUX */
+/****************************************************************************/
+ struct DMAMUX_tag {
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[16]; /* DMA Channel Configuration Register */
+
+ }; /* end of DMAMUX_tag */
+/****************************************************************************/
+/* MODULE : FlexRay */
+/****************************************************************************/
+
+ typedef union uMVR {
+ vuint16_t R;
+ struct {
+ vuint16_t CHIVER:8; /* CHI Version Number */
+ vuint16_t PEVER:8; /* PE Version Number */
+ } B;
+ } MVR_t;
+
+ typedef union uMCR {
+ vuint16_t R;
+ struct {
+ vuint16_t MEN:1; /* module enable */
+ vuint16_t:1;
+ vuint16_t SCMD:1; /* single channel mode */
+ vuint16_t CHB:1; /* channel B enable */
+ vuint16_t CHA:1; /* channel A enable */
+ vuint16_t SFFE:1; /* synchronization frame filter enable */
+ vuint16_t:5;
+ vuint16_t CLKSEL:1; /* protocol engine clock source select */
+ vuint16_t BITRATE:3; /* protocol engine clock prescaler */
+ vuint16_t:1;
+ } B;
+ } MCR_t;
+ typedef union uSTBSCR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t STBSSEL:7; /* strobe signal select */
+ vuint16_t:3;
+ vuint16_t ENB:1; /* strobe signal enable */
+ vuint16_t:2;
+ vuint16_t STBPSEL:2; /* strobe port select */
+ } B;
+ } STBSCR_t;
+ typedef union uSTBPCR {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t STB3EN:1; /* strobe port enable */
+ vuint16_t STB2EN:1; /* strobe port enable */
+ vuint16_t STB1EN:1; /* strobe port enable */
+ vuint16_t STB0EN:1; /* strobe port enable */
+ } B;
+ } STBPCR_t;
+
+ typedef union uMBDSR {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
+ vuint16_t:1;
+ vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
+ } B;
+ } MBDSR_t;
+
+ typedef union uMBSSUTR {
+ vuint16_t R;
+ struct {
+
+ vuint16_t:2;
+ vuint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */
+ vuint16_t:2;
+ vuint16_t LAST_MB_UTIL:6; /* last message buffer utilized */
+ } B;
+ } MBSSUTR_t;
+
+ typedef union uPOCR {
+ vuint16_t R;
+ vuint8_t byte[2];
+ struct {
+ vuint16_t WME:1; /* write mode external correction command */
+ vuint16_t:3;
+ vuint16_t EOC_AP:2; /* external offset correction application */
+ vuint16_t ERC_AP:2; /* external rate correction application */
+ vuint16_t BSY:1; /* command write busy / write mode command */
+ vuint16_t:3;
+ vuint16_t POCCMD:4; /* protocol command */
+ } B;
+ } POCR_t;
+/* protocol commands */
+ typedef union uGIFER {
+ vuint16_t R;
+ struct {
+ vuint16_t MIF:1; /* module interrupt flag */
+ vuint16_t PRIF:1; /* protocol interrupt flag */
+ vuint16_t CHIF:1; /* CHI interrupt flag */
+ vuint16_t WKUPIF:1; /* wakeup interrupt flag */
+ vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
+ vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
+ vuint16_t RBIF:1; /* receive message buffer interrupt flag */
+ vuint16_t TBIF:1; /* transmit buffer interrupt flag */
+ vuint16_t MIE:1; /* module interrupt enable */
+ vuint16_t PRIE:1; /* protocol interrupt enable */
+ vuint16_t CHIE:1; /* CHI interrupt enable */
+ vuint16_t WKUPIE:1; /* wakeup interrupt enable */
+ vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
+ vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
+ vuint16_t RBIE:1; /* receive message buffer interrupt enable */
+ vuint16_t TBIE:1; /* transmit buffer interrupt enable */
+ } B;
+ } GIFER_t;
+ typedef union uPIFR0 {
+ vuint16_t R;
+ struct {
+ vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
+ vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
+ vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
+ vuint16_t CSAIF:1; /* cold start abort interrupt flag */
+ vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */
+ vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */
+ vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
+ vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */
+ vuint16_t MTXIF:1; /* media access test symbol received flag */
+ vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
+ vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
+ vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
+ vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
+ vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */
+ vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */
+ vuint16_t CYSIF:1; /* cycle start interrupt flag */
+ } B;
+ } PIFR0_t;
+ typedef union uPIFR1 {
+ vuint16_t R;
+ struct {
+ vuint16_t EMCIF:1; /* error mode changed interrupt flag */
+ vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */
+ vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
+ vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
+ vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t:2;
+ vuint16_t EVTIF:1; /* even cycle table written interrupt flag */
+ vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */
+ vuint16_t:4;
+ } B;
+ } PIFR1_t;
+ typedef union uPIER0 {
+ vuint16_t R;
+ struct {
+ vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
+ vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
+ vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
+ vuint16_t CSAIE:1; /* cold start abort interrupt enable */
+ vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */
+ vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */
+ vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
+ vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */
+ vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */
+ vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
+ vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
+ vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
+ vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
+ vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */
+ vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */
+ vuint16_t CYSIE:1; /* cycle start interrupt enable */
+ } B;
+ } PIER0_t;
+ typedef union uPIER1 {
+ vuint16_t R;
+ struct {
+ vuint16_t EMCIE:1; /* error mode changed interrupt enable */
+ vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */
+ vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
+ vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
+ vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t:2;
+ vuint16_t EVTIE:1; /* even cycle table written interrupt enable */
+ vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */
+ vuint16_t:4;
+ } B;
+ } PIER1_t;
+ typedef union uCHIERFR {
+ vuint16_t R;
+ struct {
+ vuint16_t FRLBEF:1; /* flame lost channel B error flag */
+ vuint16_t FRLAEF:1; /* frame lost channel A error flag */
+ vuint16_t PCMIEF:1; /* command ignored error flag */
+ vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
+ vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
+ vuint16_t MSBEF:1; /* message buffer search error flag */
+ vuint16_t MBUEF:1; /* message buffer utilization error flag */
+ vuint16_t LCKEF:1; /* lock error flag */
+ vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */
+ vuint16_t SBCFEF:1; /* system bus communication failure error flag */
+ vuint16_t FIDEF:1; /* frame ID error flag */
+ vuint16_t DPLEF:1; /* dynamic payload length error flag */
+ vuint16_t SPLEF:1; /* static payload length error flag */
+ vuint16_t NMLEF:1; /* network management length error flag */
+ vuint16_t NMFEF:1; /* network management frame error flag */
+ vuint16_t ILSAEF:1; /* illegal access error flag */
+ } B;
+ } CHIERFR_t;
+ typedef union uMBIVEC {
+ vuint16_t R;
+ struct {
+
+ vuint16_t:2;
+ vuint16_t TBIVEC:6; /* transmit buffer interrupt vector */
+ vuint16_t:2;
+ vuint16_t RBIVEC:6; /* receive buffer interrupt vector */
+ } B;
+ } MBIVEC_t;
+
+ typedef union uPSR0 {
+ vuint16_t R;
+ struct {
+ vuint16_t ERRMODE:2; /* error mode */
+ vuint16_t SLOTMODE:2; /* slot mode */
+ vuint16_t:1;
+ vuint16_t PROTSTATE:3; /* protocol state */
+ vuint16_t SUBSTATE:4; /* protocol sub state */
+ vuint16_t:1;
+ vuint16_t WAKEUPSTATUS:3; /* wakeup status */
+ } B;
+ } PSR0_t;
+
+/* protocol states */
+/* protocol sub-states */
+/* wakeup status */
+ typedef union uPSR1 {
+ vuint16_t R;
+ struct {
+ vuint16_t CSAA:1; /* cold start attempt abort flag */
+ vuint16_t CSP:1; /* cold start path */
+ vuint16_t:1;
+ vuint16_t REMCSAT:5; /* remanining coldstart attempts */
+ vuint16_t CPN:1; /* cold start noise path */
+ vuint16_t HHR:1; /* host halt request pending */
+ vuint16_t FRZ:1; /* freeze occured */
+ vuint16_t APTAC:5; /* allow passive to active counter */
+ } B;
+ } PSR1_t;
+ typedef union uPSR2 {
+ vuint16_t R;
+ struct {
+ vuint16_t NBVB:1; /* NIT boundary violation on channel B */
+ vuint16_t NSEB:1; /* NIT syntax error on channel B */
+ vuint16_t STCB:1; /* symbol window transmit conflict on channel B */
+ vuint16_t SBVB:1; /* symbol window boundary violation on channel B */
+ vuint16_t SSEB:1; /* symbol window syntax error on channel B */
+ vuint16_t MTB:1; /* media access test symbol MTS received on channel B */
+ vuint16_t NBVA:1; /* NIT boundary violation on channel A */
+ vuint16_t NSEA:1; /* NIT syntax error on channel A */
+ vuint16_t STCA:1; /* symbol window transmit conflict on channel A */
+ vuint16_t SBVA:1; /* symbol window boundary violation on channel A */
+ vuint16_t SSEA:1; /* symbol window syntax error on channel A */
+ vuint16_t MTA:1; /* media access test symbol MTS received on channel A */
+ vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
+ } B;
+ } PSR2_t;
+ typedef union uPSR3 {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t WUB:1; /* wakeup symbol received on channel B */
+ vuint16_t ABVB:1; /* aggregated boundary violation on channel B */
+ vuint16_t AACB:1; /* aggregated additional communication on channel B */
+ vuint16_t ACEB:1; /* aggregated content error on channel B */
+ vuint16_t ASEB:1; /* aggregated syntax error on channel B */
+ vuint16_t AVFB:1; /* aggregated valid frame on channel B */
+ vuint16_t:2;
+ vuint16_t WUA:1; /* wakeup symbol received on channel A */
+ vuint16_t ABVA:1; /* aggregated boundary violation on channel A */
+ vuint16_t AACA:1; /* aggregated additional communication on channel A */
+ vuint16_t ACEA:1; /* aggregated content error on channel A */
+ vuint16_t ASEA:1; /* aggregated syntax error on channel A */
+ vuint16_t AVFA:1; /* aggregated valid frame on channel A */
+ } B;
+ } PSR3_t;
+ typedef union uCIFRR {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t MIFR:1; /* module interrupt flag */
+ vuint16_t PRIFR:1; /* protocol interrupt flag */
+ vuint16_t CHIFR:1; /* CHI interrupt flag */
+ vuint16_t WUPIFR:1; /* wakeup interrupt flag */
+ vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
+ vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
+ vuint16_t RBIFR:1; /* receive message buffer interrupt flag */
+ vuint16_t TBIFR:1; /* transmit buffer interrupt flag */
+ } B;
+ } CIFRR_t;
+ typedef union uSFCNTR {
+ vuint16_t R;
+ struct {
+ vuint16_t SFEVB:4; /* sync frames channel B, even cycle */
+ vuint16_t SFEVA:4; /* sync frames channel A, even cycle */
+ vuint16_t SFODB:4; /* sync frames channel B, odd cycle */
+ vuint16_t SFODA:4; /* sync frames channel A, odd cycle */
+ } B;
+ } SFCNTR_t;
+
+ typedef union uSFTCCSR {
+ vuint16_t R;
+ struct {
+ vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
+ vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
+ vuint16_t CYCNUM:6; /* cycle number */
+ vuint16_t ELKS:1; /* even cycle tables lock status */
+ vuint16_t OLKS:1; /* odd cycle tables lock status */
+ vuint16_t EVAL:1; /* even cycle tables valid */
+ vuint16_t OVAL:1; /* odd cycle tables valid */
+ vuint16_t:1;
+ vuint16_t OPT:1; /*one pair trigger */
+ vuint16_t SDVEN:1; /* sync frame deviation table enable */
+ vuint16_t SIDEN:1; /* sync frame ID table enable */
+ } B;
+ } SFTCCSR_t;
+ typedef union uSFIDRFR {
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t SYNFRID:10; /* sync frame rejection ID */
+ } B;
+ } SFIDRFR_t;
+
+ typedef union uTICCR {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t T2CFG:1; /* timer 2 configuration */
+ vuint16_t T2REP:1; /* timer 2 repetitive mode */
+ vuint16_t:1;
+ vuint16_t T2SP:1; /* timer 2 stop */
+ vuint16_t T2TR:1; /* timer 2 trigger */
+ vuint16_t T2ST:1; /* timer 2 state */
+ vuint16_t:3;
+ vuint16_t T1REP:1; /* timer 1 repetitive mode */
+ vuint16_t:1;
+ vuint16_t T1SP:1; /* timer 1 stop */
+ vuint16_t T1TR:1; /* timer 1 trigger */
+ vuint16_t T1ST:1; /* timer 1 state */
+
+ } B;
+ } TICCR_t;
+ typedef union uTI1CYSR {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
+ vuint16_t:2;
+ vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
+
+ } B;
+ } TI1CYSR_t;
+
+ typedef union uSSSR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* static slot number */
+ vuint16_t:1;
+ vuint16_t SLOTNUMBER:11; /* selector */
+ } B;
+ } SSSR_t;
+
+ typedef union uSSCCR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* selector */
+ vuint16_t:1;
+ vuint16_t CNTCFG:2; /* counter configuration */
+ vuint16_t MCY:1; /* multi cycle selection */
+ vuint16_t VFR:1; /* valid frame selection */
+ vuint16_t SYF:1; /* sync frame selection */
+ vuint16_t NUF:1; /* null frame selection */
+ vuint16_t SUF:1; /* startup frame selection */
+ vuint16_t STATUSMASK:4; /* slot status mask */
+ } B;
+ } SSCCR_t;
+ typedef union uSSR {
+ vuint16_t R;
+ struct {
+ vuint16_t VFB:1; /* valid frame on channel B */
+ vuint16_t SYB:1; /* valid sync frame on channel B */
+ vuint16_t NFB:1; /* valid null frame on channel B */
+ vuint16_t SUB:1; /* valid startup frame on channel B */
+ vuint16_t SEB:1; /* syntax error on channel B */
+ vuint16_t CEB:1; /* content error on channel B */
+ vuint16_t BVB:1; /* boundary violation on channel B */
+ vuint16_t TCB:1; /* tx conflict on channel B */
+ vuint16_t VFA:1; /* valid frame on channel A */
+ vuint16_t SYA:1; /* valid sync frame on channel A */
+ vuint16_t NFA:1; /* valid null frame on channel A */
+ vuint16_t SUA:1; /* valid startup frame on channel A */
+ vuint16_t SEA:1; /* syntax error on channel A */
+ vuint16_t CEA:1; /* content error on channel A */
+ vuint16_t BVA:1; /* boundary violation on channel A */
+ vuint16_t TCA:1; /* tx conflict on channel A */
+ } B;
+ } SSR_t;
+ typedef union uMTSCFR {
+ vuint16_t R;
+ struct {
+ vuint16_t MTE:1; /* media access test symbol transmission enable */
+ vuint16_t:1;
+ vuint16_t CYCCNTMSK:6; /* cycle counter mask */
+ vuint16_t:2;
+ vuint16_t CYCCNTVAL:6; /* cycle counter value */
+ } B;
+ } MTSCFR_t;
+
+ typedef union uRSBIR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* selector */
+ vuint16_t:5;
+ vuint16_t RSBIDX:7; /* receive shadow buffer index */
+ } B;
+ } RSBIR_t;
+
+ typedef union uRFDSR {
+ vuint16_t R;
+ struct {
+ vuint16_t FIFODEPTH:8; /* fifo depth */
+ vuint16_t:1;
+ vuint16_t ENTRYSIZE:7; /* entry size */
+ } B;
+ } RFDSR_t;
+
+ typedef union uRFRFCFR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t IBD:1; /* interval boundary */
+ vuint16_t SEL:2; /* filter number */
+ vuint16_t:1;
+ vuint16_t SID:11; /* slot ID */
+ } B;
+ } RFRFCFR_t;
+
+ typedef union uRFRFCTR {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t F3MD:1; /* filter mode */
+ vuint16_t F2MD:1; /* filter mode */
+ vuint16_t F1MD:1; /* filter mode */
+ vuint16_t F0MD:1; /* filter mode */
+ vuint16_t:4;
+ vuint16_t F3EN:1; /* filter enable */
+ vuint16_t F2EN:1; /* filter enable */
+ vuint16_t F1EN:1; /* filter enable */
+ vuint16_t F0EN:1; /* filter enable */
+ } B;
+ } RFRFCTR_t;
+ typedef union uPCR0 {
+ vuint16_t R;
+ struct {
+ vuint16_t ACTION_POINT_OFFSET:6;
+ vuint16_t STATIC_SLOT_LENGTH:10;
+ } B;
+ } PCR0_t;
+
+ typedef union uPCR1 {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
+ } B;
+ } PCR1_t;
+
+ typedef union uPCR2 {
+ vuint16_t R;
+ struct {
+ vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
+ vuint16_t NUMBER_OF_STATIC_SLOTS:10;
+ } B;
+ } PCR2_t;
+
+ typedef union uPCR3 {
+ vuint16_t R;
+ struct {
+ vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
+ vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
+ vuint16_t COLDSTART_ATTEMPTS:5;
+ } B;
+ } PCR3_t;
+
+ typedef union uPCR4 {
+ vuint16_t R;
+ struct {
+ vuint16_t CAS_RX_LOW_MAX:7;
+ vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
+ } B;
+ } PCR4_t;
+
+ typedef union uPCR5 {
+ vuint16_t R;
+ struct {
+ vuint16_t TSS_TRANSMITTER:4;
+ vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
+ vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
+ } B;
+ } PCR5_t;
+
+ typedef union uPCR6 {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
+ vuint16_t MACRO_INITIAL_OFFSET_A:7;
+ } B;
+ } PCR6_t;
+
+ typedef union uPCR7 {
+ vuint16_t R;
+ struct {
+ vuint16_t DECODING_CORRECTION_B:9;
+ vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
+ } B;
+ } PCR7_t;
+
+ typedef union uPCR8 {
+ vuint16_t R;
+ struct {
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
+ vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
+ } B;
+ } PCR8_t;
+
+ typedef union uPCR9 {
+ vuint16_t R;
+ struct {
+ vuint16_t MINISLOT_EXISTS:1;
+ vuint16_t SYMBOL_WINDOW_EXISTS:1;
+ vuint16_t OFFSET_CORRECTION_OUT:14;
+ } B;
+ } PCR9_t;
+
+ typedef union uPCR10 {
+ vuint16_t R;
+ struct {
+ vuint16_t SINGLE_SLOT_ENABLED:1;
+ vuint16_t WAKEUP_CHANNEL:1;
+ vuint16_t MACRO_PER_CYCLE:14;
+ } B;
+ } PCR10_t;
+
+ typedef union uPCR11 {
+ vuint16_t R;
+ struct {
+ vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
+ vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
+ vuint16_t OFFSET_CORRECTION_START:14;
+ } B;
+ } PCR11_t;
+
+ typedef union uPCR12 {
+ vuint16_t R;
+ struct {
+ vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
+ vuint16_t KEY_SLOT_HEADER_CRC:11;
+ } B;
+ } PCR12_t;
+
+ typedef union uPCR13 {
+ vuint16_t R;
+ struct {
+ vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
+ vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
+ } B;
+ } PCR13_t;
+
+ typedef union uPCR14 {
+ vuint16_t R;
+ struct {
+ vuint16_t RATE_CORRECTION_OUT:11;
+ vuint16_t LISTEN_TIMEOUT_H:5;
+ } B;
+ } PCR14_t;
+
+ typedef union uPCR15 {
+ vuint16_t R;
+ struct {
+ vuint16_t LISTEN_TIMEOUT_L:16;
+ } B;
+ } PCR15_t;
+
+ typedef union uPCR16 {
+ vuint16_t R;
+ struct {
+ vuint16_t MACRO_INITIAL_OFFSET_B:7;
+ vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
+ } B;
+ } PCR16_t;
+
+ typedef union uPCR17 {
+ vuint16_t R;
+ struct {
+ vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
+ } B;
+ } PCR17_t;
+
+ typedef union uPCR18 {
+ vuint16_t R;
+ struct {
+ vuint16_t WAKEUP_PATTERN:6;
+ vuint16_t KEY_SLOT_ID:10;
+ } B;
+ } PCR18_t;
+
+ typedef union uPCR19 {
+ vuint16_t R;
+ struct {
+ vuint16_t DECODING_CORRECTION_A:9;
+ vuint16_t PAYLOAD_LENGTH_STATIC:7;
+ } B;
+ } PCR19_t;
+
+ typedef union uPCR20 {
+ vuint16_t R;
+ struct {
+ vuint16_t MICRO_INITIAL_OFFSET_B:8;
+ vuint16_t MICRO_INITIAL_OFFSET_A:8;
+ } B;
+ } PCR20_t;
+
+ typedef union uPCR21 {
+ vuint16_t R;
+ struct {
+ vuint16_t EXTERN_RATE_CORRECTION:3;
+ vuint16_t LATEST_TX:13;
+ } B;
+ } PCR21_t;
+
+ typedef union uPCR22 {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
+ vuint16_t MICRO_PER_CYCLE_H:4;
+ } B;
+ } PCR22_t;
+
+ typedef union uPCR23 {
+ vuint16_t R;
+ struct {
+ vuint16_t micro_per_cycle_l:16;
+ } B;
+ } PCR23_t;
+
+ typedef union uPCR24 {
+ vuint16_t R;
+ struct {
+ vuint16_t CLUSTER_DRIFT_DAMPING:5;
+ vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
+ vuint16_t MICRO_PER_CYCLE_MIN_H:4;
+ } B;
+ } PCR24_t;
+
+ typedef union uPCR25 {
+ vuint16_t R;
+ struct {
+ vuint16_t MICRO_PER_CYCLE_MIN_L:16;
+ } B;
+ } PCR25_t;
+
+ typedef union uPCR26 {
+ vuint16_t R;
+ struct {
+ vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
+ vuint16_t MICRO_PER_CYCLE_MAX_H:4;
+ } B;
+ } PCR26_t;
+
+ typedef union uPCR27 {
+ vuint16_t R;
+ struct {
+ vuint16_t MICRO_PER_CYCLE_MAX_L:16;
+ } B;
+ } PCR27_t;
+
+ typedef union uPCR28 {
+ vuint16_t R;
+ struct {
+ vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
+ vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
+ } B;
+ } PCR28_t;
+
+ typedef union uPCR29 {
+ vuint16_t R;
+ struct {
+ vuint16_t EXTERN_OFFSET_CORRECTION:3;
+ vuint16_t MINISLOTS_MAX:13;
+ } B;
+ } PCR29_t;
+
+ typedef union uPCR30 {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t SYNC_NODE_MAX:4;
+ } B;
+ } PCR30_t;
+
+ typedef struct uMSG_BUFF_CCS {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t MCM:1; /* message buffer commit mode */
+ vuint16_t MBT:1; /* message buffer type */
+ vuint16_t MTD:1; /* message buffer direction */
+ vuint16_t CMT:1; /* commit for transmission */
+ vuint16_t EDT:1; /* enable / disable trigger */
+ vuint16_t LCKT:1; /* lock request trigger */
+ vuint16_t MBIE:1; /* message buffer interrupt enable */
+ vuint16_t:3;
+ vuint16_t DUP:1; /* data updated */
+ vuint16_t DVAL:1; /* data valid */
+ vuint16_t EDS:1; /* lock status */
+ vuint16_t LCKS:1; /* enable / disable status */
+ vuint16_t MBIF:1; /* message buffer interrupt flag */
+ } B;
+ } MBCCSR;
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t MTM:1; /* message buffer transmission mode */
+ vuint16_t CHNLA:1; /* channel assignement */
+ vuint16_t CHNLB:1; /* channel assignement */
+ vuint16_t CCFE:1; /* cycle counter filter enable */
+ vuint16_t CCFMSK:6; /* cycle counter filter mask */
+ vuint16_t CCFVAL:6; /* cycle counter filter value */
+ } B;
+ } MBCCFR;
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FID:11; /* frame ID */
+ } B;
+ } MBFIDR;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:9;
+ vuint16_t MBIDX:7; /* message buffer index */
+ } B;
+ } MBIDXR;
+ } MSG_BUFF_CCS_t;
+ typedef union uSYSBADHR {
+ vuint16_t R;
+ } SYSBADHR_t;
+ typedef union uSYSBADLR {
+ vuint16_t R;
+ } SYSBADLR_t;
+ typedef union uPADR {
+ vuint16_t R;
+ } PADR_t;
+ typedef union uPDAR {
+ vuint16_t R;
+ } PDAR_t;
+ typedef union uCASERCR {
+ vuint16_t R;
+ } CASERCR_t;
+ typedef union uCBSERCR {
+ vuint16_t R;
+ } CBSERCR_t;
+ typedef union uCYCTR {
+ vuint16_t R;
+ } CYCTR_t;
+ typedef union uMTCTR {
+ vuint16_t R;
+ } MTCTR_t;
+ typedef union uSLTCTAR {
+ vuint16_t R;
+ } SLTCTAR_t;
+ typedef union uSLTCTBR {
+ vuint16_t R;
+ } SLTCTBR_t;
+ typedef union uRTCORVR {
+ vuint16_t R;
+ } RTCORVR_t;
+ typedef union uOFCORVR {
+ vuint16_t R;
+ } OFCORVR_t;
+ typedef union uSFTOR {
+ vuint16_t R;
+ } SFTOR_t;
+ typedef union uSFIDAFVR {
+ vuint16_t R;
+ } SFIDAFVR_t;
+ typedef union uSFIDAFMR {
+ vuint16_t R;
+ } SFIDAFMR_t;
+ typedef union uNMVR {
+ vuint16_t R;
+ } NMVR_t;
+ typedef union uNMVLR {
+ vuint16_t R;
+ } NMVLR_t;
+ typedef union uT1MTOR {
+ vuint16_t R;
+ } T1MTOR_t;
+ typedef union uTI2CR0 {
+ vuint16_t R;
+ } TI2CR0_t;
+ typedef union uTI2CR1 {
+ vuint16_t R;
+ } TI2CR1_t;
+ typedef union uSSCR {
+ vuint16_t R;
+ } SSCR_t;
+ typedef union uRFSR {
+ vuint16_t R;
+ } RFSR_t;
+ typedef union uRFSIR {
+ vuint16_t R;
+ } RFSIR_t;
+ typedef union uRFARIR {
+ vuint16_t R;
+ } RFARIR_t;
+ typedef union uRFBRIR {
+ vuint16_t R;
+ } RFBRIR_t;
+ typedef union uRFMIDAFVR {
+ vuint16_t R;
+ } RFMIDAFVR_t;
+ typedef union uRFMIAFMR {
+ vuint16_t R;
+ } RFMIAFMR_t;
+ typedef union uRFFIDRFVR {
+ vuint16_t R;
+ } RFFIDRFVR_t;
+ typedef union uRFFIDRFMR {
+ vuint16_t R;
+ } RFFIDRFMR_t;
+ typedef union uLDTXSLAR {
+ vuint16_t R;
+ } LDTXSLAR_t;
+ typedef union uLDTXSLBR {
+ vuint16_t R;
+ } LDTXSLBR_t;
+
+ typedef struct FR_tag {
+ volatile MVR_t MVR; /*module version register *//*0 */
+ volatile MCR_t MCR; /*module configuration register *//*2 */
+ volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
+ volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
+ volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
+ volatile STBPCR_t STBPCR; /*strobe port control register *//*A */
+ volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
+ volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
+ volatile PADR_t PADR; /*PE address register *//*10 */
+ volatile PDAR_t PDAR; /*PE data register *//*12 */
+ volatile POCR_t POCR; /*Protocol operation control register *//*14 */
+ volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
+ volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
+ volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
+ volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
+ volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
+ volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
+ volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
+ volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
+ volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
+ volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
+ volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
+ volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
+ volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
+ volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
+ volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
+ volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
+ volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
+ volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
+ volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
+ volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
+ vuint16_t reserved3[1]; /*3E */
+ volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
+ volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
+ volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
+ volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
+ volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
+ volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
+ volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
+ volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
+ volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
+ volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
+ volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
+ volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
+ volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
+ volatile SSSR_t SSSR; /*slot status selection register *//*64 */
+ volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
+ volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
+ volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
+ volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
+ volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
+ volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
+ volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
+ volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
+ volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
+ volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
+ volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
+ volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
+ volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
+ volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
+ volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
+ volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
+ volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
+ volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
+ volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
+ volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
+ volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
+ volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
+ volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
+ volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
+ volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
+ volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
+ volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
+ volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
+ volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
+ volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
+ volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
+ volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
+ volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
+ volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
+ volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
+ volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
+ volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
+ volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
+ volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
+ volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
+ volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
+ volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
+ volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
+ volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
+ volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
+ volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
+ volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
+ volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
+ volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
+ volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
+ vuint16_t reserved2[17];
+ volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
+ } FR_tag_t;
+
+ typedef union uF_HEADER /* frame header */
+ {
+ struct {
+ vuint16_t:5;
+ vuint16_t HDCRC:11; /* Header CRC */
+ vuint16_t:2;
+ vuint16_t CYCCNT:6; /* Cycle Count */
+ vuint16_t:1;
+ vuint16_t PLDLEN:7; /* Payload Length */
+ vuint16_t:1;
+ vuint16_t PPI:1; /* Payload Preamble Indicator */
+ vuint16_t NUF:1; /* Null Frame Indicator */
+ vuint16_t SYF:1; /* Sync Frame Indicator */
+ vuint16_t SUF:1; /* Startup Frame Indicator */
+ vuint16_t FID:11; /* Frame ID */
+ } B;
+ vuint16_t WORDS[3];
+ } F_HEADER_t;
+ typedef union uS_STSTUS /* slot status */
+ {
+ struct {
+ vuint16_t VFB:1; /* Valid Frame on channel B */
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */
+ vuint16_t SEB:1; /* Syntax Error on channel B */
+ vuint16_t CEB:1; /* Content Error on channel B */
+ vuint16_t BVB:1; /* Boundary Violation on channel B */
+ vuint16_t CH:1; /* Channel */
+ vuint16_t VFA:1; /* Valid Frame on channel A */
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */
+ vuint16_t SEA:1; /* Syntax Error on channel A */
+ vuint16_t CEA:1; /* Content Error on channel A */
+ vuint16_t BVA:1; /* Boundary Violation on channel A */
+ vuint16_t:1;
+ } RX;
+ struct {
+ vuint16_t VFB:1; /* Valid Frame on channel B */
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */
+ vuint16_t SEB:1; /* Syntax Error on channel B */
+ vuint16_t CEB:1; /* Content Error on channel B */
+ vuint16_t BVB:1; /* Boundary Violation on channel B */
+ vuint16_t TCB:1; /* Tx Conflict on channel B */
+ vuint16_t VFA:1; /* Valid Frame on channel A */
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */
+ vuint16_t SEA:1; /* Syntax Error on channel A */
+ vuint16_t CEA:1; /* Content Error on channel A */
+ vuint16_t BVA:1; /* Boundary Violation on channel A */
+ vuint16_t TCA:1; /* Tx Conflict on channel A */
+ } TX;
+ vuint16_t R;
+ } S_STATUS_t;
+
+ typedef struct uMB_HEADER /* message buffer header */
+ {
+ F_HEADER_t FRAME_HEADER;
+ vuint16_t DATA_OFFSET;
+ S_STATUS_t SLOT_STATUS;
+ } MB_HEADER_t;
+/****************************************************************************/
+/* MODULE : LCD */
+/****************************************************************************/
+ struct LCD_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LCDEN:1;
+ vuint32_t LCDRST:1;
+ vuint32_t LCDRCS:1;
+ vuint32_t DUTY:3;
+ vuint32_t BIAS:1;
+ vuint32_t VLCDS:1;
+ vuint32_t PWR:2;
+ vuint32_t BSTEN:1;
+ vuint32_t BSTSEL:1;
+ vuint32_t BSTAO:1;
+ vuint32_t:1;
+ vuint32_t LCDINT:1;
+ vuint32_t EOFF:1;
+ vuint32_t NOF:8;
+ vuint32_t:2;
+ vuint32_t LCDBPA:1;
+ vuint32_t:2;
+ vuint32_t LCDBPS:3;
+ } B;
+ } CR; /* LCD Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t LCLK:4;
+ vuint32_t:24;
+ } B;
+ } PCR; /* LCD Prescaler Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CCEN:1;
+ vuint32_t:4;
+ vuint32_t LCC:11;
+ vuint32_t:16;
+ } B;
+ } CCR; /* LCD Contrast Control Register */
+
+ int32_t LCD_reserved1; /* (0x10 - 0x0C)/4 = 0x01 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FP31EN:1;
+ vuint32_t FP30EN:1;
+ vuint32_t FP29EN:1;
+ vuint32_t FP28EN:1;
+ vuint32_t FP27EN:1;
+ vuint32_t FP26EN:1;
+ vuint32_t FP25EN:1;
+ vuint32_t FP24EN:1;
+ vuint32_t FP23EN:1;
+ vuint32_t FP22EN:1;
+ vuint32_t FP21EN:1;
+ vuint32_t FP20EN:1;
+ vuint32_t FP19EN:1;
+ vuint32_t FP18EN:1;
+ vuint32_t FP17EN:1;
+ vuint32_t FP16EN:1;
+ vuint32_t FP15EN:1;
+ vuint32_t FP14EN:1;
+ vuint32_t FP13EN:1;
+ vuint32_t FP12EN:1;
+ vuint32_t FP11EN:1;
+ vuint32_t FP10EN:1;
+ vuint32_t FP9EN:1;
+ vuint32_t FP8EN:1;
+ vuint32_t FP7EN:1;
+ vuint32_t FP6EN:1;
+ vuint32_t FP5EN:1;
+ vuint32_t FP4EN:1;
+ vuint32_t FP3EN:1;
+ vuint32_t FP2EN:1;
+ vuint32_t FP1EN:1;
+ vuint32_t FP0EN:1;
+ } B;
+ } FPENR0; /* LCD Frontplane Enable Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FP63EN:1;
+ vuint32_t FP62EN:1;
+ vuint32_t FP61EN:1;
+ vuint32_t FP60EN:1;
+ vuint32_t FP59EN:1;
+ vuint32_t FP58EN:1;
+ vuint32_t FP57EN:1;
+ vuint32_t FP56EN:1;
+ vuint32_t FP55EN:1;
+ vuint32_t FP54EN:1;
+ vuint32_t FP53EN:1;
+ vuint32_t FP52EN:1;
+ vuint32_t FP51EN:1;
+ vuint32_t FP50EN:1;
+ vuint32_t FP49EN:1;
+ vuint32_t FP48EN:1;
+ vuint32_t FP47EN:1;
+ vuint32_t FP46EN:1;
+ vuint32_t FP45EN:1;
+ vuint32_t FP44EN:1;
+ vuint32_t FP43EN:1;
+ vuint32_t FP42EN:1;
+ vuint32_t FP41EN:1;
+ vuint32_t FP40EN:1;
+ vuint32_t FP39EN:1;
+ vuint32_t FP38EN:1;
+ vuint32_t FP37EN:1;
+ vuint32_t FP36EN:1;
+ vuint32_t FP35EN:1;
+ vuint32_t FP34EN:1;
+ vuint32_t FP33EN:1;
+ vuint32_t FP32EN:1;
+ } B;
+ } FPENR1; /* LCD Frontplane Enable Register 1 */
+
+ int32_t LCD_reserved2[2]; /* (0x20 - 0x18)/4 = 0x02 */
+
+ union {
+ vuint32_t R;
+ } RAM[16]; /* LCD RAM Register */
+
+ }; /* end of LCD_tag */
+/****************************************************************************/
+/* MODULE : External Bus Interface (EBI) */
+/****************************************************************************/
+ struct EBI_CS_tag {
+ union { /* Base Register Bank */
+ vuint32_t R;
+ struct {
+ vuint32_t BA:17;
+ vuint32_t:3;
+ vuint32_t PS:1;
+ vuint32_t:4;
+ vuint32_t BL:1;
+ vuint32_t WEBS:1;
+ vuint32_t TBDIP:1;
+ vuint32_t:2;
+ vuint32_t BI:1;
+ vuint32_t V:1;
+ } B;
+ } BR;
+
+ union { /* Option Register Bank */
+ vuint32_t R;
+ struct {
+ vuint32_t AM:17;
+ vuint32_t:7;
+ vuint32_t SCY:4;
+ vuint32_t:1;
+ vuint32_t BSCY:2;
+ vuint32_t:1;
+ } B;
+ } OR;
+ }; /* end of EBI_CS_tag */
+
+ struct EBI_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t SIZEN:1;
+ vuint32_t SIZE:2;
+ vuint32_t:8;
+ vuint32_t ACGE:1;
+ vuint32_t EXTM:1;
+ vuint32_t EARB:1;
+ vuint32_t EARP:2;
+ vuint32_t:4;
+ vuint32_t MDIS:1;
+ vuint32_t:4;
+ vuint32_t AD_MUX:1;
+ vuint32_t DBM:1;
+ } B;
+ } MCR;
+
+ uint32_t EBI_reserved1;
+
+ union { /* Transfer Error Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TEAF:1;
+ vuint32_t BMTF:1;
+ } B;
+ } TESR;
+
+ union { /* Bus Monitor Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t BMT:8;
+ vuint32_t BME:1;
+ vuint32_t:7;
+ } B;
+ } BMCR;
+
+ struct EBI_CS_tag CS[2];
+
+ }; /* end of EBI_tag */
+/****************************************************************************/
+/* MODULE : DFLASH */
+/****************************************************************************/
+ struct DFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:23;
+ vuint32_t HBLOCK:8;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ int32_t Dflash_reserved0[8]; /* {0x003C-0x001C}/0x4 = 0x08 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of Dflash_tag */
+/****************************************************************************/
+/* MODULE : CFLASH */
+/****************************************************************************/
+ struct CFLASH_tag {
+ union { /* Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t:4;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* LML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t TSLK:1;
+ vuint32_t:2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* HBL Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:23;
+ vuint32_t HBLOCK:8;
+ } B;
+ } HBL;
+
+ union { /* SLML Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t STSLK:1;
+ vuint32_t:2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* LMS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6;
+ } B;
+ } HBS;
+
+ union { /* Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t ADD:20;
+ vuint32_t:3;
+ } B;
+ } ADR;
+
+ union { /* CFLASH Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK0_APC:5;
+ vuint32_t BK0_WWSC:5;
+ vuint32_t BK0_RWSC:5;
+ vuint32_t BK0_RWWC2:1;
+ vuint32_t BK0_RWWC1:1;
+ vuint32_t B0_P1_BCFG:2;
+ vuint32_t B0_P1_DPFE:1;
+ vuint32_t B0_P1_IPFE:1;
+ vuint32_t B0_P1_PFLM:2;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK0_RWWC0:1;
+ vuint32_t B0_P0_BCFG:2;
+ vuint32_t B0_P0_DPFE:1;
+ vuint32_t B0_P0_IPFE:1;
+ vuint32_t B0_P0_PFLM:2;
+ vuint32_t B0_P0_BFE:1;
+ } B;
+ } PFCR0;
+
+ union { /* CFLASH Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t BK1_APC:5;
+ vuint32_t BK1_WWSC:5;
+ vuint32_t BK1_RWSC:5;
+ vuint32_t BK1_RWWC2:1;
+ vuint32_t BK1_RWWC1:1;
+ vuint32_t:6;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK1_RWWC0:1;
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1;
+ } B;
+ } PFCR1;
+
+ union { /* cflash Access Protection Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t ARBM:2;
+ vuint32_t M7PFD:1;
+ vuint32_t M6PFD:1;
+ vuint32_t M5PFD:1;
+ vuint32_t M4PFD:1;
+ vuint32_t M3PFD:1;
+ vuint32_t M2PFD:1;
+ vuint32_t M1PFD:1;
+ vuint32_t M0PFD:1;
+ vuint32_t M7AP:2;
+ vuint32_t M6AP:2;
+ vuint32_t M5AP:2;
+ vuint32_t M4AP:2;
+ vuint32_t M3AP:2;
+ vuint32_t M2AP:2;
+ vuint32_t M1AP:2;
+ vuint32_t M0AP:2;
+ } B;
+ } FAPR;
+
+ int32_t CFLASH_reserved0[5]; /* {0x003C-0x0028}/0x4 = 0x05 */
+
+ union { /* User Test Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t:7;
+ vuint32_t DSI:8;
+ vuint32_t:10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-4 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ }; /* end of CFLASH_tag */
+
+/****************************************************************************/
+/* MODULE : CRC */
+/****************************************************************************/
+ struct CRC_SUB_tag {
+ union {
+ vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W; /* Data buffer in words (32 bits) */
+ struct {
+ vuint32_t INV:1;
+ vuint32_t SWAP:1;
+ vuint32_t POLYG:1;
+ vuint32_t:29;
+ }BIT;
+ } CRC_CFG; /* CRC Configuration Register */
+
+ union {
+ vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W; /* Data buffer in words (32 bits) */
+ } CRC_INP; /* CRC Input Register */
+
+ union {
+ vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W; /* Data buffer in words (32 bits) */
+ } CRC_CSTAT; /*CRC Current Status Register */
+
+ union {
+ vuint8_t B[4]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[2]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W; /* Data buffer in words (32 bits) */
+ } CRC_OUTP; /* CRC Output Register */
+
+ }; /* end of CRC_tag */
+
+ struct CRC_tag {
+ struct CRC_SUB_tag CNTX[2];
+ };
+
+/******************************************************************
+| defines and macros (scope: module-local)
+|-----------------------------------------------------------------*/
+/* Define instances of modules */
+#define ADC_0 (*(volatile struct ADC_tag *) 0xFFE00000UL)
+#define ADC_1 (*(volatile struct ADC_tag *) 0xFFE04000UL)
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
+#define CFLASH (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
+#define CTU_0 (*(volatile struct CTU_tag *) 0xFFE0C000UL)
+#define CTU_1 (*(volatile struct CTU_tag *) 0xFFE10000UL)
+#define CTUL (*(volatile struct CTUL_tag *) 0xFFE64000UL)
+#define DCU (*(volatile struct DCU_tag *) 0xFFE7C000UL)
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
+#define EBI (*(volatile struct EBI_tag *) 0xC3F84000UL)
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
+#define ETIMER_0 (*(volatile struct ETIMER_tag *) 0xFFE18000UL)
+#define ETIMER_1 (*(volatile struct ETIMER_tag *) 0xFFE1C000UL)
+#define FCU (*(volatile struct FCU_tag *) 0xFFE6C000UL)
+#define FLEXPWM_0 (*(volatile struct FLEXPWM_tag *) 0xFFE24000UL)
+#define FLEXPWM_1 (*(volatile struct FLEXPWM_tag *) 0xFFE28000UL)
+#define FR (*(volatile struct FR_tag *) 0xFFFE0000UL)
+#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE30000UL)
+#define I2C_1 (*(volatile struct I2C_tag *) 0xFFE34000UL)
+#define I2C_2 (*(volatile struct I2C_tag *) 0xFFE38000UL)
+#define I2C_3 (*(volatile struct I2C_tag *) 0xFFE3C000UL)
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
+#define LCD (*(volatile struct LCD_tag *) 0xFFE74000UL)
+#define LINFLEX_0 (*(volatile struct LINFLEX_tag *) 0xFFE40000UL)
+#define LINFLEX_1 (*(volatile struct LINFLEX_tag *) 0xFFE44000UL)
+#define LINFLEX_2 (*(volatile struct LINFLEX_tag *) 0xFFE48000UL)
+#define LINFLEX_3 (*(volatile struct LINFLEX_tag *) 0xFFE4C000UL)
+#define MCM (*(volatile struct MCM_tag *) 0xFFF40000UL)
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
+#define SAFEPORT (*(volatile struct FLEXCAN_tag *) 0xFFFE8000UL)
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
+#define SMC (*(volatile struct SMC_tag *) 0xFFE60000UL)
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
+#define SSD_0 (*(volatile struct SSD_tag *) 0xFFE61000UL)
+#define SSD_1 (*(volatile struct SSD_tag *) 0xFFE61800UL)
+#define SSD_2 (*(volatile struct SSD_tag *) 0xFFE62000UL)
+#define SSD_3 (*(volatile struct SSD_tag *) 0xFFE62800UL)
+#define SSD_4 (*(volatile struct SSD_tag *) 0xFFE63000UL)
+#define SSD_5 (*(volatile struct SSD_tag *) 0xFFE63800UL)
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
+#define CRC (*(volatile struct CRC_tag *) 0xFFE68000UL)
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ifdef _JDP_H */
+/* End of file */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC563Mxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..77099ddf4 --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/cfg/mcuconf.h.ftl @@ -0,0 +1,209 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC563Mxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC563Mxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_CLK_BYPASS ${conf.instance.initialization_settings.clock_bypass.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_CLK_PREDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.prediv_value.value[0]}
+#define SPC5_CLK_MFD_VALUE ${conf.instance.initialization_settings.fmpll0_settings.mfd_value.value[0]}
+#define SPC5_CLK_RFD ${conf.instance.initialization_settings.fmpll0_settings.rfd_value.value[0]}
+#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
+ BIUCR_MASTER4_PREFETCH | \
+ BIUCR_MASTER0_PREFETCH | \
+ BIUCR_DPFEN | \
+ BIUCR_IPFEN | \
+ BIUCR_PFLIM_ON_MISS | \
+ BIUCR_BFEN)
+#define SPC5_EMIOS_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios_global_prescaler.value[0]}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_GROUP1_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_1_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * ADC driver settings.
+ */
+#define SPC5_ADC_USE_ADC0_Q0 ${conf.instance.eqadc_settings.fifo0.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC0_Q1 ${conf.instance.eqadc_settings.fifo1.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC0_Q2 ${conf.instance.eqadc_settings.fifo2.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC1_Q3 ${conf.instance.eqadc_settings.fifo3.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC1_Q4 ${conf.instance.eqadc_settings.fifo4.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC1_Q5 ${conf.instance.eqadc_settings.fifo5.value[0]?upper_case}
+#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo0.value[0]}
+#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo1.value[0]}
+#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo2.value[0]}
+#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo3.value[0]}
+#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo4.value[0]}
+#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo5.value[0]}
+#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(${conf.instance.eqadc_settings.divider.value[0]})
+[#assign AN0 = conf.instance.eqadc_settings.an0.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN1 = conf.instance.eqadc_settings.an1.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN2 = conf.instance.eqadc_settings.an2.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN3 = conf.instance.eqadc_settings.an3.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN4 = conf.instance.eqadc_settings.an4.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN5 = conf.instance.eqadc_settings.an5.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN6 = conf.instance.eqadc_settings.an6.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN7 = conf.instance.eqadc_settings.an7.value[0]?upper_case?replace(" ", "_") /]
+#define SPC5_ADC_PUDCR {ADC_PUDCR_${AN0},ADC_PUDCR_${AN1},ADC_PUDCR_${AN2},ADC_PUDCR_${AN3},ADC_PUDCR_${AN4},ADC_PUDCR_${AN5},ADC_PUDCR_${AN6},ADC_PUDCR_${AN7}}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_USE_ESCIA ${(conf.instance.esci_settings.esci0.value[0] == "Serial")?string?upper_case}
+#define SPC5_USE_ESCIB ${(conf.instance.esci_settings.esci1.value[0] == "Serial")?string?upper_case}
+#define SPC5_ESCIA_PRIORITY ${conf.instance.irq_priority_settings.esci0.value[0]}
+#define SPC5_ESCIB_PRIORITY ${conf.instance.irq_priority_settings.esci1.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_b.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_c.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign bs0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs0[0].@index[0]?trim?number] /]
+[#assign bs1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs1[0].@index[0]?trim?number] /]
+[#assign bs2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs2[0].@index[0]?trim?number] /]
+[#assign bs3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs3[0].@index[0]?trim?number] /]
+[#assign bs4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs4[0].@index[0]?trim?number] /]
+[#assign bs5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${bs0 + bs1 + bs2 + bs3 + bs4 + bs5})
+[#assign cs0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs0[0].@index[0]?trim?number] /]
+[#assign cs1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs1[0].@index[0]?trim?number] /]
+[#assign cs2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs2[0].@index[0]?trim?number] /]
+[#assign cs3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs3[0].@index[0]?trim?number] /]
+[#assign cs4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs4[0].@index[0]?trim?number] /]
+[#assign cs5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${cs0 + cs1 + cs2 + cs3 + cs4 + cs5})
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_b.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_c.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_b.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_c.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * ICU driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS_CH0 ${(conf.instance.emios200_settings.emios_uc0.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH1 ${(conf.instance.emios200_settings.emios_uc1.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH2 ${(conf.instance.emios200_settings.emios_uc2.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH3 ${(conf.instance.emios200_settings.emios_uc3.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH4 ${(conf.instance.emios200_settings.emios_uc4.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH5 ${(conf.instance.emios200_settings.emios_uc5.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH6 ${(conf.instance.emios200_settings.emios_uc6.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH8 ${(conf.instance.emios200_settings.emios_uc8.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH9 ${(conf.instance.emios200_settings.emios_uc9.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH10 ${(conf.instance.emios200_settings.emios_uc10.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH11 ${(conf.instance.emios200_settings.emios_uc11.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH12 ${(conf.instance.emios200_settings.emios_uc12.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH13 ${(conf.instance.emios200_settings.emios_uc13.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH14 ${(conf.instance.emios200_settings.emios_uc14.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH15 ${(conf.instance.emios200_settings.emios_uc15.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH23 ${(conf.instance.emios200_settings.emios_uc23.value[0] == "ICU")?string?upper_case}
+
+/*
+ * PWM driver system settings.
+ */
+#define SPC5_PWM_USE_EMIOS_CH0 ${(conf.instance.emios200_settings.emios_uc0.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH8 ${(conf.instance.emios200_settings.emios_uc8.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH9 ${(conf.instance.emios200_settings.emios_uc9.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH10 ${(conf.instance.emios200_settings.emios_uc10.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH12 ${(conf.instance.emios200_settings.emios_uc12.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH14 ${(conf.instance.emios200_settings.emios_uc14.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH15 ${(conf.instance.emios200_settings.emios_uc15.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH23 ${(conf.instance.emios200_settings.emios_uc23.value[0] == "PWM")?string?upper_case}
+
+/*
+ * eMIOS channel priorities.
+ */
+#define SPC5_EMIOS_FLAG_F0_PRIORITY ${conf.instance.irq_priority_settings.emios_uc0.value[0]}
+#define SPC5_EMIOS_FLAG_F1_PRIORITY ${conf.instance.irq_priority_settings.emios_uc1.value[0]}
+#define SPC5_EMIOS_FLAG_F2_PRIORITY ${conf.instance.irq_priority_settings.emios_uc2.value[0]}
+#define SPC5_EMIOS_FLAG_F3_PRIORITY ${conf.instance.irq_priority_settings.emios_uc3.value[0]}
+#define SPC5_EMIOS_FLAG_F4_PRIORITY ${conf.instance.irq_priority_settings.emios_uc4.value[0]}
+#define SPC5_EMIOS_FLAG_F5_PRIORITY ${conf.instance.irq_priority_settings.emios_uc5.value[0]}
+#define SPC5_EMIOS_FLAG_F6_PRIORITY ${conf.instance.irq_priority_settings.emios_uc6.value[0]}
+#define SPC5_EMIOS_FLAG_F8_PRIORITY ${conf.instance.irq_priority_settings.emios_uc8.value[0]}
+#define SPC5_EMIOS_FLAG_F9_PRIORITY ${conf.instance.irq_priority_settings.emios_uc9.value[0]}
+#define SPC5_EMIOS_FLAG_F10_PRIORITY ${conf.instance.irq_priority_settings.emios_uc10.value[0]}
+#define SPC5_EMIOS_FLAG_F11_PRIORITY ${conf.instance.irq_priority_settings.emios_uc11.value[0]}
+#define SPC5_EMIOS_FLAG_F12_PRIORITY ${conf.instance.irq_priority_settings.emios_uc12.value[0]}
+#define SPC5_EMIOS_FLAG_F13_PRIORITY ${conf.instance.irq_priority_settings.emios_uc13.value[0]}
+#define SPC5_EMIOS_FLAG_F14_PRIORITY ${conf.instance.irq_priority_settings.emios_uc14.value[0]}
+#define SPC5_EMIOS_FLAG_F15_PRIORITY ${conf.instance.irq_priority_settings.emios_uc15.value[0]}
+#define SPC5_EMIOS_FLAG_F23_PRIORITY ${conf.instance.irq_priority_settings.emios_uc23.value[0]}
+
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/hal_lld.c b/os/hal/ports/SPC5/SPC563Mxx/hal_lld.c new file mode 100644 index 000000000..2e07eb423 --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/hal_lld.c @@ -0,0 +1,125 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/hal_lld.c
+ * @brief SPC563Mxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t n;
+
+ /* Optimal crossbar settings. The DMA priority is placed above the CPU
+ priority in order to not starve I/O activities while the CPU is
+ executing tight loops (FLASH and SRAM slave ports only).
+ The SRAM is parked on the load/store port, for some unknown reason it
+ is defaulted on the instructions port and this kills performance.*/
+ XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
+ XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities:
+ eDMA (1): 0 (highest)
+ Core Instructions (0): 1
+ Undocumented (2): 2
+ Core Data (4): 3 */
+ XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities:
+ eDMA (1): 0 (highest)
+ Core Instructions (0): 1
+ Undocumented (2): 2
+ Core Data (4): 3 */
+
+ /* Decrementer timer initialized for system tick use, note, it is
+ initialized here because in the OSAL layer the system clock frequency
+ is not yet known.*/
+ n = SPC5_SYSCLK / OSAL_ST_FREQUENCY;
+ asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */
+ "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
+ "e_lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
+ "mtspr 340, %%r3" /* TCR register. */
+ : : [n] "r" (n) : "r3");
+
+ /* TB counter enabled for debug and measurements.*/
+ asm volatile ("e_li %%r3, 0x4000 \t\n" /* TBEN bit. */
+ "mtspr 1008, %%r3" /* HID0 register. */
+ : : : "r3");
+
+ /* eMIOS initialization.*/
+ EMIOS.MCR.R = (1U << 26) | SPC5_EMIOS_GPRE; /* GPREN and GPRE. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC563 clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+#if !SPC5_NO_INIT
+ /* PLL activation.*/
+ FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
+ FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
+#if !SPC5_CLK_BYPASS
+ FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
+ FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
+ FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
+ FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
+ while (!FMPLL.SYNSR.B.LOCK)
+ ;
+ FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
+#endif /* !SPC5_CLK_BYPASS */
+
+ /* FLASH wait states and prefetching setup.*/
+ CFLASH0.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ CFLASH0.BIUCR2.R = 0;
+ CFLASH0.PFCR3.R = 0;
+#endif /* !SPC5_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/hal_lld.h b/os/hal/ports/SPC5/SPC563Mxx/hal_lld.h new file mode 100644 index 000000000..49e1c3082 --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/hal_lld.h @@ -0,0 +1,322 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/hal_lld.h
+ * @brief SPC563Mxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS TRUE
+
+/**
+ * @brief Platform name.
+ */
+#define PLATFORM_NAME "SPC563Mxx Powertrain"
+
+/**
+ * @name ESYNCR2 register definitions
+ * @{
+ */
+#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
+#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
+#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
+#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
+/** @} */
+
+/**
+ * @name BIUCR register definitions
+ * @{
+ */
+#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
+#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
+#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
+#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
+#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
+#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
+#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
+#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
+#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
+#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
+#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
+#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
+#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
+#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
+#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
+#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
+#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
+#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
+#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
+#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
+#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
+#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
+#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
+#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
+#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
+#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
+#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
+#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
+#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
+#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
+#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
+#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
+#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
+#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
+#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
+#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
+#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
+#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Clock bypass.
+ * @note If set to @p TRUE then the PLL is not started and initialized, the
+ * external clock is used as-is and the other clock-related settings
+ * are ignored.
+ */
+#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
+#define SPC5_CLK_BYPASS FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief External clock pre-divider.
+ * @note Must be in range 1...15.
+ */
+#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_CLK_PREDIV_VALUE 2
+#endif
+
+/**
+ * @brief Multiplication factor divider.
+ * @note Must be in range 32...96.
+ */
+#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
+#define SPC5_CLK_MFD_VALUE 80
+#endif
+
+/**
+ * @brief Reduced frequency divider.
+ */
+#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
+#define SPC5_CLK_RFD RFD_DIV4
+#endif
+
+/**
+ * @brief Flash buffer and prefetching settings.
+ * @note Please refer to the SPC563Mxx reference manual about the meaning
+ * of the following bits, if in doubt DO NOT MODIFY IT.
+ * @note Do not specify the APC, WWSC, RWSC bits in this value because
+ * those are calculated from the system clock and ORed with this
+ * value.
+ */
+#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
+#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
+ BIUCR_MASTER4_PREFETCH | \
+ BIUCR_MASTER0_PREFETCH | \
+ BIUCR_DPFEN | \
+ BIUCR_IPFEN | \
+ BIUCR_PFLIM_ON_MISS | \
+ BIUCR_BFEN)
+#endif
+
+/**
+ * @brief eMIOS global prescaler value.
+ */
+#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_GPRE_VALUE 20
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC563Mxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC563Mxx_MCUCONF not defined"
+#endif
+
+#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
+#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
+#endif
+
+#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
+#error "invalid SPC5_CLK_MFD_VALUE value specified"
+#endif
+
+#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \
+ (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
+#error "invalid SPC5_CLK_RFD value specified"
+#endif
+
+#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
+#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input divider.
+ */
+#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1)
+
+/**
+ * @brief PLL multiplier.
+ */
+#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE)
+
+/**
+ * @brief PLL output clock.
+ */
+#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \
+ SPC5_CLK_MFD_VALUE)
+
+#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
+#error "VCO frequency out of the acceptable range (256...512)"
+#endif
+
+/**
+ * @brief PLL output clock.
+ */
+#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
+#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
+#else
+#define SPC5_SYSCLK SPC5_XOSC_CLK
+#endif
+
+#if (SPC5_SYSCLK > 80000000) && !SPC5_ALLOW_OVERCLOCK
+#error "System clock above maximum rated frequency (80MHz)"
+#endif
+
+/**
+ * @brief Flash wait states are a function of the system clock.
+ */
+#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
+#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
+#elif SPC5_SYSCLK <= 40000000
+#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1)
+#elif SPC5_SYSCLK <= 64000000
+#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1)
+#else
+#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_1)
+#endif
+
+/**
+ * @brief eMIOS global prescaler setting.
+ */
+#define SPC5_EMIOS_GPRE (SPC5_EMIOS_GPRE_VALUE << 8)
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * TBL register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+static inline
+halrtcnt_t hal_lld_get_counter_value(void) {
+ halrtcnt_t cnt;
+
+ asm volatile ("mfspr %[cnt], 284" : [cnt] "=r" (cnt) : : );
+ return cnt;
+}
+
+/**
+ * @brief Realtime counter frequency.
+ * @note The TBL register is incremented directly by the system
+ * clock so this function returns SPC5_SYSCLK.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() SPC5_SYSCLK
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/platform.mk b/os/hal/ports/SPC5/SPC563Mxx/platform.mk new file mode 100644 index 000000000..75d0a5bc8 --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/platform.mk @@ -0,0 +1,23 @@ +# List of all the SPC563Mxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC563Mxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EQADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1/spc5_emios.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ESCI_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIU_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC563Mxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EQADC_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ESCI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIU_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC563Mxx/registers.h b/os/hal/ports/SPC5/SPC563Mxx/registers.h new file mode 100644 index 000000000..d6e3228fd --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc563m.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/spc5_registry.h b/os/hal/ports/SPC5/SPC563Mxx/spc5_registry.h new file mode 100644 index 000000000..13e8bedd3 --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/spc5_registry.h @@ -0,0 +1,225 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/spc5_registry.h
+ * @brief SPC563Mxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC563Mxx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 FALSE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_HAS_DSPI3 FALSE
+#define SPC5_HAS_DSPI4 FALSE
+#define SPC5_HAS_DSPI5 FALSE
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+#define SPC5_DSPI_FIFO_DEPTH 4
+#define SPC5_DSPI1_TFFF_HANDLER vector133
+#define SPC5_DSPI1_TFFF_NUMBER 133
+#define SPC5_DSPI1_RFDF_HANDLER vector135
+#define SPC5_DSPI1_RFDF_NUMBER 135
+#define SPC5_DSPI2_TFFF_HANDLER vector138
+#define SPC5_DSPI2_TFFF_NUMBER 138
+#define SPC5_DSPI2_RFDF_HANDLER vector140
+#define SPC5_DSPI2_RFDF_NUMBER 140
+#define SPC5_DSPI1_ENABLE_CLOCK()
+#define SPC5_DSPI1_DISABLE_CLOCK()
+#define SPC5_DSPI2_ENABLE_CLOCK()
+#define SPC5_DSPI2_DISABLE_CLOCK()
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 32
+#define SPC5_EDMA_HAS_MUX FALSE
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 12
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 25
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 13
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 14
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 26
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 15
+
+/* eQADC attributes.*/
+#define SPC5_HAS_EQADC TRUE
+
+/* eSCI attributes.*/
+#define SPC5_HAS_ESCIA TRUE
+#define SPC5_ESCIA_HANDLER vector146
+#define SPC5_ESCIA_NUMBER 146
+
+#define SPC5_HAS_ESCIB TRUE
+#define SPC5_ESCIB_HANDLER vector149
+#define SPC5_ESCIB_NUMBER 149
+
+#define SPC5_HAS_ESCIC FALSE
+
+/* SIU attributes.*/
+#define SPC5_HAS_SIU TRUE
+#define SPC5_SIU_SUPPORTS_PORTS FALSE
+
+/* EMIOS attributes.*/
+#define SPC5_HAS_EMIOS TRUE
+
+#define SPC5_EMIOS_NUM_CHANNELS 16
+
+#define SPC5_EMIOS_FLAG_F0_HANDLER vector51
+#define SPC5_EMIOS_FLAG_F1_HANDLER vector52
+#define SPC5_EMIOS_FLAG_F2_HANDLER vector53
+#define SPC5_EMIOS_FLAG_F3_HANDLER vector54
+#define SPC5_EMIOS_FLAG_F4_HANDLER vector55
+#define SPC5_EMIOS_FLAG_F5_HANDLER vector56
+#define SPC5_EMIOS_FLAG_F6_HANDLER vector57
+#define SPC5_EMIOS_FLAG_F8_HANDLER vector59
+#define SPC5_EMIOS_FLAG_F9_HANDLER vector60
+#define SPC5_EMIOS_FLAG_F10_HANDLER vector61
+#define SPC5_EMIOS_FLAG_F11_HANDLER vector62
+#define SPC5_EMIOS_FLAG_F12_HANDLER vector63
+#define SPC5_EMIOS_FLAG_F13_HANDLER vector64
+#define SPC5_EMIOS_FLAG_F14_HANDLER vector65
+#define SPC5_EMIOS_FLAG_F15_HANDLER vector66
+#define SPC5_EMIOS_FLAG_F23_HANDLER vector209
+#define SPC5_EMIOS_FLAG_F0_NUMBER 51
+#define SPC5_EMIOS_FLAG_F1_NUMBER 52
+#define SPC5_EMIOS_FLAG_F2_NUMBER 53
+#define SPC5_EMIOS_FLAG_F3_NUMBER 54
+#define SPC5_EMIOS_FLAG_F4_NUMBER 55
+#define SPC5_EMIOS_FLAG_F5_NUMBER 56
+#define SPC5_EMIOS_FLAG_F6_NUMBER 57
+#define SPC5_EMIOS_FLAG_F8_NUMBER 59
+#define SPC5_EMIOS_FLAG_F9_NUMBER 60
+#define SPC5_EMIOS_FLAG_F10_NUMBER 61
+#define SPC5_EMIOS_FLAG_F11_NUMBER 62
+#define SPC5_EMIOS_FLAG_F12_NUMBER 63
+#define SPC5_EMIOS_FLAG_F13_NUMBER 64
+#define SPC5_EMIOS_FLAG_F14_NUMBER 65
+#define SPC5_EMIOS_FLAG_F15_NUMBER 66
+#define SPC5_EMIOS_FLAG_F23_NUMBER 209
+
+#define SPC5_EMIOS_CLK (SPC5_SYSCLK / \
+ SPC5_EMIOS_GPRE_VALUE)
+#define SPC5_EMIOS_ENABLE_CLOCK()
+#define SPC5_EMIOS_DISABLE_CLOCK()
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_SHARED_IRQ FALSE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector152
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector153
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER vector155
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_HANDLER vector156
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_HANDLER vector157
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_HANDLER vector158
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_HANDLER vector159
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_HANDLER vector160
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_HANDLER vector161
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_HANDLER vector162
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_HANDLER vector163
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_HANDLER vector164
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_HANDLER vector165
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_HANDLER vector166
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_HANDLER vector167
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_HANDLER vector168
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_HANDLER vector169
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_HANDLER vector170
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector171
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector172
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 152
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 153
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_NUMBER 155
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_NUMBER 156
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_NUMBER 157
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_NUMBER 158
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_NUMBER 159
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_NUMBER 160
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_NUMBER 161
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_NUMBER 162
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_NUMBER 163
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_NUMBER 164
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_NUMBER 165
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_NUMBER 166
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_NUMBER 167
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_NUMBER 168
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_NUMBER 169
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_NUMBER 170
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 171
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 172
+#define SPC5_FLEXCAN0_ENABLE_CLOCK()
+#define SPC5_FLEXCAN0_DISABLE_CLOCK()
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_MB 32
+#define SPC5_FLEXCAN1_SHARED_IRQ FALSE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector173
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector174
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER vector176
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_HANDLER vector177
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_HANDLER vector178
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_HANDLER vector179
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_HANDLER vector180
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_HANDLER vector181
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_HANDLER vector182
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_HANDLER vector183
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_HANDLER vector184
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_HANDLER vector185
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_HANDLER vector186
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_HANDLER vector187
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_HANDLER vector188
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_HANDLER vector189
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_HANDLER vector190
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_HANDLER vector191
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector192
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 173
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 174
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_NUMBER 176
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_NUMBER 177
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_NUMBER 178
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_NUMBER 179
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_NUMBER 180
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_NUMBER 181
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_NUMBER 182
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_NUMBER 183
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_NUMBER 184
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_NUMBER 185
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_NUMBER 186
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_NUMBER 187
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_NUMBER 188
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_NUMBER 189
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_NUMBER 190
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_NUMBER 191
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 192
+#define SPC5_FLEXCAN1_ENABLE_CLOCK()
+#define SPC5_FLEXCAN1_DISABLE_CLOCK()
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/typedefs.h b/os/hal/ports/SPC5/SPC563Mxx/typedefs.h new file mode 100644 index 000000000..b1db5e9bf --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC563Mxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC563Mxx/xpc563m.h b/os/hal/ports/SPC5/SPC563Mxx/xpc563m.h new file mode 100644 index 000000000..8ee2b5787 --- /dev/null +++ b/os/hal/ports/SPC5/SPC563Mxx/xpc563m.h @@ -0,0 +1,4123 @@ +/**************************************************************************/
+
+/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */
+/* VERSION: 2.0 All Rights Reserved */
+/* */
+/* DESCRIPTION: */
+/* This file contain all of the register and bit field definitions for */
+/* MPC563xM. This version supports revision 1.0 and later. */
+/*========================================================================*/
+/* UPDATE HISTORY */
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
+/* --- ----------- --------- --------------------- */
+/* 1.0 G. Emerson 31/OCT/07 Initial version. */
+/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */
+/* Added ESYNCR1 ESYNCR2 SYNFMMR */
+/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */
+/* 8 channels in the middle of the range */
+/* do not exist */
+/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */
+/* RXIMR added */
+/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */
+/* SIU - Added SIU.ISEL0-3 */
+/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */
+/* MCM - Replaced ECSM with MCM */
+/* removing SWT registers as defined at */
+/* seperate memory location. PFLASH */
+/* registers pre-fixed with P*. Added PCT,*/
+/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/
+/* PBRIDGE - Removed as no PBRIDGE */
+/* registers. */
+/* INTC - Updated number of PSR from */
+/* 358 to 360. */
+/* mpc5500_spr.h - Added RI to MSR and NMI*/
+/* to MSCR. */
+/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */
+/* Changes to SIU.MIDR as per RM. */
+/* 1.5 May 2009 Changes to match documentation, removed*/
+/* Not released */
+/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/
+/* & R. Dees */
+/* INTC - All Processor 0 regs matched to previous */
+/* version */
+/* INTC - BCR renamed to MCR to match previous */
+/* version */
+/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */
+/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */
+/* registers added */
+/* INTC - 512 PSR registers instead of 364 */
+/* ECSM - (Internal - mcm -> ecsm in the source files*/
+/* for generating the header file */
+/* ECSM - All bits and regs got an additional "p" in */
+/* the name in the user manual for "Platform" */
+/* -> deleted to match */
+/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */
+/* MPC563xM -> deleted */
+/* ECSM - PROTECTION in the URM is one bitfield, */
+/* in mop5534 this are four: PROT1-4 -> */
+/* changed to match */
+/* EMCM - removed undocumented registers */
+/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */
+/* XBAR - removed AMPR and ASGPCR registers */
+/* XBAR - removed HPE bits for nonexistant masters */
+/* EBI - added: D16_31, AD_MUX and SETA bits */
+/* EBI - Added reserved register at address 0x4. */
+/* EBI - Corrected number of chip selects in for both*/
+/* the EBI_CS and the CAL_EBI_CS */
+/* SIU - corrected number of GPDO registers and */
+/* allowed for maximum PCR registers. */
+/* SWT - add KEY bit to CR, correct WND (from WNO) */
+/* SWT - add SK register */
+/* PMC - moved bits from CFGR to Status Register (SR)*/
+/* PMC - Added SR */
+/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */
+/* TORE, & TRFE to MCR. Added IBIC, OBIC, */
+/* DIVRC, IBIF, OBIF, DIVR to MSR. */
+/* changed OUTTEG to OUTTAG in OB */
+/* Change COEF to TAG in TAG register */
+/* EQADC - removed REDLCCR - not supported */
+/* FLASH - Aligned register and bit names with legacy*/
+/* 1.7 K. Odenthal 10/November/09 */
+/* SIU - changed PCR[n].PA from 3 bit to 4 bit */
+/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */
+/* DECFIL - changed COEF.R and TAP.R from 16 bit to */
+/* 32 bit */
+/* 2.0 K. Odenthal 12/February/2010 */
+/* TSENS - Temperature Sensor Module added to */
+/* header file */
+/* ANSI C Compliance - Register structures have a */
+/* Bitfield Tag ('B') tag only if there is */
+/* at least one Bitfiels defined. Empty */
+/* tags like 'vuint32_t:32;' are not */
+/* allowed. */
+/* DECFIL - removed MXCR register. This register is */
+/* not supported on this part */
+/* SIU - SWT_SEL bit added in SIU DIRER register */
+/* EDMA - removed HRSL, HRSH and GPOR registers. */
+/* Those registers are not supported in */
+/* that part. */
+/* ESCI - removed LDBG and DSF bits from LCR */
+/* registers. Those bits are not supported */
+/* in that part. */
+/* Those registers are not supported in */
+/* that part. */
+/**************************************************************************/
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
+
+#ifndef _MPC563M_H_
+#define _MPC563M_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+
+#endif /*
+ */
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif /*
+ */
+
+/****************************************************************************/
+/* MODULE : FMPLL */
+/****************************************************************************/
+ struct FMPLL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t PREDIV:3;
+ vuint32_t MFD:5;
+ vuint32_t:1;
+ vuint32_t RFD:3;
+ vuint32_t LOCEN:1;
+ vuint32_t LOLRE:1;
+ vuint32_t LOCRE:1;
+ vuint32_t:1; /* Reserved in MPC563xM
+
+ Deleted for legacy header version [mpc5534.h]:
+
+ <vuint32_t DISCLK:1> */
+ vuint32_t LOLIRQ:1;
+ vuint32_t LOCIRQ:1;
+ vuint32_t:13; /* Reserved in MPC563xM
+
+ Deleted for legacy header version [mpc5534.h]:
+
+ <vuint32_t RATE:1 >
+
+ <vuint32_t DEPTH:2>
+
+ <vuint32_t EXP:10 > */
+ } B;
+ } SYNCR;
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t LOLF:1;
+ vuint32_t LOC:1;
+ vuint32_t MODE:1;
+ vuint32_t PLLSEL:1;
+ vuint32_t PLLREF:1;
+ vuint32_t LOCKS:1;
+ vuint32_t LOCK:1;
+ vuint32_t LOCF:1;
+ vuint32_t:2; /* Reserved in MPC563xM
+
+ Deleted for legacy header version [mpc5534.h]:
+
+ <vuint32_t CALDONE:1>
+
+ <vuint32_t CALPASS:1> */
+ } B;
+ } SYNSR;
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EMODE:1;
+ vuint32_t CLKCFG:3;
+ vuint32_t:8;
+ vuint32_t EPREDIV:4;
+ vuint32_t:9;
+ vuint32_t EMFD:7;
+ } B;
+ } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t LOCEN:1;
+ vuint32_t LOLRE:1;
+ vuint32_t LOCRE:1;
+ vuint32_t LOLIRQ:1;
+ vuint32_t LOCIRQ:1;
+ vuint32_t:17;
+ vuint32_t ERFD:2;
+ } B;
+ } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */
+ int32_t FMPLL_reserved0[2];
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BSY:1;
+ vuint32_t MODEN:1;
+ vuint32_t MODSEL:1;
+ vuint32_t MODPERIOD:13;
+ vuint32_t:1;
+ vuint32_t INCSTEP:15;
+ } B;
+ } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */
+ };
+/****************************************************************************/
+/* MODULE : EBI */
+/****************************************************************************/
+ struct CS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BA:17; /* */
+ vuint32_t:3; /* */
+ vuint32_t PS:1; /* */
+ vuint32_t:3; /* */
+ vuint32_t AD_MUX:1; /* new in MPC563xM */
+ vuint32_t BL:1; /* */
+ vuint32_t WEBS:1; /* */
+ vuint32_t TBDIP:1; /* */
+ vuint32_t:1; /* */
+ vuint32_t SETA:1; /* new in MPC563xM */
+ vuint32_t BI:1; /* */
+ vuint32_t V:1; /* */
+ } B;
+ } BR; /* <URM>EBI_BR</URM> */
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AM:17; /* */
+ vuint32_t:7; /* */
+ vuint32_t SCY:4; /* */
+ vuint32_t:1; /* */
+ vuint32_t BSCY:2; /* */
+ vuint32_t:1; /* */
+ } B;
+ } OR; /* <URM>EBI_OR</URM> */
+ };
+ struct CAL_CS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BA:17; /* */
+ vuint32_t:3; /* */
+ vuint32_t PS:1; /* */
+ vuint32_t:3; /* */
+ vuint32_t AD_MUX:1; /* new in MPC563xM */
+ vuint32_t BL:1; /* */
+ vuint32_t WEBS:1; /* */
+ vuint32_t TBDIP:1; /* */
+ vuint32_t:1; /* */
+ vuint32_t SETA:1; /* new in MPC563xM */
+ vuint32_t BI:1; /* */
+ vuint32_t V:1; /* */
+ } B;
+ } BR; /* <URM>EBI_CAL_BR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AM:17; /* */
+ vuint32_t:7; /* */
+ vuint32_t SCY:4; /* */
+ vuint32_t:1; /* */
+ vuint32_t BSCY:2; /* */
+ vuint32_t:1; /* */
+ } B;
+ } OR; /* <URM>EBI_CAL_OR</URM> */
+
+ };
+
+ struct EBI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:5; /* */
+ vuint32_t SIZEEN:1; /* <URM>SIZEN</URM> */
+ vuint32_t SIZE:2; /* */
+ vuint32_t:8; /* */
+ vuint32_t ACGE:1; /* */
+ vuint32_t EXTM:1; /* */
+ vuint32_t EARB:1; /* */
+ vuint32_t EARP:2; /* */
+ vuint32_t:4; /* */
+ vuint32_t MDIS:1; /* */
+ vuint32_t:3; /* */
+ vuint32_t D16_31:1; /* new in MPC563xM */
+ vuint32_t AD_MUX:1; /* new in MPC563xM */
+ vuint32_t DBM:1; /* */
+ } B;
+ } MCR; /* EBI Module Configuration Register (MCR) <URM>EBI_MCR</URM> @baseaddress + 0x00 */
+
+ uint32_t EBI_reserved1[1];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30; /* */
+ vuint32_t TEAF:1; /* */
+ vuint32_t BMTF:1; /* */
+ } B;
+ } TESR; /* EBI Transfer Error Status Register (TESR) <URM>EBI_TESR</URM> @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16; /* */
+ vuint32_t BMT:8; /* */
+ vuint32_t BME:1; /* */
+ vuint32_t:7; /* */
+ } B;
+ } BMCR; /* <URM>EBI_BMCR</URM> @baseaddress + 0x0C */
+
+ struct CS_tag CS[4];
+
+ uint32_t EBI_reserved2[4];
+
+ /* Calibration registers */
+ struct CAL_CS_tag CAL_CS[4];
+
+ }; /* end of EBI_tag */
+/****************************************************************************/
+/* MODULE : FLASH */
+/****************************************************************************/
+/* 3 flash modules implemented. */
+/* HBL and HBS not used in Bank 0 / Array 0 */
+/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */
+/* Bank 1 / Array 1 or Bank 1 / Array 3 */
+/****************************************************************************/
+ struct FLASH_tag {
+ union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */
+ vuint32_t:4; /* Reserved */
+ vuint32_t SIZE:3; /* Array Size (Read Only) */
+ vuint32_t:1; /* Reserved */
+ vuint32_t LAS:3; /* Low Address Space (Read Only) */
+ vuint32_t:3; /* Reserved */
+ vuint32_t MAS:1; /* Mid Address Space (Read Only) */
+ vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* <LEGACY> BBEPE and EPE </LEGACY> */
+ vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */
+ vuint32_t:2; /* Reserved */
+ vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */
+ vuint32_t DONE:1; /* Status (Read Only) */
+ vuint32_t PEG:1; /* Program/Erase Good (Read Only) */
+ vuint32_t:4; /* Reserved *//* <LEGACY> RSD PEG STOP RSVD </LEGACY> */
+ vuint32_t PGM:1; /* Program (Read/Write) */
+ vuint32_t PSUS:1; /* Program Suspend (Read/Write) */
+ vuint32_t ERS:1; /* Erase (Read/Write) */
+ vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */
+ vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */
+ } B;
+ } MCR;
+
+ union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */
+ vuint32_t:10; /* Reserved */
+ vuint32_t SLOCK:1; /*<URM>SLK</URM> *//* Shadow address space block lock (Read/Write) */
+ vuint32_t:2; /* Reserved */
+ vuint32_t MLOCK:2; /*<URM>MLK</URM> *//* Mid address space block lock (Read/Write) */
+ vuint32_t:8; /* Reserved */
+ vuint32_t LLOCK:8; /*<URM>LLK</URM> *//* Low address space block lock (Read/Write) */
+ } B;
+ } LMLR; /*<URM>LML</URM> */
+
+ union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1; /* High address space Block Enable (Read Only) */
+ vuint32_t:27; /* Reserved */
+ vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */
+ } B;
+ } HLR; /*<URM>HBL</URM> */
+
+ union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */
+ vuint32_t:10; /* Reserved */
+ vuint32_t SSLOCK:1; /*<URM>SSLK</URM> *//* Secondary shadow address space block lock (Read/Write) */
+ vuint32_t:2; /* Reserved */
+ vuint32_t SMLOCK:2; /*<URM>SMK</URM> *//* Secondary mid address space block lock (Read/Write) */
+ vuint32_t:8; /* Reserved */
+ vuint32_t SLLOCK:8; /*<URM>SLK</URM> *//* Secondary low address space block lock (Read/Write) */
+ } B;
+ } SLMLR; /*<URM>SLL</URM> */
+
+ union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */
+ vuint32_t R;
+ struct {
+ vuint32_t:14; /* Reserved */
+ vuint32_t MSEL:2; /*<URM>MSL</URM> *//* Mid address space block select (Read/Write) */
+ vuint32_t:8; /* Reserved */
+ vuint32_t LSEL:8; /*<URM>LSL</URM> *//* Low address space block select (Read/Write) */
+ } B;
+ } LMSR; /*<URM>LMS</URM> */
+
+ union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* Reserved */
+ vuint32_t HBSEL:4; /*<URM>HSL</URM> *//* High address space block select (Read/Write) */
+ } B;
+ } HSR; /*<URM>HBS</URM> */
+
+ union { /* Address Register (ADR)@baseaddress + 0x18 */
+ vuint32_t R;
+ struct {
+ vuint32_t SAD:1; /* Shadow address (Read Only) */
+ vuint32_t:10; /* Reserved */
+ vuint32_t ADDR:18; /*<URM>AD</URM> *//* Address 20-3 (Read Only) */
+ vuint32_t:3; /* Reserved */
+ } B;
+ } AR; /*<URM>ADR</URM> */
+
+ union { /* @baseaddress + 0x1C */
+ vuint32_t R;
+ struct {
+ vuint32_t:7; /* Reserved */
+ vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */
+ vuint32_t:4; /* Reserved */
+ vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */
+ vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */
+ vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */
+ vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */
+ vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */
+ vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */
+ vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */
+ vuint32_t:1; /* Reserved */
+ vuint32_t DPFEN:1; /*<URM>DPFE</URM> *//* Data Prefetch Enable (Read/Write) */
+ vuint32_t:1; /* Reserved */
+ vuint32_t IPFEN:1; /*<URM>IPFE</URM> *//* Instruction Prefetch Enable (Read/Write) */
+ vuint32_t:1; /* Reserved */
+ vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */
+ vuint32_t BFEN:1; /*<URM>BFE</URM> *//* Buffer Enable (Read/Write) */
+ } B;
+ } BIUCR; /*<URM>PFCR1</URM> */
+
+ union { /* @baseaddress + 0x20 */
+ vuint32_t R;
+ struct {
+ vuint32_t:24; /* Reserved */
+ vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */
+ vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */
+ vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */
+ vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */
+ } B;
+ } BIUAPR; /*<URM>PFAPR</URM> */
+
+ union { /* @baseaddress + 0x24 */
+ vuint32_t R;
+ struct {
+ vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */
+ vuint32_t:30; /* Reserved */
+ } B;
+ } BIUCR2;
+
+ union { /* @baseaddress + 0x28 */
+ vuint32_t R;
+ struct {
+ vuint32_t:25; /* Reserved */
+ vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */
+ vuint32_t:1; /* Reserved */
+ vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */
+ vuint32_t:1; /* Reserved */
+ vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */
+ vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */
+ } B;
+ } PFCR3;
+
+ int32_t FLASH_reserverd_89[4];
+
+ union { /* User Test 0 (UT0) register@baseaddress + 0x3c */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1; /* User test enable (Read/Clear) */
+ vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */
+ vuint32_t:6; /* Reserved */
+ vuint32_t DSI:8; /* Data syndrome input (Read/Write) */
+ vuint32_t:9; /* Reserved */
+ vuint32_t:1; /* Reserved (Read/Write) */
+ vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */
+ vuint32_t MRV:1; /* Margin Read Value (Read/Write) */
+ vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */
+ vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */
+ vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */
+ vuint32_t AID:1; /* Array Integrity Done (Read Only) */
+ } B;
+ } UT0;
+
+ union { /* User Test 1 (UT1) register@baseaddress + 0x40 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32; /* Data Array Input (Read/Write) */
+ } B;
+ } UT1;
+
+ union { /* User Test 2 (UT2) register@baseaddress + 0x44 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32; /* Data Array Input (Read/Write) */
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32; /* Multiple input Signature (Read/Write) */
+ } B;
+ } UMISR[5];
+
+ }; /* end of FLASH_tag */
+/****************************************************************************/
+/* MODULE : SIU */
+/****************************************************************************/
+ struct SIU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t S_F:1; /* Identifies the Manufacturer <URM>S/F</URM> */
+ vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) <URM>Flash Size 1</URM> */
+ vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) <URM>Flash Size 1</URM> */
+ vuint32_t TEMP_RANGE:2; /* Define maximum operating range <URM>Temp Range</URM> */
+ vuint32_t:1; /* Reserved for future enhancements */
+ vuint32_t MAX_FREQ:2; /* Define maximum device speed <URM>Max Freq</URM> */
+ vuint32_t:1; /* Reserved for future enhancements */
+ vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V <URM>Supply</URM> */
+ vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product <URM>Part Number</URM> */
+ vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */
+ vuint32_t:2; /* Reserved for future enhancements */
+ vuint32_t EE:1; /* Indicates if Data Flash is present */
+ vuint32_t:3; /* Reserved for future enhancements */
+ vuint32_t FR:1; /* Indicates if Data FlexRay is present */
+ } B;
+ } MIDR2; /* MCU ID Register 2 <URM>SIU_MIDR2</URM> @baseaddress + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16; /* Device part number: 0x5633 */
+ vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */
+ vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */
+ vuint32_t:2; /* Reserved */
+ vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */
+ } B;
+ } MIDR; /* MCU ID Register (MIDR) <URM>SIU_MIDR</URM> @baseaddress + 0x8 */
+
+ union {
+ vuint32_t R;
+ } TST; /* SIU Test Register (SIU_TST) <URM>SIU_TST</URM> @baseaddress + 0xC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PORS:1; /* Power-On Reset Status */
+ vuint32_t ERS:1; /* External Reset Status */
+ vuint32_t LLRS:1; /* Loss of Lock Reset Status */
+ vuint32_t LCRS:1; /* Loss of Clock Reset Status */
+ vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */
+ vuint32_t CRS:1; /* Checkstop Reset Status */
+ vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */
+ vuint32_t:7; /* */
+ vuint32_t SSRS:1; /* Software System Reset Status */
+ vuint32_t SERF:1; /* Software External Reset Flag */
+ vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */
+ vuint32_t:11; /* */
+ vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */
+ vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */
+ vuint32_t RGF:1; /* RESET Glitch Flag */
+ } B;
+ } RSR; /* Reset Status Register (SIU_RSR) <URM>SIU_RSR</URM> @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SSR:1; /* Software System Reset */
+ vuint32_t SER:1; /* Software External Reset */
+ vuint32_t:14; /* */
+ vuint32_t CRE:1; /* Checkstop Reset Enable */
+ vuint32_t:15; /* */
+ } B;
+ } SRCR; /* System Reset Control Register (SRCR) <URM>SIU_SRCR</URM> @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */
+ vuint32_t:7; /* */
+ vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */
+ vuint32_t:7; /* */
+ vuint32_t EIF15:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF14:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF13:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF12:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF11:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF10:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF9:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF8:1; /* External Interrupt Request Flag x */
+ vuint32_t:3; /* (reserved in MPC563xM) */
+ vuint32_t EIF4:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF3:1; /* External Interrupt Request Flag x */
+ vuint32_t:2; /* (reserved in MPC563xM) */
+ vuint32_t EIF0:1; /* External Interrupt Request Flag x */
+ } B;
+ } EISR; /* SIU External Interrupt Status Register (EISR) <URM>SIU_EISR</URM> @baseaddress + 0x18 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */
+ vuint32_t:7; /* */
+ vuint32_t SWT_SEL:1;
+ vuint32_t:7;
+ vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */
+ } B;
+ } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) <URM>SIU_DIRER</URM> @baseaddress + 0x1C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* */
+ vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */
+ vuint32_t:2; /* reserved in MPC563xM */
+ vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */
+ } B;
+ } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) <URM>SIU_DIRSR</URM> @baseaddress + 0x20 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16; /* */
+ vuint32_t OVF15:1; /* Overrun Flag x */
+ vuint32_t OVF14:1; /* Overrun Flag x */
+ vuint32_t OVF13:1; /* Overrun Flag x */
+ vuint32_t OVF12:1; /* Overrun Flag x */
+ vuint32_t OVF11:1; /* Overrun Flag x */
+ vuint32_t OVF10:1; /* Overrun Flag x */
+ vuint32_t OVF9:1; /* Overrun Flag x */
+ vuint32_t OVF8:1; /* Overrun Flag x */
+ vuint32_t:3; /* reserved in MPC563xM */
+ vuint32_t OVF4:1; /* Overrun Flag x */
+ vuint32_t OVF3:1; /* Overrun Flag x */
+ vuint32_t:2; /* reserved in MPC563xM */
+ vuint32_t OVF0:1; /* Overrun Flag x */
+ } B;
+ } OSR; /* Overrun Status Register (OSR) <URM>SIU_OSR</URM> @baseaddress + 0x24 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16; /* */
+ vuint32_t ORE15:1; /* Overrun Request Enable x */
+ vuint32_t ORE14:1; /* Overrun Request Enable x */
+ vuint32_t ORE13:1; /* Overrun Request Enable x */
+ vuint32_t ORE12:1; /* Overrun Request Enable x */
+ vuint32_t ORE11:1; /* Overrun Request Enable x */
+ vuint32_t ORE10:1; /* Overrun Request Enable x */
+ vuint32_t ORE9:1; /* Overrun Request Enable x */
+ vuint32_t ORE8:1; /* Overrun Request Enable x */
+ vuint32_t:3; /* reserved in MPC563xM */
+ vuint32_t ORE4:1; /* Overrun Request Enable x */
+ vuint32_t ORE3:1; /* Overrun Request Enable x */
+ vuint32_t:2; /* reserved in MPC563xM */
+ vuint32_t ORE0:1; /* Overrun Request Enable x */
+ } B;
+ } ORER; /* Overrun Request Enable Register (ORER) <URM>SIU_ORER</URM> @baseaddress + 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */
+ vuint32_t:15; /* reserved in MPC563xM */
+ vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t:3; /* reserved in MPC563xM */
+ vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t:2; /* reserved in MPC563xM */
+ vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */
+ } B;
+ } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) <URM>SIU_IREER</URM> @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */
+ vuint32_t Reserverd:15; /* */
+ vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t:3; /* reserved in MPC563xM */
+ vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t:2; /* reserved in MPC563xM */
+ vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */
+ } B;
+ } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) <URM>SIU_IFEER</URM> @baseaddress + 0x30 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* */
+ vuint32_t DFL:4; /* Digital Filter Length */
+ } B;
+ } IDFR; /* External IRQ Digital Filter Register (IDFR) <URM>SIU_IDFR</URM> @baseaddress + 0x40 */
+
+ int32_t SIU_reserverd_153[3];
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2; /* */
+ vuint16_t PA:4; /* */
+ vuint16_t OBE:1; /* */
+ vuint16_t IBE:1; /* */
+ vuint16_t DSC:2; /* */
+ vuint16_t ODE:1; /* */
+ vuint16_t HYS:1; /* */
+ vuint16_t SRC:2; /* */
+ vuint16_t WPE:1; /* */
+ vuint16_t WPS:1; /* */
+ } B;
+ } PCR[512]; /* Pad Configuration Register (PCR) <URM>SIU_PCR</URM> @baseaddress + 0x600 */
+
+ int32_t SIU_reserverd_164[112];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:7; /* */
+ vuint8_t PDO:1; /* */
+ } B;
+ } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) <URM>SIU_GDPO</URM> @baseaddress + 0x800 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:7; /* */
+ vuint8_t PDI:1; /* */
+ } B;
+ } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) <URM>SIU_GDPI</URM> @baseaddress + 0x900 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */
+ vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */
+ vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */
+ vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */
+ vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */
+ vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */
+ vuint32_t:20; /* */
+ } B;
+ } ETISR; /* eQADC Trigger Input Select Register (ETISR) <URM>SIU_ETISR</URM> @baseaddress + 0x904 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ESEL15:2; /* External IRQ Input Select x */
+ vuint32_t ESEL14:2; /* External IRQ Input Select x */
+ vuint32_t ESEL13:2; /* External IRQ Input Select x */
+ vuint32_t ESEL12:2; /* External IRQ Input Select x */
+ vuint32_t ESEL11:2; /* External IRQ Input Select x */
+ vuint32_t ESEL10:2; /* External IRQ Input Select x */
+ vuint32_t ESEL9:2; /* External IRQ Input Select x */
+ vuint32_t ESEL8:2; /* External IRQ Input Select x */
+ vuint32_t ESEL7:2; /* External IRQ Input Select x */
+ vuint32_t ESEL6:2; /* External IRQ Input Select x */
+ vuint32_t ESEL5:2; /* External IRQ Input Select x */
+ vuint32_t ESEL4:2; /* External IRQ Input Select x */
+ vuint32_t ESEL3:2; /* External IRQ Input Select x */
+ vuint32_t ESEL2:2; /* External IRQ Input Select x */
+ vuint32_t ESEL1:2; /* External IRQ Input Select x */
+ vuint32_t ESEL0:2; /* External IRQ Input Select x */
+ } B;
+ } EIISR; /* External IRQ Input Select Register (EIISR) <URM>SIU_EIISR</URM> @baseaddress + 0x908 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* reserved in MPC563xM */
+ vuint32_t SINSELB:2; /* DSPI_B Data Input Select <URM>SIN-SELB</URM> */
+ vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select <URM>SS-SELB</URM> */
+ vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select <URM>SCK-SELB</URM> */
+ vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select <URM>TRIG-SELB</URM> */
+ vuint32_t SINSELC:2; /* DSPI_C Data Input Select <URM>SIN-SELC</URM> */
+ vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select <URM>SSSELC</URM> */
+ vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select <URM>SCK-SELC</URM> */
+ vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select <URM>TRIG-SELC</URM> */
+ vuint32_t:8; /* reserved in MPC563xM */
+ } B;
+ } DISR; /* DSPI Input Select Register (DISR) <URM>SIU_DISR</URM> @baseaddress + 0x90c */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2; /* */
+ vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL5</URM> */
+ vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL4</URM> */
+ vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL3</URM> */
+ vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL2</URM> */
+ vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL1</URM> */
+ vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection <URM>eTSEL0</URM> */
+ } B;
+ } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) <URM>SIU_ISEL3</URM> @baseaddress + 0x920 */
+
+ int32_t SIU_reserverd_214[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11; /* */
+ vuint32_t ESEL5:1; /* <URM>eSEL5</URM> */
+ vuint32_t:3; /* */
+ vuint32_t ESEL4:1; /* <URM>eSEL4</URM> */
+ vuint32_t:3; /* */
+ vuint32_t ESEL3:1; /* <URM>eSEL3</URM> */
+ vuint32_t:3; /* */
+ vuint32_t ESEL2:1; /* <URM>eSEL2</URM> */
+ vuint32_t:3; /* */
+ vuint32_t ESEL1:1; /* <URM>eSEL1</URM> */
+ vuint32_t:3; /* */
+ vuint32_t ESEL0:1; /* <URM>eSEL0</URM> */
+ } B;
+ } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) <URM>SIU_ISEL8</URM> @baseaddress + 0x924 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27; /* */
+ vuint32_t ETSEL0A:5; /* <URM>eTSEL0A</URM> */
+ } B;
+ } ISEL9; /* MUX Select Register 9(ISEL9) <URM>SIU_ISEL9</URM> @baseaddress + 0x980 */
+
+ int32_t SIU_reserverd_230[22];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14; /* */
+ vuint32_t MATCH:1; /* Compare Register Match */
+ vuint32_t DISNEX:1; /* Disable Nexus */
+ vuint32_t:14; /* */
+ vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */
+ vuint32_t:1; /* */
+ } B;
+ } CCR; /* Chip Configuration Register (CCR) <URM>SIU_CCR</URM> @baseaddress + 0x984 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */
+ vuint32_t EBTS:1; /* External Bus Tap Select */
+ vuint32_t:1; /* */
+ vuint32_t EBDF:2; /* External Bus Division Factor */
+ } B;
+ } ECCR; /* External Clock Control Register (ECCR) <URM>SIU_ECCR</URM> @baseaddress + 0x988 */
+
+ union {
+ vuint32_t R;
+ } CARH; /* Compare A High Register (CARH) <URM>SIU_CMPAH</URM> @baseaddress + 0x98C */
+
+ union {
+ vuint32_t R;
+ } CARL; /* Compare A Low Register (CARL) <URM>SIU_CMPAL</URM> @baseaddress + 0x990 */
+
+ union {
+ vuint32_t R;
+ } CBRH; /* Compare B High Register (CBRH) <URM>SIU_CMPBH</URM> @baseaddress + 0x994 */
+
+ union {
+ vuint32_t R;
+ } CBRL; /* Compare B Low Register (CBRL) <URM>SIU_CMPBL</URM> @baseaddress + 0x9A0 */
+
+ int32_t SIU_reserverd_250[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27; /* Reserved */
+ vuint32_t BYPASS:1; /* Bypass bit <URM>BY-PASS</URM> */
+ vuint32_t SYSCLKDIV:2; /* System Clock Divide <URM>SYS-CLKDIV</URM> */
+ vuint32_t:2; /* Reserved */
+ } B;
+ } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) <URM>SIU_SYSDIV</URM> @baseaddress + 0x9A4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */
+ vuint32_t:2; /* Reserved */
+ vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */
+ vuint32_t:1; /* Reserved */
+ vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */
+ vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */
+ vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */
+ vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */
+ vuint32_t:1; /* Reserved */
+ vuint32_t MIOSSTP:1; /* Stop mode request */
+ vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */
+ vuint32_t:1; /* Reserved */
+ vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */
+ vuint32_t:3; /* Reserved */
+ vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */
+ vuint32_t:1; /* Reserved */
+ vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */
+ vuint32_t:1; /* Reserved */
+ vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */
+ vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */
+ vuint32_t:7; /* Reserved */
+ vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */
+ vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */
+ } B;
+ } HLT; /* Halt Register (HLT) (new in MPC563xM) <URM>SIU_HLT</URM> @baseaddress + 0x9A8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:2; /* Reserved */
+ vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:1; /* Reserved */
+ vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:1; /* Reserved */
+ vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */
+ vuint32_t:1; /* Reserved */
+ vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:3; /* Reserved */
+ vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */
+ vuint32_t:1; /* Reserved */
+ vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */
+ vuint32_t:1; /* Reserved */
+ vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:7; /* Reserved */
+ vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */
+ vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */
+ } B;
+ } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) <URM>SIU_HLTACK</URM> @baseaddress + 0x9ac */
+
+ int32_t SIU_reserved3[21];
+
+ }; /* end of SIU_tag */
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+ struct EMIOS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DOZEEN:1; /* new in MPC563xM */
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t ETB:1;
+ vuint32_t GPREN:1;
+ vuint32_t:6;
+ vuint32_t SRV:4;
+ vuint32_t GPRE:8;
+ vuint32_t:8;
+ } B;
+ } MCR; /* Module Configuration Register <URM>EMIOSMCR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR; /* Global FLAG Register <URM>EMIOSGFLAG</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR; /* Output Update Disable Register <URM>EMIOSOUDIS</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* */
+ vuint32_t CHDIS23:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS22:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS21:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS20:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS19:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS18:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS17:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS16:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS15:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS14:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS13:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS12:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS11:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS10:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS9:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS8:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS7:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS6:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS5:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS4:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS3:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS2:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS1:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS0:1; /* Enable Channel [n] bit */
+ } B;
+ } UCDIS; /* Disable Channel (EMIOSUCDIS) <URM>EMIOSUCDIS</URM> (new in MPC563xM) @baseaddress + 0x0C */
+
+ int32_t EMIOS_reserverd_30[4];
+
+ struct {
+ union {
+ vuint32_t R; /* Channel A Data Register */
+ } CADR; /* <URM>EMIOSA</URM> */
+
+ union {
+ vuint32_t R; /* Channel B Data Register */
+ } CBDR; /* <URM>EMIOSB</URM> */
+
+ union {
+ vuint32_t R; /* Channel Counter Register */
+ } CCNTR; /* <URM>EMIOSCNT</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t ODIS:1;
+ vuint32_t ODISSL:2;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPREN:1;
+ vuint32_t DMA:1;
+ vuint32_t:1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t:3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t:1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR; /* Channel Control Register <URM>EMIOSC</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:15;
+ vuint32_t OVFL:1;
+ vuint32_t:12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR; /* Channel Status Register <URM>EMIOSS</URM> */
+
+ union {
+ vuint32_t R; /* Alternate Channel A Data Register */
+ } ALTA; /* new in MPC563xM <URM>EMIOSALTA</URM> */
+
+ uint32_t emios_channel_reserved[2];
+
+ } CH[24];
+
+ }; /* end of EMIOS_tag */
+/****************************************************************************/
+/* MODULE : ETPU */
+/****************************************************************************/
+ struct ETPU_tag { /* offset 0x0000 */
+ union { /* eTPU module configuration register@baseaddress + 0x00 */
+ vuint32_t R;
+ struct {
+ vuint32_t GEC:1; /* Global Exception Clear */
+ vuint32_t SDMERR:1; /* */
+ vuint32_t WDTOA:1; /* */
+ vuint32_t WDTOB:1; /* */
+ vuint32_t MGE1:1; /* <URM>MGEA</URM> */
+ vuint32_t MGE2:1; /* <URM>MGEB</URM> */
+ vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. <URM>ILFFA</URM> */
+ vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. <URM>ILFFB</URM> */
+ vuint32_t SCMERR:1; /* . */
+ vuint32_t:2; /* */
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */
+ vuint32_t:4; /* */
+ vuint32_t SCMMISC:1; /* SCM MISC Flag */
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */
+ vuint32_t:2; /* */
+ vuint32_t VIS:1; /* SCM Visability */
+ vuint32_t:5; /* */
+ vuint32_t GTBE:1; /* Global Time Base Enable */
+ } B;
+ } MCR; /* <URM>ETPU_MCR</URM> */
+
+ /* offset 0x0004 */
+ union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */
+ vuint32_t R;
+ struct {
+ vuint32_t STS:1; /* Start Status bit */
+ vuint32_t CTBASE:5; /* Channel Transfer Base */
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address <URM>PBBASE</URM> */
+ vuint32_t PWIDTH:1; /* Parameter Width */
+ vuint32_t PARAM0:7; /* Channel Parameter 0 <URM>PARM0</URM> */
+ vuint32_t WR:1; /* */
+ vuint32_t PARAM1:7; /* Channel Parameter 1 <URM>PARM1</URM> */
+ } B;
+ } CDCR; /*<URM>ETPU_CDCR</URM> */
+
+ vuint32_t ETPU_reserved_0;
+
+ /* offset 0x000C */
+ union { /* eTPU MISC Compare Register@baseaddress + 0x0c */
+ vuint32_t R;
+ struct {
+ vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. <URM>EMISCCMP</URM> */
+ } B;
+ } MISCCMPR /*<URM>ETPU_MISCCMPR</URM> */ ;
+
+ /* offset 0x0010 */
+ union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */
+ vuint32_t R;
+ struct {
+ vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */
+ } B;
+ } SCMOFFDATAR; /*<URM>ETPU_SCMOFFDATAR</URM> */
+
+ /* offset 0x0014 */
+ union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */
+ vuint32_t R;
+ struct {
+ vuint32_t FEND:1; /* Force END */
+ vuint32_t MDIS:1; /* Low power Stop */
+ vuint32_t:1; /* */
+ vuint32_t STF:1; /* Stop Flag */
+ vuint32_t:4; /* */
+ vuint32_t HLTF:1; /* Halt Mode Flag */
+ vuint32_t:3; /* */
+ vuint32_t FCSS:1;
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
+ vuint32_t CDFC:2; /* */
+ vuint32_t:1; /* */
+ vuint32_t ERBA:5; /* */
+ vuint32_t SPPDIS:1; /* */
+ vuint32_t:2; /* */
+ vuint32_t ETB:5; /* Entry Table Base */
+ } B;
+ } ECR_A; /*<URM>ETPU_ECR</URM> */
+
+ vuint32_t ETPU_reserved_1[2];
+
+ /* offset 0x0020 */
+ union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */
+ vuint32_t R;
+ struct {
+ vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
+ vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
+ vuint32_t AM:2; /* Angle Mode */
+ vuint32_t:3; /* */
+ vuint32_t TCR2P:6; /* TCR2 Prescaler Control */
+ vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
+ vuint32_t TCR1CS:1; /* */
+ vuint32_t:5; /* */
+ vuint32_t TCR1P:8; /* TCR1 Prescaler Control */
+ } B;
+ } TBCR_A; /*<URM>ETPU_TBCR</URM> */
+
+ /* offset 0x0024 */
+ union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* */
+ vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */
+ } B;
+ } TB1R_A; /*<URM>ETPU_TB1R</URM> */
+
+ /* offset 0x0028 */
+ union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* */
+ vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */
+ } B;
+ } TB2R_A; /*<URM>ETPU_TB2R</URM> */
+
+ /* offset 0x002C */
+ union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */
+ vuint32_t R;
+ struct {
+ vuint32_t REN1:1; /* Resource Enable TCR1 */
+ vuint32_t RSC1:1; /* Resource Control TCR1 */
+ vuint32_t:2; /* */
+ vuint32_t SERVER_ID1:4; /* */
+ vuint32_t:4; /* */
+ vuint32_t SRV1:4; /* Resource Server Slot */
+ vuint32_t REN2:1; /* Resource Enable TCR2 */
+ vuint32_t RSC2:1; /* Resource Control TCR2 */
+ vuint32_t:2; /* */
+ vuint32_t SERVER_ID2:4; /* */
+ vuint32_t:4; /* */
+ vuint32_t SRV2:4; /* Resource Server Slot */
+ } B;
+ } REDCR_A; /*<URM>ETPU_REDCR</URM> */
+
+ vuint32_t ETPU_reserved_2[12];
+
+ /* offset 0x0060 */
+ union { /* ETPU1 WDTR Register */
+ vuint32_t R;
+ struct {
+ vuint32_t WDM:2;
+ vuint32_t:14;
+ vuint32_t WDCNT:16;
+ } B;
+ } WDTR_A;
+
+ vuint32_t ETPU1_reserved_3;
+
+ /* offset 0x0068 */
+ union { /* ETPU1 IDLE Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IDLE_CNT:31;
+ vuint32_t ICLR:1;
+ } B;
+ } IDLE_A;
+
+ vuint32_t ETPU_reserved_4[101];
+
+ /* offset 0x0200 */
+ union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */
+ } B;
+ } CISR_A; /* <URM>ETPU_CISR</URM> */
+
+ int32_t ETPU_reserved_5[3];
+
+ /* offset 0x0210 */
+ union { /* @baseaddress + 0x210 */
+ vuint32_t R;
+ struct {
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
+ } B;
+ } CDTRSR_A; /* <URM>ETPU_CDTRSR</URM> */
+
+ int32_t ETPU_reserved_6[3];
+
+ /* offset 0x0220 */
+ union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
+ } B;
+ } CIOSR_A; /* <URM>ETPU_CIOSR</URM> */
+
+ int32_t ETPU_reserved_7[3];
+
+ /* offset 0x0230 */
+ union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */
+ vuint32_t R;
+ struct {
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
+ } B;
+ } CDTROSR_A; /* <URM>ETPU_CDTROSR</URM> */
+
+ int32_t ETPU_reserved_8[3];
+
+ /* offset 0x0240 */
+ union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
+ } B;
+ } CIER_A; /* <URM>ETPU_CIER</URM> */
+
+ int32_t ETPU_reserved_9[3];
+
+ /* offset 0x0250 */
+ union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */
+ vuint32_t R;
+ struct {
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } CDTRER_A; /* <URM>ETPU_CDTRER</URM> */
+
+ int32_t ETPU_reserved_10[3];
+
+ /* offset 0x0260 */
+ union { /* ETPUWDSR - eTPU Watchdog Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } WDSR_A;
+
+ int32_t ETPU_reserved_11[7];
+
+ /* offset 0x0280 */
+ union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } CPSSR_A; /* <URM>ETPU_CPSSR</URM> */
+
+ int32_t ETPU_reserved_12[3];
+
+ /* offset 0x0290 */
+ union { /* ETPUCSSR - eTPU Channel Service Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } CSSR_A; /* <URM>ETPU_CSSR</URM> */
+
+ int32_t ETPU_reserved_13[3];
+ int32_t ETPU_reserved_14[88];
+
+/***************************** Channels ********************************/
+/* Note not all devices implement all channels or even 2 engines */
+/* Each eTPU engine can implement 64 channels, however most devcies */
+/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */
+/* engines per instantiation */
+/***********************************************************************/
+
+ struct {
+ union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIE:1; /* Channel Interruput Enable */
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */
+ vuint32_t CPR:2; /* Channel Priority */
+ vuint32_t:2; /* */
+ vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */
+ vuint32_t ETCS:1; /* Entry Table Condition Select */
+ vuint32_t:3; /* */
+ vuint32_t CFS:5; /* Channel Function Select */
+ vuint32_t ODIS:1; /* Output disable */
+ vuint32_t OPOL:1; /* output polarity */
+ vuint32_t:3; /* */
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */
+ } B;
+ } CR; /* <URM>ETPU_CnCR</URM> */
+
+ union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIS:1; /* Channel Interruput Status */
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */
+ vuint32_t:6; /* */
+ vuint32_t DTRS:1; /* Data Transfer Status */
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */
+ vuint32_t:6; /* */
+ vuint32_t IPS:1; /* Input Pin State */
+ vuint32_t OPS:1; /* Output Pin State */
+ vuint32_t OBE:1; /* Output Pin State */
+ vuint32_t:11; /* */
+ vuint32_t FM1:1; /* Function mode */
+ vuint32_t FM0:1; /* Function mode */
+ } B;
+ } SCR; /* <URM>ETPU_CnSCR</URM> */
+
+ union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */
+ vuint32_t R;
+ struct {
+ vuint32_t:29; /* Host Service Request */
+ vuint32_t HSR:3; /* */
+ } B;
+ } HSRR; /* <URM>ETPU_CnHSRR</URM> */
+ int32_t ETPU_reserved_18;
+
+ } CHAN[127];
+ /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */
+ }; /* end of ETPU_tag */
+/****************************************************************************/
+/* MODULE : XBAR */
+/****************************************************************************/
+ struct XBAR_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4; /* Master 7 Priority - Not implemented */
+ vuint32_t:4; /* Master 6 Priority - Not implemented */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */
+ vuint32_t:1; /* */
+ vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */
+ vuint32_t:1; /* */
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */
+ } B;
+ } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */
+
+ int32_t XBAR_reserverd_35[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1; /* Read Only */
+ vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */
+ vuint32_t:6; /* Slave General Purpose Control Register Reserved */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:6; /* */
+ vuint32_t ARB:2; /* Arbitration Mode */
+ vuint32_t:2; /* */
+ vuint32_t PCTL:2; /* Parking Control */
+ vuint32_t:1; /* */
+ vuint32_t PARK:3; /* PARK */
+ } B;
+ } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */
+
+ int32_t XBAR_reserverd_71[59];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4; /* Master 7 Priority - Not implemented */
+ vuint32_t:4; /* Master 6 Priority - Not implemented */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */
+ vuint32_t:1; /* */
+ vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */
+ vuint32_t:1; /* */
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */
+ } B;
+ } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */
+
+ int32_t XBAR_reserverd_105[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1; /* Read Only */
+ vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */
+ vuint32_t:6; /* Slave General Purpose Control Register Reserved */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:6; /* */
+ vuint32_t ARB:2; /* Arbitration Mode */
+ vuint32_t:2; /* */
+ vuint32_t PCTL:2; /* Parking Control */
+ vuint32_t:1; /* */
+ vuint32_t PARK:3; /* PARK */
+ } B;
+ } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */
+
+ int32_t XBAR_reserverd_141[59];
+
+/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */
+
+ int32_t XBAR_reserverd_211[64];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4; /* Master 7 Priority - Not implemented */
+ vuint32_t:4; /* Master 6 Priority - Not implemented */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */
+ vuint32_t:1; /* */
+ vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */
+ vuint32_t:1; /* */
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */
+ } B;
+ } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */
+
+ int32_t XBAR_reserverd_245[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1; /* Read Only */
+ vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */
+ vuint32_t:6; /* Slave General Purpose Control Register Reserved */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:6; /* */
+ vuint32_t ARB:2; /* Arbitration Mode */
+ vuint32_t:2; /* */
+ vuint32_t PCTL:2; /* Parking Control */
+ vuint32_t:1; /* */
+ vuint32_t PARK:3; /* PARK */
+ } B;
+ } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */
+
+ int32_t XBAR_reserverd_281[59];
+
+ /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */
+
+ int32_t XBAR_reserverd_351[64];
+
+ /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */
+
+ int32_t XBAR_reserverd_421[64];
+
+ /* Slave Port 6 not implemented @baseaddress + 0x610 */
+
+ int32_t XBAR_reserverd_491[64];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4; /* Master 7 Priority - Not implemented */
+ vuint32_t:4; /* Master 6 Priority - Not implemented */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:1; /* */
+ vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */
+ vuint32_t:1; /* */
+ vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */
+ vuint32_t:1; /* */
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */
+ } B;
+ } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */
+
+ int32_t XBAR_reserverd_525[3];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1; /* Read Only */
+ vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */
+ vuint32_t:6; /* Slave General Purpose Control Register Reserved */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */
+ vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */
+ vuint32_t:6; /* */
+ vuint32_t ARB:2; /* Arbitration Mode */
+ vuint32_t:2; /* */
+ vuint32_t PCTL:2; /* Parking Control */
+ vuint32_t:1; /* */
+ vuint32_t PARK:3; /* PARK */
+ } B;
+ } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */
+
+ int32_t XBAR_reserverd_561[59];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29; /* */
+ vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
+ } B;
+ } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */
+
+ int32_t XBAR_reserverd_564[63];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29; /* */
+ vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
+ } B;
+ } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */
+
+ int32_t XBAR_reserverd_567[63];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29; /* */
+ vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
+ } B;
+ } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */
+
+ int32_t XBAR_reserverd_570[63];
+
+ /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */
+
+ int32_t XBAR_reserverd_573[64];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29; /* */
+ vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
+ } B;
+ } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */
+
+ int32_t XBAR_reserverd_576[64];
+
+ /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */
+
+ int32_t XBAR_reserverd_579[64];
+
+ /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */
+
+ int32_t XBAR_reserverd_582[64];
+
+ /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */
+
+ }; /* end of XBAR_tag */
+/****************************************************************************/
+/* MODULE : ECSM */
+/****************************************************************************/
+ struct ECSM_tag {
+ /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */
+ uint32_t ecsm_reserved1[16];
+
+ uint8_t ecsm_reserved3[3]; /* base + 0x40 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t ERNCR:1; /* <URM>EPRNCR</URM> */
+ vuint8_t EFNCR:1; /* <URM>EPFNCR</URM> */
+ } B;
+ } ECR; /* ECC Configuration Register */
+
+ uint8_t ecsm_reserved4[3]; /* base + 0x44 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t RNCE:1; /* <URM>PRNCE</URM> */
+ vuint8_t FNCE:1; /* <URM>PFNCE</URM> */
+ } B;
+ } ESR; /* ECC Status Register */
+
+ /* EEGR don't exist in MPC563xM */
+ uint32_t ecsm_reserved4a[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEAR:32; /* <URM>PFEAR</URM> */
+ } B;
+ } FEAR; /* Flash ECC Address Register <URM>PFEAR</URM> - 0x50 */
+
+ uint16_t ecsm_reserved4b;
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t FEMR:4; /* <URM>PFEMR</URM> */
+ } B;
+ } FEMR; /* Flash ECC Master Register <URM>PFEMR</URM> */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROT0:1; /* <URM>PROTECTION</URM> */
+ vuint8_t PROT1:1; /* <URM>PROTECTION</URM> */
+ vuint8_t PROT2:1; /* <URM>PROTECTION</URM> */
+ vuint8_t PROT3:1; /* <URM>PROTECTION</URM> */
+ } B;
+ } FEAT; /* Flash ECC Attributes Register <URM>PFEAT</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEDH:32; /* <URM>PFEDR</URM> */
+ } B;
+ } FEDRH; /* Flash ECC Data High Register <URM>PFEDRH</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEDL:32; /* <URM>PFEDR</URM> */
+ } B;
+ } FEDRL; /* Flash ECC Data Low Register <URM>PFEDRL</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REAR:32; /* <URM>PREAR</URM> */
+ } B;
+ } REAR; /* RAM ECC Address <URM>PREAR</URM> */
+
+ uint8_t ecsm_reserved5;
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t PRESR:8;
+ } B;
+ } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t REMR:4; /* <URM>PREMR</URM> */
+ } B;
+ } REMR; /* RAM ECC Master <URM>PREMR</URM> */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROT0:1; /* <URM>PROTECTION</URM> */
+ vuint8_t PROT1:1; /* <URM>PROTECTION</URM> */
+ vuint8_t PROT2:1; /* <URM>PROTECTION</URM> */
+ vuint8_t PROT3:1; /* <URM>PROTECTION</URM> */
+ } B;
+ } REAT; /* RAM ECC Attributes Register <URM>PREAT</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REDH:32; /* <URM>PREDR</URM> */
+ } B;
+ } REDRH; /* RAM ECC Data High Register <URM>PREDRH</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REDL:32; /* <URM>PREDR</URM> */
+ } B;
+ } REDRL; /* RAMECC Data Low Register <URM>PREDRL</URM> */
+
+ };
+/****************************************************************************/
+/* MODULE : EDMA */
+/****************************************************************************/
+ struct EDMA_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14; /* Reserved */
+ vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */
+ vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */
+ vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */
+ vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */
+ vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */
+ vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */
+ vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */
+ vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */
+ vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */
+ vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */
+ vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */
+ vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */
+ vuint32_t EDBG:1; /* Enable Debug */
+ vuint32_t EBW:1; /* Enable Buffered Writes */
+ } B;
+ } CR; /* DMA Control Register <URM>DMACR</URM> @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1; /* Logical OR of all DMAERRH */
+
+ vuint32_t:14; /* Reserved */
+ vuint32_t ECX:1; /* (new in MPC563xM) */
+ vuint32_t GPE:1; /* Group Priority Error */
+ vuint32_t CPE:1; /* Channel Priority Error */
+ vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */
+ vuint32_t SAE:1; /* Source Address Error 0 */
+ vuint32_t SOE:1; /* Source Offset Error */
+ vuint32_t DAE:1; /* Destination Address Error */
+ vuint32_t DOE:1; /* Destination Offset Error */
+ vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */
+ vuint32_t SGE:1; /* Scatter/Gather Configuration Error */
+ vuint32_t SBE:1; /* Source Bus Error */
+ vuint32_t DBE:1; /* Destination Bus Error */
+
+ } B;
+ } ESR; /* <URM>DMAES</URM> Error Status Register */
+
+ uint32_t edma_reserved_erqrh;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ31:1;
+ vuint32_t ERQ30:1;
+ vuint32_t ERQ29:1;
+ vuint32_t ERQ28:1;
+ vuint32_t ERQ27:1;
+ vuint32_t ERQ26:1;
+ vuint32_t ERQ25:1;
+ vuint32_t ERQ24:1;
+ vuint32_t ERQ23:1;
+ vuint32_t ERQ22:1;
+ vuint32_t ERQ21:1;
+ vuint32_t ERQ20:1;
+ vuint32_t ERQ19:1;
+ vuint32_t ERQ18:1;
+ vuint32_t ERQ17:1;
+ vuint32_t ERQ16:1;
+ vuint32_t ERQ15:1;
+ vuint32_t ERQ14:1;
+ vuint32_t ERQ13:1;
+ vuint32_t ERQ12:1;
+ vuint32_t ERQ11:1;
+ vuint32_t ERQ10:1;
+ vuint32_t ERQ09:1;
+ vuint32_t ERQ08:1;
+ vuint32_t ERQ07:1;
+ vuint32_t ERQ06:1;
+ vuint32_t ERQ05:1;
+ vuint32_t ERQ04:1;
+ vuint32_t ERQ03:1;
+ vuint32_t ERQ02:1;
+ vuint32_t ERQ01:1;
+ vuint32_t ERQ00:1;
+ } B;
+ } ERQRL; /* <URM>DMAERQL</URM> ,DMA Enable Request Register Low */
+
+ uint32_t edma_reserved_eeirh;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EEI31:1;
+ vuint32_t EEI30:1;
+ vuint32_t EEI29:1;
+ vuint32_t EEI28:1;
+ vuint32_t EEI27:1;
+ vuint32_t EEI26:1;
+ vuint32_t EEI25:1;
+ vuint32_t EEI24:1;
+ vuint32_t EEI23:1;
+ vuint32_t EEI22:1;
+ vuint32_t EEI21:1;
+ vuint32_t EEI20:1;
+ vuint32_t EEI19:1;
+ vuint32_t EEI18:1;
+ vuint32_t EEI17:1;
+ vuint32_t EEI16:1;
+ vuint32_t EEI15:1;
+ vuint32_t EEI14:1;
+ vuint32_t EEI13:1;
+ vuint32_t EEI12:1;
+ vuint32_t EEI11:1;
+ vuint32_t EEI10:1;
+ vuint32_t EEI09:1;
+ vuint32_t EEI08:1;
+ vuint32_t EEI07:1;
+ vuint32_t EEI06:1;
+ vuint32_t EEI05:1;
+ vuint32_t EEI04:1;
+ vuint32_t EEI03:1;
+ vuint32_t EEI02:1;
+ vuint32_t EEI01:1;
+ vuint32_t EEI00:1;
+ } B;
+ } EEIRL; /* <URM>DMAEEIL</URM> , DMA Enable Error Interrupt Register Low */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 SERQ:7</URM> */
+ } SERQR; /* <URM>DMASERQ</URM> , DMA Set Enable Request Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 CERQ:7</URM> */
+ } CERQR; /* <URM>DMACERQ</URM> , DMA Clear Enable Request Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 SEEI:7</URM> */
+ } SEEIR; /* <URM>DMASEEI</URM> , DMA Set Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 CEEI:7</URM> */
+ } CEEIR; /* <URM>DMACEEI</URM> , DMA Clear Enable Error Interrupt Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 CINT:7</URM> */
+ } CIRQR; /* <URM>DMACINT</URM> , DMA Clear Interrupt Request Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 CERR:7</URM> */
+ } CER; /* <URM>DMACERR</URM> , DMA Clear error Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 SSRT:7</URM> */
+ } SSBR; /* <URM>DMASSRT</URM> , Set Start Bit Register */
+
+ union {
+ vuint8_t R;
+ vuint8_t B; /* <URM>NOP:1 CDNE:7</URM> */
+ } CDSBR; /* <URM>DMACDNE</URM> , Clear Done Status Bit Register */
+
+ uint32_t edma_reserved_irqrh;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT31:1;
+ vuint32_t INT30:1;
+ vuint32_t INT29:1;
+ vuint32_t INT28:1;
+ vuint32_t INT27:1;
+ vuint32_t INT26:1;
+ vuint32_t INT25:1;
+ vuint32_t INT24:1;
+ vuint32_t INT23:1;
+ vuint32_t INT22:1;
+ vuint32_t INT21:1;
+ vuint32_t INT20:1;
+ vuint32_t INT19:1;
+ vuint32_t INT18:1;
+ vuint32_t INT17:1;
+ vuint32_t INT16:1;
+ vuint32_t INT15:1;
+ vuint32_t INT14:1;
+ vuint32_t INT13:1;
+ vuint32_t INT12:1;
+ vuint32_t INT11:1;
+ vuint32_t INT10:1;
+ vuint32_t INT09:1;
+ vuint32_t INT08:1;
+ vuint32_t INT07:1;
+ vuint32_t INT06:1;
+ vuint32_t INT05:1;
+ vuint32_t INT04:1;
+ vuint32_t INT03:1;
+ vuint32_t INT02:1;
+ vuint32_t INT01:1;
+ vuint32_t INT00:1;
+ } B;
+ } IRQRL; /* <URM>DMAINTL</URM> , DMA Interrupt Request Low */
+
+ uint32_t edma_reserved_erh;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR31:1;
+ vuint32_t ERR30:1;
+ vuint32_t ERR29:1;
+ vuint32_t ERR28:1;
+ vuint32_t ERR27:1;
+ vuint32_t ERR26:1;
+ vuint32_t ERR25:1;
+ vuint32_t ERR24:1;
+ vuint32_t ERR23:1;
+ vuint32_t ERR22:1;
+ vuint32_t ERR21:1;
+ vuint32_t ERR20:1;
+ vuint32_t ERR19:1;
+ vuint32_t ERR18:1;
+ vuint32_t ERR17:1;
+ vuint32_t ERR16:1;
+ vuint32_t ERR15:1;
+ vuint32_t ERR14:1;
+ vuint32_t ERR13:1;
+ vuint32_t ERR12:1;
+ vuint32_t ERR11:1;
+ vuint32_t ERR10:1;
+ vuint32_t ERR09:1;
+ vuint32_t ERR08:1;
+ vuint32_t ERR07:1;
+ vuint32_t ERR06:1;
+ vuint32_t ERR05:1;
+ vuint32_t ERR04:1;
+ vuint32_t ERR03:1;
+ vuint32_t ERR02:1;
+ vuint32_t ERR01:1;
+ vuint32_t ERR00:1;
+ } B;
+ } ERL; /* <URM>DMAERRL</URM> , DMA Error Low */
+
+ int32_t edma_reserverd_hrsh[1];
+
+ int32_t edma_reserverd_hrsl[1];
+
+ int32_t edma_reserverd_gpor[1];
+
+ int32_t EDMA_reserverd_223[49];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[64]; /* <URM>DCHPRI [32]</URM> , Channel n Priority */
+
+ uint32_t edma_reserved2[944];
+
+/****************************************************************************/
+/* DMA2 Transfer Control Descriptor */
+/****************************************************************************/
+
+ struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+ vuint32_t NBYTES; /* inner (“minor”) byte count */
+ vint32_t SLAST; /* last destination address adjustment, or
+
+ scatter/gather address (if e_sg = 1) */
+ vuint32_t DADDR; /* destination address */
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITER:15;
+ vint16_t DOFF; /* signed destination address offset */
+ vint32_t DLAST_SGA;
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */
+ vuint16_t BITER:15;
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+ } TCD[64]; /* <URM>TCD [32]</URM> , transfer_control_descriptor */
+ };
+
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
+
+ struct tcd_alt1_t {
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+ vuint32_t NBYTES; /* inner (“minor”) byte count */
+ vint32_t SLAST; /* last destination address adjustment, or
+
+ scatter/gather address (if e_sg = 1) */
+ vuint32_t DADDR; /* destination address */
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITERLINKCH:6;
+ vuint16_t CITER:9;
+ vint16_t DOFF; /* signed destination address offset */
+ vint32_t DLAST_SGA;
+ vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */
+ vuint16_t BITERLINKCH:6;
+ vuint16_t BITER:9;
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+ } TCD[64]; /* <URM>TCD [32]</URM> , transfer_control_descriptor */
+ };
+
+/****************************************************************************/
+/* MODULE : INTC */
+/****************************************************************************/
+ struct INTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18; /* Reserved */
+ vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */
+ vuint32_t:4; /* Reserved */
+ vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */
+ vuint32_t:2; /* Reserved */
+ vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 <URM>VTES_PRC0</URM> */
+ vuint32_t:4; /* Reserved */
+ vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 <URM>HVEN_PRC0</URM> */
+ } B;
+ } MCR; /* INTC Module Configuration Register (MCR) <URM>INTC_BCR</URM> @baseaddress + 0x00 */
+ int32_t INTC_reserverd_10[1];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* Reserved */
+ vuint32_t PRI:4; /* Priority */
+ } B;
+ } CPR; /* INTC Current Priority Register for Processor 0 (CPR) <URM>INTC_CPR_PRC0</URM> @baseaddress + 0x08 */
+
+ int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) <URM>INTC_CPR_PRC1</URM> @baseaddress + 0x0c */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA:21; /* Vector Table Base Address <URM>VTBA_PRC0</URM> */
+ vuint32_t INTVEC:9; /* Interrupt Vector <URM>INTVEC_PRC0</URM> */
+ vuint32_t:2; /* Reserved */
+ } B;
+ } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) <URM>INTC_IACKR_PRC0</URM> @baseaddress + 0x10 */
+
+ int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) <URM>INTC_IACKR_PRC1</URM> @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) <URM>INTC_EOIR_PRC0</URM> @baseaddress + 0x18 */
+
+ int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) <URM>INTC_EOIR_PRC1</URM> @baseaddress + 0x1C */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6; /* Reserved */
+ vuint8_t SET:1; /* Set Flag bits */
+ vuint8_t CLR:1; /* Clear Flag bits */
+ } B;
+ } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) <URM>INTC_SSCIRn</URM> @baseaddress + 0x20 */
+
+ int32_t INTC_reserverd_32[6];
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */
+ vuint8_t:2; /* Reserved */
+ vuint8_t PRI:4; /* Priority Select */
+ } B;
+ } PSR[512]; /* INTC Priority Select Registers (PSR) <URM>INTC_PSR</URM> @baseaddress + 0x40 */
+
+ }; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : EQADC */
+/****************************************************************************/
+ struct EQADC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t ICEA0:1;
+ vuint32_t ICEA1:1;
+ vuint32_t:1;
+ vuint32_t ESSIE:2;
+ vuint32_t:1;
+ vuint32_t DBG:2;
+ } B;
+ } MCR; /* Module Configuration Register <URM>EQADC_MCR</URM> */
+
+ int32_t EQADC_reserved00;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t NMF:26;
+ } B;
+ } NMSFR; /* Null Message Send Format Register <URM>EQADC_NMSFR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DFL:4;
+ } B;
+ } ETDFR; /* External Trigger Digital Filter Register <URM>EQADC_ETDFR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFPUSH:32; /* <URM>CF_PUSH</URM> */
+ } B;
+ } CFPR[6]; /* CFIFO Push Registers <URM>EQADC_CFPR</URM> */
+
+ uint32_t eqadc_reserved1;
+
+ uint32_t eqadc_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RFPOP:16; /* <URM>RF_POP</URM> */
+ } B;
+ } RFPR[6]; /* Result FIFO Pop Registers <URM>EQADC_RFPR</URM> */
+
+ uint32_t eqadc_reserved3;
+
+ uint32_t eqadc_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t CFEE0:1;
+ vuint16_t STRME0:1;
+ vuint16_t SSE:1;
+ vuint16_t CFINV:1;
+ vuint16_t:1;
+ vuint16_t MODE:4;
+ vuint16_t AMODE0:4; /* CFIFO0 only */
+ } B;
+ } CFCR[6]; /* CFIFO Control Registers <URM>EQADC_CFCR</URM> */
+
+ uint32_t eqadc_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t NCIE:1;
+ vuint16_t TORIE:1;
+ vuint16_t PIE:1;
+ vuint16_t EOQIE:1;
+ vuint16_t CFUIE:1;
+ vuint16_t:1;
+ vuint16_t CFFE:1;
+ vuint16_t CFFS:1;
+ vuint16_t:4;
+ vuint16_t RFOIE:1;
+ vuint16_t:1;
+ vuint16_t RFDE:1;
+ vuint16_t RFDS:1;
+ } B;
+ } IDCR[6]; /* Interrupt and DMA Control Registers <URM>EQADC_IDCR</URM> */
+
+ uint32_t eqadc_reserved6;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NCF:1;
+ vuint32_t TORF:1;
+ vuint32_t PF:1;
+ vuint32_t EOQF:1;
+ vuint32_t CFUF:1;
+ vuint32_t SSS:1;
+ vuint32_t CFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t CFCTR:4;
+ vuint32_t TNXTPTR:4;
+ vuint32_t RFCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } FISR[6]; /* FIFO and Interrupt Status Registers <URM>EQADC_FISR</URM> */
+
+ uint32_t eqadc_reserved7;
+
+ uint32_t eqadc_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t TCCF:11; /* <URM>TC_CF</URM> */
+ } B;
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers <URM>EQADC_CFTCR</URM> */
+
+ uint32_t eqadc_reserved9;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2; /* <URM>CFS0_TCB0</URM> */
+ vuint32_t CFS1:2; /* <URM>CFS1_TCB0</URM> */
+ vuint32_t CFS2:2; /* <URM>CFS2_TCB0</URM> */
+ vuint32_t CFS3:2; /* <URM>CFS3_TCB0</URM> */
+ vuint32_t CFS4:2; /* <URM>CFS4_TCB0</URM> */
+ vuint32_t CFS5:2; /* <URM>CFS5_TCB0</URM> */
+ vuint32_t:5;
+ vuint32_t LCFTCB0:4;
+ vuint32_t TC_LCFTCB0:11;
+ } B;
+ } CFSSR0; /* CFIFO Status Register 0 <URM>EQADC_CFSSR0</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2; /* <URM>CFS0_TCB1</URM> */
+ vuint32_t CFS1:2; /* <URM>CFS1_TCB1</URM> */
+ vuint32_t CFS2:2; /* <URM>CFS2_TCB1</URM> */
+ vuint32_t CFS3:2; /* <URM>CFS3_TCB1</URM> */
+ vuint32_t CFS4:2; /* <URM>CFS4_TCB1</URM> */
+ vuint32_t CFS5:2; /* <URM>CFS5_TCB1</URM> */
+ vuint32_t:5;
+ vuint32_t LCFTCB1:4;
+ vuint32_t TC_LCFTCB1:11;
+ } B;
+ } CFSSR1; /* CFIFO Status Register 1 <URM>EQADC_CFSSR1</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2; /* <URM>CFS0_TSSI</URM> */
+ vuint32_t CFS1:2; /* <URM>CFS1_TSSI</URM> */
+ vuint32_t CFS2:2; /* <URM>CFS2_TSSI</URM> */
+ vuint32_t CFS3:2; /* <URM>CFS3_TSSI</URM> */
+ vuint32_t CFS4:2; /* <URM>CFS4_TSSI</URM> */
+ vuint32_t CFS5:2; /* <URM>CFS5_TSSI</URM> */
+ vuint32_t:4;
+ vuint32_t ECBNI:1;
+ vuint32_t LCFTSSI:4;
+ vuint32_t TC_LCFTSSI:11;
+ } B;
+ } CFSSR2; /* CFIFO Status Register 2 <URM>EQADC_CFSSR2</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2;
+ vuint32_t CFS1:2;
+ vuint32_t CFS2:2;
+ vuint32_t CFS3:2;
+ vuint32_t CFS4:2;
+ vuint32_t CFS5:2;
+ vuint32_t:20;
+ } B;
+ } CFSR; /* <URM>EQADC_CFSR</URM> */
+
+ uint32_t eqadc_reserved11;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:21;
+ vuint32_t MDT:3;
+ vuint32_t:4;
+ vuint32_t BR:4;
+ } B;
+ } SSICR; /* SSI Control Register <URM>EQADC_SSICR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RDV:1;
+ vuint32_t:5;
+ vuint32_t RDATA:26;
+ } B;
+ } SSIRDR; /* SSI Recieve Data Register <URM>EQADC_SSIRDR</URM> @ baseaddress + 0xB8 */
+
+ uint32_t eqadc_reserved11b[5];
+
+ uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */
+ /* REDLCCR is not implemented in the MPC563xM */
+
+ uint32_t eqadc_reserved12[11];
+
+ struct {
+ union {
+ vuint32_t R;
+
+ /*<URM>B.CFIFOx_DATAw</URM> */
+
+ } R[4]; /*<URM>EQADC_CFxRw<URM> */
+
+ union {
+ vuint32_t R;
+ /*<URM>B.CFIFOx_EDATAw</URM> */
+ } EDATA[4]; /*<URM>EQADC_CFxERw</URM> (new in MPC563xM) */
+
+ uint32_t eqadc_reserved13[8];
+
+ } CF[6];
+
+ uint32_t eqadc_reserved14[32];
+
+ struct {
+ union {
+ vuint32_t R;
+ /*<URM>RFIFOx_DATAw</URM> */
+ } R[4]; /*<URM>EQADC_RFxRw</URM> */
+
+ uint32_t eqadc_reserved15[12];
+
+ } RF[6];
+
+ };
+ /****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+ struct DSPI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t PCSIS7:1; /* new in MPC563xM */
+ vuint32_t PCSIS6:1; /* new in MPC563xM */
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t DOZE:1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t:7;
+ vuint32_t HALT:1;
+ } B;
+ } MCR; /* Module Configuration Register <URM>DSPI_MCR</URM> @baseaddress + 0x00 */
+
+ uint32_t dspi_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16; /* <URM>SPI_TCNT</URM> */
+ vuint32_t:16;
+ } B;
+ } TCR; /* DSPI Transfer Count Register <URM>DSPI_TCR</URM> @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers <URM>DSPI_CTARx</URM> @baseaddress + 0x0C - 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t:1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t:1;
+ vuint32_t TFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR; /* Status Register <URM>DSPI_SR</URM> @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1; /*<URM>TCF_RE</URM> */
+ vuint32_t:2;
+ vuint32_t EOQFRE:1; /*<URM>EQQF_RE</URM> */
+ vuint32_t TFUFRE:1; /*<URM>TFUF_RE</URM> */
+ vuint32_t:1;
+ vuint32_t TFFFRE:1; /*<URM>TFFF_RE</URM> */
+ vuint32_t TFFFDIRS:1; /*<URM>TFFF_DIRS</URM> */
+ vuint32_t:4;
+ vuint32_t RFOFRE:1; /*<URM>RFOF_RE</URM> */
+ vuint32_t:1;
+ vuint32_t RFDFRE:1; /*<URM>RFDF_RE</URM> */
+ vuint32_t RFDFDIRS:1; /*<URM>RFDF_DIRS</URM> */
+ vuint32_t:16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register <URM>DSPI_RSER</URM> @baseaddress + 0x30 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t:2;
+ vuint32_t PCS7:1; /* new in MPC563xM */
+ vuint32_t PCS6:1; /* new in MPC563xM */
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register <URM>DSPI_PUSHR</URM> @baseaddress + 0x34 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR; /* POP RX FIFO Register <URM>DSPI_POPR</URM> @baseaddress + 0x38 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4]; /* Transmit FIFO Registers <URM>DSPI_TXFRx</URM> @baseaddress + 0x3c - 0x78 */
+
+ vuint32_t DSPI_reserved_txf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[4]; /* Transmit FIFO Registers <URM>DSPI_RXFRx</URM> @baseaddress + 0x7c - 0xB8 */
+
+ vuint32_t DSPI_reserved_rxf[12];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t:1;
+ vuint32_t MTOCNT:6;
+ vuint32_t:3;
+ vuint32_t TSBC:1;
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t:4;
+ vuint32_t DPCS7:1;
+ vuint32_t DPCS6:1;
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR; /* DSI Configuration Register <URM>DSPI_DSICR</URM> @baseaddress + 0xBC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */
+ } B;
+ } SDR; /* DSI Serialization Data Register <URM>DSPI_SDR</URM> @baseaddress + 0xC0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register <URM>DSPI_ASDR</URM> @baseaddress + 0xC4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register <URM>DSPI_COMPR</URM> @baseaddress + 0xC8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */
+ } B;
+ } DDR; /* DSI deserialization Data Register <URM>DSPI_DDR</URM> @baseaddress + 0xCC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t TSBCNT:5;
+ vuint32_t:16;
+ vuint32_t DPCS1_7:1;
+ vuint32_t DPCS1_6:1;
+ vuint32_t DPCS1_5:1;
+ vuint32_t DPCS1_4:1;
+ vuint32_t DPCS1_3:1;
+ vuint32_t DPCS1_2:1;
+ vuint32_t DPCS1_1:1;
+ vuint32_t DPCS1_0:1;
+ } B;
+ } DSICR1; /* DSI Configuration Register 1 <URM>DSPI_DSICR1</URM> @baseaddress + 0xD0 */
+
+ };
+/****************************************************************************/
+/* MODULE : eSCI */
+/****************************************************************************/
+ struct ESCI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t SBR:13;
+ vuint32_t LOOPS:1;
+ vuint32_t:1; /* Reserved in MPC563xM */
+ vuint32_t RSRC:1;
+ vuint32_t M:1;
+ vuint32_t WAKE:1;
+ vuint32_t ILT:1;
+ vuint32_t PE:1;
+ vuint32_t PT:1;
+ vuint32_t TIE:1;
+ vuint32_t TCIE:1;
+ vuint32_t RIE:1;
+ vuint32_t ILIE:1;
+ vuint32_t TE:1;
+ vuint32_t RE:1;
+ vuint32_t RWU:1;
+ vuint32_t SBK:1;
+ } B;
+ } CR1; /* Control Register 1 <URM>SCIBDH, SCIBDL, SCICR1, SCICR2</URM> @baseaddress + 0x00 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t MDIS:1;
+ vuint16_t FBR:1;
+ vuint16_t BSTP:1;
+ vuint16_t IEBERR:1; /* <URM>BERIE</URM> */
+ vuint16_t RXDMA:1;
+ vuint16_t TXDMA:1;
+ vuint16_t BRK13:1; /* <URM>BRCL</URM> */
+ vuint16_t TXDIR:1;
+ vuint16_t BESM13:1; /* <URM>BESM</URM> */
+ vuint16_t SBSTP:1; /* <URM>BESTP</URM> */
+ vuint16_t RXPOL:1;
+ vuint16_t PMSK:1;
+ vuint16_t ORIE:1;
+ vuint16_t NFIE:1;
+ vuint16_t FEIE:1;
+ vuint16_t PFIE:1;
+ } B;
+ } CR2; /* Control Register 2 <URM>SCICR3, SCICR4</URM> @baseaddress + 0x04 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t R8:1; /* <URM>RN</URM> */
+ vuint16_t T8:1; /* <URM>TN</URM> */
+ vuint16_t ERR:1;
+ vuint16_t:1;
+ vuint16_t R:4;
+ vuint8_t D;
+ } B;
+ } DR; /* Data Register <URM>SCIDRH, SCIDRL</URM> @baseaddress + 0x06 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TDRE:1;
+ vuint32_t TC:1;
+ vuint32_t RDRF:1;
+ vuint32_t IDLE:1;
+ vuint32_t OR:1;
+ vuint32_t NF:1;
+ vuint32_t FE:1;
+ vuint32_t PF:1;
+ vuint32_t:3;
+ vuint32_t BERR:1;
+ vuint32_t:2;
+ vuint32_t TACT:1;
+ vuint32_t RAF:1; /* <URM>RACT</URM> */
+ vuint32_t RXRDY:1;
+ vuint32_t TXRDY:1;
+ vuint32_t LWAKE:1;
+ vuint32_t STO:1;
+ vuint32_t PBERR:1;
+ vuint32_t CERR:1;
+ vuint32_t CKERR:1;
+ vuint32_t FRC:1;
+ vuint32_t:6;
+ vuint32_t UREQ:1;
+ vuint32_t OVFL:1;
+ } B;
+ } SR; /* Status Register <URM>SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 </URM> @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LRES:1;
+ vuint32_t WU:1;
+ vuint32_t WUD0:1;
+ vuint32_t WUD1:1;
+ vuint32_t:2; /* reserved: LDBG and DSF not longer supported */
+ vuint32_t PRTY:1;
+ vuint32_t LIN:1;
+ vuint32_t RXIE:1;
+ vuint32_t TXIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t STIE:1;
+ vuint32_t PBIE:1;
+ vuint32_t CIE:1;
+ vuint32_t CKIE:1;
+ vuint32_t FCIE:1;
+ vuint32_t:6;
+ vuint32_t UQIE:1;
+ vuint32_t OFIE:1;
+ vuint32_t:8;
+ } B;
+ } LCR; /* LIN Control Register <URM>LINCTRL1, LINCTRL2, LINCTRL3 </URM> @baseaddress + 0x0C */
+
+ union {
+ vuint32_t R;
+ } LTR; /* LIN Transmit Register <URM>LINTX</URM> @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ } LRR; /* LIN Recieve Register <URM>LINRX</URM> @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t P:16;
+ vuint32_t:3;
+ vuint32_t SYNM:1;
+ vuint32_t EROE:1;
+ vuint32_t ERFE:1;
+ vuint32_t ERPE:1;
+ vuint32_t M2:1;
+ vuint32_t:8;
+ } B;
+ } LPR; /* LIN CRC Polynom Register <URM>LINCRCP1, LINCRCP2, SCICR5</URM> @baseaddress + 0x18 */
+
+ };
+/****************************************************************************/
+/* MODULE : eSCI */
+/****************************************************************************/
+ struct ESCI_12_13_bit_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t R8:1;
+ vuint16_t T8:1;
+ vuint16_t ERR:1;
+ vuint16_t:1;
+ vuint16_t D:12;
+ } B;
+ } DR; /* Data Register */
+ };
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+ struct FLEXCAN_BUF_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
+ } DATA;
+
+ }; /* end of FLEXCAN_BUF_t */
+
+ struct FLEXCAN_RXFIFO_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+ }; /* end of FLEXCAN_RXFIFO_t */
+
+ struct FLEXCAN2_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1; /* new in MPC563xM */
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1; /* <URM>NOT_RDY</URM> */
+ vuint32_t WAK_MSK:1; /* new in MPC563xM */
+ vuint32_t SOFTRST:1; /* <URM>SOFT_RST</URM> */
+ vuint32_t FRZACK:1; /* <URM>FRZ_ACK</URM> */
+ vuint32_t SUPV:1; /* new in MPC563xM */
+ vuint32_t SLF_WAK:1; /* new in MPC563xM */
+
+ vuint32_t WRNEN:1; /* <URM>WRN_EN</URM> */
+
+ vuint32_t MDISACK:1; /* <URM>LPM_ACK</URM> */
+ vuint32_t WAK_SRC:1; /* new in MPC563xM */
+ vuint32_t DOZE:1; /* new in MPC563xM */
+
+ vuint32_t SRXDIS:1; /* <URM>SRX_DIS</URM> */
+ vuint32_t MBFEN:1; /* <URM>BCC</URM> */
+ vuint32_t:2;
+
+ vuint32_t LPRIO_EN:1; /* new in MPC563xM */
+ vuint32_t AEN:1; /* new in MPC563xM */
+ vuint32_t:2;
+ vuint32_t IDAM:2; /* new in MPC563xM */
+ vuint32_t:2;
+
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1; /* <URM>BOFF_MSK</URM> */
+ vuint32_t ERRMSK:1; /* <URM>ERR_MSK</URM> */
+ vuint32_t CLKSRC:1; /* <URM>CLK_SRC</URM> */
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1; /* <URM>TWRN_MSK</URM> */
+ vuint32_t RWRNMSK:1; /* <URM>RWRN_MSK</URM> */
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1; /* <URM>BOFF_REC</URM> */
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B; /* Control Register */
+ } CR; /* <URM>CTRL</URM> */
+
+ union {
+ vuint32_t R;
+ } TIMER; /* Free Running Timer */
+
+ int32_t FLEXCAN_reserved00;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t MI:29;
+ } B;
+ } RXGMASK; /* RX Global Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t MI:29;
+ } B;
+ } RX14MASK; /* RX 14 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t MI:29;
+ } B;
+ } RX15MASK; /* RX 15 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1; /* <URM>TWRN_INT</URM> */
+ vuint32_t RWRNINT:1; /* <URM>RWRN_INT</URM> */
+ vuint32_t BIT1ERR:1; /* <URM>BIT1_ERR</URM> */
+ vuint32_t BIT0ERR:1; /* <URM>BIT0_ERR</URM> */
+ vuint32_t ACKERR:1; /* <URM>ACK_ERR</URM> */
+ vuint32_t CRCERR:1; /* <URM>CRC_ERR</URM> */
+ vuint32_t FRMERR:1; /* <URM>FRM_ERR</URM> */
+ vuint32_t STFERR:1; /* <URM>STF_ERR</URM> */
+ vuint32_t TXWRN:1; /* <URM>TX_WRN</URM> */
+ vuint32_t RXWRN:1; /* <URM>RX_WRN</URM> */
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2; /* <URM>FLT_CONF</URM> */
+ vuint32_t:1;
+ vuint32_t BOFFINT:1; /* <URM>BOFF_INT</URM> */
+ vuint32_t ERRINT:1; /* <URM>ERR_INT</URM> */
+ vuint32_t WAK_INT:1; /* new in MPC563xM */
+ } B;
+ } ESR; /* Error and Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B; /* Interruput Masks Register */
+ } IMRH; /* <URM>IMASK2</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B; /* Interruput Masks Register */
+ } IMRL; /* <URM>IMASK1</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B; /* Interruput Flag Register */
+ } IFRH; /* <URM>IFLAG2</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B; /* Interruput Flag Register */
+ } IFRL; /* <URM>IFLAG1</URM> */
+
+ uint32_t flexcan2_reserved2[19];
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure *//* New options in MPC563xM */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B; /* RX Individual Mask Registers */
+ } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */
+
+ }; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : Decimation Filter (DECFIL) */
+/****************************************************************************/
+ struct DECFIL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FREN:1;
+ vuint32_t:1;
+ vuint32_t FRZ:1;
+ vuint32_t SRES:1;
+ vuint32_t:2; /* CASCD not supported in MPC563xM */
+ vuint32_t IDEN:1;
+ vuint32_t ODEN:1;
+ vuint32_t ERREN:1;
+ vuint32_t:1;
+ vuint32_t FTYPE:2;
+ vuint32_t:1;
+ vuint32_t SCAL:2;
+ vuint32_t:1;
+ vuint32_t SAT:1;
+ vuint32_t ISEL:1;
+ vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */
+ vuint32_t DEC_RATE:4;
+ vuint32_t:1; /* SDIE not supported in MPC563xM */
+ vuint32_t DSEL:1;
+ vuint32_t IBIE:1;
+ vuint32_t OBIE:1;
+ vuint32_t EDME:1;
+ vuint32_t TORE:1;
+ vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */
+ } B;
+ } MCR; /* Configuration Register <URM>DECFILTER_MCR</URM> @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BSY:1;
+ vuint32_t:1;
+ vuint32_t DEC_COUNTER:4;
+ vuint32_t IDFC:1;
+ vuint32_t ODFC:1;
+ vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */
+ vuint32_t IBIC:1;
+ vuint32_t OBIC:1;
+ vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */
+ vuint32_t DIVRC:1;
+ vuint32_t OVFC:1;
+ vuint32_t OVRC:1;
+ vuint32_t IVRC:1;
+ vuint32_t:6;
+ vuint32_t IDF:1;
+ vuint32_t ODF:1;
+ vuint32_t SDF:1; /* SDF not supported in MPC563xM */
+ vuint32_t IBIF:1;
+ vuint32_t OBIF:1;
+ vuint32_t SVR:1; /* SVR not supported in MPC563xM */
+ vuint32_t DIVR:1;
+ vuint32_t OVF:1;
+ vuint32_t OVR:1;
+ vuint32_t IVR:1;
+ } B;
+ } MSR; /* Status Register <URM>DECFILTER_MSR</URM> @baseaddress + 0x04 */
+
+ /* Module Extended Config.Register - not siupported on the MPC563xM <URM>DECFILTER_MXCR</URM> @baseaddress + 0x08 */
+
+ uint32_t decfil_reserved1[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t INTAG:4;
+ vuint32_t:6;
+ vuint32_t PREFILL:1;
+ vuint32_t FLUSH:1;
+ vuint32_t INPBUF:16;
+ } B;
+ } IB; /* Interface Input Buffer <URM>DECFILTER_IB</URM> @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t OUTTAG:4;
+ vuint32_t OUTBUF:16;
+ } B;
+ } OB; /* Interface Output Buffer <URM>DECFILTER_OB</URM> @baseaddress + 0x14 */
+
+ uint32_t decfil_reserved2[2];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t COEF:24;
+ } B;
+ } COEF[9]; /* Filter Coefficient Registers <URM>DECFILTER_COEFx</URM> @baseaddress + 0x20 - 0x40 */
+
+ uint32_t decfil_reserved3[13];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t TAP:24;
+ } B;
+ } TAP[8]; /* Filter TAP Registers <URM>DECFILTER_TAPx</URM> @baseaddress + 0x78 - 0x94 */
+
+ uint32_t decfil_reserved4[14];
+
+ /* 0x0D0 */
+ union {
+ vuint16_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SAMP_DATA:16;
+ } B;
+ } EDID; /* Filter EDID Registers <URM>DECFILTER_EDID</URM> @baseaddress + 0xD0 */
+
+ uint32_t decfil_reserved5[3];
+
+ /* 0x0E0 */
+ uint32_t decfil_reserved6;
+ /* Filter FINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_FINTVAL</URM> @baseaddress + 0xE0 */
+
+ /* 0x0E4 */
+ uint32_t decfil_reserved7;
+ /* Filter FINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_FINTCNT</URM> @baseaddress + 0xE4 */
+
+ /* 0x0E8 */
+ uint32_t decfil_reserved8;
+ /* Filter CINTVAL Registers - Not supported on MPC563xM <URM>DECFILTER_CINTVAL</URM> @baseaddress + 0xE8 */
+
+ /* 0x0EC */
+ uint32_t decfil_reserved9;
+ /* Filter CINTCNT Registers - Not supported on MPC563xM <URM>DECFILTER_CINTCNT</URM> @baseaddress + 0xEC */
+
+ };
+/****************************************************************************/
+/* MODULE : Periodic Interval Timer (PIT) */
+/****************************************************************************/
+ struct PIT_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t MDIS_RTI:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR; /* PIT Module Control Register */
+
+ uint32_t pit_reserved1[59];
+
+ struct {
+ union {
+ vuint32_t R; /* <URM>TSVn</URM> */
+ } LDVAL; /* Timer Load Value Register */
+
+ union {
+ vuint32_t R; /* <URM>TVLn</URM> */
+ } CVAL; /* Current Timer Value Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL; /* Timer Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG; /* Timer Flag Register */
+ } RTI; /* RTI Channel */
+
+ struct {
+ union {
+ vuint32_t R;
+ } LDVAL; /* Timer Load Value Register */
+
+ union {
+ vuint32_t R;
+ } CVAL; /* Current Timer Value Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL; /* Timer Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG; /* Timer Flag Register */
+ } TIMER[4]; /* Timer Channels */
+
+ };
+/****************************************************************************/
+/* MODULE : System Timer Module (STM) */
+/****************************************************************************/
+ struct STM_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8;
+ vuint32_t:6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR; /* STM Control Register <URM>STM_CR</URM> (new in MPC563xM) Offset 0x0000 */
+
+ union {
+ vuint32_t R;
+ } CNT; /* STM Count Register <URM>STM_CNT</URM> (new in MPC563xM) Offset Offset 0x0004 */
+
+ uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR0; /* STM Channel Control Register <URM>STM_CCR0</URM> (new in MPC563xM) Offset 0x0010 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR0; /* STM Channel Interrupt Register <URM>STM_CIR0</URM> (new in MPC563xM) Offset 0x0014 */
+
+ union {
+ vuint32_t R;
+ } CMP0; /* STM Channel Compare Register <URM>STM_CMP0</URM> (new in MPC563xM) Offset Offset 0x0018 */
+
+ uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR1; /* STM Channel Control Register <URM>STM_CCR1</URM> (new in MPC563xM) Offset 0x0020 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR1; /* STM Channel Interrupt Register <URM>STM_CIR1</URM> (new in MPC563xM) Offset 0x0024 */
+
+ union {
+ vuint32_t R;
+ } CMP1; /* STM Channel Compare Register <URM>STM_CMP1</URM> (new in MPC563xM) Offset Offset 0x0028 */
+
+ uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR2; /* STM Channel Control Register <URM>STM_CCR2</URM> (new in MPC563xM) Offset 0x0030 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR2; /* STM Channel Interrupt Register <URM>STM_CIR2</URM> (new in MPC563xM) Offset 0x0034 */
+
+ union {
+ vuint32_t R;
+ } CMP2; /* STM Channel Compare Register <URM>STM_CMP2</URM> (new in MPC563xM) Offset Offset 0x0038 */
+
+ uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR3; /* STM Channel Control Register <URM>STM_CCR3</URM> (new in MPC563xM) Offset 0x0040 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR3; /* STM Channel Interrupt Register <URM>STM_CIR3</URM> (new in MPC563xM) Offset 0x0044 */
+
+ union {
+ vuint32_t R;
+ } CMP3; /* STM Channel Compare Register <URM>STM_CMP3</URM> (new in MPC563xM) Offset Offset 0x0048 */
+
+ uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */
+ };
+
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+
+ struct SWT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t:14;
+ vuint32_t KEY:1;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } MCR; /*<URM>SWT_CR</URM> *//* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } IR; /* Interrupt register <URM>SWT_IR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO; /* Timeout register <URM>SWT_TO</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+
+ } B;
+ } WN; /* Window register <URM>SWT_WN</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16;
+ } B;
+ } SR; /* Service register <URM>SWT_SR</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO; /* Counter output register <URM>SWT_CO</URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SK:16;
+ } B;
+ } SK; /* Service key register <URM>SWT_SK</URM> */
+ };
+/****************************************************************************/
+/* MODULE : Power Management Controller (PMC) */
+/****************************************************************************/
+ struct PMC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LVRER:1; /* <URM> LVIRR </URM> */
+ vuint32_t LVREH:1; /* <URM> LVIHR </URM> */
+ vuint32_t LVRE50:1; /* <URM> LVI5R </URM> */
+ vuint32_t LVRE33:1; /* <URM> LVI3R </URM> */
+ vuint32_t LVREC:1; /* <URM> LVI1R </URM> */
+ vuint32_t:3;
+ vuint32_t LVIER:1; /* <URM> LVIRE </URM> */
+ vuint32_t LVIEH:1; /* <URM> LVIHE </URM> */
+ vuint32_t LVIE50:1; /* <URM> LVI5E </URM> */
+ vuint32_t LVIE33:1; /* <URM> LVI3E </URM> */
+ vuint32_t LVIC:1; /* <URM> LVI1E </URM> */
+ vuint32_t:2;
+ vuint32_t TLK:1;
+ vuint32_t:16;
+ } B;
+ } MCR; /* Module Configuration register <URM> CFGR </URM> */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t LVDREGTRIM:4; /* <URM> LVI50TRIM </URM> */
+ vuint32_t VDD33TRIM:4; /* <URM> BV33TRIM </URM> */
+ vuint32_t LVD33TRIM:4; /* <URM> LVI33TRIM </URM> */
+ vuint32_t VDDCTRIM:4; /* <URM> V12TRIM </URM> */
+ vuint32_t LVDCTRIM:4; /* <URM> LVI33TRIM </URM> */
+ } B;
+ } TRIMR; /* Trimming register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t LVFVSTBY:1;
+ vuint32_t BGRDY:1; /* <URM> BGS1 </URM> */
+ vuint32_t BGTS:1; /* <URM> BGS2 </URM> */
+ vuint32_t:5;
+ vuint32_t LVFCSTBY:1;
+ vuint32_t:1;
+ vuint32_t V33DIS:1; /* 3.3V Regulator Disable <URM> V33S </URM> */
+ vuint32_t LVFCR:1; /* Clear LVFR <URM> LVIRC </URM> */
+ vuint32_t LVFCH:1; /* Clear LVFH <URM> LVIHC </URM> */
+ vuint32_t LVFC50:1; /* Clear LVF5 <URM> LVI5 </URM> */
+ vuint32_t LVFC33:1; /* Clear LVF3 <URM> LVI3 </URM> */
+ vuint32_t LVFCC:1; /* Clear LVFC <URM> LVI1 </URM> */
+ vuint32_t:3;
+ vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply <URM> LVIRF </URM> */
+ vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply <URM> LVIHF </URM> */
+ vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply <URM> LVI5F </URM> */
+ vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply <URM> LVI3F </URM> */
+ vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) <URM> LVI1F </URM> */
+ vuint32_t:3;
+
+ } B;
+ } SR; /* status register */
+ };
+/****************************************************************************/
+/* MODULE : TSENS (Temperature Sensor) */
+/****************************************************************************/
+
+ struct TSENS_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSCV2:16;
+ vuint32_t TSCV1:16;
+ } B;
+ } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TSCV3:16;
+ } B;
+ } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */
+
+ uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */
+
+ };
+
+/* Define memories */
+/* Comments need to be moved for different memory sizes */
+
+#define SRAM_START 0x40000000
+ /*#define SRAM_SIZE 0xC000 48K SRAM */
+ /*#define SRAM_SIZE 0x10000 64K SRAM */
+#define SRAM_SIZE 0x17800 /* 94K SRAM */
+ /*#define SRAM_END 0x4000BFFF 48K SRAM */
+ /*#define SRAM_END 0x4000FFFF 64K SRAM */
+#define SRAM_END 0x400177FF /* 94K SRAM */
+
+#define FLASH_START 0x0
+ /*#define FLASH_SIZE 0x100000 1M Flash */
+#define FLASH_SIZE 0x180000 /* 1.5M Flash */
+ /*#define FLASH_END 0xFFFFF 1M Flash */
+#define FLASH_END 0x17FFFF /* 1.5M Flash */
+
+/* Shadow Flash start and end address */
+#define FLASH_SHADOW_START 0x00FFC000
+#define FLASH_SHADOW_SIZE 0x4000
+#define FLASH_SHADOW_END 0x00FFFFFF
+
+/* Define instances of modules */
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)
+#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)
+#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000)
+#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000)
+#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000)
+#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)
+
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)
+#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)
+#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
+#define ETPU_DATA_RAM_END 0xC3FC8BFC
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
+#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)
+
+#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)
+#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)
+#define STM (*( volatile struct STM_tag *) 0xFFF3C000)
+#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)
+
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)
+#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000)
+
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)
+
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)
+#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006)
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)
+#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006)
+
+#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)
+#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)
+
+#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000)
+
+#ifdef __MWERKS__
+#pragma pop
+#endif /*
+ */
+
+#ifdef __cplusplus
+}
+#endif /*
+ */
+
+#endif /* ifdef _MPC563M_H */
+/*********************************************************************
+ *
+ * Copyright:
+ * Freescale Semiconductor, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Freescale
+ * Semiconductor, Inc. This software is provided on an "AS IS"
+ * basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, Freescale
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Freescale Semiconductor assumes no responsibility for the
+ * maintenance and support of this software
+ *
+ ********************************************************************/
+
diff --git a/os/hal/ports/SPC5/SPC564Axx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC564Axx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..9e16987f1 --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/cfg/mcuconf.h.ftl @@ -0,0 +1,281 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC564Axx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC564Axx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_CLK_BYPASS ${conf.instance.initialization_settings.clock_bypass.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_CLK_PREDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.prediv_value.value[0]}
+#define SPC5_CLK_MFD_VALUE ${conf.instance.initialization_settings.fmpll0_settings.mfd_value.value[0]}
+#define SPC5_CLK_RFD ${conf.instance.initialization_settings.fmpll0_settings.rfd_value.value[0]}
+#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
+ BIUCR_MASTER4_PREFETCH | \
+ BIUCR_MASTER0_PREFETCH | \
+ BIUCR_DPFEN | \
+ BIUCR_IPFEN | \
+ BIUCR_PFLIM_ON_MISS | \
+ BIUCR_BFEN)
+#define SPC5_EMIOS_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios_global_prescaler.value[0]}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
+ EDMA_CR_GRP2PRI(2) | \
+ EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_GROUP1_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_1_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_GROUP2_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_2_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_GROUP3_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_3_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * ADC driver settings.
+ */
+#define SPC5_ADC_USE_ADC0_Q0 ${conf.instance.eqadc_settings.fifo0.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC0_Q1 ${conf.instance.eqadc_settings.fifo1.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC0_Q2 ${conf.instance.eqadc_settings.fifo2.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC1_Q3 ${conf.instance.eqadc_settings.fifo3.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC1_Q4 ${conf.instance.eqadc_settings.fifo4.value[0]?upper_case}
+#define SPC5_ADC_USE_ADC1_Q5 ${conf.instance.eqadc_settings.fifo5.value[0]?upper_case}
+#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo0.value[0]}
+#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo1.value[0]}
+#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo2.value[0]}
+#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo3.value[0]}
+#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo4.value[0]}
+#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.eqadc_fifo5.value[0]}
+#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(${conf.instance.eqadc_settings.divider.value[0]})
+[#assign AN0 = conf.instance.eqadc_settings.an0.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN1 = conf.instance.eqadc_settings.an1.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN2 = conf.instance.eqadc_settings.an2.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN3 = conf.instance.eqadc_settings.an3.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN4 = conf.instance.eqadc_settings.an4.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN5 = conf.instance.eqadc_settings.an5.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN6 = conf.instance.eqadc_settings.an6.value[0]?upper_case?replace(" ", "_") /]
+[#assign AN7 = conf.instance.eqadc_settings.an7.value[0]?upper_case?replace(" ", "_") /]
+#define SPC5_ADC_PUDCR {ADC_PUDCR_${AN0},ADC_PUDCR_${AN1},ADC_PUDCR_${AN2},ADC_PUDCR_${AN3},ADC_PUDCR_${AN4},ADC_PUDCR_${AN5},ADC_PUDCR_${AN6},ADC_PUDCR_${AN7}}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_USE_ESCIA ${(conf.instance.esci_settings.esci0.value[0] == "Serial")?string?upper_case}
+#define SPC5_USE_ESCIB ${(conf.instance.esci_settings.esci1.value[0] == "Serial")?string?upper_case}
+#define SPC5_USE_ESCIC ${(conf.instance.esci_settings.esci2.value[0] == "Serial")?string?upper_case}
+#define SPC5_ESCIA_PRIORITY ${conf.instance.irq_priority_settings.esci0.value[0]}
+#define SPC5_ESCIB_PRIORITY ${conf.instance.irq_priority_settings.esci1.value[0]}
+#define SPC5_ESCIC_PRIORITY ${conf.instance.irq_priority_settings.esci2.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_b.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_c.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI3 ${conf.instance.dspi_settings.dspi_c.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign bs0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs0[0].@index[0]?trim?number] /]
+[#assign bs1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs1[0].@index[0]?trim?number] /]
+[#assign bs2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs2[0].@index[0]?trim?number] /]
+[#assign bs3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs3[0].@index[0]?trim?number] /]
+[#assign bs4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs4[0].@index[0]?trim?number] /]
+[#assign bs5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs5[0].@index[0]?trim?number] /]
+[#assign bs6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs6[0].@index[0]?trim?number] /]
+[#assign bs7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs7[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${bs0 + bs1 + bs2 + bs3 + bs4 + bs5 + bs6 + bs7})
+[#assign cs0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs0[0].@index[0]?trim?number] /]
+[#assign cs1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs1[0].@index[0]?trim?number] /]
+[#assign cs2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs2[0].@index[0]?trim?number] /]
+[#assign cs3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs3[0].@index[0]?trim?number] /]
+[#assign cs4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs4[0].@index[0]?trim?number] /]
+[#assign cs5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs5[0].@index[0]?trim?number] /]
+[#assign cs6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs6[0].@index[0]?trim?number] /]
+[#assign cs7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs7[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${cs0 + cs1 + cs2 + cs3 + cs4 + cs5 + cs6 + cs7})
+[#assign ds0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs0[0].@index[0]?trim?number] /]
+[#assign ds1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs1[0].@index[0]?trim?number] /]
+[#assign ds2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs2[0].@index[0]?trim?number] /]
+[#assign ds3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs3[0].@index[0]?trim?number] /]
+[#assign ds4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs4[0].@index[0]?trim?number] /]
+[#assign ds5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs5[0].@index[0]?trim?number] /]
+[#assign ds6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs6[0].@index[0]?trim?number] /]
+[#assign ds7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_d___pcs7[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI3_MCR (0${ds0 + ds1 + ds2 + ds3 + ds4 + ds5 + ds6 + ds7})
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_b.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_c.value[0]}
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_d.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_b.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_c.value[0]}
+#define SPC5_SPI_DSPI3_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_d.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * ICU driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS_CH0 ${(conf.instance.emios200_settings.emios_uc0.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH1 ${(conf.instance.emios200_settings.emios_uc1.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH2 ${(conf.instance.emios200_settings.emios_uc2.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH3 ${(conf.instance.emios200_settings.emios_uc3.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH4 ${(conf.instance.emios200_settings.emios_uc4.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH5 ${(conf.instance.emios200_settings.emios_uc5.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH6 ${(conf.instance.emios200_settings.emios_uc6.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH7 ${(conf.instance.emios200_settings.emios_uc7.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH8 ${(conf.instance.emios200_settings.emios_uc8.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH9 ${(conf.instance.emios200_settings.emios_uc9.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH10 ${(conf.instance.emios200_settings.emios_uc10.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH11 ${(conf.instance.emios200_settings.emios_uc11.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH12 ${(conf.instance.emios200_settings.emios_uc12.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH13 ${(conf.instance.emios200_settings.emios_uc13.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH14 ${(conf.instance.emios200_settings.emios_uc14.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH15 ${(conf.instance.emios200_settings.emios_uc15.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH16 ${(conf.instance.emios200_settings.emios_uc16.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH17 ${(conf.instance.emios200_settings.emios_uc17.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH18 ${(conf.instance.emios200_settings.emios_uc18.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH19 ${(conf.instance.emios200_settings.emios_uc19.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH20 ${(conf.instance.emios200_settings.emios_uc20.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH21 ${(conf.instance.emios200_settings.emios_uc21.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH22 ${(conf.instance.emios200_settings.emios_uc22.value[0] == "ICU")?string?upper_case}
+#define SPC5_ICU_USE_EMIOS_CH23 ${(conf.instance.emios200_settings.emios_uc23.value[0] == "ICU")?string?upper_case}
+
+/*
+ * PWM driver system settings.
+ */
+#define SPC5_PWM_USE_EMIOS_CH0 ${(conf.instance.emios200_settings.emios_uc0.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH1 ${(conf.instance.emios200_settings.emios_uc1.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH2 ${(conf.instance.emios200_settings.emios_uc2.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH3 ${(conf.instance.emios200_settings.emios_uc3.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH4 ${(conf.instance.emios200_settings.emios_uc4.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH5 ${(conf.instance.emios200_settings.emios_uc5.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH6 ${(conf.instance.emios200_settings.emios_uc6.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH7 ${(conf.instance.emios200_settings.emios_uc7.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH8 ${(conf.instance.emios200_settings.emios_uc8.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH9 ${(conf.instance.emios200_settings.emios_uc9.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH10 ${(conf.instance.emios200_settings.emios_uc10.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH11 ${(conf.instance.emios200_settings.emios_uc11.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH12 ${(conf.instance.emios200_settings.emios_uc12.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH13 ${(conf.instance.emios200_settings.emios_uc13.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH14 ${(conf.instance.emios200_settings.emios_uc14.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH15 ${(conf.instance.emios200_settings.emios_uc15.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH16 ${(conf.instance.emios200_settings.emios_uc16.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH17 ${(conf.instance.emios200_settings.emios_uc17.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH18 ${(conf.instance.emios200_settings.emios_uc18.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH19 ${(conf.instance.emios200_settings.emios_uc19.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH20 ${(conf.instance.emios200_settings.emios_uc20.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH21 ${(conf.instance.emios200_settings.emios_uc21.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH22 ${(conf.instance.emios200_settings.emios_uc22.value[0] == "PWM")?string?upper_case}
+#define SPC5_PWM_USE_EMIOS_CH23 ${(conf.instance.emios200_settings.emios_uc23.value[0] == "PWM")?string?upper_case}
+
+/*
+ * eMIOS channel priorities.
+ */
+#define SPC5_EMIOS_FLAG_F0_PRIORITY ${conf.instance.irq_priority_settings.emios_uc0.value[0]}
+#define SPC5_EMIOS_FLAG_F1_PRIORITY ${conf.instance.irq_priority_settings.emios_uc1.value[0]}
+#define SPC5_EMIOS_FLAG_F2_PRIORITY ${conf.instance.irq_priority_settings.emios_uc2.value[0]}
+#define SPC5_EMIOS_FLAG_F3_PRIORITY ${conf.instance.irq_priority_settings.emios_uc3.value[0]}
+#define SPC5_EMIOS_FLAG_F4_PRIORITY ${conf.instance.irq_priority_settings.emios_uc4.value[0]}
+#define SPC5_EMIOS_FLAG_F5_PRIORITY ${conf.instance.irq_priority_settings.emios_uc5.value[0]}
+#define SPC5_EMIOS_FLAG_F6_PRIORITY ${conf.instance.irq_priority_settings.emios_uc6.value[0]}
+#define SPC5_EMIOS_FLAG_F7_PRIORITY ${conf.instance.irq_priority_settings.emios_uc7.value[0]}
+#define SPC5_EMIOS_FLAG_F8_PRIORITY ${conf.instance.irq_priority_settings.emios_uc8.value[0]}
+#define SPC5_EMIOS_FLAG_F9_PRIORITY ${conf.instance.irq_priority_settings.emios_uc9.value[0]}
+#define SPC5_EMIOS_FLAG_F10_PRIORITY ${conf.instance.irq_priority_settings.emios_uc10.value[0]}
+#define SPC5_EMIOS_FLAG_F11_PRIORITY ${conf.instance.irq_priority_settings.emios_uc11.value[0]}
+#define SPC5_EMIOS_FLAG_F12_PRIORITY ${conf.instance.irq_priority_settings.emios_uc12.value[0]}
+#define SPC5_EMIOS_FLAG_F13_PRIORITY ${conf.instance.irq_priority_settings.emios_uc13.value[0]}
+#define SPC5_EMIOS_FLAG_F14_PRIORITY ${conf.instance.irq_priority_settings.emios_uc14.value[0]}
+#define SPC5_EMIOS_FLAG_F15_PRIORITY ${conf.instance.irq_priority_settings.emios_uc15.value[0]}
+#define SPC5_EMIOS_FLAG_F16_PRIORITY ${conf.instance.irq_priority_settings.emios_uc16.value[0]}
+#define SPC5_EMIOS_FLAG_F17_PRIORITY ${conf.instance.irq_priority_settings.emios_uc17.value[0]}
+#define SPC5_EMIOS_FLAG_F18_PRIORITY ${conf.instance.irq_priority_settings.emios_uc18.value[0]}
+#define SPC5_EMIOS_FLAG_F19_PRIORITY ${conf.instance.irq_priority_settings.emios_uc19.value[0]}
+#define SPC5_EMIOS_FLAG_F20_PRIORITY ${conf.instance.irq_priority_settings.emios_uc20.value[0]}
+#define SPC5_EMIOS_FLAG_F21_PRIORITY ${conf.instance.irq_priority_settings.emios_uc21.value[0]}
+#define SPC5_EMIOS_FLAG_F22_PRIORITY ${conf.instance.irq_priority_settings.emios_uc22.value[0]}
+#define SPC5_EMIOS_FLAG_F23_PRIORITY ${conf.instance.irq_priority_settings.emios_uc23.value[0]}
+
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+
+#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC564Axx/hal_lld.c b/os/hal/ports/SPC5/SPC564Axx/hal_lld.c new file mode 100644 index 000000000..ac5b9669f --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/hal_lld.c @@ -0,0 +1,146 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/hal_lld.c
+ * @brief SPC564Axx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+ #include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t n;
+
+ /* The SRAM is parked on the load/store port, for some unknown reason it
+ is defaulted on the instructions port and this kills performance.*/
+ XBAR.SGPCR2.B.PARK = 1; /* RAM slave on load/store port.*/
+
+ /* The DMA priority is placed above the CPU priority in order to not
+ starve I/O activities while the CPU is executing tight loops (FLASH
+ and SRAM slave ports only).*/
+#if !defined(_SPC564A70_)
+ XBAR.MPR0.R = 0x34000021; /* Flash slave port priorities:
+ eDMA (4): 0 (highest)
+ Core Instructions (0): 1
+ Core Data (1): 2
+ EBI (7): 3
+ Flexray (6): 4 */
+ XBAR.MPR2.R = 0x34000021; /* SRAM slave port priorities:
+ eDMA (4): 0 (highest)
+ Core Instructions (0): 1
+ Core Data (1): 2
+ EBI (7): 3
+ FlexRay (6): 4 */
+#else /* defined(_SPC564A70_) */
+ XBAR.MPR0.R = 0x03000021; /* Flash slave port priorities:
+ eDMA (4): 0 (highest)
+ Core Instructions (0): 1
+ Core Data (1): 2
+ Flexray (6): 3 */
+ XBAR.MPR2.R = 0x03000021; /* SRAM slave port priorities:
+ eDMA (4): 0 (highest)
+ Core Instructions (0): 1
+ Core Data (1): 2
+ FlexRay (6): 3 */
+#endif /* defined(_SPC564A70_) */
+
+ /* Decrementer timer initialized for system tick use, note, it is
+ initialized here because in the OSAL layer the system clock frequency
+ is not yet known.*/
+ n = SPC5_SYSCLK / OSAL_ST_FREQUENCY;
+ asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */
+ "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
+ "e_lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
+ "mtspr 340, %%r3" /* TCR register. */
+ : : [n] "r" (n) : "r3");
+
+ /* TB counter enabled for debug and measurements.*/
+ asm volatile ("e_li %%r3, 0x4000 \t\n" /* TBEN bit. */
+ "mtspr 1008, %%r3" /* HID0 register. */
+ : : : "r3");
+
+ /* eMIOS initialization.*/
+ EMIOS.MCR.R = (1U << 26) | SPC5_EMIOS_GPRE; /* GPREN and GPRE. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC563 clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+#if !SPC5_NO_INIT
+ /* PLL activation.*/
+ FMPLL.ESYNCR1.B.EMODE = 1; /* Enhanced mode on. */
+ FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/
+#if !SPC5_CLK_BYPASS
+ FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */
+ FMPLL.ESYNCR1.B.EPREDIV = SPC5_CLK_PREDIV;
+ FMPLL.ESYNCR1.B.EMFD = SPC5_CLK_MFD;
+ FMPLL.ESYNCR2.B.ERFD = SPC5_CLK_RFD;
+ while (!FMPLL.SYNSR.B.LOCK)
+ ;
+ FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */
+#endif /* !SPC5_CLK_BYPASS */
+
+ /* Setting up RAM/Flash wait states and the prefetching bits.*/
+ ECSM.MUDCR.R = SPC5_RAM_WS;
+ FLASH_A.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ FLASH_A.BIUCR2.R = 0;
+#if !defined(_SPC564A70_)
+ /* The second controller is only present in Andorra 3M or 4M.*/
+ FLASH_B.BIUCR.R = SPC5_FLASH_BIUCR | SPC5_FLASH_WS;
+ FLASH_B.BIUCR2.R = 0;
+#endif /* !defined(_SPC564A70_) */
+#endif /* !SPC5_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC564Axx/hal_lld.h b/os/hal/ports/SPC5/SPC564Axx/hal_lld.h new file mode 100644 index 000000000..1c093e666 --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/hal_lld.h @@ -0,0 +1,294 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/hal_lld.h
+ * @brief SPC564Axx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @brief Platform name.
+ */
+#define PLATFORM_NAME "SPC564Axx Powertrain"
+
+/**
+ * @name ESYNCR2 register definitions
+ * @{
+ */
+#define SPC5_RFD_DIV2 0 /**< Divide VCO frequency by 2. */
+#define SPC5_RFD_DIV4 1 /**< Divide VCO frequency by 4. */
+#define SPC5_RFD_DIV8 2 /**< Divide VCO frequency by 8. */
+#define SPC5_RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
+/** @} */
+
+/**
+ * @name BIUCR register definitions
+ * @{
+ */
+#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
+#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
+#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
+#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
+#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
+#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
+#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
+#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
+#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
+#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
+#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
+#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
+#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
+#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
+#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
+#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
+#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
+#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
+#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
+#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
+#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
+#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
+#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
+#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
+#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
+#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
+#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
+#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
+#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
+#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
+#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
+#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
+#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
+#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
+#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
+#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
+#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
+#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Clock bypass.
+ * @note If set to @p TRUE then the PLL is not started and initialized, the
+ * external clock is used as-is and the other clock-related settings
+ * are ignored.
+ */
+#if !defined(SPC5_CLK_BYPASS) || defined(__DOXYGEN__)
+#define SPC5_CLK_BYPASS FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief External clock pre-divider.
+ * @note Must be in range 1...15.
+ */
+#if !defined(SPC5_CLK_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_CLK_PREDIV_VALUE 2
+#endif
+
+/**
+ * @brief Multiplication factor divider.
+ * @note Must be in range 32...96.
+ */
+#if !defined(SPC5_CLK_MFD_VALUE) || defined(__DOXYGEN__)
+#define SPC5_CLK_MFD_VALUE 75
+#endif
+
+/**
+ * @brief Reduced frequency divider.
+ */
+#if !defined(SPC5_CLK_RFD) || defined(__DOXYGEN__)
+#define SPC5_CLK_RFD RFD_DIV2
+#endif
+
+/**
+ * @brief Flash buffer and prefetching settings.
+ * @note Please refer to the SPC564Axx reference manual about the meaning
+ * of the following bits, if in doubt DO NOT MODIFY IT.
+ * @note Do not specify the APC, WWSC, RWSC bits in this value because
+ * those are calculated from the system clock and ORed with this
+ * value.
+ */
+#if !defined(SPC5_FLASH_BIUCR) || defined(__DOXYGEN__)
+#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
+ BIUCR_MASTER4_PREFETCH | \
+ BIUCR_MASTER0_PREFETCH | \
+ BIUCR_DPFEN | \
+ BIUCR_IPFEN | \
+ BIUCR_PFLIM_ON_MISS | \
+ BIUCR_BFEN)
+#endif
+
+/**
+ * @brief eMIOS global prescaler value.
+ */
+#if !defined(SPC5_EMIOS_GPRE_VALUE) || defined(__DOXYGEN__)
+#define SPC5_EMIOS_GPRE_VALUE 20
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC564Axx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC564Axx_MCUCONF not defined"
+#endif
+
+#if (SPC5_CLK_PREDIV_VALUE < 1) || (SPC5_CLK_PREDIV_VALUE > 15)
+#error "invalid SPC5_CLK_PREDIV_VALUE value specified"
+#endif
+
+#if (SPC5_CLK_MFD_VALUE < 32) || (SPC5_CLK_MFD_VALUE > 96)
+#error "invalid SPC5_CLK_MFD_VALUE value specified"
+#endif
+
+#if (SPC5_CLK_RFD != SPC5_RFD_DIV2) && (SPC5_CLK_RFD != SPC5_RFD_DIV4) && \
+ (SPC5_CLK_RFD != SPC5_RFD_DIV8) && (SPC5_CLK_RFD != SPC5_RFD_DIV16)
+#error "invalid SPC5_CLK_RFD value specified"
+#endif
+
+#if (SPC5_EMIOS_GPRE_VALUE < 1) || (SPC5_EMIOS_GPRE_VALUE > 256)
+#error "invalid SPC5_EMIOS_GPRE_VALUE value specified"
+#endif
+
+/**
+ * @brief PLL input divider.
+ */
+#define SPC5_CLK_PREDIV (SPC5_CLK_PREDIV_VALUE - 1)
+
+/**
+ * @brief PLL multiplier.
+ */
+#define SPC5_CLK_MFD (SPC5_CLK_MFD_VALUE)
+
+/**
+ * @brief PLL output clock.
+ */
+#define SPC5_PLLCLK ((SPC5_XOSC_CLK / SPC5_CLK_PREDIV_VALUE) * \
+ SPC5_CLK_MFD_VALUE)
+
+#if (SPC5_PLLCLK < 256000000) || (SPC5_PLLCLK > 512000000)
+#error "VCO frequency out of the acceptable range (256...512)"
+#endif
+
+/**
+ * @brief PLL output clock.
+ */
+#if !SPC5_CLK_BYPASS || defined(__DOXYGEN__)
+#define SPC5_SYSCLK (SPC5_PLLCLK / (1 << (SPC5_CLK_RFD + 1)))
+#else
+#define SPC5_SYSCLK SPC5_XOSC_CLK
+#endif
+
+#if (SPC5_SYSCLK > 150000000) && !SPC5_ALLOW_OVERCLOCK
+#error "System clock above maximum rated frequency (150MHz)"
+#endif
+
+/**
+ * @brief Flash wait states are a function of the system clock.
+ */
+#if (SPC5_SYSCLK <= 20000000) || defined(__DOXYGEN__)
+#define SPC5_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_3)
+#elif SPC5_SYSCLK <= 61000000
+#define SPC5_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_3)
+#elif SPC5_SYSCLK <= 90000000
+#define SPC5_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_3)
+#elif SPC5_SYSCLK <= 123000000
+#define SPC5_FLASH_WS (BIUCR_APC_3 | BIUCR_RWSC_3 | BIUCR_WWSC_3)
+#else
+#define SPC5_FLASH_WS (BIUCR_APC_4 | BIUCR_RWSC_4 | BIUCR_WWSC_3)
+#endif
+
+/**
+ * @brief RAM wait states are a function of the system clock.
+ */
+#if (SPC5_SYSCLK <= 98000000) || defined(__DOXYGEN__)
+#define SPC5_RAM_WS 0
+#else
+#define SPC5_RAM_WS 0x40000000
+#endif
+
+/**
+ * @brief eMIOS global prescaler setting.
+ */
+#define SPC5_EMIOS_GPRE (SPC5_EMIOS_GPRE_VALUE << 8)
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC564Axx/platform.mk b/os/hal/ports/SPC5/SPC564Axx/platform.mk new file mode 100644 index 000000000..e0934d7db --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/platform.mk @@ -0,0 +1,23 @@ +# List of all the SPC564Axx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC564Axx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EQADC_v1/hal_adc_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1/spc5_emios.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ESCI_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIU_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC564Axx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EQADC_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eMIOS200_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/ESCI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIU_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC564Axx/registers.h b/os/hal/ports/SPC5/SPC564Axx/registers.h new file mode 100644 index 000000000..983e342bc --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc564a.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC564Axx/spc5_registry.h b/os/hal/ports/SPC5/SPC564Axx/spc5_registry.h new file mode 100644 index 000000000..b6f4b0a41 --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/spc5_registry.h @@ -0,0 +1,314 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/spc5_registry.h
+ * @brief SPC564Axx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if defined(_SPC564A70B4_) || defined(_SPC564A70L7_)
+#define _SPC564A70_
+#elif defined(_SPC564A74B4_) || defined(_SPC564A74L7_)
+#define _SPC564A74_
+#elif defined(_SPC564A80B4_) || defined(_SPC564A80L7_)
+#define _SPC564A80_
+#else
+#error "SPC564Axx platform not defined"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC564Axx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 FALSE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_HAS_DSPI4 FALSE
+#define SPC5_HAS_DSPI5 FALSE
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+#define SPC5_DSPI_FIFO_DEPTH 4
+#define SPC5_DSPI1_TFFF_HANDLER vector133
+#define SPC5_DSPI1_TFFF_NUMBER 133
+#define SPC5_DSPI1_RFDF_HANDLER vector135
+#define SPC5_DSPI1_RFDF_NUMBER 135
+#define SPC5_DSPI2_TFFF_HANDLER vector138
+#define SPC5_DSPI2_TFFF_NUMBER 138
+#define SPC5_DSPI2_RFDF_HANDLER vector140
+#define SPC5_DSPI2_RFDF_NUMBER 140
+#define SPC5_DSPI3_TFFF_HANDLER vector143
+#define SPC5_DSPI3_TFFF_NUMBER 143
+#define SPC5_DSPI3_RFDF_HANDLER vector145
+#define SPC5_DSPI3_RFDF_NUMBER 145
+#define SPC5_DSPI1_ENABLE_CLOCK()
+#define SPC5_DSPI1_DISABLE_CLOCK()
+#define SPC5_DSPI2_ENABLE_CLOCK()
+#define SPC5_DSPI2_DISABLE_CLOCK()
+#define SPC5_DSPI3_ENABLE_CLOCK()
+#define SPC5_DSPI3_DISABLE_CLOCK()
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 64
+#define SPC5_EDMA_HAS_MUX FALSE
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 12
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 24
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 13
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 14
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 25
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 15
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 16
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 26
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 17
+
+/* eQADC attributes.*/
+#define SPC5_HAS_EQADC TRUE
+
+/* eSCI attributes.*/
+#define SPC5_HAS_ESCIA TRUE
+#define SPC5_ESCIA_HANDLER vector146
+#define SPC5_ESCIA_NUMBER 146
+
+#define SPC5_HAS_ESCIB TRUE
+#define SPC5_ESCIB_HANDLER vector149
+#define SPC5_ESCIB_NUMBER 149
+
+#define SPC5_HAS_ESCIC TRUE
+#define SPC5_ESCIC_HANDLER vector473
+#define SPC5_ESCIC_NUMBER 473
+
+/* SIU attributes.*/
+#define SPC5_HAS_SIU TRUE
+#define SPC5_SIU_SUPPORTS_PORTS FALSE
+
+/* EMIOS attributes.*/
+#define SPC5_HAS_EMIOS TRUE
+
+#define SPC5_EMIOS_NUM_CHANNELS 24
+
+#define SPC5_EMIOS_FLAG_F0_HANDLER vector51
+#define SPC5_EMIOS_FLAG_F1_HANDLER vector52
+#define SPC5_EMIOS_FLAG_F2_HANDLER vector53
+#define SPC5_EMIOS_FLAG_F3_HANDLER vector54
+#define SPC5_EMIOS_FLAG_F4_HANDLER vector55
+#define SPC5_EMIOS_FLAG_F5_HANDLER vector56
+#define SPC5_EMIOS_FLAG_F6_HANDLER vector57
+#define SPC5_EMIOS_FLAG_F7_HANDLER vector58
+#define SPC5_EMIOS_FLAG_F8_HANDLER vector59
+#define SPC5_EMIOS_FLAG_F9_HANDLER vector60
+#define SPC5_EMIOS_FLAG_F10_HANDLER vector61
+#define SPC5_EMIOS_FLAG_F11_HANDLER vector62
+#define SPC5_EMIOS_FLAG_F12_HANDLER vector63
+#define SPC5_EMIOS_FLAG_F13_HANDLER vector64
+#define SPC5_EMIOS_FLAG_F14_HANDLER vector65
+#define SPC5_EMIOS_FLAG_F15_HANDLER vector66
+#define SPC5_EMIOS_FLAG_F16_HANDLER vector202
+#define SPC5_EMIOS_FLAG_F17_HANDLER vector203
+#define SPC5_EMIOS_FLAG_F18_HANDLER vector204
+#define SPC5_EMIOS_FLAG_F19_HANDLER vector205
+#define SPC5_EMIOS_FLAG_F20_HANDLER vector206
+#define SPC5_EMIOS_FLAG_F21_HANDLER vector207
+#define SPC5_EMIOS_FLAG_F22_HANDLER vector208
+#define SPC5_EMIOS_FLAG_F23_HANDLER vector209
+#define SPC5_EMIOS_FLAG_F0_NUMBER 51
+#define SPC5_EMIOS_FLAG_F1_NUMBER 52
+#define SPC5_EMIOS_FLAG_F2_NUMBER 53
+#define SPC5_EMIOS_FLAG_F3_NUMBER 54
+#define SPC5_EMIOS_FLAG_F4_NUMBER 55
+#define SPC5_EMIOS_FLAG_F5_NUMBER 56
+#define SPC5_EMIOS_FLAG_F6_NUMBER 57
+#define SPC5_EMIOS_FLAG_F7_NUMBER 58
+#define SPC5_EMIOS_FLAG_F8_NUMBER 59
+#define SPC5_EMIOS_FLAG_F9_NUMBER 60
+#define SPC5_EMIOS_FLAG_F10_NUMBER 61
+#define SPC5_EMIOS_FLAG_F11_NUMBER 62
+#define SPC5_EMIOS_FLAG_F12_NUMBER 63
+#define SPC5_EMIOS_FLAG_F13_NUMBER 64
+#define SPC5_EMIOS_FLAG_F14_NUMBER 65
+#define SPC5_EMIOS_FLAG_F15_NUMBER 66
+#define SPC5_EMIOS_FLAG_F16_NUMBER 202
+#define SPC5_EMIOS_FLAG_F17_NUMBER 203
+#define SPC5_EMIOS_FLAG_F18_NUMBER 204
+#define SPC5_EMIOS_FLAG_F19_NUMBER 205
+#define SPC5_EMIOS_FLAG_F20_NUMBER 206
+#define SPC5_EMIOS_FLAG_F21_NUMBER 207
+#define SPC5_EMIOS_FLAG_F22_NUMBER 208
+#define SPC5_EMIOS_FLAG_F23_NUMBER 209
+
+#define SPC5_EMIOS_CLK (SPC5_SYSCLK / \
+ SPC5_EMIOS_GPRE_VALUE)
+#define SPC5_EMIOS_ENABLE_CLOCK()
+#define SPC5_EMIOS_DISABLE_CLOCK()
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_SHARED_IRQ FALSE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector152
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector153
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_HANDLER vector155
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_HANDLER vector156
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_HANDLER vector157
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_HANDLER vector158
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_HANDLER vector159
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_HANDLER vector160
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_HANDLER vector161
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_HANDLER vector162
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_HANDLER vector163
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_HANDLER vector164
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_HANDLER vector165
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_HANDLER vector166
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_HANDLER vector167
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_HANDLER vector168
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_HANDLER vector169
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_HANDLER vector170
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector171
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector172
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 152
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 153
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_NUMBER 155
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_01_NUMBER 156
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_02_NUMBER 157
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_03_NUMBER 158
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_NUMBER 159
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_05_NUMBER 160
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_06_NUMBER 161
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_07_NUMBER 162
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_NUMBER 163
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_09_NUMBER 164
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_10_NUMBER 165
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_11_NUMBER 166
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_NUMBER 167
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_13_NUMBER 168
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_14_NUMBER 169
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_15_NUMBER 170
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 171
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 172
+#define SPC5_FLEXCAN0_ENABLE_CLOCK()
+#define SPC5_FLEXCAN0_DISABLE_CLOCK()
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_MB 64
+#define SPC5_FLEXCAN1_SHARED_IRQ FALSE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector173
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector174
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_HANDLER vector176
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_HANDLER vector177
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_HANDLER vector178
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_HANDLER vector179
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_HANDLER vector180
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_HANDLER vector181
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_HANDLER vector182
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_HANDLER vector183
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_HANDLER vector184
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_HANDLER vector185
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_HANDLER vector186
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_HANDLER vector187
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_HANDLER vector188
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_HANDLER vector189
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_HANDLER vector190
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_HANDLER vector191
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector192
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector193
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 173
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 174
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_NUMBER 176
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_01_NUMBER 177
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_02_NUMBER 178
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_03_NUMBER 179
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_NUMBER 180
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_05_NUMBER 181
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_06_NUMBER 182
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_07_NUMBER 183
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_NUMBER 184
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_09_NUMBER 185
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_10_NUMBER 186
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_11_NUMBER 187
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_NUMBER 188
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_13_NUMBER 189
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_14_NUMBER 190
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_15_NUMBER 191
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 192
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 193
+#define SPC5_FLEXCAN1_ENABLE_CLOCK()
+#define SPC5_FLEXCAN1_DISABLE_CLOCK()
+
+#define SPC5_HAS_FLEXCAN2 TRUE
+#define SPC5_FLEXCAN2_MB 64
+#define SPC5_FLEXCAN2_SHARED_IRQ FALSE
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector280
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector281
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_HANDLER vector283
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_01_HANDLER vector284
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_02_HANDLER vector285
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_03_HANDLER vector286
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_HANDLER vector287
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_05_HANDLER vector288
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_06_HANDLER vector289
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_07_HANDLER vector290
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_HANDLER vector291
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_09_HANDLER vector292
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_10_HANDLER vector293
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_11_HANDLER vector294
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_HANDLER vector295
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_13_HANDLER vector296
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_14_HANDLER vector297
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_15_HANDLER vector298
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector299
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector300
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 280
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 281
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_NUMBER 283
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_01_NUMBER 284
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_02_NUMBER 285
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_03_NUMBER 286
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_NUMBER 287
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_05_NUMBER 288
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_06_NUMBER 289
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_07_NUMBER 290
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_NUMBER 291
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_09_NUMBER 292
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_10_NUMBER 293
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_11_NUMBER 294
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_NUMBER 295
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_13_NUMBER 296
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_14_NUMBER 297
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_15_NUMBER 298
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 299
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 300
+#define SPC5_FLEXCAN2_ENABLE_CLOCK()
+#define SPC5_FLEXCAN2_DISABLE_CLOCK()
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC564Axx/typedefs.h b/os/hal/ports/SPC5/SPC564Axx/typedefs.h new file mode 100644 index 000000000..92a9f1f40 --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC564Axx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC564Axx/xpc564a.h b/os/hal/ports/SPC5/SPC564Axx/xpc564a.h new file mode 100644 index 000000000..24c159e13 --- /dev/null +++ b/os/hal/ports/SPC5/SPC564Axx/xpc564a.h @@ -0,0 +1,6377 @@ +/**************************************************************************/
+/* FILE NAME: MPC5644A.h COPYRIGHT(c) Freescale & STMicroelectronics */
+/* VERSION: 0.5 2010 - All Rights Reserved */
+/* */
+/* DESCRIPTION: */
+/* This file contains all of the register and bit field definitions for */
+/* MPC5644A. */
+/*========================================================================*/
+/* UPDATE HISTORY */
+/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
+/* --- ----------- --------- --------------------- */
+/* 0.1 R. MORAN 10/Aug/09 Initial Alpha version. */
+/* 0.2 R. Moran 09/Nov/09 Several Updates: */
+/* - XBAR - MPR/SGPCR'3' changed to '2' */
+/* - CFCR, IDCR, CFTCR array sizes altered*/
+/* - IDIS,CASCD added to DEC_Filter MCR */
+/* - WDM fields changed in eTPU_WDTR reg */
+/* - Additional ECSM registers added */
+/* 0.3 R. Moran 14/Jan/10 Several Updates: */
+/* - Flash User Test Register implemented */
+/* - MPU.EDR[3] register removed */
+/* - Minor Loop TCD bits implemented */
+/* - Temperature Sensor implemented */
+/* - DSPI.MCR.B.PES implemented */
+/* 0.4 R. Moran 30/Mar/10 - Added DTS Module Registers */
+/* - Added Reaction Module */
+/* - eQADC REDLCCR register */
+/* - Temp Sensor TCCR0 corrected */
+/* - CFTCR definition changed */
+/* - EBI CAL_BR/OR updated */
+/* - XBAR MPR0,1,3,7 fixed master fields */
+/* - Decimation filter updated to support */
+/* Integration filter and rev2 changes */
+/* 0.5 I. Harris 25/May/10 - Updated ECSM_ESR with 1bit cor. fld */
+/* - Updated ECSM_ECR with 1bit cor. ena */
+/* - Corrected ECSM_MUDR endianness */
+/* - Corrected ECSM_MWCR ENBWCR field name*/
+/* - Updated SIU_IREEx fields */
+/* - Added EBI_MCR DBM field */
+/* - Added PBRIDGE Registers */
+/* - Added SIU EMPCR0 Register */
+/* - Included FlexCAN RXFIFO structure */
+/**************************************************************************/
+
+/**************************************************************************/
+/* Example instantiation and use: */
+/* */
+/* <MODULE>.<REGISTER>.B.<BIT> = 1; */
+/* <MODULE>.<REGISTER>.R = 0x10000000; */
+/* */
+/**************************************************************************/
+
+#ifndef _MPC5644_H_
+#define _MPC5644_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+
+/****************************************************************************/
+/* DMA2 Transfer Control Descriptor */
+/****************************************************************************/
+
+ struct EDMA_TCD_STD_tag { /* for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
+ /* 00 */
+ vuint32_t SADDR; /* Source Address */
+
+ /* 04 */ /* Transfer Attributes */
+ vuint16_t SMOD:5; /* Source Address Modulo */
+ vuint16_t SSIZE:3; /* Source Data Transfer Size */
+ vuint16_t DMOD:5; /* Destination Address Modulo */
+ vuint16_t DSIZE:3; /* Destination Data Transfer Size */
+
+ /* 06 */
+ vint16_t SOFF; /* Signed Source Address Offset */
+
+ /* 08 */
+ vuint32_t NBYTES; /* Inner ("Minor") Byte Transfer Count */
+
+ /* 0C */
+ vint32_t SLAST; /* Last Source Address Adjustment */
+
+ /* 10 */
+ vuint32_t DADDR; /* Destination Address */
+
+ /* 14 */
+ vuint16_t CITERE_LINK:1; /* Enable Channel-to-Channel */
+ /* Linking on Minor Loop Completion */
+ vuint16_t CITER:15; /* Current Major Iteration Count */
+
+ /* 16 */
+ vint16_t DOFF; /* Signed Destination Address Offset */
+
+ /* 18 */
+ vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or */
+ /* Scatter/Gather Address (if E_SG = 1) */
+
+ /* 1C */
+ vuint16_t BITERE_LINK:1; /* Enable Channel-to-Channel */
+ /* Linking on Minor Loop Complete */
+ vuint16_t BITER:15; /* Starting ("Major") Iteration Count */
+
+ /* 1E */ /* Channel Control/Status */
+ vuint16_t BWC:2; /* Bandwidth Control */
+ vuint16_t MAJORLINKCH:6; /* Link Channel Number */
+ vuint16_t DONE:1; /* Channel Done */
+ vuint16_t ACTIVE:1;
+ vuint16_t MAJORE_LINK:1; /* Enable Channel-to-Channel Link */
+ vuint16_t E_SG:1; /* Enable Scatter/Gather Descriptor */
+ vuint16_t D_REQ:1; /* Disable IPD_REQ When Done */
+ vuint16_t INT_HALF:1; /* Interrupt on CITER = (BITER >> 1) */
+ vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */
+ vuint16_t START:1; /* Explicit Channel Start */
+ };
+
+
+
+ struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */
+
+ /* 00 */
+ vuint32_t SADDR; /* Source Address */
+
+ /* 04 */ /* Transfer Attributes */
+ vuint16_t SMOD:5; /* Source Address Modulo */
+ vuint16_t SSIZE:3; /* Source Data Transfer Size */
+ vuint16_t DMOD:5; /* Destination Address Modulo */
+ vuint16_t DSIZE:3; /* Destination Data Transfer Size */
+
+ /* 06 */
+ vint16_t SOFF; /* Signed Source Address Offset */
+
+ /* 08 */
+ vuint32_t NBYTES; /* Inner ("Minor") Byte Transfer Count */
+
+ /* 0C */
+ vint32_t SLAST; /* Last Source Address Adjustment */
+
+ /* 10 */
+ vuint32_t DADDR; /* Destination Address */
+
+ /* 14 */
+ vuint16_t CITERE_LINK:1; /* Enable Channel-to-Channel */
+ /* Linking on Minor Loop Completion */
+ vuint16_t CITERLINKCH:6; /* Link Channel Number */
+ vuint16_t CITER:9; /* Current Major Iteration Count */
+
+ /* 16 */
+ vint16_t DOFF; /* Signed Destination Address Offset */
+
+ /* 18 */
+ vint32_t DLAST_SGA; /* Last Destination Address Adjustment, or */
+ /* Scatter/Gather Address (if E_SG = 1) */
+
+ /* 1C */
+ vuint16_t BITERE_LINK:1; /* Enable Channel-to-Channel */
+ /* Linking on Minor Loop Complete */
+ vuint16_t BITERLINKCH:6; /* Link Channel Number */
+ vuint16_t BITER:9; /* Starting ("Major") Iteration Count */
+
+ /* 1E */ /* Channel Control/Status */
+ vuint16_t BWC:2; /* Bandwidth Control */
+ vuint16_t MAJORLINKCH:6; /* Link Channel Number */
+ vuint16_t DONE:1; /* Channel Done */
+ vuint16_t ACTIVE:1; /* Channel Active */
+ vuint16_t MAJORE_LINK:1; /* Enable Channel-to-Channel Link */
+ vuint16_t E_SG:1; /* Enable Scatter/Gather Descriptor */
+ vuint16_t D_REQ:1; /* Disable IPD_REQ When Done */
+ vuint16_t INT_HALF:1; /* Interrupt on CITER = (BITER >> 1) */
+ vuint16_t INT_MAJ:1; /* Interrupt on Major Loop Completion */
+ vuint16_t START:1; /* Explicit Channel Start */
+ };
+
+ struct EDMA_TCD_alt2_tag { /* for alternate format TCDs (when EDMA.EMLM=1) */
+
+ vuint32_t SADDR; /* source address */
+
+ vuint16_t SMOD:5; /* source address modulo */
+ vuint16_t SSIZE:3; /* source transfer size */
+ vuint16_t DMOD:5; /* destination address modulo */
+ vuint16_t DSIZE:3; /* destination transfer size */
+ vint16_t SOFF; /* signed source address offset */
+
+ vuint16_t SMLOE:1; /* Source minor loop offset enable */
+ vuint16_t DMLOE:1; /* Destination minor loop offset enable */
+ vuint32_t MLOFF:20; /* Minor loop Offset */
+ vuint16_t NBYTES:10; /* inner (“minor”) byte count */
+
+ vint32_t SLAST; /* last destination address adjustment, or
+
+ scatter/gather address (if e_sg = 1) */
+ vuint32_t DADDR; /* destination address */
+
+ vuint16_t CITERE_LINK:1;
+ vuint16_t CITER:15;
+
+ vint16_t DOFF; /* signed destination address offset */
+
+ vint32_t DLAST_SGA;
+
+ vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */
+ vuint16_t BITER:15;
+
+ vuint16_t BWC:2; /* bandwidth control */
+ vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */
+ vuint16_t DONE:1; /* channel done */
+ vuint16_t ACTIVE:1; /* channel active */
+ vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */
+ vuint16_t E_SG:1; /* enable scatter/gather descriptor */
+ vuint16_t D_REQ:1; /* disable ipd_req when done */
+ vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop completion */
+ vuint16_t START:1; /* explicit channel start */
+ };
+
+
+/****************************************************************************/
+/* MODULE : eDMA */
+/****************************************************************************/
+
+ struct EDMA_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14; /* Reserved */
+ vuint32_t CX:1; /* Cancel Transfer */
+ vuint32_t ECX:1; /* Error Cancel Transfer */
+ vuint32_t GRP3PRI:2; /* Channel Group 3 Priority */
+ vuint32_t GRP2PRI:2; /* Channel Group 2 Priority */
+ vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */
+ vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */
+ vuint32_t EMLM:1; /* Enable Minor Loop Mapping */
+ vuint32_t CLM:1; /* Continuous Link Mode */
+ vuint32_t HALT:1; /* Halt DMA Operations */
+ vuint32_t HOE:1; /* Halt On Error */
+ vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */
+ vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */
+ vuint32_t EDBG:1; /* Enable Debug */
+ vuint32_t:1; /* Enable Buffered Writes */
+ } B;
+ } CR; /* DMA Control Register @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1; /* Logical OR of all DMAERRH */
+ vuint32_t:14; /* Reserved */
+ vuint32_t ECX:1; /* Transfer Canceled */
+ vuint32_t GPE:1; /* Group Priority Error */
+ vuint32_t CPE:1; /* Channel Priority Error */
+ vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */
+ vuint32_t SAE:1; /* Source Address Error 0 */
+ vuint32_t SOE:1; /* Source Offset Error */
+ vuint32_t DAE:1; /* Destination Address Error */
+ vuint32_t DOE:1; /* Destination Offset Error */
+ vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */
+ vuint32_t SGE:1; /* Scatter/Gather Configuration Error */
+ vuint32_t SBE:1; /* Source Bus Error */
+ vuint32_t DBE:1; /* Destination Bus Error */
+ } B;
+ } ESR; /* Error Status Register @baseaddress + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ63:1;
+ vuint32_t ERQ62:1;
+ vuint32_t ERQ61:1;
+ vuint32_t ERQ60:1;
+ vuint32_t ERQ59:1;
+ vuint32_t ERQ58:1;
+ vuint32_t ERQ57:1;
+ vuint32_t ERQ56:1;
+ vuint32_t ERQ55:1;
+ vuint32_t ERQ54:1;
+ vuint32_t ERQ53:1;
+ vuint32_t ERQ52:1;
+ vuint32_t ERQ51:1;
+ vuint32_t ERQ50:1;
+ vuint32_t ERQ49:1;
+ vuint32_t ERQ48:1;
+ vuint32_t ERQ47:1;
+ vuint32_t ERQ46:1;
+ vuint32_t ERQ45:1;
+ vuint32_t ERQ44:1;
+ vuint32_t ERQ43:1;
+ vuint32_t ERQ42:1;
+ vuint32_t ERQ41:1;
+ vuint32_t ERQ40:1;
+ vuint32_t ERQ39:1;
+ vuint32_t ERQ38:1;
+ vuint32_t ERQ37:1;
+ vuint32_t ERQ36:1;
+ vuint32_t ERQ35:1;
+ vuint32_t ERQ34:1;
+ vuint32_t ERQ33:1;
+ vuint32_t ERQ32:1;
+ } B;
+ } ERQRH; /* DMA Enable Request Register High @baseaddress + 0x8*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ31:1;
+ vuint32_t ERQ30:1;
+ vuint32_t ERQ29:1;
+ vuint32_t ERQ28:1;
+ vuint32_t ERQ27:1;
+ vuint32_t ERQ26:1;
+ vuint32_t ERQ25:1;
+ vuint32_t ERQ24:1;
+ vuint32_t ERQ23:1;
+ vuint32_t ERQ22:1;
+ vuint32_t ERQ21:1;
+ vuint32_t ERQ20:1;
+ vuint32_t ERQ19:1;
+ vuint32_t ERQ18:1;
+ vuint32_t ERQ17:1;
+ vuint32_t ERQ16:1;
+ vuint32_t ERQ15:1;
+ vuint32_t ERQ14:1;
+ vuint32_t ERQ13:1;
+ vuint32_t ERQ12:1;
+ vuint32_t ERQ11:1;
+ vuint32_t ERQ10:1;
+ vuint32_t ERQ09:1;
+ vuint32_t ERQ08:1;
+ vuint32_t ERQ07:1;
+ vuint32_t ERQ06:1;
+ vuint32_t ERQ05:1;
+ vuint32_t ERQ04:1;
+ vuint32_t ERQ03:1;
+ vuint32_t ERQ02:1;
+ vuint32_t ERQ01:1;
+ vuint32_t ERQ00:1;
+ } B;
+ } ERQRL; /* DMA Enable Request Register Low @baseaddress + 0xC*/
+
+ union {
+ vuint32_t R;
+ struct {
+
+ vuint32_t EEI63:1;
+ vuint32_t EEI62:1;
+ vuint32_t EEI61:1;
+ vuint32_t EEI60:1;
+ vuint32_t EEI59:1;
+ vuint32_t EEI58:1;
+ vuint32_t EEI57:1;
+ vuint32_t EEI56:1;
+ vuint32_t EEI55:1;
+ vuint32_t EEI54:1;
+ vuint32_t EEI53:1;
+ vuint32_t EEI52:1;
+ vuint32_t EEI51:1;
+ vuint32_t EEI50:1;
+ vuint32_t EEI49:1;
+ vuint32_t EEI48:1;
+ vuint32_t EEI47:1;
+ vuint32_t EEI46:1;
+ vuint32_t EEI45:1;
+ vuint32_t EEI44:1;
+ vuint32_t EEI43:1;
+ vuint32_t EEI42:1;
+ vuint32_t EEI41:1;
+ vuint32_t EEI40:1;
+ vuint32_t EEI39:1;
+ vuint32_t EEI38:1;
+ vuint32_t EEI37:1;
+ vuint32_t EEI36:1;
+ vuint32_t EEI35:1;
+ vuint32_t EEI34:1;
+ vuint32_t EEI33:1;
+ vuint32_t EEI32:1;
+ } B;
+ } EEIRH; /* DMA Enable Error Interrupt Register High @baseaddress + 0x10*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EEI31:1;
+ vuint32_t EEI30:1;
+ vuint32_t EEI29:1;
+ vuint32_t EEI28:1;
+ vuint32_t EEI27:1;
+ vuint32_t EEI26:1;
+ vuint32_t EEI25:1;
+ vuint32_t EEI24:1;
+ vuint32_t EEI23:1;
+ vuint32_t EEI22:1;
+ vuint32_t EEI21:1;
+ vuint32_t EEI20:1;
+ vuint32_t EEI19:1;
+ vuint32_t EEI18:1;
+ vuint32_t EEI17:1;
+ vuint32_t EEI16:1;
+ vuint32_t EEI15:1;
+ vuint32_t EEI14:1;
+ vuint32_t EEI13:1;
+ vuint32_t EEI12:1;
+ vuint32_t EEI11:1;
+ vuint32_t EEI10:1;
+ vuint32_t EEI09:1;
+ vuint32_t EEI08:1;
+ vuint32_t EEI07:1;
+ vuint32_t EEI06:1;
+ vuint32_t EEI05:1;
+ vuint32_t EEI04:1;
+ vuint32_t EEI03:1;
+ vuint32_t EEI02:1;
+ vuint32_t EEI01:1;
+ vuint32_t EEI00:1;
+ } B;
+ } EEIRL; /* DMA Enable Error Interrupt Register Low @baseaddress + 0x14*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t SERQ:7;
+ } B;
+ } SERQR; /* DMA Set Enable Request Register @baseaddress + 0x18*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t CERQ:7;
+ } B;
+ } CERQR; /* DMA Clear Enable Request Register @baseaddress + 0x19*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t SEEI:7;
+ } B;
+ } SEEIR; /* DMA Set Enable Error Interrupt Register @baseaddress + 0x1A*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t CEEI:7;
+ } B;
+ } CEEIR; /* DMA Clear Enable Error Interrupt Register @baseaddress + 0x1B*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t CINT:7;
+ } B;
+ } CIRQR; /* DMA Clear Interrupt Request Register @baseaddress + 0x1C */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t CERR:7;
+ } B;
+ } CER; /* DMA Clear error Register @baseaddress + 0x1D */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t SSB:7;
+ } B;
+ } SSBR; /* Set Start Bit Register @baseaddress + 0x1E */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t CDSB:7;
+ } B;
+ } CDSBR; /* Clear Done Status Bit Register @baseaddress + 0x1F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT63:1;
+ vuint32_t INT62:1;
+ vuint32_t INT61:1;
+ vuint32_t INT60:1;
+ vuint32_t INT59:1;
+ vuint32_t INT58:1;
+ vuint32_t INT57:1;
+ vuint32_t INT56:1;
+ vuint32_t INT55:1;
+ vuint32_t INT54:1;
+ vuint32_t INT53:1;
+ vuint32_t INT52:1;
+ vuint32_t INT51:1;
+ vuint32_t INT50:1;
+ vuint32_t INT49:1;
+ vuint32_t INT48:1;
+ vuint32_t INT47:1;
+ vuint32_t INT46:1;
+ vuint32_t INT45:1;
+ vuint32_t INT44:1;
+ vuint32_t INT43:1;
+ vuint32_t INT42:1;
+ vuint32_t INT41:1;
+ vuint32_t INT40:1;
+ vuint32_t INT39:1;
+ vuint32_t INT38:1;
+ vuint32_t INT37:1;
+ vuint32_t INT36:1;
+ vuint32_t INT35:1;
+ vuint32_t INT34:1;
+ vuint32_t INT33:1;
+ vuint32_t INT32:1;
+ } B;
+ } IRQRH; /* DMA Interrupt Request High @baseaddress + 0x20 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t INT31:1;
+ vuint32_t INT30:1;
+ vuint32_t INT29:1;
+ vuint32_t INT28:1;
+ vuint32_t INT27:1;
+ vuint32_t INT26:1;
+ vuint32_t INT25:1;
+ vuint32_t INT24:1;
+ vuint32_t INT23:1;
+ vuint32_t INT22:1;
+ vuint32_t INT21:1;
+ vuint32_t INT20:1;
+ vuint32_t INT19:1;
+ vuint32_t INT18:1;
+ vuint32_t INT17:1;
+ vuint32_t INT16:1;
+ vuint32_t INT15:1;
+ vuint32_t INT14:1;
+ vuint32_t INT13:1;
+ vuint32_t INT12:1;
+ vuint32_t INT11:1;
+ vuint32_t INT10:1;
+ vuint32_t INT09:1;
+ vuint32_t INT08:1;
+ vuint32_t INT07:1;
+ vuint32_t INT06:1;
+ vuint32_t INT05:1;
+ vuint32_t INT04:1;
+ vuint32_t INT03:1;
+ vuint32_t INT02:1;
+ vuint32_t INT01:1;
+ vuint32_t INT00:1;
+ } B;
+ } IRQRL; /* DMA Interrupt Request Low @baseaddress + 0x24 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR63:1;
+ vuint32_t ERR62:1;
+ vuint32_t ERR61:1;
+ vuint32_t ERR60:1;
+ vuint32_t ERR59:1;
+ vuint32_t ERR58:1;
+ vuint32_t ERR57:1;
+ vuint32_t ERR56:1;
+ vuint32_t ERR55:1;
+ vuint32_t ERR54:1;
+ vuint32_t ERR53:1;
+ vuint32_t ERR52:1;
+ vuint32_t ERR51:1;
+ vuint32_t ERR50:1;
+ vuint32_t ERR49:1;
+ vuint32_t ERR48:1;
+ vuint32_t ERR47:1;
+ vuint32_t ERR46:1;
+ vuint32_t ERR45:1;
+ vuint32_t ERR44:1;
+ vuint32_t ERR43:1;
+ vuint32_t ERR42:1;
+ vuint32_t ERR41:1;
+ vuint32_t ERR40:1;
+ vuint32_t ERR39:1;
+ vuint32_t ERR38:1;
+ vuint32_t ERR37:1;
+ vuint32_t ERR36:1;
+ vuint32_t ERR35:1;
+ vuint32_t ERR34:1;
+ vuint32_t ERR33:1;
+ vuint32_t ERR32:1;
+ } B;
+ } ERH; /* DMA Error High @baseaddress + 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ERR31:1;
+ vuint32_t ERR30:1;
+ vuint32_t ERR29:1;
+ vuint32_t ERR28:1;
+ vuint32_t ERR27:1;
+ vuint32_t ERR26:1;
+ vuint32_t ERR25:1;
+ vuint32_t ERR24:1;
+ vuint32_t ERR23:1;
+ vuint32_t ERR22:1;
+ vuint32_t ERR21:1;
+ vuint32_t ERR20:1;
+ vuint32_t ERR19:1;
+ vuint32_t ERR18:1;
+ vuint32_t ERR17:1;
+ vuint32_t ERR16:1;
+ vuint32_t ERR15:1;
+ vuint32_t ERR14:1;
+ vuint32_t ERR13:1;
+ vuint32_t ERR12:1;
+ vuint32_t ERR11:1;
+ vuint32_t ERR10:1;
+ vuint32_t ERR09:1;
+ vuint32_t ERR08:1;
+ vuint32_t ERR07:1;
+ vuint32_t ERR06:1;
+ vuint32_t ERR05:1;
+ vuint32_t ERR04:1;
+ vuint32_t ERR03:1;
+ vuint32_t ERR02:1;
+ vuint32_t ERR01:1;
+ vuint32_t ERR00:1;
+ } B;
+ } ERL; /* DMA Error Low @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HRS63:1;
+ vuint32_t HRS62:1;
+ vuint32_t HRS61:1;
+ vuint32_t HRS60:1;
+ vuint32_t HRS59:1;
+ vuint32_t HRS58:1;
+ vuint32_t HRS57:1;
+ vuint32_t HRS56:1;
+ vuint32_t HRS55:1;
+ vuint32_t HRS54:1;
+ vuint32_t HRS53:1;
+ vuint32_t HRS52:1;
+ vuint32_t HRS51:1;
+ vuint32_t HRS50:1;
+ vuint32_t HRS49:1;
+ vuint32_t HRS48:1;
+ vuint32_t HRS47:1;
+ vuint32_t HRS46:1;
+ vuint32_t HRS45:1;
+ vuint32_t HRS44:1;
+ vuint32_t HRS43:1;
+ vuint32_t HRS42:1;
+ vuint32_t HRS41:1;
+ vuint32_t HRS40:1;
+ vuint32_t HRS39:1;
+ vuint32_t HRS38:1;
+ vuint32_t HRS37:1;
+ vuint32_t HRS36:1;
+ vuint32_t HRS35:1;
+ vuint32_t HRS34:1;
+ vuint32_t HRS33:1;
+ vuint32_t HRS32:1;
+ } B;
+ } HRSH; /* hardware request status high @baseaddress + 0x30 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HRS31:1;
+ vuint32_t HRS30:1;
+ vuint32_t HRS29:1;
+ vuint32_t HRS28:1;
+ vuint32_t HRS27:1;
+ vuint32_t HRS26:1;
+ vuint32_t HRS25:1;
+ vuint32_t HRS24:1;
+ vuint32_t HRS23:1;
+ vuint32_t HRS22:1;
+ vuint32_t HRS21:1;
+ vuint32_t HRS20:1;
+ vuint32_t HRS19:1;
+ vuint32_t HRS18:1;
+ vuint32_t HRS17:1;
+ vuint32_t HRS16:1;
+ vuint32_t HRS15:1;
+ vuint32_t HRS14:1;
+ vuint32_t HRS13:1;
+ vuint32_t HRS12:1;
+ vuint32_t HRS11:1;
+ vuint32_t HRS10:1;
+ vuint32_t HRS09:1;
+ vuint32_t HRS08:1;
+ vuint32_t HRS07:1;
+ vuint32_t HRS06:1;
+ vuint32_t HRS05:1;
+ vuint32_t HRS04:1;
+ vuint32_t HRS03:1;
+ vuint32_t HRS02:1;
+ vuint32_t HRS01:1;
+ vuint32_t HRS00:1;
+ } B;
+ } HRSL; /* hardware request status low @baseaddress + 0x34 */
+
+ uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[64]; /* Channel n Priority @baseaddress + 0x100 */
+
+ uint32_t eDMA_reserved0140[944]; /* 0x0140-0x0FFF */
+
+ /* Select one of the following declarations depending on the DMA mode chosen */
+ struct EDMA_TCD_STD_tag TCD[64]; /* Standard Format */
+ /* struct EDMA_TCD_alt1_tag TCD[64]; */ /* CITER/BITER Link */
+ /* struct EDMA_TCD_alt2_tag TCD[64]; */ /* Minor Loop Offset */
+
+ };
+
+
+
+/****************************************************************************/
+/* MODULE : XBAR */
+/****************************************************************************/
+ struct XBAR_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */
+ vuint32_t:1;
+ vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:4; /* Master 2 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */
+ vuint32_t:1;
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */
+ } B;
+ } MPR0; /* Master Priority Register for Slave port 0 (Flash) @baseaddress + 0x00 */
+
+ int32_t XBAR_reserved_0004[3]; /* 0x0004 - 0x000F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1; /* Halt Low Priority */
+ vuint32_t:6;
+ vuint32_t HPE7:1; /* High Priority Enable */
+ vuint32_t HPE6:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t HPE4:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t HPE1:1; /* High Priority Enable */
+ vuint32_t HPE0:1; /* High Priority Enable */
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR0; /* Slave General Purpose Control Register 0 (Flash) @baseaddress + 0x10 */
+
+ int32_t XBAR_reserved_0014[59]; /* 0x0014 - 0x01FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */
+ vuint32_t:1;
+ vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:4; /* Master 2 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */
+ vuint32_t:1;
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */
+ } B;
+ } MPR1; /* Master Priority Register for Slave port 1 (EBI) @baseaddress + 0x100 */
+
+ int32_t XBAR_reserved_0100[3]; /* 0x0100 - 0x010F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1; /* Halt Low Priority */
+ vuint32_t:6;
+ vuint32_t HPE7:1; /* High Priority Enable */
+ vuint32_t HPE6:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t HPE4:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t HPE1:1; /* High Priority Enable */
+ vuint32_t HPE0:1; /* High Priority Enable */
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR1; /* Slave General Purpose Control Register 1 (EBI) @baseaddress + 0x110 */
+
+ int32_t XBAR_reserved_0114[59]; /* 0x0114 - 0x01FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */
+ vuint32_t:1;
+ vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:4; /* Master 2 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */
+ vuint32_t:1;
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */
+ } B;
+ } MPR2; /* Master Priority Register for Slave port 2 (RAM) @baseaddress + 0x200 */
+
+ int32_t XBAR_reserved_0204[3]; /* 0x0204 - 0x020F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1; /* Halt Low Priority */
+ vuint32_t:6;
+ vuint32_t HPE7:1; /* High Priority Enable */
+ vuint32_t HPE6:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t HPE4:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t HPE1:1; /* High Priority Enable */
+ vuint32_t HPE0:1; /* High Priority Enable */
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR2; /* Slave General Purpose Control Register 2 (RAM)@baseaddress + 0x210 */
+
+ int32_t XBAR_reserved_0214[59]; /* 0x0214 - 0x02FF */
+
+ /* Slave General Purpose Control Register 3 @baseaddress + 0x310 - not implemented */
+
+ int32_t XBAR_reserved_0300[64]; /* 0x0300 - 0x03FF */
+
+ /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */
+
+ int32_t XBAR_reserved_0400[64]; /* 0x0400 - 0x04FF */
+
+ /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */
+
+ int32_t XBAR_reserved_0500[64]; /* 0x0500 - 0x05FF */
+
+ /* Slave Port 6 not implemented @baseaddress + 0x610 */
+
+ int32_t XBAR_reserved_0600[64]; /* 0x0600 - 0x06FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR7:3; /* Master 7 Priority - Reserved */
+ vuint32_t:1;
+ vuint32_t MSTR6:3; /* Master 6 Priority - FlexRay */
+ vuint32_t:4; /* Master 5 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR4:3; /* Master 4 Priority - eDMA */
+ vuint32_t:4; /* Master 3 Priority - Not implemented */
+ vuint32_t:4; /* Master 2 Priority - Not implemented */
+ vuint32_t:1;
+ vuint32_t MSTR1:3; /* Master 1 Priority - e200z4 Core load/store & Nexus port */
+ vuint32_t:1;
+ vuint32_t MSTR0:3; /* Master 0 Priority - e200z4 core Instruction */
+ } B;
+ } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */
+
+ int32_t XBAR_reserved_0704[3]; /* 0x0704 - 0x070F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1; /* Halt Low Priority */
+ vuint32_t:6;
+ vuint32_t HPE7:1; /* High Priority Enable */
+ vuint32_t HPE6:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t HPE4:1; /* High Priority Enable */
+ vuint32_t:1;
+ vuint32_t:1;
+ vuint32_t HPE1:1; /* High Priority Enable */
+ vuint32_t HPE0:1; /* High Priority Enable */
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */
+
+ int32_t XBAR_reserved_0714[59]; /* 0x0714 - 0x07FF */
+
+ int32_t XBAR_reserved_0800[3584]; /* 0x0800-0x3FFF */
+
+ };
+
+
+/****************************************************************************/
+/* MODULE : PBRIDGE Peripheral Bridge */
+/****************************************************************************/
+
+ struct PBRIDGE_tag {
+
+ union { /* Master Privilege Registers 0-7 @baseaddress + 0x00*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MTR0:1; /* z4 core: Master 0 Trusted for Reads */
+ vuint32_t MTW0:1; /* z4 core: Master 0 Trusted for Writes */
+ vuint32_t MPL0:1; /* z4 core: Master 0 Priviledge Level */
+ vuint32_t:13;
+ vuint32_t MTR4:1; /* DMA: Master 4 Trusted for Reads */
+ vuint32_t MTW4:1; /* DMA: Master 4 Trusted for Writes */
+ vuint32_t MPL4:1; /* DMA: Master 4 Priviledge Level */
+ vuint32_t:5;
+ vuint32_t MTR6:1; /* FlexRay: Master 6 Trusted for Reads */
+ vuint32_t MTW6:1; /* FlexRay: Master 6 Trusted for Writes */
+ vuint32_t MPL6:1; /* FlexRay: Master 6 Priviledge Level */
+ vuint32_t:1;
+ vuint32_t MTR7:1; /* EBI: Master 7 Trusted for Reads */
+ vuint32_t MTW7:1; /* EBI: Master 7 Trusted for Writes */
+ vuint32_t MPL7:1; /* EBI: Master 7 Priviledge Level */
+ } B;
+ } MPCR;
+
+ union { /* Master Privilege Registers 8-15 @baseaddress + 0x04*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MTR0:1; /* Nexus: Master 8 Trusted for Reads */
+ vuint32_t MTW0:1; /* Nexus: Master 8 Trusted for Writes */
+ vuint32_t MPL0:1; /* Nexus: Master 8 Priviledge Level */
+ vuint32_t:28;
+ } B;
+ } MPCR1;
+
+ uint32_t PRIDGE_reserved0008[6]; /* 0x0008-0x001F */
+
+ union { /* Peripheral Access Conrol Registers 0-7 @baseaddress + 0x20*/
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t SP1:1; /* Crossbar: Supervisor Protect */
+ vuint32_t WP1:1; /* Crossbar: Write Protect */
+ vuint32_t TP1:1; /* Crossbar: Trusted Protect */
+ vuint32_t:9;
+ vuint32_t SP4:1; /* MPU: Supervisor Protect */
+ vuint32_t WP4:1; /* MPU: Write Protect */
+ vuint32_t TP4:1; /* MPU: Trusted Protect */
+ vuint32_t:12;
+ } B;
+ } PACR0;
+
+ union { /* Peripheral Access Conrol Registers 8-15 @baseaddress + 0x24*/
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t SP6:1; /* SWT: Supervisor Protect */
+ vuint32_t WP6:1; /* SWT: Write Protect */
+ vuint32_t TP6:1; /* SWT: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP7:1; /* STM: Supervisor Protect */
+ vuint32_t WP7:1; /* STM: Write Protect */
+ vuint32_t TP7:1; /* STM: Trusted Protect */
+ } B;
+ } PACR1;
+
+ union { /* Peripheral Access Conrol Registers 16-23 @baseaddress + 0x28*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* ECSM: Supervisor Protect */
+ vuint32_t WP0:1; /* ECSM: Write Protect */
+ vuint32_t TP0:1; /* ECSM: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP1:1; /* DMA: Supervisor Protect */
+ vuint32_t WP1:1; /* DMA: Write Protect */
+ vuint32_t TP1:1; /* DMA: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP2:1; /* INTC: Supervisor Protect */
+ vuint32_t WP2:1; /* INTC: Write Protect */
+ vuint32_t TP2:1; /* INTC: Trusted Protect */
+ vuint32_t:20;
+ } B;
+ } PACR2;
+
+ union { /* Peripheral Access Conrol Registers 24-31 @baseaddress + 0x2C*/
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } PACR3;
+
+ uint32_t PRIDGE_reserved0030[4]; /* 0x0030-0x003C */
+
+ union { /* Off-Platform Access Control Registers 0-7 @baseaddress + 0x40*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* eQADC: Supervisor Protect */
+ vuint32_t WP0:1; /* eQADC: Write Protect */
+ vuint32_t TP0:1; /* eQADC: Trusted Protect */
+ vuint32_t:5;
+ vuint32_t SP2:1; /* Dec Filter A: Supervisor Protect */
+ vuint32_t WP2:1; /* Dec Filter A: Write Protect */
+ vuint32_t TP2:1; /* Dec Filter A: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP3:1; /* Dec Filter B: Supervisor Protect */
+ vuint32_t WP3:1; /* Dec Filter B: Write Protect */
+ vuint32_t TP3:1; /* Dec Filter B: Trusted Protect */
+ vuint32_t:5;
+ vuint32_t SP5:1; /* DSPIB: Supervisor Protect */
+ vuint32_t WP5:1; /* DSPIB: Write Protect */
+ vuint32_t TP5:1; /* DSPIB: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP6:1; /* DSPIC: Supervisor Protect */
+ vuint32_t WP6:1; /* DSPIC: Write Protect */
+ vuint32_t TP6:1; /* DSPIC: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP7:1; /* DSPID: Supervisor Protect */
+ vuint32_t WP7:1; /* DSPID: Write Protect */
+ vuint32_t TP7:1; /* DSPID: Trusted Protect */
+ } B;
+ } OPACR0;
+
+ union { /* Off-Platform Access Control Registers 8-15 @baseaddress + 0x44*/
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t SP4:1; /* eSCIA: Supervisor Protect */
+ vuint32_t WP4:1; /* eSCIA: Write Protect */
+ vuint32_t TP4:1; /* eSCIA: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP5:1; /* eSCIB: Supervisor Protect */
+ vuint32_t WP5:1; /* eSCIB: Write Protect */
+ vuint32_t TP5:1; /* eSCIB: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP6:1; /* eSCIC: Supervisor Protect */
+ vuint32_t WP6:1; /* eSCIC: Write Protect */
+ vuint32_t TP6:1; /* eSCIC: Trusted Protect */
+ vuint32_t:4;
+ } B;
+ } OPACR1;
+
+ union { /* Off-Platform Access Control Registers 16-23 @baseaddress + 0x48*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* FlexCANA: Supervisor Protect */
+ vuint32_t WP0:1; /* FlexCANA: Write Protect */
+ vuint32_t TP0:1; /* FlexCANA: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP1:1; /* FlexCANB: Supervisor Protect */
+ vuint32_t WP1:1; /* FlexCANB: Write Protect */
+ vuint32_t TP1:1; /* FlexCANB: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP2:1; /* FlexCANC: Supervisor Protect */
+ vuint32_t WP2:1; /* FlexCANC: Write Protect */
+ vuint32_t TP2:1; /* FlexCANC: Trusted Protect */
+ vuint32_t:20;
+ } B;
+ } OPACR2;
+
+ union { /* Off-Platform Access Control Registers 24-31 @baseaddress + 0x4C*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* FlexRay: Supervisor Protect */
+ vuint32_t WP0:1; /* FlexRay: Write Protect */
+ vuint32_t TP0:1; /* FlexRay: Trusted Protect */
+ vuint32_t:9;
+ vuint32_t SP3:1; /* SIM: Supervisor Protect */
+ vuint32_t WP3:1; /* SIM: Write Protect */
+ vuint32_t TP3:1; /* SIM: Trusted Protect */
+ vuint32_t:13;
+ vuint32_t SP7:1; /* BAM: Supervisor Protect */
+ vuint32_t WP7:1; /* BAM: Write Protect */
+ vuint32_t TP7:1; /* BAM: Trusted Protect */
+ } B;
+ } OPACR3;
+
+ union { /* Off-Platform Access Control Registers 32-39 @baseaddress + 0x50*/
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } OPACR4;
+
+ union { /* Off-Platform Access Control Registers 40-47 @baseaddress + 0x54*/
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } OPACR5;
+
+ union { /* Off-Platform Access Control Registers 48-55 @baseaddress + 0x58*/
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } OPACR6;
+
+ union { /* Off-Platform Access Control Registers 56-63 @baseaddress + 0x5C*/
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SP2:1; /* CRC: Supervisor Protect */
+ vuint32_t WP2:1; /* CRC: Write Protect */
+ vuint32_t TP2:1; /* CRC: Trusted Protect */
+ vuint32_t:20;
+ } B;
+ } OPACR7;
+
+ union { /* Off-Platform Access Control Registers 64-71 @baseaddress + 0x60*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* FMPLL: Supervisor Protect */
+ vuint32_t WP0:1; /* FMPLL: Write Protect */
+ vuint32_t TP0:1; /* FMPLL: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP1:1; /* EBI: Supervisor Protect */
+ vuint32_t WP1:1; /* EBI: Write Protect */
+ vuint32_t TP1:1; /* EBI: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP2:1; /* FlashA: Supervisor Protect */
+ vuint32_t WP2:1; /* FlashA: Write Protect */
+ vuint32_t TP2:1; /* FlashA: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP3:1; /* FlashB: Supervisor Protect */
+ vuint32_t WP3:1; /* FlashB: Write Protect */
+ vuint32_t TP3:1; /* FlashB: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP4:1; /* SIU: Supervisor Protect */
+ vuint32_t WP4:1; /* SIU: Write Protect */
+ vuint32_t TP4:1; /* SIU: Trusted Protect */
+ vuint32_t:9;
+ vuint32_t SP7:1; /* DTS: Supervisor Protect */
+ vuint32_t WP7:1; /* DTS: Write Protect */
+ vuint32_t TP7:1; /* DTS: Trusted Protect */
+ } B;
+ } OPACR8;
+
+ union { /* Off-Platform Access Control Registers 72-79 @baseaddress + 0x64*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* eMIOS: Supervisor Protect */
+ vuint32_t WP0:1; /* eMIOS: Write Protect */
+ vuint32_t TP0:1; /* eMIOS: Trusted Protect */
+ vuint32_t:25;
+ vuint32_t SP7:1; /* PMC: Supervisor Protect */
+ vuint32_t WP7:1; /* PMC: Write Protect */
+ vuint32_t TP7:1; /* PMC: Trusted Protect */
+ } B;
+ } OPACR9;
+
+ union { /* Off-Platform Access Control Registers 80-87 @baseaddress + 0x68*/
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SP0:1; /* eTPU2: Supervisor Protect */
+ vuint32_t WP0:1; /* eTPU2: Write Protect */
+ vuint32_t TP0:1; /* eTPU2: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP1:1; /* REACM: Supervisor Protect */
+ vuint32_t WP1:1; /* REACM: Write Protect */
+ vuint32_t TP1:1; /* REACM: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP2:1; /* eTPU PRAM: Supervisor Protect */
+ vuint32_t WP2:1; /* eTPU PRAM: Write Protect */
+ vuint32_t TP2:1; /* eTPU PRAM: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP3:1; /* eTPU PRAM mirror: Supervisor Protect */
+ vuint32_t WP3:1; /* eTPU PRAM mirror: Write Protect */
+ vuint32_t TP3:1; /* eTPU PRAM mirror: Trusted Protect */
+ vuint32_t:1;
+ vuint32_t SP4:1; /* eTPU CRAM: Supervisor Protect */
+ vuint32_t WP4:1; /* eTPU CRAM: Write Protect */
+ vuint32_t TP4:1; /* eTPU CRAM: Trusted Protect */
+ vuint32_t:12;
+ } B;
+ } OPACR10;
+
+ union { /* Off-Platform Access Control Registers 88-95 @baseaddress + 0x6C*/
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t SP4:1; /* PIT: Supervisor Protect */
+ vuint32_t WP4:1; /* PIT: Write Protect */
+ vuint32_t TP4:1; /* PIT: Trusted Protect */
+ vuint32_t:12;
+ } B;
+ } OPACR11;
+
+ uint32_t PRIDGE_reserved0070[4068]; /* 0x0070-0x3FFF */
+
+ };
+
+/****************************************************************************/
+/* MODULE : FLASH */
+/****************************************************************************/
+
+ struct FLASH_tag {
+
+ union { /* Module Configuration Register @baseaddress + 0x00*/
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t SIZE:3;
+ vuint32_t:1;
+ vuint32_t LAS:3;
+ vuint32_t:3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t SBC:1;
+ vuint32_t:1;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t:4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t:10;
+ vuint32_t SLOCK:1;
+ vuint32_t:2;
+ vuint32_t MLOCK:2;
+ vuint32_t:6;
+ vuint32_t LLOCK:10;
+ } B; /* Low/Mid Address Space Block Locking Register @baseaddress + 0x04*/
+ } LMLR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t:25;
+ vuint32_t HBLOCK:6;
+ } B;
+ } HLR; /* High Address Space Block Locking Register @baseaddress + 0x08*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t:10;
+ vuint32_t SSLOCK:1;
+ vuint32_t:2;
+ vuint32_t SMLOCK:2;
+ vuint32_t:6;
+ vuint32_t SLLOCK:10;
+ } B;
+ } SLMLR; /* Secondary Low/Mid Block Locking Register @baseaddress + 0x0C*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSEL:2;
+ vuint32_t:6;
+ vuint32_t LSEL:10;
+ } B;
+ } LMSR; /* Low/Mid Address Space Block Select Register @baseaddress + 0x10*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HBSEL:6;
+ } B;
+ } HSR; /* High Address Space Block Select Register @baseaddress + 0x14*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SAD:1;
+ vuint32_t:13;
+ vuint32_t ADDR:15;
+ vuint32_t:3;
+ } B;
+ } AR; /* Address Register @baseaddress + 0x18*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t:1; /* Reserved */
+ vuint32_t:1; /* EBI Testing - Reserved */
+ vuint32_t M6PFE:1; /* FlexRay */
+ vuint32_t:1; /* Reserved */
+ vuint32_t M4PFE:1; /* eDMA */
+ vuint32_t:1; /* Reserved */
+ vuint32_t:1; /* Reserved */
+ vuint32_t M1PFE:1; /* z4 Core Load/Store */
+ vuint32_t M0PFE:1; /* z4 Core Instruction */
+ vuint32_t APC:3;
+ vuint32_t WWSC:2;
+ vuint32_t RWSC:3;
+ vuint32_t:1;
+ vuint32_t DPFEN:1;
+ vuint32_t:1;
+ vuint32_t IPFEN:1;
+ vuint32_t:1;
+ vuint32_t PFLIM:2;
+ vuint32_t BFEN:1;
+ } B;
+ } BIUCR; /* Bus Interface Unit Configuration Register 1 @baseaddress + 0x1C*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t:2; /* Reserved */
+ vuint32_t:2; /* EBI Testing - Reserved */
+ vuint32_t M6AP:2; /* FlexRay */
+ vuint32_t:2; /* Reserved */
+ vuint32_t M4AP:2; /* eDMA_A */
+ vuint32_t:2; /* Reserved */
+ vuint32_t:2; /* Reserved */
+ vuint32_t M1AP:2; /* z4 Core Load/Store */
+ vuint32_t M0AP:2; /* z4 Core Instruction */
+ } B;
+ } BIUAPR; /*Bus Interface Unit Access Protection Register @baseaddress + 0x20*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LBCFG:2;
+ vuint32_t:30;
+ } B;
+ } BIUCR2; /* Bus Interface Unit Configuration Register 2 @baseaddress + 0x24*/
+
+ uint32_t FLASH_reserved0028[5]; /* 0x0028-0x003B */
+
+ union { /* User Test 0 (UT0) register@baseaddress + 0x3C */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1; /* User test enable (Read/Clear) */
+ vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */
+ vuint32_t:6; /* Reserved */
+ vuint32_t DSI:8; /* Data syndrome input (Read/Write) */
+ vuint32_t:9; /* Reserved */
+ vuint32_t:1; /* Reserved (Read/Write) */
+ vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */
+ vuint32_t MRV:1; /* Margin Read Value (Read/Write) */
+ vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */
+ vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */
+ vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */
+ vuint32_t AID:1; /* Array Integrity Done (Read Only) */
+ } B;
+ } UT0;
+
+ union { /* User Test 1 (UT1) register@baseaddress + 0x40 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32; /* Data Array Input (Read/Write) */
+ } B;
+ } UT1;
+
+ union { /* User Test 2 (UT2) register@baseaddress + 0x44 */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32; /* Data Array Input (Read/Write) */
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32; /* Multiple input Signature (Read/Write) */
+ } B;
+ } UMISR[5];
+
+ uint32_t FLASH_reserved005C[4073]; /* 0x005C-0x3FFF */
+ };
+
+
+
+
+/****************************************************************************/
+/* MODULE : EBI */
+/****************************************************************************/
+ struct CS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BA:17;
+ vuint32_t:3;
+ vuint32_t PS:1;
+ vuint32_t:3;
+ vuint32_t AD_MUX:1;
+ vuint32_t BL:1;
+ vuint32_t WEBS:1;
+ vuint32_t TBDIP:1;
+ vuint32_t:1;
+ vuint32_t SETA:1;
+ vuint32_t BI:1;
+ vuint32_t V:1;
+ } B;
+ } BR; /* EBI Base Registers (BR) @baseaddress + 0x10 - 0x28 */
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AM:17;
+ vuint32_t:7;
+ vuint32_t SCY:4;
+ vuint32_t:1;
+ vuint32_t BSCY:2;
+ vuint32_t:1;
+ } B;
+ } OR; /* EBI Option Registers (OR) @baseaddress + 0x14 - 0x2C */
+ };
+ struct CAL_CS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BA:17;
+ vuint32_t:3;
+ vuint32_t PS:1;
+ vuint32_t:3;
+ vuint32_t AD_MUX:1;
+ vuint32_t BL:1;
+ vuint32_t WEBS:1;
+ vuint32_t TBDIP:1;
+ vuint32_t:1;
+ vuint32_t SETA:1;
+ vuint32_t BI:1;
+ vuint32_t V:1;
+ } B;
+ } BR; /* EBI CAL Base Registers (CAL_BR) @baseaddress + 0x40 - 0x58 */
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t AM:17;
+ vuint32_t:7;
+ vuint32_t SCY:4;
+ vuint32_t:1;
+ vuint32_t BSCY:2;
+ vuint32_t:1;
+
+ } B;
+ } OR; /* EBI CAL Option Registers (CAL_OR) @baseaddress + 0x44 - 0x5C */
+ };
+
+
+ struct EBI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ACGE:1;
+ vuint32_t:8;
+ vuint32_t MDIS:1;
+ vuint32_t:3;
+ vuint32_t D16_31:1;
+ vuint32_t AD_MUX:1;
+ vuint32_t DBM:1;
+ } B;
+ } MCR; /* EBI Module Configuration Register (MCR) @baseaddress + 0x00 */
+
+ uint32_t EBI_reserved0004[1]; /* 0x0004-0x0008 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t BMTF:1;
+ } B;
+ } TESR; /* EBI Transfer Error Status Register (TESR) @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t BMT:8;
+ vuint32_t BME:1;
+ vuint32_t:7;
+ } B;
+ } BMCR; /* EBI Bus Montior Control Register (BMCR) @baseaddress + 0x0C */
+
+ struct CS_tag CS[4]; /* EBI CS Registers (BR / OR) @baseaddress + 0x10 - 0x2C */
+
+ uint32_t EBI_reserved0030[4]; /* 0x0030 - 0x003C */
+
+ struct CAL_CS_tag CAL_CS[4]; /* EBI CAL_CS Registers (CAL_BR / CAL_OR) @baseaddress + 0x40 - 0x5C */
+ };
+
+
+/****************************************************************************/
+/* MODULE : INTC */
+/****************************************************************************/
+ struct INTC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18; /* Reserved */
+ vuint32_t:1; /* Reserved */
+ vuint32_t:4; /* Reserved */
+ vuint32_t:1; /* Reserved */
+ vuint32_t:2; /* Reserved */
+ vuint32_t VTES:1; /* Vector Table Entry Size */
+ vuint32_t:4; /* Reserved */
+ vuint32_t HVEN:1; /* Hardware Vector Enable */
+ } B;
+ } MCR; /* INTC Module Configuration Register (MCR) @baseaddress + 0x00 */
+
+ int32_t INTC_Reserved_0004[1]; /* 0x0004 - 0x0007 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* Reserved */
+ vuint32_t PRI:4; /* Priority */
+ } B;
+ } CPR; /* INTC Current Priority Register (CPR) @baseaddress + 0x08 */
+
+ int32_t INTC_reserved_000C; /* 0x000C - 0x000F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA:21; /* Vector Table Base Address */
+ vuint32_t INTVEC:9; /* Interrupt Vector */
+ vuint32_t:2; /* Reserved */
+ } B;
+ } IACKR; /* INTC Interrupt Acknowledge Register (IACKR) @baseaddress + 0x10 */
+
+ int32_t INTC_Reserved_0014; /* 0x0014 - 0x00017 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32; /* Reserved */
+ } B;
+ } EOIR; /* INTC End of Interrupt Register (EOIR) @baseaddress + 0x18 */
+
+ int32_t INTC_Reserved_001C; /* 0x001C - 0x001F */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:6; /* Reserved */
+ vuint8_t SET:1; /* Set Flag bits */
+ vuint8_t CLR:1; /* Clear Flag bits */
+ } B;
+ } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) @baseaddress + 0x20 */
+
+ int32_t INTC_Reserved_0028[6]; /* 0x0028 - 0x003F */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2; /* Reserved */
+ vuint8_t:2; /* Reserved */
+ vuint8_t PRI:4; /* Priority Select */
+ } B;
+ } PSR[512]; /* INTC Priority Select Registers (PSR) @baseaddress + 0x40 */
+
+ };
+
+
+/****************************************************************************/
+/* MODULE : SIU */
+/****************************************************************************/
+ struct SIU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t S_F:1; /* Identifies the Manufacturer */
+ vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) */
+ vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity */
+ vuint32_t TEMP_RANGE:2; /* Define maximum operating range */
+ vuint32_t:1; /* Reserved for future enhancements */
+ vuint32_t MAX_FREQ:2; /* Define maximum device speed */
+ vuint32_t:1; /* Reserved for future enhancements */
+ vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V */
+ vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product */
+ vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */
+ vuint32_t:2; /* Reserved for future enhancements */
+ vuint32_t EE:1; /* Indicates if Data Flash is present */
+ vuint32_t:3; /* Reserved for future enhancements */
+ vuint32_t FR:1; /* Indicates if Data FlexRay is present */
+ } B;
+ } MIDR2; /* MCU ID Register 2 @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16; /* Device part number */
+ vuint32_t CSP:1; /* CSP configuration */
+ vuint32_t PKG:5; /* Indicate the package the die is mounted in. */
+ vuint32_t:2; /* Reserved */
+ vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */
+ } B;
+ } MIDR; /* MCU ID Register (MIDR) @baseaddress + 0x4 */
+
+ int32_t SIU_Reserved_0008; /* 0x0008 - 0x000B */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PORS:1; /* Power-On Reset Status */
+ vuint32_t ERS:1; /* External Reset Status */
+ vuint32_t LLRS:1; /* Loss of Lock Reset Status */
+ vuint32_t LCRS:1; /* Loss of Clock Reset Status */
+ vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */
+ vuint32_t :1;
+ vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status */
+ vuint32_t:7;
+ vuint32_t SSRS:1; /* Software System Reset Status */
+ vuint32_t SERF:1; /* Software External Reset Flag */
+ vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */
+ vuint32_t:11;
+ vuint32_t ABR:1; /* Auto Baud Rate */
+ vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */
+ vuint32_t RGF:1; /* RESET Glitch Flag */
+ } B;
+ } RSR; /* Reset Status Register (SIU_RSR) @baseaddress + 0xC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SSR:1; /* Software System Reset */
+ vuint32_t SER:1; /* Software External Reset */
+ vuint32_t:14;
+ vuint32_t:1;
+ vuint32_t:15;
+ } B;
+ } SRCR; /* System Reset Control Register (SRCR) @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMI:1; /* Non-Maskable Interrupt Flag */
+ vuint32_t:7; /* */
+ vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform */
+ vuint32_t:7; /* */
+ vuint32_t EIF15:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF14:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF13:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF12:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF11:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF10:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF9:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF8:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF7:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF6:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF5:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF4:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF3:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF2:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF1:1; /* External Interrupt Request Flag x */
+ vuint32_t EIF0:1; /* External Interrupt Request Flag x */
+ } B;
+ } EISR; /* SIU External Interrupt Status Register (EISR) @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection */
+ vuint32_t:7;
+ vuint32_t NMISEL0:1; /* SWT Interrupt Platform Input Selection */
+ vuint32_t:7;
+ vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */
+ vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */
+ } B;
+ } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) @baseaddress + 0x18 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28; /* */
+ vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */
+ vuint32_t DIRS2:1; /* DMA/Interrupt Request Select x */
+ vuint32_t DIRS1:1; /* DMA/Interrupt Request Select x */
+ vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */
+ } B;
+ } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) @baseaddress + 0x1C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16; /* */
+ vuint32_t OVF15:1; /* Overrun Flag x */
+ vuint32_t OVF14:1; /* Overrun Flag x */
+ vuint32_t OVF13:1; /* Overrun Flag x */
+ vuint32_t OVF12:1; /* Overrun Flag x */
+ vuint32_t OVF11:1; /* Overrun Flag x */
+ vuint32_t OVF10:1; /* Overrun Flag x */
+ vuint32_t OVF9:1; /* Overrun Flag x */
+ vuint32_t OVF8:1; /* Overrun Flag x */
+ vuint32_t OVF7:1; /* Overrun Flag x */
+ vuint32_t OVF6:1; /* Overrun Flag x */
+ vuint32_t OVF5:1; /* Overrun Flag x */
+ vuint32_t OVF4:1; /* Overrun Flag x */
+ vuint32_t OVF3:1; /* Overrun Flag x */
+ vuint32_t OVF2:1; /* Overrun Flag x */
+ vuint32_t OVF1:1; /* Overrun Flag x */
+ vuint32_t OVF0:1; /* Overrun Flag x */
+ } B;
+ } OSR; /* Overrun Status Register (OSR) @baseaddress + 0x20 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ORE15:1; /* Overrun Request Enable x */
+ vuint32_t ORE14:1; /* Overrun Request Enable x */
+ vuint32_t ORE13:1; /* Overrun Request Enable x */
+ vuint32_t ORE12:1; /* Overrun Request Enable x */
+ vuint32_t ORE11:1; /* Overrun Request Enable x */
+ vuint32_t ORE10:1; /* Overrun Request Enable x */
+ vuint32_t ORE9:1; /* Overrun Request Enable x */
+ vuint32_t ORE8:1; /* Overrun Request Enable x */
+ vuint32_t ORE7:1; /* Overrun Request Enable x */
+ vuint32_t ORE6:1; /* Overrun Request Enable x */
+ vuint32_t ORE5:1; /* Overrun Request Enable x */
+ vuint32_t ORE4:1; /* Overrun Request Enable x */
+ vuint32_t ORE3:1; /* Overrun Request Enable x */
+ vuint32_t ORE2:1; /* Overrun Request Enable x */
+ vuint32_t ORE1:1; /* Overrun Request Enable x */
+ vuint32_t ORE0:1; /* Overrun Request Enable x */
+ } B;
+ } ORER; /* Overrun Request Enable Register (ORER) @baseaddress + 0x24 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x */
+ vuint32_t:7;
+ vuint32_t NMIRE0:1; /* NMI Falling-Edge Event Enable (SWT) x */
+ vuint32_t:7;
+ vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE7:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE6:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE5:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE2:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE1:1; /* IRQ Rising-Edge Event Enable x */
+ vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */
+ } B;
+ } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) @baseaddress + 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable (NMI Input) x */
+ vuint32_t:7;
+ vuint32_t NMIFE0:1; /* NMI Falling-Edge Event Enable (SWT) x */
+ vuint32_t:7;
+ vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE7:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE6:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE5:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE2:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE1:1; /* IRQ Falling-Edge Event Enable x */
+ vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */
+ } B;
+ } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DFL:4; /* Digital Filter Length */
+ } B;
+ } IDFR; /* External IRQ Digital Filter Register (IDFR) @baseaddress + 0x30 */
+
+ int32_t SIU_Reserved_0034[3]; /* 0x0034 - 0x003F */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t PA:3;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t DSC:2;
+ vuint16_t ODE:1;
+ vuint16_t HYS:1;
+ vuint16_t SRC:2;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[512]; /* Pad Configuration Register (PCR) @baseaddress + 0x40 */
+
+ int32_t SIU_Reserved_0374[112]; /* 0x0374 - 0x05FF */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) @baseaddress + 0x600 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) @baseaddress + 0x800 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */
+ vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */
+ vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */
+ vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */
+ vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */
+ vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */
+ vuint32_t:20; /* */
+ } B;
+ } ETISR; /* eQADC Trigger Input Select Register (ETISR) @baseaddress + 0x900 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ESEL15:2; /* External IRQ Input Select x */
+ vuint32_t ESEL14:2; /* External IRQ Input Select x */
+ vuint32_t ESEL13:2; /* External IRQ Input Select x */
+ vuint32_t ESEL12:2; /* External IRQ Input Select x */
+ vuint32_t ESEL11:2; /* External IRQ Input Select x */
+ vuint32_t ESEL10:2; /* External IRQ Input Select x */
+ vuint32_t ESEL9:2; /* External IRQ Input Select x */
+ vuint32_t ESEL8:2; /* External IRQ Input Select x */
+ vuint32_t ESEL7:2; /* External IRQ Input Select x */
+ vuint32_t ESEL6:2; /* External IRQ Input Select x */
+ vuint32_t ESEL5:2; /* External IRQ Input Select x */
+ vuint32_t ESEL4:2; /* External IRQ Input Select x */
+ vuint32_t ESEL3:2; /* External IRQ Input Select x */
+ vuint32_t ESEL2:2; /* External IRQ Input Select x */
+ vuint32_t ESEL1:2; /* External IRQ Input Select x */
+ vuint32_t ESEL0:2; /* External IRQ Input Select x */
+ } B;
+ } EIISR; /* External IRQ Input Select Register (EIISR) @baseaddress + 0x904 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SINSELB:2; /* DSPI_B Data Input Select */
+ vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select */
+ vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select */
+ vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select */
+ vuint32_t SINSELC:2; /* DSPI_C Data Input Select */
+ vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select */
+ vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select */
+ vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select */
+ vuint32_t SINSELD:2; /* DSPI_D Data Input Select */
+ vuint32_t SSSELD:2; /* DSPI_D Slave Select Input Select */
+ vuint32_t SCKSELD:2; /* DSPI_D Clock Input Select */
+ vuint32_t TRIGSELD:2; /* DSPI_D Trigger Input Select */
+ } B;
+ } DISR; /* DSPI Input Select Register (DISR) @baseaddress + 0x908 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2; /* */
+ vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection */
+ vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection */
+ vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection */
+ vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection */
+ vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection */
+ vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection */
+ } B;
+ } ISEL3; /* MUX Select Register 3 (ISEL3) @baseaddress + 0x90C */
+
+ int32_t SIU_Reserved_0910[4]; /* 0x0910 - 0x091F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t ESEL5:1;
+ vuint32_t:3;
+ vuint32_t ESEL4:1;
+ vuint32_t:3;
+ vuint32_t ESEL3:1;
+ vuint32_t:3;
+ vuint32_t ESEL2:1;
+ vuint32_t:3;
+ vuint32_t ESEL1:1;
+ vuint32_t:3;
+ vuint32_t ESEL0:1;
+ } B;
+ } ISEL8; /* MUX Select Register 8 (ISEL8) @baseaddress + 0x920 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t ETSEL0A:5;
+ } B;
+ } ISEL9; /* MUX Select Register 9(ISEL9) @baseaddress + 0x924 */
+
+ int32_t SIU_Reserved_0928[22]; /* 0x0928 - 0x097F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MATCH:1; /* Compare Register Match */
+ vuint32_t DISNEX:1; /* Disable Nexus */
+ vuint32_t:14;
+ vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable */
+ vuint32_t:1;
+ } B;
+ } CCR; /* Chip Configuration Register (CCR) @baseaddress + 0x980 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t ENGDIV:6;
+ vuint32_t ENGSSE:1;
+ vuint32_t:3;
+ vuint32_t EBTS:1;
+ vuint32_t:1;
+ vuint32_t EBDF:2;
+ } B;
+ } ECCR; /* External Clock Control Register (ECCR) @baseaddress + 0x984 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMPAH:32;
+ } B;
+ } CARH; /* Compare A High Register (CARH) @baseaddress + 0x988 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMPAL:32;
+ } B;
+ } CARL; /* Compare A Low Register (CARL) @baseaddress + 0x98C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMPBH:32;
+ } B;
+ } CBRH; /* Compare B High Register (CBRH) @baseaddress + 0x990 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMPBL:32;
+ } B;
+ } CBRL; /* Compare B Low Register (CBRL) @baseaddress + 0x994 */
+
+ int32_t SIU_Reserved_0998[2]; /* 0x0998 - 0x099F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t CAN_SRC:1; /* CAN 2:1 Mode */
+ vuint32_t:11;
+ vuint32_t BYPASS:1; /* Bypass bit */
+ vuint32_t SYSCLKDIV:2; /* System Clock Divide */
+ vuint32_t:2;
+ } B;
+ } SYSDIV; /* System Clock Register (SYSDIV) @baseaddress + 0x9A0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */
+ vuint32_t:2; /* Reserved */
+ vuint32_t:1;
+ vuint32_t:1; /* Reserved */
+ vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */
+ vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */
+ vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */
+ vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */
+ vuint32_t:1; /* Reserved */
+ vuint32_t MIOSSTP:1; /* Stop mode request */
+ vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */
+ vuint32_t:1; /* Reserved */
+ vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */
+ vuint32_t:3; /* Reserved */
+ vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */
+ vuint32_t CNBSTP:1; /* FlexCAN B stop request. When asserted, a stop request is sent to the FlexCAN B */
+ vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */
+ vuint32_t SPIDSTP:1; /* DSPI D stop request. When asserted, a stop request is sent to the DSPI D. */
+ vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */
+ vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */
+ vuint32_t:6; /* Reserved */
+ vuint32_t SCICSTP:1; /* eSCI C stop request. When asserted, a stop request is sent to the eSCI C module. */
+ vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */
+ vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */
+ } B;
+ } HLT; /* Halt Register (HLT) @baseaddress + 0x9A4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:2; /* Reserved */
+ vuint32_t:1;
+ vuint32_t:1; /* Reserved */
+ vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:1; /* Reserved */
+ vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */
+ vuint32_t:1; /* Reserved */
+ vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:3; /* Reserved */
+ vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */
+ vuint32_t CNBACK:1; /* FlexCAN B stop acknowledge. When asserted, indicates that a stop acknowledge */
+ vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */
+ vuint32_t SPIDACK:1; /* DSPI D stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */
+ vuint32_t:6; /* Reserved */
+ vuint32_t SCICACK:1; /* eSCI C stop acknowledge */
+ vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */
+ vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */
+ } B;
+ } HLTACK; /* Halt Acknowledge Register (HLTACK) @baseaddress + 0x9A8 */
+
+ int32_t SIU_reserved09AC[2]; /* 0x09AC - 0x09B0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EXT_PID_EN:1; /* External PID Selection Enable */
+ vuint32_t EXT_PID_SYNC0:1; /* External PID Synchronization 0 */
+ vuint32_t:28; /* Reserved */
+ vuint32_t EXT_PID6:1; /* EXT_PID6 */
+ vuint32_t EXT_PID7:1; /* EXT_PID7 */
+ } B;
+ } EMPCR0; /* Core MMU PID Control Register (EMPCR0) @baseaddress + 0x9B4 */
+
+ int32_t SIU_reserved09B8[19]; /* 0x09B8 - 0x09B0 */
+
+ };
+
+/****************************************************************************/
+/* MODULE : FMPLL */
+/****************************************************************************/
+ struct FMPLL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t PREDIV:3;
+ vuint32_t MFD:5;
+ vuint32_t:1;
+ vuint32_t RFD:3;
+ vuint32_t LOCEN:1;
+ vuint32_t LOLRE:1;
+ vuint32_t LOCRE:1;
+ vuint32_t:1;
+ vuint32_t LOLIRQ:1;
+ vuint32_t LOCIRQ:1;
+ vuint32_t:13;
+ } B;
+ } SYNCR; /* Synthesizer Control Register (SYNCR) @baseaddress + 0x0000 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t LOLF:1;
+ vuint32_t LOC:1;
+ vuint32_t MODE:1;
+ vuint32_t PLLSEL:1;
+ vuint32_t PLLREF:1;
+ vuint32_t LOCKS:1;
+ vuint32_t LOCK:1;
+ vuint32_t LOCF:1;
+ vuint32_t:2;
+ } B;
+ } SYNSR; /* Synthesizer Status Register (SYNSR) @baseaddress + 0x0004 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t EMODE:1;
+ vuint32_t CLKCFG:3;
+ vuint32_t:8;
+ vuint32_t EPREDIV:4;
+ vuint32_t:9;
+ vuint32_t EMFD:7;
+ } B;
+ } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) @baseaddress + 0x0008 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t LOCEN:1;
+ vuint32_t LOLRE:1;
+ vuint32_t LOCRE:1;
+ vuint32_t LOLIRQ:1;
+ vuint32_t LOCIRQ:1;
+ vuint32_t:17;
+ vuint32_t ERFD:2;
+ } B;
+ } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) @baseaddress + 0x000C */
+
+ int32_t FMPLL_reserved0010[2]; /* 0x0010-0x0017 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BSY:1;
+ vuint32_t MODEN:1;
+ vuint32_t MODSEL:1;
+ vuint32_t MODPERIOD:13;
+ vuint32_t:1;
+ vuint32_t INCSTEP:15;
+ } B;
+ } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) @baseaddress + 0x0018 */
+ };
+
+
+/****************************************************************************/
+/* MODULE : ECSM */
+/****************************************************************************/
+ struct ECSM_tag {
+
+ union { /* Processor core type */
+ vuint16_t R;
+ } PCT;
+
+ union { /* Platform revision */
+ vuint16_t R;
+ } REV;
+
+ union { /* AXBS Master Configuration */
+ vuint16_t R;
+ } AMC;
+
+ union { /* AXBS Slave Configuration */
+ vuint16_t R;
+ } ASC;
+
+ union { /* IPS Module Configuration */
+ vuint32_t R;
+ } IMC;
+
+ uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */
+
+ union { /* Miscellaneous Reset Status Register */
+ vuint8_t R;
+ struct {
+ vuint8_t POR:1;
+ vuint8_t DIR:1;
+ vuint8_t SWTR:1;
+ vuint8_t:5;
+ } B;
+ } MRSR;
+
+ uint8_t ECSM_reserved0010[3]; /* 0x0010-0x0012 */
+
+ union { /* Miscellaneous Wakeup Control */
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1;
+ vuint8_t:3;
+ vuint8_t PRILVL:4;
+ } B;
+ } MWCR;
+
+ uint32_t ecsm_reserved0014[4]; /* 0x0014 - 0x0023 */
+
+ union { /* Miscellaneous User Defined Control */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t SWSC:1;
+ vuint32_t:30;
+ } B;
+ } MUDCR;
+
+ uint32_t ecsm_reserved0028[6]; /* 0x0028 - 0x003C*/
+
+ uint8_t ecsm_reserved0040[3]; /* 0x0040 - 0x0042*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t:2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR; /* ECC Configuration Register @baseaddress + 0x43 */
+
+ uint8_t ecsm_reserved0044[3]; /* 0x0044 - 0x0046*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t:2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR; /* ECC Status Register @baseaddress + 0x47 */
+
+ uint8_t ecsm_reserved0048[2]; /* 0x0048 - 0x0049*/
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t FRCAP:1;
+ vuint16_t:1;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t:2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t:1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR; /* ECC Error Generation Register @baseaddress + 0x4A */
+
+ uint32_t ecsm_reserved004C; /* 0x004C - 0x004F*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEAR:32;
+ } B;
+ } FEAR; /* Flash ECC Address Register @baseaddress + 0x50 */
+
+ uint16_t ecsm_reserved0054; /* 0x0054 - 0x0055*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR; /* Flash ECC Master Register @baseaddress + 0x56 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROT0:1;
+ vuint8_t PROT1:1;
+ vuint8_t PROT2:1;
+ vuint8_t PROT3:1;
+ } B;
+ } FEAT; /* Flash ECC Attributes Register @baseaddress + 0x57 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEDH:32;
+ } B;
+ } FEDRH; /* Flash ECC Data High Register @baseaddress + 0x58 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEDL:32;
+ } B;
+ } FEDRL; /* Flash ECC Data Low Register @baseaddress + 0x5C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REAR:32;
+ } B;
+ } REAR; /* RAM ECC Address @baseaddress + 0x60 */
+
+ uint8_t ecsm_reserved0064; /* 0x0064 - 0x0065*/
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t PRESR:8;
+ } B;
+ } PRESR; /* RAM ECC Syndrome @baseaddress + 0x65 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR; /* RAM ECC Master @baseaddress + 0x66 */
+
+ union {
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROT0:1;
+ vuint8_t PROT1:1;
+ vuint8_t PROT2:1;
+ vuint8_t PROT3:1;
+ } B;
+ } REAT; /* RAM ECC Attributes Register @baseaddress + 0x67 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REDH:32;
+ } B;
+ } REDRH; /* RAM ECC Data High Register @baseaddress + 0x68 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REDL:32;
+ } B;
+ } REDRL; /* RAMECC Data Low Register @baseaddress + 0x6C */
+
+ };
+
+/****************************************************************************/
+/* MODULE : System Timer Module (STM) */
+/****************************************************************************/
+ struct STM_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8;
+ vuint32_t:6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR; /* STM Control Register @baseaddress + 0x0000 */
+
+ union {
+ vuint32_t R;
+ } CNT; /* STM Count Register @baseaddress + 0x0004 */
+
+ uint32_t stm_reserved0008[2]; /* 0x0008 - 0x000F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR0; /* STM Channel Control Register @baseaddress + 0x0010 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR0; /* STM Channel Interrupt Register @baseaddress + 0x0014 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMP;
+ } B;
+ } CMP0; /* STM Channel Compare Register @baseaddress + 0x0018 */
+
+ uint32_t stm_reserved001C; /* 0x001C - 0x001F*/
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR1; /* STM Channel Control Register @baseaddress + 0x0020 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR1; /* STM Channel Interrupt Register @baseaddress + 0x0024 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMP;
+ } B;
+ } CMP1; /* STM Channel Compare Register @baseaddress + 0x0028 */
+
+ uint32_t stm_reserved002C; /* 0x002C - 0x002F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR2; /* STM Channel Control Register @baseaddress + 0x0030 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR2; /* STM Channel Interrupt Register @baseaddress + 0x0034 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMP;
+ } B;
+ } CMP2; /* STM Channel Compare Register @baseaddress + 0x0038 */
+
+ uint32_t stm_reserved003C; /* 0x003C - 0x003F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR3; /* STM Channel Control Register @baseaddress + 0x0040 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR3; /* STM Channel Interrupt Register @baseaddress + 0x0044 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CMP;
+ } B;
+ } CMP3; /* STM Channel Compare Register @baseaddress + 0x0048 */
+
+ uint32_t stm_reserved004C; /* 0x004C - 0x004F */
+ };
+
+
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+
+ struct SWT_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t:14;
+ vuint32_t KEY:1;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } MCR; /* Module Configuration Register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } IR; /* Interrupt register @baseaddress + 0x04 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO; /* Timeout register @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+
+ } B;
+ } WN; /* Window register @baseaddress + 0x0C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16;
+ } B;
+ } SR; /* Service register @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO; /* Counter output register @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SK:16;
+ } B;
+ } SK; /* Service key register @baseaddress + 0x18 */
+ };
+
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+ struct EMIOS_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DOZEEN:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t ETB:1;
+ vuint32_t GPREN:1;
+ vuint32_t:6;
+ vuint32_t SRV:4;
+ vuint32_t GPRE:8;
+ vuint32_t:8;
+ } B;
+ } MCR; /* Module Configuration Register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR; /* Global FLAG Register @baseaddress + 0x04 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR; /* Output Update Disable Register @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* */
+ vuint32_t CHDIS23:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS22:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS21:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS20:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS19:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS18:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS17:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS16:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS15:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS14:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS13:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS12:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS11:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS10:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS9:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS8:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS7:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS6:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS5:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS4:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS3:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS2:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS1:1; /* Enable Channel [n] bit */
+ vuint32_t CHDIS0:1; /* Enable Channel [n] bit */
+ } B;
+ } UCDIS; /* Disable Channel (EMIOSUCDIS) @baseaddress + 0x0C */
+
+ int32_t EMIOS_Reserved_0010[4]; /* 0x0010 - 0x001F */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t A;
+ }B;
+ } CADR; /* Channel A Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t B;
+ }B;
+ } CBDR; /* Channel B Data Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t C;
+ }B;
+ } CCNTR; /* Channel Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t ODIS:1;
+ vuint32_t ODISSL:2;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPREN:1;
+ vuint32_t DMA:1;
+ vuint32_t:1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t:3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t:1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR; /* Channel Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:15;
+ vuint32_t OVFL:1;
+ vuint32_t:12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR; /* Channel Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ALTA;
+ } B;
+ } ALTA; /* Alternate Channel A Data Register */
+
+ uint32_t emios_channel_reserved[2];
+
+ } CH[24];
+
+ };
+
+/****************************************************************************/
+/* MODULE : ETPU */
+/****************************************************************************/
+ struct ETPU_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t GEC:1; /* Global Exception Clear */
+ vuint32_t SDMERR:1; /* */
+ vuint32_t WDTOA:1; /* */
+ vuint32_t WDTOB:1; /* */
+ vuint32_t MGE1:1; /* */
+ vuint32_t MGE2:1; /* */
+ vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. */
+ vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. */
+ vuint32_t SCMERR:1; /* . */
+ vuint32_t:2; /* */
+ vuint32_t SCMSIZE:5; /* Shared Code Memory size */
+ vuint32_t:4; /* */
+ vuint32_t SCMMISC:1; /* SCM MISC Flag */
+ vuint32_t SCMMISF:1; /* SCM MISC Flag */
+ vuint32_t SCMMISEN:1; /* SCM MISC Enable */
+ vuint32_t:2; /* */
+ vuint32_t VIS:1; /* SCM Visability */
+ vuint32_t:5; /* */
+ vuint32_t GTBE:1; /* Global Time Base Enable */
+ } B;
+ } MCR; /* eTPU module configuration register@baseaddress + 0x00 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t STS:1; /* Start Status bit */
+ vuint32_t CTBASE:5; /* Channel Transfer Base */
+ vuint32_t PBASE:10; /* Parameter Buffer Base Address */
+ vuint32_t PWIDTH:1; /* Parameter Width */
+ vuint32_t PARAM0:7; /* Channel Parameter 0 */
+ vuint32_t WR:1; /* */
+ vuint32_t PARAM1:7; /* Channel Parameter 1 */
+ } B;
+ } CDCR; /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */
+
+ vuint32_t ETPU_reserved_0008; /* 0x0008 - 0x000B */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. */
+ } B;
+ } MISCCMPR; /* eTPU MISC Compare Register@baseaddress + 0x0c */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */
+ } B;
+ } SCMOFFDATAR; /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t FEND:1; /* Force END */
+ vuint32_t MDIS:1; /* Low power Stop */
+ vuint32_t:1; /* */
+ vuint32_t STF:1; /* Stop Flag */
+ vuint32_t:4; /* */
+ vuint32_t HLTF:1; /* Halt Mode Flag */
+ vuint32_t:3; /* */
+ vuint32_t FCSS:1;
+ vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
+ vuint32_t CDFC:2; /* */
+ vuint32_t:1; /* */
+ vuint32_t ERBA:5; /* */
+ vuint32_t SPPDIS:1; /* */
+ vuint32_t:2; /* */
+ vuint32_t ETB:5; /* Entry Table Base */
+ } B;
+ } ECR_A; /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */
+
+ vuint32_t ETPU_reserved_0018[2]; /* 0x0018 - 0x001B */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
+ vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
+ vuint32_t AM:2; /* Angle Mode */
+ vuint32_t:3; /* */
+ vuint32_t TCR2P:6; /* TCR2 Prescaler Control */
+ vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
+ vuint32_t TCR1CS:1; /* */
+ vuint32_t:5; /* */
+ vuint32_t TCR1P:8; /* TCR1 Prescaler Control */
+ } B;
+ } TBCR_A; /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */
+
+ /* offset 0x0024 */
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* */
+ vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */
+ } B;
+ } TB1R_A; /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */
+
+ /* offset 0x0028 */
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8; /* */
+ vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */
+ } B;
+ } TB2R_A; /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t REN1:1; /* Resource Enable TCR1 */
+ vuint32_t RSC1:1; /* Resource Control TCR1 */
+ vuint32_t:2; /* */
+ vuint32_t SERVER_ID1:4; /* */
+ vuint32_t:4; /* */
+ vuint32_t SRV1:4; /* Resource Server Slot */
+ vuint32_t REN2:1; /* Resource Enable TCR2 */
+ vuint32_t RSC2:1; /* Resource Control TCR2 */
+ vuint32_t:2; /* */
+ vuint32_t SERVER_ID2:4; /* */
+ vuint32_t:4; /* */
+ vuint32_t SRV2:4; /* Resource Server Slot */
+ } B;
+ } REDCR_A; /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */
+
+ vuint32_t ETPU_reserved_0030[12]; /* 0x0030 - 0x005F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WDM:2;
+ vuint32_t:14;
+ vuint32_t WDCNT:16;
+ } B;
+ } WDTR_A; /* ETPU1 WDTR Register @baseaddress + 0x60 */
+
+ vuint32_t ETPU1_reserved_0064; /* 0x0064 - 0x0067 */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t IDLE_CNT:31;
+ vuint32_t ICLR:1;
+ } B;
+ } IDLE_A; /* ETPU1 IDLE Register @baseaddress + 0x68 */
+
+ vuint32_t ETPU_reserved_006C[101]; /* 0x006C - 0x01FF */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIS31:1; /* Channel 31 Interrut Status */
+ vuint32_t CIS30:1; /* Channel 30 Interrut Status */
+ vuint32_t CIS29:1; /* Channel 29 Interrut Status */
+ vuint32_t CIS28:1; /* Channel 28 Interrut Status */
+ vuint32_t CIS27:1; /* Channel 27 Interrut Status */
+ vuint32_t CIS26:1; /* Channel 26 Interrut Status */
+ vuint32_t CIS25:1; /* Channel 25 Interrut Status */
+ vuint32_t CIS24:1; /* Channel 24 Interrut Status */
+ vuint32_t CIS23:1; /* Channel 23 Interrut Status */
+ vuint32_t CIS22:1; /* Channel 22 Interrut Status */
+ vuint32_t CIS21:1; /* Channel 21 Interrut Status */
+ vuint32_t CIS20:1; /* Channel 20 Interrut Status */
+ vuint32_t CIS19:1; /* Channel 19 Interrut Status */
+ vuint32_t CIS18:1; /* Channel 18 Interrut Status */
+ vuint32_t CIS17:1; /* Channel 17 Interrut Status */
+ vuint32_t CIS16:1; /* Channel 16 Interrut Status */
+ vuint32_t CIS15:1; /* Channel 15 Interrut Status */
+ vuint32_t CIS14:1; /* Channel 14 Interrut Status */
+ vuint32_t CIS13:1; /* Channel 13 Interrut Status */
+ vuint32_t CIS12:1; /* Channel 12 Interrut Status */
+ vuint32_t CIS11:1; /* Channel 11 Interrut Status */
+ vuint32_t CIS10:1; /* Channel 10 Interrut Status */
+ vuint32_t CIS9:1; /* Channel 9 Interrut Status */
+ vuint32_t CIS8:1; /* Channel 8 Interrut Status */
+ vuint32_t CIS7:1; /* Channel 7 Interrut Status */
+ vuint32_t CIS6:1; /* Channel 6 Interrut Status */
+ vuint32_t CIS5:1; /* Channel 5 Interrut Status */
+ vuint32_t CIS4:1; /* Channel 4 Interrut Status */
+ vuint32_t CIS3:1; /* Channel 3 Interrut Status */
+ vuint32_t CIS2:1; /* Channel 2 Interrut Status */
+ vuint32_t CIS1:1; /* Channel 1 Interrut Status */
+ vuint32_t CIS0:1; /* Channel 0 Interrut Status */
+ } B;
+ } CISR_A; /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */
+
+ int32_t ETPU_reserved_0204[3]; /* 0x0204 - 0x20F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
+ vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
+ vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
+ vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
+ vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
+ vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
+ vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
+ vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
+ vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
+ vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
+ vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
+ vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
+ vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
+ vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
+ vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
+ vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
+ vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
+ vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
+ vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
+ vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
+ vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
+ vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
+ vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
+ vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
+ vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
+ vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
+ vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
+ vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
+ vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
+ vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
+ vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
+ vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
+ } B;
+ } CDTRSR_A; /* eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR) @baseaddress + 0x210 */
+
+ int32_t ETPU_reserved_0214[3]; /* 0x0214 - 0x021F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
+ vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
+ vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
+ vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
+ vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
+ vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
+ vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
+ vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
+ vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
+ vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
+ vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
+ vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
+ vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
+ vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
+ vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
+ vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
+ vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
+ vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
+ vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
+ vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
+ vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
+ vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
+ vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
+ vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
+ vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
+ vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
+ vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
+ vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
+ vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
+ vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
+ vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
+ vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
+ } B;
+ } CIOSR_A; /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */
+
+ int32_t ETPU_reserved_0224[3]; /* 0x0224 - 0x022F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
+ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
+ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
+ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
+ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
+ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
+ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
+ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
+ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
+ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
+ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
+ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
+ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
+ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
+ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
+ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
+ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
+ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
+ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
+ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
+ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
+ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
+ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
+ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
+ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
+ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
+ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
+ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
+ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
+ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
+ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
+ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
+ } B;
+ } CDTROSR_A; /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */
+
+ int32_t ETPU_reserved_0234[3]; /* 0x0234 - 0x023F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIE31:1; /* Channel 31 Interruput Enable */
+ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */
+ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */
+ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */
+ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */
+ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */
+ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */
+ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */
+ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */
+ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */
+ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */
+ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */
+ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */
+ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */
+ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */
+ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */
+ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */
+ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */
+ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */
+ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */
+ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */
+ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */
+ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */
+ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */
+ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */
+ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */
+ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */
+ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */
+ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */
+ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */
+ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */
+ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */
+ } B;
+ } CIER_A; /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */
+
+ int32_t ETPU_reserved_0244[3]; /* 0x0244 - 0x25F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } CDTRER_A; /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */
+
+ int32_t ETPU_reserved_0254[3]; /* 0x0254 - 0x025F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } WDSR_A; /* ETPUWDSR - eTPU Watchdog Status Register @baseaddress + 0x260 */
+
+ int32_t ETPU_reserved_0264[7]; /* 0x0264 - 0x027F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } CPSSR_A; /* ETPUCPSSR - eTPU Channel Pending Service Status Register @baseaddress + 0x280 */
+
+ int32_t ETPU_reserved_0x0284[3]; /* 0x0284 - 0x028F */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */
+ vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */
+ vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */
+ vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */
+ vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */
+ vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */
+ vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */
+ vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */
+ vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */
+ vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */
+ vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */
+ vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */
+ vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */
+ vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */
+ vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */
+ vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */
+ vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */
+ vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */
+ vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */
+ vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */
+ vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */
+ vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */
+ vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */
+ vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */
+ vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */
+ vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */
+ vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */
+ vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */
+ vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */
+ vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */
+ vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */
+ vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */
+ } B;
+ } CSSR_A; /* ETPUCSSR - eTPU Channel Service Status Register @baseaddress + 0x290 */
+
+ int32_t ETPU_reserved_0294[91]; /* 0x0294 - 0x03FF */
+
+
+/***************************** Channels ********************************/
+/* Note not all devices implement all channels or even 2 engines */
+/* Each eTPU engine can implement 64 channels, however most devcies */
+/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */
+/* engines per instantiation */
+/***********************************************************************/
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIE:1; /* Channel Interruput Enable */
+ vuint32_t DTRE:1; /* Data Transfer Request Enable */
+ vuint32_t CPR:2; /* Channel Priority */
+ vuint32_t:2; /* */
+ vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */
+ vuint32_t ETCS:1; /* Entry Table Condition Select */
+ vuint32_t:3; /* */
+ vuint32_t CFS:5; /* Channel Function Select */
+ vuint32_t ODIS:1; /* Output disable */
+ vuint32_t OPOL:1; /* output polarity */
+ vuint32_t:3; /* */
+ vuint32_t CPBA:11; /* Channel Parameter Base Address */
+ } B;
+ } CR; /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CIS:1; /* Channel Interruput Status */
+ vuint32_t CIOS:1; /* Channel Interruput Overflow Status */
+ vuint32_t:6; /* */
+ vuint32_t DTRS:1; /* Data Transfer Status */
+ vuint32_t DTROS:1; /* Data Transfer Overflow Status */
+ vuint32_t:6; /* */
+ vuint32_t IPS:1; /* Input Pin State */
+ vuint32_t OPS:1; /* Output Pin State */
+ vuint32_t OBE:1; /* Output Pin State */
+ vuint32_t:11; /* */
+ vuint32_t FM1:1; /* Function mode */
+ vuint32_t FM0:1; /* Function mode */
+ } B;
+ } SCR; /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29; /* Host Service Request */
+ vuint32_t HSR:3; /* */
+ } B;
+ } HSRR; /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */
+
+ int32_t ETPU_reserved_0C; /* CHAN Base + 0x0C */
+
+ } CHAN[127];
+ /**** Note: Not all channels implemented on all devices. *******/
+ };
+
+/****************************************************************************/
+/* MODULE : EQADC */
+/****************************************************************************/
+ struct EQADC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t ICEA0:1;
+ vuint32_t ICEA1:1;
+ vuint32_t:1;
+ vuint32_t ESSIE:2;
+ vuint32_t:1;
+ vuint32_t DBG:2;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ int32_t EQADC_reserved0004; /* 0x0004 - 0x0007 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t NMF:26;
+ } B;
+ } NMSFR; /* Null Message Send Format Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DFL:4;
+ } B;
+ } ETDFR; /* External Trigger Digital Filter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFPUSH:32;
+ } B;
+ } CFPR[6]; /* CFIFO Push Registers */
+
+ uint32_t eqadc_reserved1;
+
+ uint32_t eqadc_reserved2;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RFPOP:16;
+ } B;
+ } RFPR[6]; /* Result FIFO Pop Registers*/
+
+ uint32_t eqadc_reserved3;
+
+ uint32_t eqadc_reserved4;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t CFEE0:1;
+ vuint16_t STRME0:1;
+ vuint16_t SSE:1;
+ vuint16_t CFINV:1;
+ vuint16_t:1;
+ vuint16_t MODE:4;
+ vuint16_t AMODE0:4; /* CFIFO0 only */
+ } B;
+ } CFCR[6]; /* CFIFO Control Registers */
+
+ uint32_t eqadc_reserved5;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t NCIE:1;
+ vuint16_t TORIE:1;
+ vuint16_t PIE:1;
+ vuint16_t EOQIE:1;
+ vuint16_t CFUIE:1;
+ vuint16_t:1;
+ vuint16_t CFFE:1;
+ vuint16_t CFFS:1;
+ vuint16_t:4;
+ vuint16_t RFOIE:1;
+ vuint16_t:1;
+ vuint16_t RFDE:1;
+ vuint16_t RFDS:1;
+ } B;
+ } IDCR[6]; /* Interrupt and DMA Control Registers */
+
+ uint32_t eqadc_reserved6;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t NCF:1;
+ vuint32_t TORF:1;
+ vuint32_t PF:1;
+ vuint32_t EOQF:1;
+ vuint32_t CFUF:1;
+ vuint32_t SSS:1;
+ vuint32_t CFFF:1;
+ vuint32_t:5;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t CFCTR:4;
+ vuint32_t TNXTPTR:4;
+ vuint32_t RFCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } FISR[6]; /* FIFO and Interrupt Status Registers */
+
+ uint32_t eqadc_reserved7;
+
+ uint32_t eqadc_reserved8;
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t TCCF:11;
+ } B;
+ } CFTCR[6]; /* CFIFO Transfer Counter Registers */
+
+ uint32_t eqadc_reserved9;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2;
+ vuint32_t CFS1:2;
+ vuint32_t CFS2:2;
+ vuint32_t CFS3:2;
+ vuint32_t CFS4:2;
+ vuint32_t CFS5:2;
+ vuint32_t:5;
+ vuint32_t LCFTCB0:4;
+ vuint32_t TC_LCFTCB0:11;
+ } B;
+ } CFSSR0; /* CFIFO Status Register 0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2;
+ vuint32_t CFS1:2;
+ vuint32_t CFS2:2;
+ vuint32_t CFS3:2;
+ vuint32_t CFS4:2;
+ vuint32_t CFS5:2;
+ vuint32_t:5;
+ vuint32_t LCFTCB1:4;
+ vuint32_t TC_LCFTCB1:11;
+ } B;
+ } CFSSR1; /* CFIFO Status Register 1 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2;
+ vuint32_t CFS1:2;
+ vuint32_t CFS2:2;
+ vuint32_t CFS3:2;
+ vuint32_t CFS4:2;
+ vuint32_t CFS5:2;
+ vuint32_t:4;
+ vuint32_t ECBNI:1;
+ vuint32_t LCFTSSI:4;
+ vuint32_t TC_LCFTSSI:11;
+ } B;
+ } CFSSR2; /* CFIFO Status Register 2 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CFS0:2;
+ vuint32_t CFS1:2;
+ vuint32_t CFS2:2;
+ vuint32_t CFS3:2;
+ vuint32_t CFS4:2;
+ vuint32_t CFS5:2;
+ vuint32_t:20;
+ } B;
+ } CFSR;
+
+ uint32_t eqadc_reserved11;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:21;
+ vuint32_t MDT:3;
+ vuint32_t:4;
+ vuint32_t BR:4;
+ } B;
+ } SSICR; /* SSI Control Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t RDV:1;
+ vuint32_t:5;
+ vuint32_t RDATA:26;
+ } B;
+ } SSIRDR; /* SSI Recieve Data Register @ baseaddress + 0xB8 */
+
+ uint32_t eqadc_reserved11b[5];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t REDBS2:4;
+ vuint32_t SRV2:4;
+ vuint32_t REDBS1:4;
+ vuint32_t SRV1:4;
+ } B;
+ } REDLCCR; /* STAC Bus Clent Configuration Register @ baseaddress + 0xD0 */
+
+
+ uint32_t eqadc_reserved12[11];
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } R[4];
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } EDATA[4];
+
+ uint32_t eqadc_reserved13[8];
+
+ } CF[6];
+
+ uint32_t eqadc_reserved14[32];
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:32;
+ } B;
+ } R[4];
+
+ uint32_t eqadc_reserved15[12];
+
+ } RF[6];
+
+ };
+
+/****************************************************************************/
+/* MODULE : Decimation Filter (DECFIL) */
+/****************************************************************************/
+ struct DECFIL_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FREN:1;
+ vuint32_t:1;
+ vuint32_t FRZ:1;
+ vuint32_t SRES:1;
+ vuint32_t CASCD:2;
+ vuint32_t IDEN:1;
+ vuint32_t ODEN:1;
+ vuint32_t ERREN:1;
+ vuint32_t:1;
+ vuint32_t FTYPE:2;
+ vuint32_t:1;
+ vuint32_t SCAL:2;
+ vuint32_t IDIS:1;
+ vuint32_t SAT:1;
+ vuint32_t ISEL:1;
+ vuint32_t MIXM:1;
+ vuint32_t DEC_RATE:4;
+ vuint32_t SDIE:1;
+ vuint32_t DSEL:1;
+ vuint32_t IBIE:1;
+ vuint32_t OBIE:1;
+ vuint32_t EDME:1;
+ vuint32_t TORE:1;
+ vuint32_t TMODE:2;
+ } B;
+ } MCR; /* Configuration Register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BSY:1;
+ vuint32_t:1;
+ vuint32_t DEC_COUNTER:4;
+ vuint32_t IDFC:1;
+ vuint32_t ODFC:1;
+ vuint32_t:1;
+ vuint32_t IBIC:1;
+ vuint32_t OBIC:1;
+ vuint32_t:1;
+ vuint32_t DIVRC:1;
+ vuint32_t OVFC:1;
+ vuint32_t OVRC:1;
+ vuint32_t IVRC:1;
+ vuint32_t:6;
+ vuint32_t IDF:1;
+ vuint32_t ODF:1;
+ vuint32_t:1;
+ vuint32_t IBIF:1;
+ vuint32_t OBIF:1;
+ vuint32_t:1;
+ vuint32_t DIVR:1;
+ vuint32_t OVF:1;
+ vuint32_t OVR:1;
+ vuint32_t IVR:1;
+ } B;
+ } MSR; /* Status Register @baseaddress + 0x04 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SDMAE:1;
+ vuint32_t SSIG:1;
+ vuint32_t SSAT:1;
+ vuint32_t SCSAT:1;
+ vuint32_t:10;
+ vuint32_t SRQ:1;
+ vuint32_t SZRO:1;
+ vuint32_t SISEL:1;
+ vuint32_t:1;
+ vuint32_t SZROSEL:2;
+ vuint32_t:2;
+ vuint32_t SHLTSEL:2;
+ vuint32_t:1;
+ vuint32_t SRQSEL:3;
+ vuint32_t:2;
+ vuint32_t SENSEL:2;
+ } B;
+ } MXCR; /* Extended Config Register @baseaddress + 0x8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t SDFC:1;
+ vuint32_t:2;
+ vuint32_t SSEC:1;
+ vuint32_t SCEC:1;
+ vuint32_t:1;
+ vuint32_t SSOVFC:1;
+ vuint32_t SCOVFC:1;
+ vuint32_t SVRC:1;
+ vuint32_t:7;
+ vuint32_t SDF:1;
+ vuint32_t:2;
+ vuint32_t SSE:1;
+ vuint32_t SCE:1;
+ vuint32_t:1;
+ vuint32_t SSOVF:1;
+ vuint32_t SCOVF:1;
+ vuint32_t SVR:1;
+ } B;
+ } MXSR; /* Extended Status Register @baseaddress + 0xC */
+
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t INTAG:4;
+ vuint32_t:6;
+ vuint32_t PREFILL:1;
+ vuint32_t FLUSH:1;
+ vuint32_t INPBUF:16;
+ } B;
+ } IB; /* Interface Input Buffer @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t OUTTAG:4;
+ vuint32_t OUTBUF:16;
+ } B;
+ } OB; /* Interface Output Buffer @baseaddress + 0x14 */
+
+ uint32_t decfil_reserved0018[2]; /* 0x0018 - 0x001F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t COEF:24;
+ } B;
+ } COEF[9]; /* Filter Coefficient Registers @baseaddress + 0x20 - 0x40 */
+
+ uint32_t decfil_reserved0044[13]; /* 0x0044 - 0x0077 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t TAP:24;
+ } B;
+ } TAP[8]; /* Filter TAP Registers @baseaddress + 0x78 - 0x94 */
+
+ uint32_t decfil_reserved00D0[14]; /* 0x00D0 - 0x00D3 */
+
+ /* 0x0D0 */
+ union {
+ vuint16_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SAMP_DATA:16;
+ } B;
+ } EDID; /* Filter EDID Registers @baseaddress + 0xD0 */
+
+ uint32_t decfil_reserved00D4[3]; /* 0x00D4 - 0x00DF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SUM_VALUE:1;
+ } B;
+ } FINTVAL; /* Final Integr. Value Register @baseaddress + 0xE0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t COUNT:1;
+ } B;
+ } FINTCNT; /* Final Integr. Count Register @baseaddress + 0xE0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SUM_VALUE:1;
+ } B;
+ } CINTVAL; /* Current Integr. Value Register @baseaddress + 0xE0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t COUNT:1;
+ } B;
+ } CINTCNT; /* Current Integr. Count Register @baseaddress + 0xE0 */
+
+ };
+
+/****************************************************************************/
+/* MODULE : CRC */
+/****************************************************************************/
+ struct CRC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t POLY:1;
+ vuint32_t SWAP:1;
+ vuint32_t INV:1;
+ } B;
+ } CFG; /* Configuration Register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct{
+ vuint32_t INP:32;
+ } B;
+ } INP; /* Input Register @baseaddress + 0x04 */
+
+ union {
+ vuint32_t R;
+ struct{
+ vuint32_t CSTAT:32;
+ } B;
+ } CSTAT; /* Current Status Register @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OUTP:32;
+ } B;
+ } OUTP; /* Output Register @baseaddress + 0x0C */
+ };
+
+/****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+ struct DSPI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t PCSIS7:1;
+ vuint32_t PCSIS6:1;
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t DOZE:1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t:6;
+ vuint32_t PES:1;
+ vuint32_t HALT:1;
+ } B;
+ } MCR; /* Module Configuration Register @baseaddress + 0x00 */
+
+ uint32_t dspi_reserved0004; /* 0x0004-0x008 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t:16;
+ } B;
+ } TCR; /* DSPI Transfer Count Register @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[8]; /* Clock and Transfer Attributes Registers @baseaddress + 0x0C - 0x28 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t:1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t:1;
+ vuint32_t TFFF:1;
+ vuint32_t:2;
+ vuint32_t DPEF:1;
+ vuint32_t SPEF:1;
+ vuint32_t DDIF:1;
+ vuint32_t RFOF:1;
+ vuint32_t:1;
+ vuint32_t RFDF:1;
+ vuint32_t:1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR; /* Status Register @baseaddress + 0x2C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t:2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t:1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t:1;
+ vuint32_t DPEFRE:1;
+ vuint32_t SPEFRE:1;
+ vuint32_t DDIFRE:1;
+ vuint32_t RFOFRE:1;
+ vuint32_t:1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t:16;
+ } B;
+ } RSER; /* DMA/Interrupt Request Select and Enable Register @baseaddress + 0x30 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t PE:1;
+ vuint32_t PP:1;
+ vuint32_t PCS7:1; /* new in MPC563xM */
+ vuint32_t PCS6:1; /* new in MPC563xM */
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR; /* PUSH TX FIFO Register @baseaddress + 0x34 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } POPR; /* POP RX FIFO Register @baseaddress + 0x38 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TXCMD:16;
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4]; /* Transmit FIFO Registers @baseaddress + 0x3c - 0x78 */
+
+ vuint32_t DSPI_reserved_004C[12]; /* 0x004C-0x0078 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16;
+ } B;
+ } RXFR[4]; /* Transmit FIFO Registers @baseaddress + 0x7c - 0xB8 */
+
+ vuint32_t DSPI_reserved_008C[12]; /* 0x008C-0x00B8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t FMSZ4:1;
+ vuint32_t MTOCNT:6;
+ vuint32_t:3;
+ vuint32_t TSBC:1;
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t:4;
+ vuint32_t DPCS7:1;
+ vuint32_t DPCS6:1;
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR; /* DSI Configuration Register @baseaddress + 0xBC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t SER_DATA:32;
+ } B;
+ } SDR; /* DSI Serialization Data Register @baseaddress + 0xC0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ASER_DATA:32;
+ } B;
+ } ASDR; /* DSI Alternate Serialization Data Register @baseaddress + 0xC4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t COMP_DATA:32;
+ } B;
+ } COMPR; /* DSI Transmit Comparison Register @baseaddress + 0xC8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t DESER_DATA:32;
+ } B;
+ } DDR; /* DSI deserialization Data Register @baseaddress + 0xCC */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t TSBCNT:5;
+ vuint32_t:16;
+ vuint32_t DPCS1_7:1;
+ vuint32_t DPCS1_6:1;
+ vuint32_t DPCS1_5:1;
+ vuint32_t DPCS1_4:1;
+ vuint32_t DPCS1_3:1;
+ vuint32_t DPCS1_2:1;
+ vuint32_t DPCS1_1:1;
+ vuint32_t DPCS1_0:1;
+ } B;
+ } DSICR1; /* DSI Configuration Register 1 @baseaddress + 0xD0 */
+
+ };
+
+/****************************************************************************/
+/* MODULE : eSCI */
+/****************************************************************************/
+ struct ESCI_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t SBR:13;
+ vuint32_t LOOPS:1;
+ vuint32_t:1;
+ vuint32_t RSRC:1;
+ vuint32_t M:1;
+ vuint32_t WAKE:1;
+ vuint32_t ILT:1;
+ vuint32_t PE:1;
+ vuint32_t PT:1;
+ vuint32_t TIE:1;
+ vuint32_t TCIE:1;
+ vuint32_t RIE:1;
+ vuint32_t ILIE:1;
+ vuint32_t TE:1;
+ vuint32_t RE:1;
+ vuint32_t RWU:1;
+ vuint32_t SBK:1;
+ } B;
+ } CR1; /* Control Register 1 @baseaddress + 0x00 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t MDIS:1;
+ vuint16_t FBR:1;
+ vuint16_t BSTP:1;
+ vuint16_t IEBERR:1;
+ vuint16_t RXDMA:1;
+ vuint16_t TXDMA:1;
+ vuint16_t BRK13:1;
+ vuint16_t TXDIR:1;
+ vuint16_t BESM13:1;
+ vuint16_t SBSTP:1;
+ vuint16_t RXPOL:1;
+ vuint16_t PMSK:1;
+ vuint16_t ORIE:1;
+ vuint16_t NFIE:1;
+ vuint16_t FEIE:1;
+ vuint16_t PFIE:1;
+ } B;
+ } CR2; /* Control Register 2 @baseaddress + 0x04 */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t R8:1;
+ vuint16_t T8:1;
+ vuint16_t ERR:1;
+ vuint16_t:1;
+ vuint16_t R:4;
+ vuint8_t D;
+ } B;
+ } DR; /* Data Register @baseaddress + 0x06 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TDRE:1;
+ vuint32_t TC:1;
+ vuint32_t RDRF:1;
+ vuint32_t IDLE:1;
+ vuint32_t OR:1;
+ vuint32_t NF:1;
+ vuint32_t FE:1;
+ vuint32_t PF:1;
+ vuint32_t:3;
+ vuint32_t BERR:1;
+ vuint32_t:2;
+ vuint32_t TACT:1;
+ vuint32_t RAF:1;
+ vuint32_t RXRDY:1;
+ vuint32_t TXRDY:1;
+ vuint32_t LWAKE:1;
+ vuint32_t STO:1;
+ vuint32_t PBERR:1;
+ vuint32_t CERR:1;
+ vuint32_t CKERR:1;
+ vuint32_t FRC:1;
+ vuint32_t:6;
+ vuint32_t UREQ:1;
+ vuint32_t OVFL:1;
+ } B;
+ } SR; /* Status Register @baseaddress + 0x08 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LRES:1;
+ vuint32_t WU:1;
+ vuint32_t WUD0:1;
+ vuint32_t WUD1:1;
+ vuint32_t LDBG:1;
+ vuint32_t DSF:1;
+ vuint32_t PRTY:1;
+ vuint32_t LIN:1;
+ vuint32_t RXIE:1;
+ vuint32_t TXIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t STIE:1;
+ vuint32_t PBIE:1;
+ vuint32_t CIE:1;
+ vuint32_t CKIE:1;
+ vuint32_t FCIE:1;
+ vuint32_t:6;
+ vuint32_t UQIE:1;
+ vuint32_t OFIE:1;
+ vuint32_t:8;
+ } B;
+ } LCR; /* LIN Control Register @baseaddress + 0x0C */
+
+ union {
+ vuint32_t R;
+ } LTR; /* LIN Transmit Register @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ } LRR; /* LIN Recieve Register @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t P:16;
+ vuint32_t:3;
+ vuint32_t SYNM:1;
+ vuint32_t EROE:1;
+ vuint32_t ERFE:1;
+ vuint32_t ERPE:1;
+ vuint32_t M2:1;
+ vuint32_t:8;
+ } B;
+ } LPR; /* LIN CRC Polynom Register @baseaddress + 0x18 */
+
+ };
+/****************************************************************************/
+/* MODULE : eSCI */
+/****************************************************************************/
+ struct ESCI_12_13_bit_tag {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t R8:1;
+ vuint16_t T8:1;
+ vuint16_t ERR:1;
+ vuint16_t:1;
+ vuint16_t D:12;
+ } B;
+ } DR; /* Data Register */
+ };
+
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+ struct FLEXCAN_BUF_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
+ } DATA;
+
+ }; /* end of FLEXCAN_BUF_t */
+
+ struct FLEXCAN_RXFIFO_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+ }; /* end of FLEXCAN_RXFIFO_t */
+
+ struct FLEXCAN2_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAK_MSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLF_WAK:1;
+
+ vuint32_t WRNEN:1;
+
+ vuint32_t MDISACK:1;
+ vuint32_t WAK_SRC:1;
+ vuint32_t DOZE:1;
+
+ vuint32_t SRXDIS:1;
+ vuint32_t MBFEN:1;
+ vuint32_t:2;
+
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B; /* Control Register @baseaddress + 0x04 */
+ } CR;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TIMER:16;
+ } B;
+ } TIMER; /* Free Running Timer @baseaddress + 0x08 */
+
+ int32_t FLEXCAN_reserved00;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t MI:29;
+ } B;
+ } RXGMASK; /* RX Global Mask @baseaddress + 0x0C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t MI:29;
+ } B;
+ } RX14MASK; /* RX 14 Mask @baseaddress + 0x10 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t MI:29;
+ } B;
+ } RX15MASK; /* RX 15 Mask @baseaddress + 0x14 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register @baseaddress + 0x18 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t:1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAK_INT:1;
+ } B;
+ } ESR; /* Error and Status Register @baseaddress + 0x1C */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B; /* Interruput Masks Register @baseaddress + 0x20 */
+ } IMRH;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B; /* Interruput Masks Register @baseaddress + 0x24 */
+ } IMRL;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B; /* Interruput Flag Register @baseaddress + 0x28 */
+ } IFRH;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B; /* Interruput Flag Register @baseaddress + 0x2C */
+ } IFRL;
+
+ uint32_t flexcan2_reserved2[19];
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B; /* RX Individual Mask Registers @baseaddress + 0x0880 */
+ } RXIMR[64];
+
+ }; /* end of FLEXCAN_tag */
+
+/****************************************************************************/
+/* MODULE : Periodic Interval Timer (PIT) */
+/****************************************************************************/
+ struct PIT_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t MDIS_RTI:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR; /* PIT Module Control Register @baseaddress + 0x00 */
+
+ uint32_t pit_reserved1[59];
+
+ struct {
+ union {
+ vuint32_t R;
+ } LDVAL; /* Timer Load Value Register @baseaddress + 0xF0 */
+
+ union {
+ vuint32_t R;
+ } CVAL; /* Current Timer Value Register @baseaddress + 0xF4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL; /* Timer Control Register @baseaddress + 0xF8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG; /* Timer Flag Register */
+ } RTI; /* RTI Channel @baseaddress + 0xFC */
+
+ struct {
+ union {
+ vuint32_t R;
+ } LDVAL; /* Timer Load Value Register @baseaddress + CH + 0x0 */
+
+ union {
+ vuint32_t R;
+ } CVAL; /* Current Timer Value Register @baseaddress + CH + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL; /* Timer Control Register @baseaddress + CH + 0x8 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG; /* Timer Flag Register @baseaddress + CH + 0xC */
+ } TIMER[4]; /* Timer Channels @baseaddress + 0x100 */
+
+ };
+
+/****************************************************************************/
+/* MODULE : FlexRay */
+/****************************************************************************/
+
+ typedef union uMVR {
+ vuint16_t R;
+ struct {
+ vuint16_t CHIVER:8; /* CHI Version Number */
+ vuint16_t PEVER:8; /* PE Version Number */
+ } B;
+ } MVR_t;
+
+ typedef union uMCR {
+ vuint16_t R;
+ struct {
+ vuint16_t MEN:1; /* module enable */
+ vuint16_t:1;
+ vuint16_t SCMD:1; /* single channel mode */
+ vuint16_t CHB:1; /* channel B enable */
+ vuint16_t CHA:1; /* channel A enable */
+ vuint16_t SFFE:1; /* synchronization frame filter enable */
+ vuint16_t:5;
+ vuint16_t CLKSEL:1; /* protocol engine clock source select */
+ vuint16_t PRESCALE:3; /* protocol engine clock prescaler */
+ vuint16_t:1;
+ } B;
+ } MCR_t;
+
+ typedef union uSTBSCR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t STBSSEL:7; /* strobe signal select */
+ vuint16_t:3;
+ vuint16_t ENB:1; /* strobe signal enable */
+ vuint16_t:2;
+ vuint16_t STBPSEL:2; /* strobe port select */
+ } B;
+ } STBSCR_t;
+ typedef union uSTBPCR {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t STB3EN:1; /* strobe port enable */
+ vuint16_t STB2EN:1; /* strobe port enable */
+ vuint16_t STB1EN:1; /* strobe port enable */
+ vuint16_t STB0EN:1; /* strobe port enable */
+ } B;
+ } STBPCR_t;
+
+ typedef union uMBDSR {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
+ vuint16_t:1;
+ vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
+ } B;
+ } MBDSR_t;
+ typedef union uMBSSUTR {
+ vuint16_t R;
+ struct {
+
+ vuint16_t:1;
+ vuint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
+ vuint16_t:1;
+ vuint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
+ } B;
+ } MBSSUTR_t;
+
+ typedef union uPOCR {
+ vuint16_t R;
+ vuint8_t byte[2];
+ struct {
+ vuint16_t WME:1; /* write mode external correction command */
+ vuint16_t:3;
+ vuint16_t EOC_AP:2; /* external offset correction application */
+ vuint16_t ERC_AP:2; /* external rate correction application */
+ vuint16_t BSY:1; /* command write busy / write mode command */
+ vuint16_t:3;
+ vuint16_t POCCMD:4; /* protocol command */
+ } B;
+ } POCR_t;
+/* protocol commands */
+ typedef union uGIFER {
+ vuint16_t R;
+ struct {
+ vuint16_t MIF:1; /* module interrupt flag */
+ vuint16_t PRIF:1; /* protocol interrupt flag */
+ vuint16_t CHIF:1; /* CHI interrupt flag */
+ vuint16_t WKUPIF:1; /* wakeup interrupt flag */
+ vuint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
+ vuint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
+ vuint16_t RBIF:1; /* receive message buffer interrupt flag */
+ vuint16_t TBIF:1; /* transmit buffer interrupt flag */
+ vuint16_t MIE:1; /* module interrupt enable */
+ vuint16_t PRIE:1; /* protocol interrupt enable */
+ vuint16_t CHIE:1; /* CHI interrupt enable */
+ vuint16_t WKUPIE:1; /* wakeup interrupt enable */
+ vuint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
+ vuint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
+ vuint16_t RBIE:1; /* receive message buffer interrupt enable */
+ vuint16_t TBIE:1; /* transmit buffer interrupt enable */
+ } B;
+ } GIFER_t;
+ typedef union uPIFR0 {
+ vuint16_t R;
+ struct {
+ vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */
+ vuint16_t INTLIF:1; /* internal protocol error interrupt flag */
+ vuint16_t ILCFIF:1; /* illegal protocol configuration flag */
+ vuint16_t CSAIF:1; /* cold start abort interrupt flag */
+ vuint16_t MRCIF:1; /* missing rate correctio interrupt flag */
+ vuint16_t MOCIF:1; /* missing offset correctio interrupt flag */
+ vuint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
+ vuint16_t MXSIF:1; /* max sync frames detected interrupt flag */
+ vuint16_t MTXIF:1; /* media access test symbol received flag */
+ vuint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
+ vuint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
+ vuint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
+ vuint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
+ vuint16_t TI2IF:1; /* timer 2 expired interrupt flag */
+ vuint16_t TI1IF:1; /* timer 1 expired interrupt flag */
+ vuint16_t CYSIF:1; /* cycle start interrupt flag */
+ } B;
+ } PIFR0_t;
+ typedef union uPIFR1 {
+ vuint16_t R;
+ struct {
+ vuint16_t EMCIF:1; /* error mode changed interrupt flag */
+ vuint16_t IPCIF:1; /* illegal protocol command interrupt flag */
+ vuint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
+ vuint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
+ vuint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
+ vuint16_t:2;
+ vuint16_t EVTIF:1; /* even cycle table written interrupt flag */
+ vuint16_t ODTIF:1; /* odd cycle table written interrupt flag */
+ vuint16_t:4;
+ } B;
+ } PIFR1_t;
+ typedef union uPIER0 {
+ vuint16_t R;
+ struct {
+ vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */
+ vuint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
+ vuint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
+ vuint16_t CSAIE:1; /* cold start abort interrupt enable */
+ vuint16_t MRCIE:1; /* missing rate correctio interrupt enable */
+ vuint16_t MOCIE:1; /* missing offset correctio interrupt enable */
+ vuint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
+ vuint16_t MXSIE:1; /* max sync frames detected interrupt enable */
+ vuint16_t MTXIE:1; /* media access test symbol received interrupt enable */
+ vuint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
+ vuint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
+ vuint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
+ vuint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
+ vuint16_t TI2IE:1; /* timer 2 expired interrupt enable */
+ vuint16_t TI1IE:1; /* timer 1 expired interrupt enable */
+ vuint16_t CYSIE:1; /* cycle start interrupt enable */
+ } B;
+ } PIER0_t;
+ typedef union uPIER1 {
+ vuint16_t R;
+ struct {
+ vuint16_t EMCIE:1; /* error mode changed interrupt enable */
+ vuint16_t IPCIE:1; /* illegal protocol command interrupt enable */
+ vuint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
+ vuint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
+ vuint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
+ vuint16_t:2;
+ vuint16_t EVTIE:1; /* even cycle table written interrupt enable */
+ vuint16_t ODTIE:1; /* odd cycle table written interrupt enable */
+ vuint16_t:4;
+ } B;
+ } PIER1_t;
+ typedef union uCHIERFR {
+ vuint16_t R;
+ struct {
+ vuint16_t FRLBEF:1; /* flame lost channel B error flag */
+ vuint16_t FRLAEF:1; /* frame lost channel A error flag */
+ vuint16_t PCMIEF:1; /* command ignored error flag */
+ vuint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
+ vuint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
+ vuint16_t MSBEF:1; /* message buffer search error flag */
+ vuint16_t MBUEF:1; /* message buffer utilization error flag */
+ vuint16_t LCKEF:1; /* lock error flag */
+ vuint16_t DBLEF:1; /* double transmit message buffer lock error flag */
+ vuint16_t SBCFEF:1; /* system bus communication failure error flag */
+ vuint16_t FIDEF:1; /* frame ID error flag */
+ vuint16_t DPLEF:1; /* dynamic payload length error flag */
+ vuint16_t SPLEF:1; /* static payload length error flag */
+ vuint16_t NMLEF:1; /* network management length error flag */
+ vuint16_t NMFEF:1; /* network management frame error flag */
+ vuint16_t ILSAEF:1; /* illegal access error flag */
+ } B;
+ } CHIERFR_t;
+ typedef union uMBIVEC {
+ vuint16_t R;
+ struct {
+
+ vuint16_t:1;
+ vuint16_t TBIVEC:7; /* transmit buffer interrupt vector */
+ vuint16_t:1;
+ vuint16_t RBIVEC:7; /* receive buffer interrupt vector */
+ } B;
+ } MBIVEC_t;
+
+ typedef union uPSR0 {
+ vuint16_t R;
+ struct {
+ vuint16_t ERRMODE:2; /* error mode */
+ vuint16_t SLOTMODE:2; /* slot mode */
+ vuint16_t:1;
+ vuint16_t PROTSTATE:3; /* protocol state */
+ vuint16_t SUBSTATE:4; /* protocol sub state */
+ vuint16_t:1;
+ vuint16_t WAKEUPSTATUS:3; /* wakeup status */
+ } B;
+ } PSR0_t;
+
+/* protocol states */
+/* protocol sub-states */
+/* wakeup status */
+ typedef union uPSR1 {
+ vuint16_t R;
+ struct {
+ vuint16_t CSAA:1; /* cold start attempt abort flag */
+ vuint16_t SCP:1; /* cold start path */
+ vuint16_t:1;
+ vuint16_t REMCSAT:5; /* remanining coldstart attempts */
+ vuint16_t CPN:1; /* cold start noise path */
+ vuint16_t HHR:1; /* host halt request pending */
+ vuint16_t FRZ:1; /* freeze occured */
+ vuint16_t APTAC:5; /* allow passive to active counter */
+ } B;
+ } PSR1_t;
+ typedef union uPSR2 {
+ vuint16_t R;
+ struct {
+ vuint16_t NBVB:1; /* NIT boundary violation on channel B */
+ vuint16_t NSEB:1; /* NIT syntax error on channel B */
+ vuint16_t STCB:1; /* symbol window transmit conflict on channel B */
+ vuint16_t SBVB:1; /* symbol window boundary violation on channel B */
+ vuint16_t SSEB:1; /* symbol window syntax error on channel B */
+ vuint16_t MTB:1; /* media access test symbol MTS received on channel B */
+ vuint16_t NBVA:1; /* NIT boundary violation on channel A */
+ vuint16_t NSEA:1; /* NIT syntax error on channel A */
+ vuint16_t STCA:1; /* symbol window transmit conflict on channel A */
+ vuint16_t SBVA:1; /* symbol window boundary violation on channel A */
+ vuint16_t SSEA:1; /* symbol window syntax error on channel A */
+ vuint16_t MTA:1; /* media access test symbol MTS received on channel A */
+ vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
+ } B;
+ } PSR2_t;
+ typedef union uPSR3 {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t WUB:1; /* wakeup symbol received on channel B */
+ vuint16_t ABVB:1; /* aggregated boundary violation on channel B */
+ vuint16_t AACB:1; /* aggregated additional communication on channel B */
+ vuint16_t ACEB:1; /* aggregated content error on channel B */
+ vuint16_t ASEB:1; /* aggregated syntax error on channel B */
+ vuint16_t AVFB:1; /* aggregated valid frame on channel B */
+ vuint16_t:2;
+ vuint16_t WUA:1; /* wakeup symbol received on channel A */
+ vuint16_t ABVA:1; /* aggregated boundary violation on channel A */
+ vuint16_t AACA:1; /* aggregated additional communication on channel A */
+ vuint16_t ACEA:1; /* aggregated content error on channel A */
+ vuint16_t ASEA:1; /* aggregated syntax error on channel A */
+ vuint16_t AVFA:1; /* aggregated valid frame on channel A */
+ } B;
+ } PSR3_t;
+ typedef union uCIFRR {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t MIFR:1; /* module interrupt flag */
+ vuint16_t PRIFR:1; /* protocol interrupt flag */
+ vuint16_t CHIFR:1; /* CHI interrupt flag */
+ vuint16_t WUPIFR:1; /* wakeup interrupt flag */
+ vuint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
+ vuint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
+ vuint16_t RBIFR:1; /* receive message buffer interrupt flag */
+ vuint16_t TBIFR:1; /* transmit buffer interrupt flag */
+ } B;
+ } CIFRR_t;
+ typedef union uSFCNTR {
+ vuint16_t R;
+ struct {
+ vuint16_t SFEVB:4; /* sync frames channel B, even cycle */
+ vuint16_t SFEVA:4; /* sync frames channel A, even cycle */
+ vuint16_t SFODB:4; /* sync frames channel B, odd cycle */
+ vuint16_t SFODA:4; /* sync frames channel A, odd cycle */
+ } B;
+ } SFCNTR_t;
+
+ typedef union uSFTCCSR {
+ vuint16_t R;
+ struct {
+ vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
+ vuint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
+ vuint16_t CYCNUM:6; /* cycle number */
+ vuint16_t ELKS:1; /* even cycle tables lock status */
+ vuint16_t OLKS:1; /* odd cycle tables lock status */
+ vuint16_t EVAL:1; /* even cycle tables valid */
+ vuint16_t OVAL:1; /* odd cycle tables valid */
+ vuint16_t:1;
+ vuint16_t OPT:1; /*one pair trigger */
+ vuint16_t SDVEN:1; /* sync frame deviation table enable */
+ vuint16_t SIDEN:1; /* sync frame ID table enable */
+ } B;
+ } SFTCCSR_t;
+ typedef union uSFIDRFR {
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t SYNFRID:10; /* sync frame rejection ID */
+ } B;
+ } SFIDRFR_t;
+
+ typedef union uTICCR {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t T2CFG:1; /* timer 2 configuration */
+ vuint16_t T2REP:1; /* timer 2 repetitive mode */
+ vuint16_t:1;
+ vuint16_t T2SP:1; /* timer 2 stop */
+ vuint16_t T2TR:1; /* timer 2 trigger */
+ vuint16_t T2ST:1; /* timer 2 state */
+ vuint16_t:3;
+ vuint16_t T1REP:1; /* timer 1 repetitive mode */
+ vuint16_t:1;
+ vuint16_t T1SP:1; /* timer 1 stop */
+ vuint16_t T1TR:1; /* timer 1 trigger */
+ vuint16_t T1ST:1; /* timer 1 state */
+
+ } B;
+ } TICCR_t;
+ typedef union uTI1CYSR {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
+ vuint16_t:2;
+ vuint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
+
+ } B;
+ } TI1CYSR_t;
+
+ typedef union uSSSR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* static slot number */
+ vuint16_t:1;
+ vuint16_t SLOTNUMBER:11; /* selector */
+ } B;
+ } SSSR_t;
+
+ typedef union uSSCCR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* selector */
+ vuint16_t:1;
+ vuint16_t CNTCFG:2; /* counter configuration */
+ vuint16_t MCY:1; /* multi cycle selection */
+ vuint16_t VFR:1; /* valid frame selection */
+ vuint16_t SYF:1; /* sync frame selection */
+ vuint16_t NUF:1; /* null frame selection */
+ vuint16_t SUF:1; /* startup frame selection */
+ vuint16_t STATUSMASK:4; /* slot status mask */
+ } B;
+ } SSCCR_t;
+ typedef union uSSR {
+ vuint16_t R;
+ struct {
+ vuint16_t VFB:1; /* valid frame on channel B */
+ vuint16_t SYB:1; /* valid sync frame on channel B */
+ vuint16_t NFB:1; /* valid null frame on channel B */
+ vuint16_t SUB:1; /* valid startup frame on channel B */
+ vuint16_t SEB:1; /* syntax error on channel B */
+ vuint16_t CEB:1; /* content error on channel B */
+ vuint16_t BVB:1; /* boundary violation on channel B */
+ vuint16_t TCB:1; /* tx conflict on channel B */
+ vuint16_t VFA:1; /* valid frame on channel A */
+ vuint16_t SYA:1; /* valid sync frame on channel A */
+ vuint16_t NFA:1; /* valid null frame on channel A */
+ vuint16_t SUA:1; /* valid startup frame on channel A */
+ vuint16_t SEA:1; /* syntax error on channel A */
+ vuint16_t CEA:1; /* content error on channel A */
+ vuint16_t BVA:1; /* boundary violation on channel A */
+ vuint16_t TCA:1; /* tx conflict on channel A */
+ } B;
+ } SSR_t;
+ typedef union uMTSCFR {
+ vuint16_t R;
+ struct {
+ vuint16_t MTE:1; /* media access test symbol transmission enable */
+ vuint16_t:1;
+ vuint16_t CYCCNTMSK:6; /* cycle counter mask */
+ vuint16_t:2;
+ vuint16_t CYCCNTVAL:6; /* cycle counter value */
+ } B;
+ } MTSCFR_t;
+ typedef union uRSBIR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* selector */
+ vuint16_t:4;
+ vuint16_t RSBIDX:8; /* receive shadow buffer index */
+ } B;
+ } RSBIR_t;
+ typedef union uRFDSR {
+ vuint16_t R;
+ struct {
+ vuint16_t FIFODEPTH:8; /* fifo depth */
+ vuint16_t:1;
+ vuint16_t ENTRYSIZE:7; /* entry size */
+ } B;
+ } RFDSR_t;
+
+ typedef union uRFRFCFR {
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* write mode */
+ vuint16_t IBD:1; /* interval boundary */
+ vuint16_t SEL:2; /* filter number */
+ vuint16_t:1;
+ vuint16_t SID:11; /* slot ID */
+ } B;
+ } RFRFCFR_t;
+
+ typedef union uRFRFCTR {
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t F3MD:1; /* filter mode */
+ vuint16_t F2MD:1; /* filter mode */
+ vuint16_t F1MD:1; /* filter mode */
+ vuint16_t F0MD:1; /* filter mode */
+ vuint16_t:4;
+ vuint16_t F3EN:1; /* filter enable */
+ vuint16_t F2EN:1; /* filter enable */
+ vuint16_t F1EN:1; /* filter enable */
+ vuint16_t F0EN:1; /* filter enable */
+ } B;
+ } RFRFCTR_t;
+ typedef union uPCR0 {
+ vuint16_t R;
+ struct {
+ vuint16_t ACTION_POINT_OFFSET:6;
+ vuint16_t STATIC_SLOT_LENGTH:10;
+ } B;
+ } PCR0_t;
+
+ typedef union uPCR1 {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
+ } B;
+ } PCR1_t;
+
+ typedef union uPCR2 {
+ vuint16_t R;
+ struct {
+ vuint16_t MINISLOT_AFTER_ACTION_POINT:6;
+ vuint16_t NUMBER_OF_STATIC_SLOTS:10;
+ } B;
+ } PCR2_t;
+
+ typedef union uPCR3 {
+ vuint16_t R;
+ struct {
+ vuint16_t WAKEUP_SYMBOL_RX_LOW:6;
+ vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;
+ vuint16_t COLDSTART_ATTEMPTS:5;
+ } B;
+ } PCR3_t;
+
+ typedef union uPCR4 {
+ vuint16_t R;
+ struct {
+ vuint16_t CAS_RX_LOW_MAX:7;
+ vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
+ } B;
+ } PCR4_t;
+
+ typedef union uPCR5 {
+ vuint16_t R;
+ struct {
+ vuint16_t TSS_TRANSMITTER:4;
+ vuint16_t WAKEUP_SYMBOL_TX_LOW:6;
+ vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;
+ } B;
+ } PCR5_t;
+
+ typedef union uPCR6 {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
+ vuint16_t MACRO_INITIAL_OFFSET_A:7;
+ } B;
+ } PCR6_t;
+
+ typedef union uPCR7 {
+ vuint16_t R;
+ struct {
+ vuint16_t DECODING_CORRECTION_B:9;
+ vuint16_t MICRO_PER_MACRO_NOM_HALF:7;
+ } B;
+ } PCR7_t;
+
+ typedef union uPCR8 {
+ vuint16_t R;
+ struct {
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
+ vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;
+ } B;
+ } PCR8_t;
+
+ typedef union uPCR9 {
+ vuint16_t R;
+ struct {
+ vuint16_t MINISLOT_EXISTS:1;
+ vuint16_t SYMBOL_WINDOW_EXISTS:1;
+ vuint16_t OFFSET_CORRECTION_OUT:14;
+ } B;
+ } PCR9_t;
+
+ typedef union uPCR10 {
+ vuint16_t R;
+ struct {
+ vuint16_t SINGLE_SLOT_ENABLED:1;
+ vuint16_t WAKEUP_CHANNEL:1;
+ vuint16_t MACRO_PER_CYCLE:14;
+ } B;
+ } PCR10_t;
+
+ typedef union uPCR11 {
+ vuint16_t R;
+ struct {
+ vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;
+ vuint16_t KEY_SLOT_USED_FOR_SYNC:1;
+ vuint16_t OFFSET_CORRECTION_START:14;
+ } B;
+ } PCR11_t;
+
+ typedef union uPCR12 {
+ vuint16_t R;
+ struct {
+ vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
+ vuint16_t KEY_SLOT_HEADER_CRC:11;
+ } B;
+ } PCR12_t;
+
+ typedef union uPCR13 {
+ vuint16_t R;
+ struct {
+ vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
+ vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
+ } B;
+ } PCR13_t;
+
+ typedef union uPCR14 {
+ vuint16_t R;
+ struct {
+ vuint16_t RATE_CORRECTION_OUT:11;
+ vuint16_t LISTEN_TIMEOUT_H:5;
+ } B;
+ } PCR14_t;
+
+ typedef union uPCR15 {
+ vuint16_t R;
+ struct {
+ vuint16_t LISTEN_TIMEOUT_L:16;
+ } B;
+ } PCR15_t;
+
+ typedef union uPCR16 {
+ vuint16_t R;
+ struct {
+ vuint16_t MACRO_INITIAL_OFFSET_B:7;
+ vuint16_t NOISE_LISTEN_TIMEOUT_H:9;
+ } B;
+ } PCR16_t;
+
+ typedef union uPCR17 {
+ vuint16_t R;
+ struct {
+ vuint16_t NOISE_LISTEN_TIMEOUT_L:16;
+ } B;
+ } PCR17_t;
+
+ typedef union uPCR18 {
+ vuint16_t R;
+ struct {
+ vuint16_t WAKEUP_PATTERN:6;
+ vuint16_t KEY_SLOT_ID:10;
+ } B;
+ } PCR18_t;
+
+ typedef union uPCR19 {
+ vuint16_t R;
+ struct {
+ vuint16_t DECODING_CORRECTION_A:9;
+ vuint16_t PAYLOAD_LENGTH_STATIC:7;
+ } B;
+ } PCR19_t;
+
+ typedef union uPCR20 {
+ vuint16_t R;
+ struct {
+ vuint16_t MICRO_INITIAL_OFFSET_B:8;
+ vuint16_t MICRO_INITIAL_OFFSET_A:8;
+ } B;
+ } PCR20_t;
+
+ typedef union uPCR21 {
+ vuint16_t R;
+ struct {
+ vuint16_t EXTERN_RATE_CORRECTION:3;
+ vuint16_t LATEST_TX:13;
+ } B;
+ } PCR21_t;
+
+ typedef union uPCR22 {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
+ vuint16_t MICRO_PER_CYCLE_H:4;
+ } B;
+ } PCR22_t;
+
+ typedef union uPCR23 {
+ vuint16_t R;
+ struct {
+ vuint16_t micro_per_cycle_l:16;
+ } B;
+ } PCR23_t;
+
+ typedef union uPCR24 {
+ vuint16_t R;
+ struct {
+ vuint16_t CLUSTER_DRIFT_DAMPING:5;
+ vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
+ vuint16_t MICRO_PER_CYCLE_MIN_H:4;
+ } B;
+ } PCR24_t;
+
+ typedef union uPCR25 {
+ vuint16_t R;
+ struct {
+ vuint16_t MICRO_PER_CYCLE_MIN_L:16;
+ } B;
+ } PCR25_t;
+
+ typedef union uPCR26 {
+ vuint16_t R;
+ struct {
+ vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
+ vuint16_t MICRO_PER_CYCLE_MAX_H:4;
+ } B;
+ } PCR26_t;
+
+ typedef union uPCR27 {
+ vuint16_t R;
+ struct {
+ vuint16_t MICRO_PER_CYCLE_MAX_L:16;
+ } B;
+ } PCR27_t;
+
+ typedef union uPCR28 {
+ vuint16_t R;
+ struct {
+ vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
+ vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
+ } B;
+ } PCR28_t;
+
+ typedef union uPCR29 {
+ vuint16_t R;
+ struct {
+ vuint16_t EXTERN_OFFSET_CORRECTION:3;
+ vuint16_t MINISLOTS_MAX:13;
+ } B;
+ } PCR29_t;
+
+ typedef union uPCR30 {
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t SYNC_NODE_MAX:4;
+ } B;
+ } PCR30_t;
+
+ typedef struct uMSG_BUFF_CCS {
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t MCM:1; /* message buffer commit mode */
+ vuint16_t MBT:1; /* message buffer type */
+ vuint16_t MTD:1; /* message buffer direction */
+ vuint16_t CMT:1; /* commit for transmission */
+ vuint16_t EDT:1; /* enable / disable trigger */
+ vuint16_t LCKT:1; /* lock request trigger */
+ vuint16_t MBIE:1; /* message buffer interrupt enable */
+ vuint16_t:3;
+ vuint16_t DUP:1; /* data updated */
+ vuint16_t DVAL:1; /* data valid */
+ vuint16_t EDS:1; /* lock status */
+ vuint16_t LCKS:1; /* enable / disable status */
+ vuint16_t MBIF:1; /* message buffer interrupt flag */
+ } B;
+ } MBCCSR;
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t MTM:1; /* message buffer transmission mode */
+ vuint16_t CHNLA:1; /* channel assignement */
+ vuint16_t CHNLB:1; /* channel assignement */
+ vuint16_t CCFE:1; /* cycle counter filter enable */
+ vuint16_t CCFMSK:6; /* cycle counter filter mask */
+ vuint16_t CCFVAL:6; /* cycle counter filter value */
+ } B;
+ } MBCCFR;
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FID:11; /* frame ID */
+ } B;
+ } MBFIDR;
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t MBIDX:8; /* message buffer index */
+ } B;
+ } MBIDXR;
+ } MSG_BUFF_CCS_t;
+ typedef union uSYSBADHR {
+ vuint16_t R;
+ } SYSBADHR_t;
+ typedef union uSYSBADLR {
+ vuint16_t R;
+ } SYSBADLR_t;
+ typedef union uPDAR {
+ vuint16_t R;
+ } PDAR_t;
+ typedef union uCASERCR {
+ vuint16_t R;
+ } CASERCR_t;
+ typedef union uCBSERCR {
+ vuint16_t R;
+ } CBSERCR_t;
+ typedef union uCYCTR {
+ vuint16_t R;
+ } CYCTR_t;
+ typedef union uMTCTR {
+ vuint16_t R;
+ } MTCTR_t;
+ typedef union uSLTCTAR {
+ vuint16_t R;
+ } SLTCTAR_t;
+ typedef union uSLTCTBR {
+ vuint16_t R;
+ } SLTCTBR_t;
+ typedef union uRTCORVR {
+ vuint16_t R;
+ } RTCORVR_t;
+ typedef union uOFCORVR {
+ vuint16_t R;
+ } OFCORVR_t;
+ typedef union uSFTOR {
+ vuint16_t R;
+ } SFTOR_t;
+ typedef union uSFIDAFVR {
+ vuint16_t R;
+ } SFIDAFVR_t;
+ typedef union uSFIDAFMR {
+ vuint16_t R;
+ } SFIDAFMR_t;
+ typedef union uNMVR {
+ vuint16_t R;
+ } NMVR_t;
+ typedef union uNMVLR {
+ vuint16_t R;
+ } NMVLR_t;
+ typedef union uT1MTOR {
+ vuint16_t R;
+ } T1MTOR_t;
+ typedef union uTI2CR0 {
+ vuint16_t R;
+ } TI2CR0_t;
+ typedef union uTI2CR1 {
+ vuint16_t R;
+ } TI2CR1_t;
+ typedef union uSSCR {
+ vuint16_t R;
+ } SSCR_t;
+ typedef union uRFSR {
+ vuint16_t R;
+ } RFSR_t;
+ typedef union uRFSIR {
+ vuint16_t R;
+ } RFSIR_t;
+ typedef union uRFARIR {
+ vuint16_t R;
+ } RFARIR_t;
+ typedef union uRFBRIR {
+ vuint16_t R;
+ } RFBRIR_t;
+ typedef union uRFMIDAFVR {
+ vuint16_t R;
+ } RFMIDAFVR_t;
+ typedef union uRFMIAFMR {
+ vuint16_t R;
+ } RFMIAFMR_t;
+ typedef union uRFFIDRFVR {
+ vuint16_t R;
+ } RFFIDRFVR_t;
+ typedef union uRFFIDRFMR {
+ vuint16_t R;
+ } RFFIDRFMR_t;
+ typedef union uLDTXSLAR {
+ vuint16_t R;
+ } LDTXSLAR_t;
+ typedef union uLDTXSLBR {
+ vuint16_t R;
+ } LDTXSLBR_t;
+
+ typedef struct FR_tag {
+ volatile MVR_t MVR; /*module version register *//*0 */
+ volatile MCR_t MCR; /*module configuration register *//*2 */
+ volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
+ volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
+ volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
+ volatile STBPCR_t STBPCR; /*strobe port control register *//*A */
+ volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
+ volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
+ vuint16_t reserved3a[1]; /*10 */
+ volatile PDAR_t PDAR; /*PE data register *//*12 */
+ volatile POCR_t POCR; /*Protocol operation control register *//*14 */
+ volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
+ volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
+ volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
+ volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
+ volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
+ volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
+ volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
+ volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
+ volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
+ volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
+ volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
+ volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
+ volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
+ volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
+ volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
+ volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
+ volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
+ volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
+ volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
+ volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
+ vuint16_t reserved3[1]; /*3E */
+ volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
+ volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
+ volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
+ volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
+ volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
+ volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
+ volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
+ volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
+ volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
+ volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
+ volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
+ volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
+ volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
+ volatile SSSR_t SSSR; /*slot status selection register *//*64 */
+ volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
+ volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
+ volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
+ volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
+ volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
+ volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
+ volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
+ volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
+ volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
+ volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
+ volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
+ volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
+ volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
+ volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
+ volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
+ volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
+ volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
+ volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
+ volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
+ volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
+ volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
+ volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
+ volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
+ volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
+ volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
+ volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
+ volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
+ volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
+ volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
+ volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
+ volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
+ volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
+ volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
+ volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
+ volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
+ volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
+ volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
+ volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
+ volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
+ volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
+ volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
+ volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
+ volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
+ volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
+ volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
+ volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
+ volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
+ volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
+ volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
+ volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
+ vuint16_t reserved2[17];
+ volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
+ } FR_tag_t;
+
+ typedef union uF_HEADER /* frame header */
+ {
+ struct {
+ vuint16_t:5;
+ vuint16_t HDCRC:11; /* Header CRC */
+ vuint16_t:2;
+ vuint16_t CYCCNT:6; /* Cycle Count */
+ vuint16_t:1;
+ vuint16_t PLDLEN:7; /* Payload Length */
+ vuint16_t:1;
+ vuint16_t PPI:1; /* Payload Preamble Indicator */
+ vuint16_t NUF:1; /* Null Frame Indicator */
+ vuint16_t SYF:1; /* Sync Frame Indicator */
+ vuint16_t SUF:1; /* Startup Frame Indicator */
+ vuint16_t FID:11; /* Frame ID */
+ } B;
+ vuint16_t WORDS[3];
+ } F_HEADER_t;
+ typedef union uS_STSTUS /* slot status */
+ {
+ struct {
+ vuint16_t VFB:1; /* Valid Frame on channel B */
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */
+ vuint16_t SEB:1; /* Syntax Error on channel B */
+ vuint16_t CEB:1; /* Content Error on channel B */
+ vuint16_t BVB:1; /* Boundary Violation on channel B */
+ vuint16_t CH:1; /* Channel */
+ vuint16_t VFA:1; /* Valid Frame on channel A */
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */
+ vuint16_t SEA:1; /* Syntax Error on channel A */
+ vuint16_t CEA:1; /* Content Error on channel A */
+ vuint16_t BVA:1; /* Boundary Violation on channel A */
+ vuint16_t:1;
+ } RX;
+ struct {
+ vuint16_t VFB:1; /* Valid Frame on channel B */
+ vuint16_t SYB:1; /* Sync Frame Indicator channel B */
+ vuint16_t NFB:1; /* Null Frame Indicator channel B */
+ vuint16_t SUB:1; /* Startup Frame Indicator channel B */
+ vuint16_t SEB:1; /* Syntax Error on channel B */
+ vuint16_t CEB:1; /* Content Error on channel B */
+ vuint16_t BVB:1; /* Boundary Violation on channel B */
+ vuint16_t TCB:1; /* Tx Conflict on channel B */
+ vuint16_t VFA:1; /* Valid Frame on channel A */
+ vuint16_t SYA:1; /* Sync Frame Indicator channel A */
+ vuint16_t NFA:1; /* Null Frame Indicator channel A */
+ vuint16_t SUA:1; /* Startup Frame Indicator channel A */
+ vuint16_t SEA:1; /* Syntax Error on channel A */
+ vuint16_t CEA:1; /* Content Error on channel A */
+ vuint16_t BVA:1; /* Boundary Violation on channel A */
+ vuint16_t TCA:1; /* Tx Conflict on channel A */
+ } TX;
+ vuint16_t R;
+ } S_STATUS_t;
+
+ typedef struct uMB_HEADER /* message buffer header */
+ {
+ F_HEADER_t FRAME_HEADER;
+ vuint16_t DATA_OFFSET;
+ S_STATUS_t SLOT_STATUS;
+ } MB_HEADER_t;
+
+/****************************************************************************/
+/* MODULE : Power Management Controller (PMC) */
+/****************************************************************************/
+ struct PMC_tag {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LVRER:1;
+ vuint32_t LVREH:1;
+ vuint32_t LVRE50:1;
+ vuint32_t LVRE33:1;
+ vuint32_t LVREC:1;
+ vuint32_t:3;
+ vuint32_t LVIER:1;
+ vuint32_t LVIEH:1;
+ vuint32_t LVIE50:1;
+ vuint32_t LVIE33:1;
+ vuint32_t LVIC:1;
+ vuint32_t:2;
+ vuint32_t TLK:1;
+ vuint32_t:16;
+ } B;
+ } MCR; /* Module Configuration register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t LVDREGTRIM:4;
+ vuint32_t VDD33TRIM:4;
+ vuint32_t LVD33TRIM:4;
+ vuint32_t VDDCTRIM:4;
+ vuint32_t LVDCTRIM:4;
+ } B;
+ } TRIMR; /* Trimming register @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t LVFVSTBY:1;
+ vuint32_t BGRDY:1;
+ vuint32_t BGTS:1;
+ vuint32_t:5;
+ vuint32_t LVFCSTBY:1;
+ vuint32_t:1;
+ vuint32_t V33DIS:1;
+ vuint32_t LVFCR:1;
+ vuint32_t LVFCH:1;
+ vuint32_t LVFC50:1;
+ vuint32_t LVFC33:1;
+ vuint32_t LVFCC:1;
+ vuint32_t:3;
+ vuint32_t LVFR:1;
+ vuint32_t LVFH:1;
+ vuint32_t LVF50:1;
+ vuint32_t LVF33:1;
+ vuint32_t LVFC:1;
+ vuint32_t:3;
+
+ } B;
+ } SR; /* status register @baseaddress + 0x00 */
+ };
+
+/****************************************************************************/
+/* MODULE : MPU */
+/****************************************************************************/
+
+ struct MPU_tag {
+
+ union { /* Module Control/Error Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SPERR:8;
+ vuint32_t:4;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NRGD:4;
+ vuint32_t:7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR;
+
+ uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */
+
+ struct {
+ union { /* MPU Error Address Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR;
+
+ union { /* MPU Error Detail Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR;
+ } PORT[2];
+
+ uint32_t MPU_reserved0020[248]; /* 0x0020-0x03FF */
+
+ struct {
+ union { /* Region Descriptor n Word 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD0;
+
+ union { /* Region Descriptor n Word 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t:5;
+ } B;
+ } WORD1;
+
+ union { /* Region Descriptor n Word 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t:2;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2;
+
+ union { /* Region Descriptor n Word 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t:15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3;
+ } RGD[16];
+
+ uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */
+
+ union { /* Region Descriptor Alternate Access Control n */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t:2;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[16];
+
+ uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */
+
+ };
+
+/****************************************************************************/
+/* MODULE : TSENS (Temperature Sensor) */
+/****************************************************************************/
+
+ struct TSENS_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t TSCV2:16;
+ vuint32_t TSCV1:16;
+ } B;
+ } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TSCV3:16;
+ } B;
+ } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */
+
+ uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */
+
+ };
+
+/****************************************************************************/
+/* MODULE : DTS (Development Trigger Semaphor) */
+/****************************************************************************/
+ struct DTS_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t DTS_EN:1;
+ }B;
+ } ENABLE; /* DTS Output Enable Register @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct{
+ vuint32_t AD31:1;
+ vuint32_t AD30:1;
+ vuint32_t AD29:1;
+ vuint32_t AD28:1;
+ vuint32_t AD27:1;
+ vuint32_t AD26:1;
+ vuint32_t AD25:1;
+ vuint32_t AD24:1;
+ vuint32_t AD23:1;
+ vuint32_t AD22:1;
+ vuint32_t AD21:1;
+ vuint32_t AD20:1;
+ vuint32_t AD19:1;
+ vuint32_t AD18:1;
+ vuint32_t AD17:1;
+ vuint32_t AD16:1;
+ vuint32_t AD15:1;
+ vuint32_t AD14:1;
+ vuint32_t AD13:1;
+ vuint32_t AD12:1;
+ vuint32_t AD11:1;
+ vuint32_t AD10:1;
+ vuint32_t AD9:1;
+ vuint32_t AD8:1;
+ vuint32_t AD7:1;
+ vuint32_t AD6:1;
+ vuint32_t AD5:1;
+ vuint32_t AD4:1;
+ vuint32_t AD3:1;
+ vuint32_t AD2:1;
+ vuint32_t AD1:1;
+ vuint32_t AD0:1;
+ }B;
+ } STARTUP; /* DTS Startup Register @baseaddress + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t ST31:1;
+ vuint32_t ST30:1;
+ vuint32_t ST29:1;
+ vuint32_t ST28:1;
+ vuint32_t ST27:1;
+ vuint32_t ST26:1;
+ vuint32_t ST25:1;
+ vuint32_t ST24:1;
+ vuint32_t ST23:1;
+ vuint32_t ST22:1;
+ vuint32_t ST21:1;
+ vuint32_t ST20:1;
+ vuint32_t ST19:1;
+ vuint32_t ST18:1;
+ vuint32_t ST17:1;
+ vuint32_t ST16:1;
+ vuint32_t ST15:1;
+ vuint32_t ST14:1;
+ vuint32_t ST13:1;
+ vuint32_t ST12:1;
+ vuint32_t ST11:1;
+ vuint32_t ST10:1;
+ vuint32_t ST9:1;
+ vuint32_t ST8:1;
+ vuint32_t ST7:1;
+ vuint32_t ST6:1;
+ vuint32_t ST5:1;
+ vuint32_t ST4:1;
+ vuint32_t ST3:1;
+ vuint32_t ST2:1;
+ vuint32_t ST1:1;
+ vuint32_t ST0:1;
+ }B;
+ } SEMAPHORE; /* DTS Semaphore Register @baseaddress + 0x8 */
+
+ uint32_t DTS_reserved000C[16381]; /* 0x000C-0xFFFF */
+
+ };
+
+/****************************************************************************/
+/* MODULE : REACM (Reaction Module) */
+/****************************************************************************/
+ struct REACM_tag {
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVRC:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t:1;
+ vuint32_t FREN:1;
+ vuint32_t TPREN:1;
+ vuint32_t HPREN:1;
+ vuint32_t GIEN:1;
+ vuint32_t OVREN:1;
+ vuint32_t:23;
+ } B;
+ } MCR; /* REACM Module Configuration @baseaddress + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t HPRE:12;
+ vuint32_t:8;
+ vuint32_t TPRE:8;
+ } B;
+ } TCR; /* REACM Timer Configuration @baseaddress + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t WREN1:1;
+ vuint32_t WREN0:1;
+ vuint32_t:12;
+ vuint32_t THRADC1:4;
+ vuint32_t:4;
+ vuint32_t THRADC0:4;
+ } B;
+ } THRR; /* REACM Threshold Router @baseaddress + 0x8 */
+
+ uint32_t REACM_reserved000C[1]; /* 0x000C-0x000F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t ADC_TAG:4;
+ vuint32_t ADC_RESULT:16;
+ } B;
+ } SINR; /* REACM ADC Sensor Input Register @baseaddress + 0x10 */
+
+ uint32_t REACM_reserved0014[3]; /* 0x0014-0x0001F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t:26;
+ vuint32_t EF4:1;
+ vuint32_t EF3:1;
+ vuint32_t EF2:1;
+ vuint32_t EF1:1;
+ vuint32_t EF0:1;
+ } B;
+ } GEFR; /* REACM Global Error Flag @baseaddress + 0x20 */
+
+ uint32_t REACM_reserved0024[55]; /* 0x0024-0x00FF */
+
+ struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t CHEN:2;
+ vuint32_t SWMC:1;
+ vuint32_t MAXLEN:1;
+ vuint32_t OCDFEN:1;
+ vuint32_t SCDFEN:1;
+ vuint32_t TAEREN:1;
+ vuint32_t SQEREN:1;
+ vuint32_t RAEREN:1;
+ vuint32_t:1;
+ vuint32_t CHOFF:1;
+ vuint32_t:2;
+ vuint32_t DOFF:3;
+ vuint32_t:5;
+ vuint32_t BSB:3;
+ vuint32_t:2;
+ vuint32_t MODULATION_ADDR:6;
+ } B;
+ } CR; /* REACM Channel n Configuration @baseaddress + 0x100 + (n*0x10) + 0x0 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t MODACT:1;
+ vuint32_t MAXL:1;
+ vuint32_t OCDF:1;
+ vuint32_t SCDF:1;
+ vuint32_t TAER:1;
+ vuint32_t SQER:1;
+ vuint32_t RAER:1;
+ vuint32_t CHOUT:3;
+ vuint32_t:7;
+ vuint32_t MAXLC:1;
+ vuint32_t OCDFC:1;
+ vuint32_t SCDFC:1;
+ vuint32_t TAERC:1;
+ vuint32_t SQERC:1;
+ vuint32_t RAERC:1;
+ vuint32_t:1;
+ vuint32_t MODULATION_POINTER:6;
+ } B;
+ } SR; /* REACM Channel n Status @baseaddress + 0x100 + (n*0x10) + 0x4 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t ADCR:4;
+ vuint32_t:12;
+ vuint32_t CHIR:4;
+ } B;
+ } RR; /* REACM Channel n Router @baseaddress + 0x100 + (n*0x10) + 0x8 */
+
+ uint32_t REACM_reserved01xC; /* 0x01xC-0x01xF */
+
+ } CH[6];
+
+ uint32_t REACM_reserved0160[104]; /* 0x0160-0x02FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SHARED_TIMER:16;
+ } B;
+ } STBK[16]; /* REACM Shared Timer Bank @baseaddress + 0x300 */
+
+ uint32_t REACM_reserved0340[16]; /* 0x0340-0x037F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HOLD_OFF:12;
+ } B;
+ } HOTBK[16]; /* REACM Hold-off Timer Bank @baseaddress + 0x380 */
+
+ uint32_t REACM_reserved03C0[16]; /* 0x03C0-0x03FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t THRESHOLD_VALUE:16;
+ } B;
+ } THBK[32]; /* REACM Threshold Timer Bank @baseaddress + 0x400 */
+
+ uint32_t REACM_reserved0480[96]; /* 0x0480-0x05FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ADC_MAX_LIMIT:16;
+ } B;
+ } ADCMAX; /* REACM ADC Result Max Limit Check @baseaddress + 0x600 */
+
+ uint32_t REACM_reserved0604[31]; /* 0x0604-0x067F */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t RANGE_PWD:12;
+ } B;
+ } RANGEPWD; /* REACM Modulation Range Pulse Width @baseaddress + 0x680 */
+
+ uint32_t REACM_reserved0684[15]; /* 0x0684-0x06BF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t MIN_PWD:12;
+ } B;
+ } MINPWD; /* REACM Modulation Minimum Pulse Width @baseaddress + 0x6C0 */
+
+ uint32_t REACM_reserved06C4[15]; /* 0x06C4-0x06FF */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t LOOP:1;
+ vuint32_t IOSS:1;
+ vuint32_t:1;
+ vuint32_t MM:2;
+ vuint32_t:1;
+ vuint32_t SM:2;
+ vuint32_t:1;
+ vuint32_t HOD:3;
+ vuint32_t:1;
+ vuint32_t LOD:3;
+ vuint32_t:1;
+ vuint32_t THRESPT:6;
+ vuint32_t STPT:4;
+ vuint32_t:1;
+ vuint32_t HDOFFTPT:4;
+ } B;
+ } MWBK[64]; /* REACM Modulation Control Word Bank @baseaddress + 0x700 */
+
+ };
+
+
+
+
+/* Define memories */
+
+#define SRAM_START 0x40000000
+#define SRAM_SIZE 0x30000
+#define SRAM_END 0x4002FFFF
+
+#define FLASH_START 0x00000000
+#define FLASH_SIZE 0x400000
+#define FLASH_END 0x003FFFFF
+
+/* Define instances of modules */
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)
+#define EBI (*( volatile struct EBI_tag *) 0xC3F84000)
+#define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000)
+#define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000)
+#define SIU (*( volatile struct SIU_tag *) 0xC3F90000)
+#define DTS (*( volatile struct DTS_tag *) 0xC3F9C000)
+
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)
+#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)
+
+#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)
+#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
+#define ETPU_DATA_RAM_END 0xC3FC8BFC
+#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
+#define CODE_RAM (*( uint32_t *) 0xC3FD0000)
+#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
+
+#define REACM (*( volatile struct REACM_tag *) 0xC3FC7000)
+
+#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)
+
+#define CRC (*( volatile struct CRC_tag *) 0xFFE68000)
+
+#define PBRIDGE (*( volatile struct PBRIDGE_tag *) 0xFFF00000)
+#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)
+#define MPU (*( volatile struct MPU_tag *) 0xFFF10000)
+#define SWT (*( volatile struct SWT_tag *) 0xFFF38000)
+#define STM (*( volatile struct STM_tag *) 0xFFF3C000)
+#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)
+
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)
+
+#define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000)
+#define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF8C000)
+
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)
+#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)
+
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)
+#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000)
+
+#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)
+#define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000)
+#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)
+
+#define FR (*( volatile struct FR_tag *) 0xFFFE0000)
+#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000)
+
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ifdef _MPC5644_H */
+
+/*********************************************************************
+ *
+ * Copyright:
+ * Freescale Semiconductor, INC. & STMicroelectronics All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Freescale
+ * Semiconductor, Inc. This software is provided on an "AS IS"
+ * basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, Freescale
+ * Semiconductor & STMicroelectronics DISCLAIMS ALL WARRANTIES WHETHER
+ * EXPRESS OR IMPLIED,INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR
+ * FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL Freescale Semiconductor or STMicroelectronics BE LIABLE FOR ANY
+ * DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF
+ * BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION,
+ * OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Freescale Semiconductor & STMicroelectronics assumes no responsibility
+ * for the maintenance and support of this software
+ *
+ ********************************************************************/
diff --git a/os/hal/ports/SPC5/SPC56ECxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC56ECxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..5a339177f --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/cfg/mcuconf.h.ftl @@ -0,0 +1,369 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC56ECxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC56ECxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+#define SPC5_XOSCDIV_VALUE ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
+#define SPC5_IRCDIV_VALUE ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
+#define SPC5_Z0_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.z0_core_clock_divider.value[0]}
+#define SPC5_FEC_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.fec_clock_divider.value[0]}
+#define SPC5_FLASH_CLK_DIV_VALUE ${conf.instance.initialization_settings.clocks.flash_controller_clock_divider.value[0]}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+#define SPC5_EMIOS0_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
+#define SPC5_EMIOS1_GPRE_VALUE ${conf.instance.initialization_settings.clocks.emios1_global_prescaler.value[0]?number}
+
+/*
+* for the unexpected Reset on "Load from RAM" Issue,
+* This switch has to be activated.
+*/
+#define SPC56ECXX_FMPLL_CLOCK_ERRATA_WORKAROUND FALSE
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_GROUP1_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_1_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX2 ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX3 ${(conf.instance.linflex_settings.linflex3.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX4 ${(conf.instance.linflex_settings.linflex4.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX5 ${(conf.instance.linflex_settings.linflex5.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX6 ${(conf.instance.linflex_settings.linflex6.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX7 ${(conf.instance.linflex_settings.linflex7.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX8 ${(conf.instance.linflex_settings.linflex8.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX9 ${(conf.instance.linflex_settings.linflex9.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+#define SPC5_SERIAL_LINFLEX2_PRIORITY ${conf.instance.irq_priority_settings.linflex2.value[0]}
+#define SPC5_SERIAL_LINFLEX3_PRIORITY ${conf.instance.irq_priority_settings.linflex3.value[0]}
+#define SPC5_SERIAL_LINFLEX4_PRIORITY ${conf.instance.irq_priority_settings.linflex4.value[0]}
+#define SPC5_SERIAL_LINFLEX5_PRIORITY ${conf.instance.irq_priority_settings.linflex5.value[0]}
+#define SPC5_SERIAL_LINFLEX6_PRIORITY ${conf.instance.irq_priority_settings.linflex6.value[0]}
+#define SPC5_SERIAL_LINFLEX7_PRIORITY ${conf.instance.irq_priority_settings.linflex7.value[0]}
+#define SPC5_SERIAL_LINFLEX8_PRIORITY ${conf.instance.irq_priority_settings.linflex8.value[0]}
+#define SPC5_SERIAL_LINFLEX9_PRIORITY ${conf.instance.irq_priority_settings.linflex9.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI3 ${conf.instance.dspi_settings.dspi_3.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI4 ${conf.instance.dspi_settings.dspi_4.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI5 ${conf.instance.dspi_settings.dspi_5.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI6 ${conf.instance.dspi_settings.dspi_6.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI7 ${conf.instance.dspi_settings.dspi_7.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3 + s4})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI3_MCR (0${s0 + s1})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs1[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI4_MCR (0${s0 + s1})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_5___pcs2[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI5_MCR (0${s0 + s1 + s2})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_6___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI6_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_7___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI7_MCR (0${s0 + s1 + s2 + s3})
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
+#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx1.value[0]}
+#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx2.value[0]}
+#define SPC5_SPI_DSPI3_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi3_rx.value[0]}
+#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx1.value[0]}
+#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx2.value[0]}
+#define SPC5_SPI_DSPI4_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi4_rx.value[0]}
+#define SPC5_SPI_DSPI5_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx1.value[0]}
+#define SPC5_SPI_DSPI5_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_tx2.value[0]}
+#define SPC5_SPI_DSPI5_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi5_rx.value[0]}
+#define SPC5_SPI_DSPI6_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi6_tx1.value[0]}
+#define SPC5_SPI_DSPI6_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi6_tx2.value[0]}
+#define SPC5_SPI_DSPI6_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi6_rx.value[0]}
+#define SPC5_SPI_DSPI7_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi7_tx1.value[0]}
+#define SPC5_SPI_DSPI7_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi7_tx2.value[0]}
+#define SPC5_SPI_DSPI7_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi7_rx.value[0]}
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI5_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
+#define SPC5_SPI_DSPI6_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_6.value[0]}
+#define SPC5_SPI_DSPI7_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_7.value[0]}
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI3_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_3.value[0]}
+#define SPC5_SPI_DSPI4_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_4.value[0]}
+#define SPC5_SPI_DSPI5_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_5.value[0]}
+#define SPC5_SPI_DSPI6_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_6.value[0]}
+#define SPC5_SPI_DSPI7_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_7.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * ICU-PWM driver system settings.
+ */
+#define SPC5_ICU_USE_EMIOS0_CH0 ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH1 ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH2 ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH3 ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH4 ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH5 ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH6 ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH7 ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
+#define SPC5_ICU_USE_EMIOS0_CH24 ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS0_GROUP0 ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS0_GROUP1 ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
+
+#define SPC5_EMIOS0_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
+#define SPC5_EMIOS0_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
+#define SPC5_EMIOS0_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
+#define SPC5_EMIOS0_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
+#define SPC5_EMIOS0_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
+#define SPC5_EMIOS0_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
+#define SPC5_EMIOS0_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
+#define SPC5_EMIOS0_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
+#define SPC5_EMIOS0_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
+#define SPC5_EMIOS0_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
+#define SPC5_EMIOS0_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
+#define SPC5_EMIOS0_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
+#define SPC5_EMIOS0_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
+
+#define SPC5_EMIOS0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_ICU_USE_EMIOS1_CH24 ${conf.instance.emios_settings.emios1_ch24.value[0]?upper_case}
+
+#define SPC5_PWM_USE_EMIOS1_GROUP0 ${conf.instance.emios_settings.emios1_group0.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP1 ${conf.instance.emios_settings.emios1_group1.value[0]?upper_case}
+#define SPC5_PWM_USE_EMIOS1_GROUP2 ${conf.instance.emios_settings.emios1_group2.value[0]?upper_case}
+
+#define SPC5_EMIOS1_GFR_F0F1_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc0.value[0]}
+#define SPC5_EMIOS1_GFR_F2F3_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc1.value[0]}
+#define SPC5_EMIOS1_GFR_F4F5_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc2.value[0]}
+#define SPC5_EMIOS1_GFR_F6F7_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc3.value[0]}
+#define SPC5_EMIOS1_GFR_F8F9_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc4.value[0]}
+#define SPC5_EMIOS1_GFR_F10F11_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc5.value[0]}
+#define SPC5_EMIOS1_GFR_F12F13_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc6.value[0]}
+#define SPC5_EMIOS1_GFR_F14F15_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc7.value[0]}
+#define SPC5_EMIOS1_GFR_F16F17_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc8.value[0]}
+#define SPC5_EMIOS1_GFR_F18F19_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc9.value[0]}
+#define SPC5_EMIOS1_GFR_F20F21_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc10.value[0]}
+#define SPC5_EMIOS1_GFR_F22F23_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc11.value[0]}
+#define SPC5_EMIOS1_GFR_F24F25_PRIORITY ${conf.instance.irq_priority_settings.emios1_uc12.value[0]}
+
+#define SPC5_EMIOS1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_EMIOS1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
+#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN3 ${conf.instance.flexcan_settings.flexcan3.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan3_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN3_PRIORITY ${conf.instance.irq_priority_settings.flexcan3.value[0]}
+#define SPC5_CAN_FLEXCAN3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN4 ${conf.instance.flexcan_settings.flexcan4.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan4_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN4_PRIORITY ${conf.instance.irq_priority_settings.flexcan4.value[0]}
+#define SPC5_CAN_FLEXCAN4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN5 ${conf.instance.flexcan_settings.flexcan5.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan5_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN5_PRIORITY ${conf.instance.irq_priority_settings.flexcan5.value[0]}
+#define SPC5_CAN_FLEXCAN5_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN5_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+
+#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
+#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
+#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
+#define SPC5_ADC_ADC0_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
+#define SPC5_ADC_ADC0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
+#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
+#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
+#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
+#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC56ECxx/hal_lld.c b/os/hal/ports/SPC5/SPC56ECxx/hal_lld.c new file mode 100644 index 000000000..a179633b3 --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/hal_lld.c @@ -0,0 +1,291 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC560BCxx/hal_lld.c
+ * @brief SPC560B/Cxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include <string.h>
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+typedef void (*storefunc_t)(volatile uint32_t *p, uint32_t w);
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*
+ * Special function to be copied in RAM.
+ */
+static void do_word_store(volatile uint32_t *p, uint32_t w) {
+
+ *p = w;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t n;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Decrementer timer initialized for system tick use, note, it is
+ initialized here because in the OSAL layer the system clock frequency
+ is not yet known.*/
+ n = halSPCGetSystemClock() / OSAL_ST_FREQUENCY;
+ port_write_spr(22, n); /* Init. DEC register. */
+ port_write_spr(54, n); /* Init. DECAR register.*/
+ n = 0x0440; /* DIE ARE bits. */
+ port_write_spr(340, n); /* TCR register. */
+
+ /* TB counter enabled for debug and measurements.*/
+ n = 0x4000; /* TBEN bit. */
+ port_write_spr(1008, n); /* HID0 register. */
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC560B/Cxx clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+#if !SPC5_NO_INIT
+ uint32_t reg;
+ uint32_t store_word[8];
+#endif
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.S_FIRC)
+ ;
+
+#if !SPC5_NO_INIT
+ /* Copies the store function in RAM, this is required in order to perform
+ some flash-related operations.*/
+ memcpy(store_word, do_word_store, sizeof(store_word));
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* Oscillators dividers setup.*/
+ CGM.FIRC_CTL.B.RCDIV = SPC5_IRCDIV_VALUE - 1;
+ CGM.FXOSC_CTL.B.OSCDIV = SPC5_XOSCDIV_VALUE - 1;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.S_CURRENTMODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a xtal then the
+ bypass must be activated.*/
+ CGM.OSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
+ CGM.SC_DC1.R = SPC5_CGM_SC_DC1;
+ CGM.SC_DC2.R = SPC5_CGM_SC_DC2;
+ CGM.Z0_DCR.R = SPC5_CGM_Z0_DCR;
+ CGM.FEC_DCR.R = SPC5_CGM_FEC_DCR;
+ CGM.FLASH_DCR.R = SPC5_CGM_FLASH_DCR;
+
+ /* Selecting the external oscillator as source for the FMPLL, note that on
+ older silicons, the settings are exchanged, a macro switch is provided.*/
+#if SPC56ECXX_FMPLL_CLOCK_ERRATA_WORKAROUND == TRUE
+ CGM.AC0_SC.R = 0x01000000;
+#else
+ CGM.AC0_SC.R = 0x00000000; /* TODO: Add a setting. */
+#endif
+
+ /* Initialization of the FMPLLs settings.*/
+ CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL_MR.R = 0; /* TODO: Add a setting. */
+
+ /* Run modes initialization.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.TEST.R = SPC5_ME_TEST_MC_BITS; /* TEST run mode. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ ME.STANDBY.R = SPC5_ME_STANDBY0_MC_BITS; /* STANDBY0 run mode. */
+ if (ME.IS.B.I_ICONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings calculated for a maximum clock of 120MHz.*/
+ reg = (CFLASH_0.PFCR0.R & 0x073EFFFF) | 0x280A0000;
+ ((storefunc_t)store_word)(&CFLASH_0.PFCR0.R, reg);
+ reg = (CFLASH_0.PFCR1.R & 0x073EFFFF) | 0x681A0000;
+ ((storefunc_t)store_word)(&CFLASH_0.PFCR1.R, reg);
+
+ /* SRAM settings, 1 wait state.*/
+ ECSM.MUDCR.B.RAM_WS = 1;
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.S_SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_DIVIRC:
+ return SPC5_IRC_CLK / SPC5_IRCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK / SPC5_XOSCDIV_VALUE;
+ case SPC5_ME_GS_SYSCLK_DIVXOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ECxx/hal_lld.h b/os/hal/ports/SPC5/SPC56ECxx/hal_lld.h new file mode 100644 index 000000000..dd89ea12b --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/hal_lld.h @@ -0,0 +1,908 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/hal_lld.h
+ * @brief SPC56ECxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS TRUE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC56ECxx Gateway"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 40000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MAX 40000
+
+/**
+ * @brief Minimum SXOSC clock frequency.
+ */
+#define SPC5_SXOSC_CLK_MIN 32000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 64000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 120000000
+
+/**
+ * @brief Maximum e200z0 core clock frequency.
+ */
+#define SPC5_Z0_CLK_MAX 80000000
+
+/**
+ * @brief Maximum FLASH BIU clock frequency.
+ */
+#define SPC5_FLASH_CLK_MAX 80000000
+
+/**
+ * @brief Maximum FEC clock frequency.
+ */
+#define SPC5_FEC_CLK_MAX 80000000
+
+/**
+ * @brief Maximum peripherals set 1 clock frequency.
+ */
+#define SPC5_PERIPHERALS_1_CLK_MAX 32000000
+
+/**
+ * @brief Maximum peripherals set 2 clock frequency.
+ */
+#define SPC5_PERIPHERALS_2_CLK_MAX 64000000
+
+/**
+ * @brief Maximum peripherals set 3 clock frequency.
+ */
+#define SPC5_PERIPHERALS_3_CLK_MAX 64000000
+
+/**
+ * @brief Maximum RAM zero wait states clock frequency.
+ */
+#define SPC5_RAM_0WS_CLK_MAX 64000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
+ oscillator. */
+#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
+ oscillator. */
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_TEST (1U << 1)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+#define SPC5_ME_ME_STANDBY0 (1U << 13)
+#define SPC5_ME_ME_RESET_DEST (1U << 15)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
+#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
+#define SPC5_ME_MC_CFLAON_PD (1U << 16)
+#define SPC5_ME_MC_CFLAON_LP (2U << 16)
+#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
+#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
+#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
+#define SPC5_ME_MC_DFLAON_PD (1U << 18)
+#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_TEST (1U << 1)
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+#define SPC5_ME_LP_PC_STANDBY0 (1U << 13)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 60
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief XOSC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Fast IRC divider value.
+ * @note The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE 1
+#endif
+
+/**
+ * @brief Peripherals Set 1 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 4
+#endif
+
+/**
+ * @brief Peripherals Set 2 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Peripherals Set 3 clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_PERIPHERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief e200z0 core clock divider value.
+ */
+#if !defined(SPC5_Z0_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_Z0_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief FEC clock divider value.
+ */
+#if !defined(SPC5_FEC_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FEC_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief CFLASH/DFLASH clock divider value.
+ */
+#if !defined(SPC5_FLASH_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FLASH_CLK_DIV_VALUE 2
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0 | \
+ SPC5_ME_ME_STANDBY0)
+#endif
+
+/**
+ * @brief TEST mode settings.
+ */
+#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STANDBY0 mode settings.
+ */
+#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_CFLAON_NORMAL | \
+ SPC5_ME_MC_DFLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
+ SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0 | \
+ SPC5_ME_LP_PC_STANDBY0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief PIT channel 0 IRQ priority.
+ * @note This PIT channel is allocated permanently for system tick
+ * generation.
+ */
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY 4
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC56ECxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC56ECxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on the XOSC divider.*/
+#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
+#error "invalid SPC5_XOSCDIV_VALUE value specified"
+#endif
+
+/* Check on the IRC divider.*/
+#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
+#error "invalid SPC5_IRCDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PERIPHERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_PERIPHERAL1_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_PERIPHERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PERIPHERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1 0
+#elif (SPC5_PERIPHERAL2_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1 (0x80 | (SPC5_PERIPHERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PERIPHERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2 0
+#elif (SPC5_PERIPHERAL3_CLK_DIV_VALUE >= 1) && \
+ (SPC5_PERIPHERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2 (0x80 | (SPC5_PERIPHERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PERIPHERAL3_CLK_DIV_VALUE value specified"
+#endif
+
+#if SPC5_Z0_CLK_DIV_VALUE == 1
+#define SPC5_CGM_Z0_DCR 0
+#elif SPC5_Z0_CLK_DIV_VALUE == 2
+#define SPC5_CGM_Z0_DCR 1
+#else
+#error "invalid SPC5_Z0_CLK_DIV_VALUE value specified"
+#endif
+
+#if SPC5_FEC_CLK_DIV_VALUE == 1
+#define SPC5_CGM_FEC_DCR 0
+#elif SPC5_FEC_CLK_DIV_VALUE == 2
+#define SPC5_CGM_FEC_DCR 1
+#else
+#error "invalid SPC5_FEC_CLK_DIV_VALUE value specified"
+#endif
+
+#if SPC5_FLASH_CLK_DIV_VALUE == 1
+#define SPC5_CGM_FLASH_DCR 0
+#elif SPC5_FLASH_CLK_DIV_VALUE == 2
+#define SPC5_CGM_FLASH_DCR 1
+#else
+#error "invalid SPC5_FLASH_CLK_DIV_VALUE value specified"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/**
+ * @brief Run modes.
+ */
+typedef enum {
+ SPC5_RUNMODE_TEST = 1,
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * TBL register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+static inline
+halrtcnt_t hal_lld_get_counter_value(void) {
+ halrtcnt_t cnt;
+
+ port_read_spr(284, cnt);
+
+ return cnt;
+}
+
+/**
+ * @brief Realtime counter frequency.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() (halclock_t)halSPCGetSystemClock()
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ECxx/platform.mk b/os/hal/ports/SPC5/SPC56ECxx/platform.mk new file mode 100644 index 000000000..d57061ddf --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/platform.mk @@ -0,0 +1,15 @@ +# List of all the SPC56ECxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC56ECxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC56ECxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/LLD/STM_v1
diff --git a/os/hal/ports/SPC5/SPC56ECxx/registers.h b/os/hal/ports/SPC5/SPC56ECxx/registers.h new file mode 100644 index 000000000..4ab36a92b --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc56ec.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ECxx/spc5_registry.h b/os/hal/ports/SPC5/SPC56ECxx/spc5_registry.h new file mode 100644 index 000000000..a6dcf4d36 --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/spc5_registry.h @@ -0,0 +1,757 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/spc5_registry.h
+ * @brief SPC56ECxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if defined(_SPC564B64L7_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 147
+
+#elif defined(_SPC564B70L7_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 147
+
+#elif defined(_SPC564B74L7_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 147
+
+#elif defined(_SPC564B64L8_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 177
+
+#elif defined(_SPC564B70L8_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 177
+
+#elif defined(_SPC564B74L8_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 177
+
+#elif defined(_SPC56EC64B3_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 199
+
+#elif defined(_SPC56EC64L7_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 147
+
+#elif defined(_SPC56EC64L8_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 177
+
+#elif defined(_SPC56EC70B3_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 199
+
+#elif defined(_SPC56EC70L7_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 147
+
+#elif defined(_SPC56EC70L8_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 177
+
+#elif defined(_SPC56EC74B3_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 199
+
+#elif defined(_SPC56EC74L7_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 147
+
+#elif defined(_SPC56EC74L8_)
+#define SPC5_NUM_DSPI 8
+#define SPC5_NUM_LINFLEX 10
+#define SPC5_NUM_GPIO 177
+
+#else
+#error "SPC56ECxx platform not defined"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC560Bxx capabilities
+ * @{
+ */
+/* DSPI attribures.*/
+#define SPC5_DSPI_FIFO_DEPTH 4
+
+#if SPC5_NUM_DSPI > 0
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI0 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 1
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI1 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 2
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI2_RFDF_HANDLER vector118
+#define SPC5_DSPI2_RFDF_NUMBER 118
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI2 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 3
+#define SPC5_HAS_DSPI3 TRUE
+#define SPC5_DSPI3_PCTL 7
+#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
+#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI3_RX_DMA_DEV_ID 8
+#define SPC5_DSPI3_TFFF_HANDLER vector184
+#define SPC5_DSPI3_TFFF_NUMBER 184
+#define SPC5_DSPI3_RFDF_HANDLER vector186
+#define SPC5_DSPI3_RFDF_NUMBER 186
+#define SPC5_DSPI3_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_START_PCTL)
+#define SPC5_DSPI3_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI3_PCTL, SPC5_SPI_DSPI3_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI3 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 4
+#define SPC5_HAS_DSPI4 TRUE
+#define SPC5_DSPI4_PCTL 8
+#define SPC5_DSPI4_TX1_DMA_DEV_ID 9
+#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI4_RX_DMA_DEV_ID 10
+#define SPC5_DSPI4_TFFF_HANDLER vector213
+#define SPC5_DSPI4_TFFF_NUMBER 213
+#define SPC5_DSPI4_RFDF_HANDLER vector215
+#define SPC5_DSPI4_RFDF_NUMBER 215
+#define SPC5_DSPI4_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_START_PCTL)
+#define SPC5_DSPI4_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI4_PCTL, SPC5_SPI_DSPI4_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI4 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 5
+#define SPC5_HAS_DSPI5 TRUE
+#define SPC5_DSPI5_PCTL 9
+#define SPC5_DSPI5_TX1_DMA_DEV_ID 11
+#define SPC5_DSPI5_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI5_RX_DMA_DEV_ID 12
+#define SPC5_DSPI5_TFFF_HANDLER vector221
+#define SPC5_DSPI5_TFFF_NUMBER 221
+#define SPC5_DSPI5_RFDF_HANDLER vector223
+#define SPC5_DSPI5_RFDF_NUMBER 223
+#define SPC5_DSPI5_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI5_PCTL, SPC5_SPI_DSPI5_START_PCTL)
+#define SPC5_DSPI5_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI5_PCTL, SPC5_SPI_DSPI5_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI5 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 6
+#define SPC5_HAS_DSPI6 TRUE
+#define SPC5_DSPI6_PCTL 10
+#define SPC5_DSPI6_TX1_DMA_DEV_ID 13
+#define SPC5_DSPI6_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI6_RX_DMA_DEV_ID 14
+#define SPC5_DSPI6_TFFF_HANDLER vector236
+#define SPC5_DSPI6_TFFF_NUMBER 236
+#define SPC5_DSPI6_RFDF_HANDLER vector238
+#define SPC5_DSPI6_RFDF_NUMBER 238
+#define SPC5_DSPI6_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI6_PCTL, SPC5_SPI_DSPI6_START_PCTL)
+#define SPC5_DSPI6_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI6_PCTL, SPC5_SPI_DSPI6_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI6 FALSE
+#endif
+
+#if SPC5_NUM_DSPI > 7
+#define SPC5_HAS_DSPI7 TRUE
+#define SPC5_DSPI7_PCTL 11
+#define SPC5_DSPI7_TX1_DMA_DEV_ID 15
+#define SPC5_DSPI7_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI7_RX_DMA_DEV_ID 16
+#define SPC5_DSPI7_TFFF_HANDLER vector241
+#define SPC5_DSPI7_TFFF_NUMBER 241
+#define SPC5_DSPI7_RFDF_HANDLER vector243
+#define SPC5_DSPI7_RFDF_NUMBER 243
+#define SPC5_DSPI7_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI7_PCTL, SPC5_SPI_DSPI7_START_PCTL)
+#define SPC5_DSPI7_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI7_PCTL, SPC5_SPI_DSPI7_STOP_PCTL)
+#else
+#define SPC5_HAS_DSPI7 FALSE
+#endif
+
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 32
+#define SPC5_EDMA_HAS_MUX TRUE
+#define SPC5_EDMA_MUX_PCTL 23
+
+/* LINFlex attributes.*/
+#if SPC5_NUM_LINFLEX > 0
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX0 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 1
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX1 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 2
+#define SPC5_HAS_LINFLEX2 TRUE
+#define SPC5_LINFLEX2_PCTL 50
+#define SPC5_LINFLEX2_RXI_HANDLER vector119
+#define SPC5_LINFLEX2_TXI_HANDLER vector120
+#define SPC5_LINFLEX2_ERR_HANDLER vector121
+#define SPC5_LINFLEX2_RXI_NUMBER 119
+#define SPC5_LINFLEX2_TXI_NUMBER 120
+#define SPC5_LINFLEX2_ERR_NUMBER 121
+#define SPC5_LINFLEX2_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX2 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 3
+#define SPC5_HAS_LINFLEX3 TRUE
+#define SPC5_LINFLEX3_PCTL 51
+#define SPC5_LINFLEX3_RXI_HANDLER vector122
+#define SPC5_LINFLEX3_TXI_HANDLER vector123
+#define SPC5_LINFLEX3_ERR_HANDLER vector124
+#define SPC5_LINFLEX3_RXI_NUMBER 122
+#define SPC5_LINFLEX3_TXI_NUMBER 123
+#define SPC5_LINFLEX3_ERR_NUMBER 124
+#define SPC5_LINFLEX3_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX3 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 4
+#define SPC5_HAS_LINFLEX4 TRUE
+#define SPC5_LINFLEX4_PCTL 52
+#define SPC5_LINFLEX4_RXI_HANDLER vector187
+#define SPC5_LINFLEX4_TXI_HANDLER vector188
+#define SPC5_LINFLEX4_ERR_HANDLER vector189
+#define SPC5_LINFLEX4_RXI_NUMBER 187
+#define SPC5_LINFLEX4_TXI_NUMBER 188
+#define SPC5_LINFLEX4_ERR_NUMBER 189
+#define SPC5_LINFLEX4_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX4 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 5
+#define SPC5_HAS_LINFLEX5 TRUE
+#define SPC5_LINFLEX5_PCTL 53
+#define SPC5_LINFLEX5_RXI_HANDLER vector199
+#define SPC5_LINFLEX5_TXI_HANDLER vector200
+#define SPC5_LINFLEX5_ERR_HANDLER vector201
+#define SPC5_LINFLEX5_RXI_NUMBER 199
+#define SPC5_LINFLEX5_TXI_NUMBER 200
+#define SPC5_LINFLEX5_ERR_NUMBER 201
+#define SPC5_LINFLEX5_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX5 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 6
+#define SPC5_HAS_LINFLEX6 TRUE
+#define SPC5_LINFLEX6_PCTL 54
+#define SPC5_LINFLEX6_RXI_HANDLER vector216
+#define SPC5_LINFLEX6_TXI_HANDLER vector217
+#define SPC5_LINFLEX6_ERR_HANDLER vector218
+#define SPC5_LINFLEX6_RXI_NUMBER 216
+#define SPC5_LINFLEX6_TXI_NUMBER 217
+#define SPC5_LINFLEX6_ERR_NUMBER 218
+#define SPC5_LINFLEX6_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX6 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 7
+#define SPC5_HAS_LINFLEX7 TRUE
+#define SPC5_LINFLEX7_PCTL 55
+#define SPC5_LINFLEX7_RXI_HANDLER vector224
+#define SPC5_LINFLEX7_TXI_HANDLER vector225
+#define SPC5_LINFLEX7_ERR_HANDLER vector226
+#define SPC5_LINFLEX7_RXI_NUMBER 224
+#define SPC5_LINFLEX7_TXI_NUMBER 225
+#define SPC5_LINFLEX7_ERR_NUMBER 226
+#define SPC5_LINFLEX7_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX7 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 8
+#define SPC5_HAS_LINFLEX8 TRUE
+#define SPC5_LINFLEX8_PCTL 12
+#define SPC5_LINFLEX8_RXI_HANDLER vector227
+#define SPC5_LINFLEX8_TXI_HANDLER vector228
+#define SPC5_LINFLEX8_ERR_HANDLER vector229
+#define SPC5_LINFLEX8_RXI_NUMBER 227
+#define SPC5_LINFLEX8_TXI_NUMBER 228
+#define SPC5_LINFLEX8_ERR_NUMBER 229
+#define SPC5_LINFLEX8_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX8 FALSE
+#endif
+
+#if SPC5_NUM_LINFLEX > 9
+#define SPC5_HAS_LINFLEX9 TRUE
+#define SPC5_LINFLEX9_PCTL 13
+#define SPC5_LINFLEX9_RXI_HANDLER vector230
+#define SPC5_LINFLEX9_TXI_HANDLER vector231
+#define SPC5_LINFLEX9_ERR_HANDLER vector232
+#define SPC5_LINFLEX9_RXI_NUMBER 230
+#define SPC5_LINFLEX9_TXI_NUMBER 231
+#define SPC5_LINFLEX9_ERR_NUMBER 232
+#define SPC5_LINFLEX9_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL1_CLK_DIV_VALUE)
+#else
+#define SPC5_HAS_LINFLEX9 FALSE
+#endif
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_PCTL 68
+#define SPC5_SIUL_NUM_PORTS 13
+#define SPC5_SIUL_NUM_PCRS 199
+#define SPC5_SIUL_NUM_PADSELS 68
+#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
+
+/* eMIOS attributes.*/
+#define SPC5_HAS_EMIOS0 TRUE
+#define SPC5_EMIOS0_PCTL 72
+#define SPC5_EMIOS0_GFR_F0F1_HANDLER vector141
+#define SPC5_EMIOS0_GFR_F2F3_HANDLER vector142
+#define SPC5_EMIOS0_GFR_F4F5_HANDLER vector143
+#define SPC5_EMIOS0_GFR_F6F7_HANDLER vector144
+#define SPC5_EMIOS0_GFR_F8F9_HANDLER vector145
+#define SPC5_EMIOS0_GFR_F10F11_HANDLER vector146
+#define SPC5_EMIOS0_GFR_F12F13_HANDLER vector147
+#define SPC5_EMIOS0_GFR_F14F15_HANDLER vector148
+#define SPC5_EMIOS0_GFR_F16F17_HANDLER vector149
+#define SPC5_EMIOS0_GFR_F18F19_HANDLER vector150
+#define SPC5_EMIOS0_GFR_F20F21_HANDLER vector151
+#define SPC5_EMIOS0_GFR_F22F23_HANDLER vector152
+#define SPC5_EMIOS0_GFR_F24F25_HANDLER vector153
+#define SPC5_EMIOS0_GFR_F26F27_HANDLER vector154
+#define SPC5_EMIOS0_GFR_F28F29_HANDLER vector155
+#define SPC5_EMIOS0_GFR_F30F31_HANDLER vector156
+#define SPC5_EMIOS0_GFR_F0F1_NUMBER 141
+#define SPC5_EMIOS0_GFR_F2F3_NUMBER 142
+#define SPC5_EMIOS0_GFR_F4F5_NUMBER 143
+#define SPC5_EMIOS0_GFR_F6F7_NUMBER 144
+#define SPC5_EMIOS0_GFR_F8F9_NUMBER 145
+#define SPC5_EMIOS0_GFR_F10F11_NUMBER 146
+#define SPC5_EMIOS0_GFR_F12F13_NUMBER 147
+#define SPC5_EMIOS0_GFR_F14F15_NUMBER 148
+#define SPC5_EMIOS0_GFR_F16F17_NUMBER 149
+#define SPC5_EMIOS0_GFR_F18F19_NUMBER 150
+#define SPC5_EMIOS0_GFR_F20F21_NUMBER 151
+#define SPC5_EMIOS0_GFR_F22F23_NUMBER 152
+#define SPC5_EMIOS0_GFR_F24F25_NUMBER 153
+#define SPC5_EMIOS0_GFR_F26F27_NUMBER 154
+#define SPC5_EMIOS0_GFR_F28F29_NUMBER 155
+#define SPC5_EMIOS0_GFR_F30F31_NUMBER 156
+
+#define SPC5_EMIOS0_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS0_GPRE_VALUE)
+
+#define SPC5_HAS_EMIOS1 TRUE
+#define SPC5_EMIOS1_PCTL 73
+#define SPC5_EMIOS1_GFR_F0F1_HANDLER vector157
+#define SPC5_EMIOS1_GFR_F2F3_HANDLER vector158
+#define SPC5_EMIOS1_GFR_F4F5_HANDLER vector159
+#define SPC5_EMIOS1_GFR_F6F7_HANDLER vector160
+#define SPC5_EMIOS1_GFR_F8F9_HANDLER vector161
+#define SPC5_EMIOS1_GFR_F10F11_HANDLER vector162
+#define SPC5_EMIOS1_GFR_F12F13_HANDLER vector163
+#define SPC5_EMIOS1_GFR_F14F15_HANDLER vector164
+#define SPC5_EMIOS1_GFR_F16F17_HANDLER vector165
+#define SPC5_EMIOS1_GFR_F18F19_HANDLER vector166
+#define SPC5_EMIOS1_GFR_F20F21_HANDLER vector167
+#define SPC5_EMIOS1_GFR_F22F23_HANDLER vector168
+#define SPC5_EMIOS1_GFR_F24F25_HANDLER vector169
+#define SPC5_EMIOS1_GFR_F26F27_HANDLER vector170
+#define SPC5_EMIOS1_GFR_F28F29_HANDLER vector171
+#define SPC5_EMIOS1_GFR_F30F31_HANDLER vector172
+#define SPC5_EMIOS1_GFR_F0F1_NUMBER 157
+#define SPC5_EMIOS1_GFR_F2F3_NUMBER 158
+#define SPC5_EMIOS1_GFR_F4F5_NUMBER 159
+#define SPC5_EMIOS1_GFR_F6F7_NUMBER 160
+#define SPC5_EMIOS1_GFR_F8F9_NUMBER 161
+#define SPC5_EMIOS1_GFR_F10F11_NUMBER 162
+#define SPC5_EMIOS1_GFR_F12F13_NUMBER 163
+#define SPC5_EMIOS1_GFR_F14F15_NUMBER 164
+#define SPC5_EMIOS1_GFR_F16F17_NUMBER 165
+#define SPC5_EMIOS1_GFR_F18F19_NUMBER 166
+#define SPC5_EMIOS1_GFR_F20F21_NUMBER 167
+#define SPC5_EMIOS1_GFR_F22F23_NUMBER 168
+#define SPC5_EMIOS1_GFR_F24F25_NUMBER 169
+#define SPC5_EMIOS1_GFR_F26F27_NUMBER 170
+#define SPC5_EMIOS1_GFR_F28F29_NUMBER 171
+#define SPC5_EMIOS1_GFR_F30F31_NUMBER 172
+
+#define SPC5_EMIOS1_CLK (halSPCGetSystemClock() / \
+ SPC5_PERIPHERAL3_CLK_DIV_VALUE / \
+ SPC5_EMIOS1_GPRE_VALUE)
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 64
+#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
+#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
+#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN2 TRUE
+#define SPC5_FLEXCAN2_PCTL 18
+#define SPC5_FLEXCAN2_MB 64
+#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
+#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+
+#define SPC5_HAS_FLEXCAN3 TRUE
+#define SPC5_FLEXCAN3_PCTL 19
+#define SPC5_FLEXCAN3_MB 64
+#define SPC5_FLEXCAN3_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
+#define SPC5_FLEXCAN3_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_START_PCTL);
+#define SPC5_FLEXCAN3_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL, SPC5_CAN_FLEXCAN3_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN4 TRUE
+#define SPC5_FLEXCAN4_PCTL 20
+#define SPC5_FLEXCAN4_MB 64
+#define SPC5_FLEXCAN4_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
+#define SPC5_FLEXCAN4_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_START_PCTL);
+#define SPC5_FLEXCAN4_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL, SPC5_CAN_FLEXCAN4_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN5 TRUE
+#define SPC5_FLEXCAN5_PCTL 21
+#define SPC5_FLEXCAN5_MB 64
+#define SPC5_FLEXCAN5_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
+#define SPC5_FLEXCAN5_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_START_PCTL);
+#define SPC5_FLEXCAN5_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL, SPC5_CAN_FLEXCAN5_STOP_PCTL);
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC FALSE
+
+#define SPC5_HAS_ADC0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR2 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR4 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR5 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL5 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL6 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL7 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL8 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL9 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL10 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL11 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 TRUE
+#define SPC5_ADC0_PCTL 32
+#define SPC5_ADC0_DMA_DEV_ID 29
+#define SPC5_ADC0_EOC_HANDLER vector62
+#define SPC5_ADC0_EOC_NUMBER 62
+#define SPC5_ADC0_WD_HANDLER vector64
+#define SPC5_ADC0_WD_NUMBER 64
+
+#define SPC5_HAS_ADC1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR3 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR4 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR5 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR6 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR7 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR8 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR9 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR10 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR11 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR12 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR13 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR14 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR15 FALSE
+#define SPC5_ADC_ADC1_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL4 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL5 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC1_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR2 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR2 TRUE
+#define SPC5_ADC1_PCTL 33
+#define SPC5_ADC1_DMA_DEV_ID 30
+#define SPC5_ADC1_EOC_HANDLER vector82
+#define SPC5_ADC1_EOC_NUMBER 82
+#define SPC5_ADC1_WD_HANDLER vector84
+#define SPC5_ADC1_WD_NUMBER 84
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ECxx/typedefs.h b/os/hal/ports/SPC5/SPC56ECxx/typedefs.h new file mode 100644 index 000000000..d3cb2effd --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ECxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h b/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h new file mode 100644 index 000000000..b0e6416ed --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ECxx/xpc56ec.h @@ -0,0 +1,8475 @@ +/*****************************************************************
+ *
+ * FILE : MPC564xBC_V1.0.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for the MPC564xB/C family of devices
+ *
+ * COPYRIGHT :(c) 2011, Freescale & STMicroelectronics
+ *
+ * VERSION : 1.0 (Based on RM Rev2 RC)
+ * DATE : April 2011
+ * AUTHOR : r19325
+ * HISTORY : Based on MPC5604B, MPC5607B and MPC5668
+ * 0.1 Jun10 : Initial release based on RM RevA, Ver 0.1
+ * 0.2 Jul10 : Corrections based on RM Rev1 Draft D
+ * 0.3 Feb11 : Corrections based on MPC5607B header and RM R2 DraftB
+ * 1.0 Mar11 : 1st official release based on RM Rev2 RC
+ *
+ *
+ * Implementation comments:
+ * -----------------------
+ *
+ * The header file does not include definitions for flexray as the
+ * expectation is that flexray will be used with drivers
+ *
+ * DSPI implementation supports master mode only
+ *
+ * The register protection registers are not included. These can
+ * be easily addressed using a macro to reference the existing
+ * registers which simplifies the protection process.
+ *
+ * Please report any comments or feedback via the "technical service
+ * request" tool listed under the support tab at www.freescale.com
+ *
+ *
+ *****************************************************************
+ * Copyright:
+ * Freescale Semiconductor, INC. All Rights Reserved.
+ * You are hereby granted a copyright license to use, modify, and
+ * distribute the SOFTWARE so long as this entire notice is
+ * retained without alteration in any modified and/or redistributed
+ * versions, and that such modified versions are clearly identified
+ * as such. No licenses are granted by implication, estoppel or
+ * otherwise under any patents or trademarks of Freescale
+ * Semiconductor, Inc. This software is provided on an "AS IS"
+ * basis and without warranty.
+ *
+ * To the maximum extent permitted by applicable law, Freescale
+ * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+ * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
+ * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
+ * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
+ * AND ANY ACCOMPANYING WRITTEN MATERIALS.
+ *
+ * To the maximum extent permitted by applicable law, IN NO EVENT
+ * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+ * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
+ * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ * Freescale Semiconductor assumes no responsibility for the
+ * maintenance and support of this software
+ *
+ ******************************************************************/
+
+/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
+
+/*****************************************************************
+* Example instantiation and use:
+*
+* <MODULE>.<REGISTER>.B.<BIT> = 1;
+* <MODULE>.<REGISTER>.R = 0x10000000;
+*
+******************************************************************/
+
+#ifndef _MPC5646x_H_
+#define _MPC5646x_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+/****************************************************************************/
+/* MODULE : CFLASH */
+/****************************************************************************/
+struct CFLASH_tag {
+
+ union { /* Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t :4;
+ vuint32_t SIZE:3;
+ vuint32_t :1;
+ vuint32_t LAS:3;
+ vuint32_t :3;
+ vuint32_t MAS:1;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t :2;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t :4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* Low/Mid address block locking (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t :10;
+ vuint32_t TSLK:1;
+ vuint32_t :2;
+ vuint32_t MLK:2;
+ vuint32_t LLK:16;
+ } B;
+ } LML;
+
+ union { /* High address space block locking (Base+0x0008)*/
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1;
+ vuint32_t :19;
+ vuint32_t HLK:12;
+ } B;
+ } HBL;
+
+ union { /* Secondary Low/Mid block lock (Base+0x000C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t :10;
+ vuint32_t STSLK:1;
+ vuint32_t :2;
+ vuint32_t SMK:2;
+ vuint32_t SLK:16;
+ } B;
+ } SLL;
+
+ union { /* Low/Mid address space block sel (Base+0x0010)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2;
+ vuint32_t LSL:16;
+ } B;
+ } LMS;
+
+ union { /* High address Space block select (Base+0x0014)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t HSL:12;
+ } B;
+ } HBS;
+
+ union { /* Address (Base+0x0018) */
+ vuint32_t R; /* Can't put ADD in array as it runs [3..22] */
+ struct {
+ vuint32_t :9;
+ vuint32_t ADD:20;
+ vuint32_t :3;
+ } B;
+ } ADR;
+
+
+ /* Note the following 3 registers, BIU[0..2] are mirrored to */
+ /* the code flash configuraiton PFCR[0..2] registers */
+ /* To make it easier to code, the BIU registers have been */
+ /* replaced with the PFCR registers in this header file! */
+ /* A commented out BIU register is shown for reference! */
+
+
+ union { /* CFLASH Configuration 0 (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t B02_APC:5;
+ vuint32_t :5; /* vuint32_t B02_WWSC:5; (removed RevD) */
+ vuint32_t B02_RWSC:5;
+ vuint32_t B02_RWWC2:1;
+ vuint32_t B02_RWWC1:1;
+ vuint32_t B02_P1_BCFG:2;
+ vuint32_t B02_P1_DPFE:1;
+ vuint32_t B02_P1_IPFE:1;
+ vuint32_t B02_P1_PFLM:2;
+ vuint32_t B02_P1_BFE:1;
+ vuint32_t B02_RWWC0:1;
+ vuint32_t B02_P0_BCFG:2;
+ vuint32_t B02_P0_DPFE:1;
+ vuint32_t B02_P0_IPFE:1;
+ vuint32_t B02_P0_PFLM:2;
+ vuint32_t B02_P0_BFE:1;
+ } B;
+ } PFCR0;
+ /* Commented out Bus Interface Unit 0 (Base+0x001C) */
+ /*union {
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t BI0:32;
+
+ } B;
+
+ } BIU0; */
+ union { /* CFLASH Configuration 1 (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t B1_APC:5;
+ vuint32_t B1_WWSC:5;
+ vuint32_t B1_RWSC:5;
+ vuint32_t B1_RWWC2:1;
+ vuint32_t B1_RWWC1:1;
+ vuint32_t :6;
+ vuint32_t B1_P1_BFE:1;
+ vuint32_t B1_RWWC0:1;
+ vuint32_t :6;
+ vuint32_t B1_P0_BFE:1;
+ } B;
+ } PFCR1;
+ /* Commented out Bus Interface Unit 1 (Base+0x0020) */
+ /*union {
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t BI1:32;
+
+ } B;
+
+ } BIU1; */
+ union { /* CFLASH Access Protection (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t :6;
+ vuint32_t ARBM:2;
+ vuint32_t M7PFD:1;
+ vuint32_t M6PFD:1;
+ vuint32_t M5PFD:1;
+ vuint32_t M4PFD:1;
+ vuint32_t M3PFD:1;
+ vuint32_t M2PFD:1;
+ vuint32_t M1PFD:1;
+ vuint32_t M0PFD:1;
+ vuint32_t M7AP:2;
+ vuint32_t M6AP:2;
+ vuint32_t M5AP:2;
+ vuint32_t M4AP:2;
+ vuint32_t M3AP:2;
+ vuint32_t M2AP:2;
+ vuint32_t M1AP:2;
+ vuint32_t M0AP:2;
+ } B;
+ } PFAPR;
+ /* Commented out Bus Interface Unit 2 (Base+0x0024) */
+ /*union {
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t BI2:32;
+
+ } B;
+
+ } BIU2; */
+ vuint8_t CFLASH_reserved0[20]; /* Reserved 20 Bytes (Base+0x0028-0x003B) */
+
+ union { /* User Test 0 (Base+0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t :7;
+ vuint32_t DSI:8;
+ vuint32_t :10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test 1 (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ union { /* User Test 2 (Base+0x0044) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT2;
+
+ union { /* User Multiple Input Sig 0..4 (Base+0x0048-0x005B) */
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[5];
+
+ vuint8_t CFLASH_reserved1[16292]; /* Reserved 16292 (Base+0x005C-0x3FFF)*/
+
+}; /* end of CFLASH_tag */
+/****************************************************************************/
+/* MODULE : DFLASH */
+/****************************************************************************/
+struct DFLASH_tag {
+
+ union { /* Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t EDC:1;
+ vuint32_t :4;
+ vuint32_t SIZE:3;
+ vuint32_t :1;
+ vuint32_t LAS:3;
+ vuint32_t :1;
+ vuint32_t MAS:3;
+ vuint32_t EER:1;
+ vuint32_t RWE:1;
+ vuint32_t :2;
+ vuint32_t PEAS:1;
+ vuint32_t DONE:1;
+ vuint32_t PEG:1;
+ vuint32_t :4;
+ vuint32_t PGM:1;
+ vuint32_t PSUS:1;
+ vuint32_t ERS:1;
+ vuint32_t ESUS:1;
+ vuint32_t EHV:1;
+ } B;
+ } MCR;
+
+ union { /* Low/Mid address block locking (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1;
+ vuint32_t :10;
+ vuint32_t TSLK:1;
+ vuint32_t :16;
+ vuint32_t LLK:4;
+ } B;
+ } LML;
+
+ vuint8_t DFLASH_reserved0[4]; /* Reserved 4 Bytes (+0x0008-0x000B) */
+
+ union { /* Secondary Low/mid block locking (Base+0x000C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1;
+ vuint32_t :10;
+ vuint32_t STSLK:1;
+ vuint32_t :16;
+ vuint32_t SLK:4;
+ } B;
+ } SLL;
+
+ union { /* Low/Mid address space block sel (Base+0x0010)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t LSL:4;
+ } B;
+ } LMS;
+
+ vuint8_t DFLASH_reserved1[4]; /* Reserved 4 Bytes (+0x0014-0x0017) */
+
+ union { /* Address (Base+0x0018) */
+ vuint32_t R; /* Can't put ADD in array as it runs [2..22] */
+ struct {
+ vuint32_t :9;
+ vuint32_t ADD:21;
+ vuint32_t :2;
+ } B;
+ } ADR;
+
+ vuint8_t DFLASH_reserved2[32]; /* Reserved 32 Bytes (+0x001C-0x003B) */
+
+ union { /* User Test 0 (Base+0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1;
+ vuint32_t :8;
+ vuint32_t DSI:7;
+ vuint32_t :10;
+ vuint32_t MRE:1;
+ vuint32_t MRV:1;
+ vuint32_t EIE:1;
+ vuint32_t AIS:1;
+ vuint32_t AIE:1;
+ vuint32_t AID:1;
+ } B;
+ } UT0;
+
+ union { /* User Test 1 (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t DAI:32;
+ } B;
+ } UT1;
+
+ vuint8_t DFLASH_reserved3[4]; /* Reserved 4 Bytes (+0x0044-0x0047) */
+
+ union { /* User Multiple Input sig 0..1 (+0x0048-0x004F)*/
+ vuint32_t R;
+ struct {
+ vuint32_t MS:32;
+ } B;
+ } UMISR[2];
+
+}; /* end of DFLASH_tag */
+/****************************************************************************/
+/* MODULE : SIU Lite (tagged as SIU for compatibility) */
+/****************************************************************************/
+struct SIU_tag {
+
+ vuint8_t SIU_reserved0[4]; /* Reserved 4 Bytes (Base+0x0) */
+
+ union { /* MCU ID1 (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16;
+ vuint32_t CSP:1;
+ vuint32_t PKG:5;
+ vuint32_t :2;
+ vuint32_t MAJOR_MASK:4;
+ vuint32_t MINOR_MASK:4;
+ } B;
+ } MIDR1;
+
+ union { /* MCU ID2 (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1;
+ vuint32_t FLASH_SIZE_1:4;
+ vuint32_t FLASH_SIZE_2:4;
+ vuint32_t :7;
+ vuint32_t PARTNUM:8;
+ vuint32_t :3;
+ vuint32_t EE:1;
+ vuint32_t :3;
+ vuint32_t FR:1;
+ } B;
+ } MIDR2;
+
+ vuint8_t SIU_reserved1[8]; /* Reserved 8 Bytes (Base+(0x000C--0x0013)) */
+
+ union { /* Interrupt Status Flag (Base+0x0014)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t EIF23:1;
+ vuint32_t EIF22:1;
+ vuint32_t EIF21:1;
+ vuint32_t EIF20:1;
+ vuint32_t EIF19:1;
+ vuint32_t EIF18:1;
+ vuint32_t EIF17:1;
+ vuint32_t EIF16:1;
+ vuint32_t EIF15:1;
+ vuint32_t EIF14:1;
+ vuint32_t EIF13:1;
+ vuint32_t EIF12:1;
+ vuint32_t EIF11:1;
+ vuint32_t EIF10:1;
+ vuint32_t EIF9:1;
+ vuint32_t EIF8:1;
+ vuint32_t EIF7:1;
+ vuint32_t EIF6:1;
+ vuint32_t EIF5:1;
+ vuint32_t EIF4:1;
+ vuint32_t EIF3:1;
+ vuint32_t EIF2:1;
+ vuint32_t EIF1:1;
+ vuint32_t EIF0:1;
+ } B;
+ } ISR;
+
+ union { /* Interrupt Request Enable (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t EIRE23:1;
+ vuint32_t EIRE22:1;
+ vuint32_t EIRE21:1;
+ vuint32_t EIRE20:1;
+ vuint32_t EIRE19:1;
+ vuint32_t EIRE18:1;
+ vuint32_t EIRE17:1;
+ vuint32_t EIRE16:1;
+ vuint32_t EIRE15:1;
+ vuint32_t EIRE14:1;
+ vuint32_t EIRE13:1;
+ vuint32_t EIRE12:1;
+ vuint32_t EIRE11:1;
+ vuint32_t EIRE10:1;
+ vuint32_t EIRE9:1;
+ vuint32_t EIRE8:1;
+ vuint32_t EIRE7:1;
+ vuint32_t EIRE6:1;
+ vuint32_t EIRE5:1;
+ vuint32_t EIRE4:1;
+ vuint32_t EIRE3:1;
+ vuint32_t EIRE2:1;
+ vuint32_t EIRE1:1;
+ vuint32_t EIRE0:1;
+ } B;
+ } IRER;
+
+ vuint8_t SIU_reserved2[12]; /* Reserved 12 Bytes (Base+0x001C-0x0027) */
+
+ union { /* Interrupt Rising-Edge Event Enable (+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IREE23:1;
+ vuint32_t IREE22:1;
+ vuint32_t IREE21:1;
+ vuint32_t IREE20:1;
+ vuint32_t IREE19:1;
+ vuint32_t IREE18:1;
+ vuint32_t IREE17:1;
+ vuint32_t IREE16:1;
+ vuint32_t IREE15:1;
+ vuint32_t IREE14:1;
+ vuint32_t IREE13:1;
+ vuint32_t IREE12:1;
+ vuint32_t IREE11:1;
+ vuint32_t IREE10:1;
+ vuint32_t IREE9:1;
+ vuint32_t IREE8:1;
+ vuint32_t IREE7:1;
+ vuint32_t IREE6:1;
+ vuint32_t IREE5:1;
+ vuint32_t IREE4:1;
+ vuint32_t IREE3:1;
+ vuint32_t IREE2:1;
+ vuint32_t IREE1:1;
+ vuint32_t IREE0:1;
+ } B;
+ } IREER;
+
+ union { /* Interrupt Falling-Edge Event Enable (+0x002C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IFEE23:1;
+ vuint32_t IFEE22:1;
+ vuint32_t IFEE21:1;
+ vuint32_t IFEE20:1;
+ vuint32_t IFEE19:1;
+ vuint32_t IFEE18:1;
+ vuint32_t IFEE17:1;
+ vuint32_t IFEE16:1;
+ vuint32_t IFEE15:1;
+ vuint32_t IFEE14:1;
+ vuint32_t IFEE13:1;
+ vuint32_t IFEE12:1;
+ vuint32_t IFEE11:1;
+ vuint32_t IFEE10:1;
+ vuint32_t IFEE9:1;
+ vuint32_t IFEE8:1;
+ vuint32_t IFEE7:1;
+ vuint32_t IFEE6:1;
+ vuint32_t IFEE5:1;
+ vuint32_t IFEE4:1;
+ vuint32_t IFEE3:1;
+ vuint32_t IFEE2:1;
+ vuint32_t IFEE1:1;
+ vuint32_t IFEE0:1;
+ } B;
+ } IFEER;
+
+ union { /* Interrupt Filter Enable (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t IFE23:1;
+ vuint32_t IFE22:1;
+ vuint32_t IFE21:1;
+ vuint32_t IFE20:1;
+ vuint32_t IFE19:1;
+ vuint32_t IFE18:1;
+ vuint32_t IFE17:1;
+ vuint32_t IFE16:1;
+ vuint32_t IFE15:1;
+ vuint32_t IFE14:1;
+ vuint32_t IFE13:1;
+ vuint32_t IFE12:1;
+ vuint32_t IFE11:1;
+ vuint32_t IFE10:1;
+ vuint32_t IFE9:1;
+ vuint32_t IFE8:1;
+ vuint32_t IFE7:1;
+ vuint32_t IFE6:1;
+ vuint32_t IFE5:1;
+ vuint32_t IFE4:1;
+ vuint32_t IFE3:1;
+ vuint32_t IFE2:1;
+ vuint32_t IFE1:1;
+ vuint32_t IFE0:1;
+ } B;
+ } IFER;
+
+ vuint8_t SIU_reserved3[12]; /* Reserved 12 Bytes (Base+0x0034-0x003F) */
+
+ union { /* Pad Configuration 0..198 (Base+0x0040-0x01CD)*/
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t SMC:1;
+ vuint16_t APC:1;
+ vuint16_t PA:3;
+ vuint16_t OBE:1;
+ vuint16_t IBE:1;
+ vuint16_t :2; /* vuint16_t DSC:2; */
+ vuint16_t ODE:1;
+ vuint16_t :2; /* vuint16_t HYS:1; */
+ vuint16_t SRC:1;
+ vuint16_t WPE:1;
+ vuint16_t WPS:1;
+ } B;
+ } PCR[199];
+
+ vuint8_t SIU_reserved4[818]; /*Reserved 818 Bytes (Base+0x01CE-0x04FF) */
+
+ union { /* Pad Selection for Mux Input (0x0500-0x543) */
+ vuint8_t R;
+ struct {
+ vuint8_t :4;
+ vuint8_t PADSEL:4;
+ } B;
+ } PSMI[68];
+
+ vuint8_t SIU_reserved5[188]; /*Reserved 188 Bytes (Base+0x0544-0x05FF) */
+
+ union { /* GPIO Pad Data Output (Base+0x0600-0x06C7) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t PDO:1;
+ } B;
+ } GPDO[200];
+
+ vuint8_t SIU_reserved6[312]; /*Reserved 312 Bytes (Base+0x06C8-0x07FF) */
+
+ union { /* GPIO Pad Data Input (Base+0x0800-0x08C7) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t PDI:1;
+ } B;
+ } GPDI[200];
+
+ vuint8_t SIU_reserved7[824]; /*Reserved 824 Bytes (Base+0x08C8-0x0BFF) */
+
+ union { /* Parallel GPIO Pad Data Out 0-6 (0x0C00-0xC018) */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDO:32;
+ } B;
+ } PGPDO[7];
+
+ vuint8_t SIU_reserved8[36]; /* Reserved 36 Bytes (Base+0x0C1C-0x0C3F) */
+
+ union { /* Parallel GPIO Pad Data In 0-6 (0x0C40-0x0C58) */
+ vuint32_t R;
+ struct {
+ vuint32_t PPDI:32;
+ } B;
+ } PGPDI[7];
+
+ vuint8_t SIU_reserved9[36]; /* Reserved 36 Bytes (Base+0x0C5C-0x0C7F) */
+
+ union { /* Masked Parallel GPIO Pad Data Out 0-12 (0x0C80-0x0CB0) */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16;
+ vuint32_t MPPDO:16;
+ } B;
+ } MPGPDO[13];
+
+ vuint8_t SIU_reserved10[844]; /*Reserved 844 Bytes (Base+0x0CB4-0x0FFF)*/
+
+ union { /* Interrupt Filter Max Counter 0..23 (+0x1000-0x105C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t MAXCNT:4;
+ } B;
+ } IFMC[24];
+
+ vuint8_t SIU_reserved11[32]; /* Reserved 32 Bytes (Base+0x1060-0x107F) */
+
+ union { /* Interrupt Filter Clock Prescaler (Base+0x1080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t IFCP:4;
+ } B;
+ } IFCPR;
+
+ vuint8_t SIU_reserved12[124]; /* Reserved 124 Bytes (+0x1084-0x10FF) */
+
+
+ /* PISR group 1 (eMIOS 0 to DSPI 0) */
+
+ union { /* Parallel Input Select 0 (Base+0x1100) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS0:4;
+ vuint32_t IPS1:4;
+ vuint32_t IPS2:4;
+ vuint32_t IPS3:4;
+ vuint32_t IPS4:4;
+ vuint32_t IPS5:4;
+ vuint32_t IPS6:4;
+ vuint32_t IPS7:4;
+ } B;
+ } PISR0;
+
+ union { /* Parallel Input Select 1 (Base+0x1104) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS8:4;
+ vuint32_t IPS9:4;
+ vuint32_t IPS10:4;
+ vuint32_t IPS11:4;
+ vuint32_t IPS12:4;
+ vuint32_t IPS13:4;
+ vuint32_t IPS14:4;
+ vuint32_t IPS15:4;
+ } B;
+ } PISR1;
+
+ union { /* Parallel Input Select 2 (Base+0x1108) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS16:4;
+ vuint32_t IPS17:4;
+ vuint32_t IPS18:4;
+ vuint32_t IPS19:4;
+ vuint32_t IPS20:4;
+ vuint32_t IPS21:4;
+ vuint32_t IPS22:4;
+ vuint32_t IPS23:4;
+ } B;
+ } PISR2;
+
+ union { /* Parallel Input Select 3 (Base+0x110C) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS24:4;
+ vuint32_t IPS25:4;
+ vuint32_t IPS26:4;
+ vuint32_t IPS27:4;
+ vuint32_t IPS28:4;
+ vuint32_t IPS29:4;
+ vuint32_t IPS30:4;
+ vuint32_t IPS31:4;
+ } B;
+ } PISR3;
+
+ /* PISR group 2 (eMIOS 1 to DSPI 1) */
+
+ union { /* Parallel Input Select 4 (Base+0x1110) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS0:4;
+ vuint32_t IPS1:4;
+ vuint32_t IPS2:4;
+ vuint32_t IPS3:4;
+ vuint32_t IPS4:4;
+ vuint32_t IPS5:4;
+ vuint32_t IPS6:4;
+ vuint32_t IPS7:4;
+ } B;
+ } PISR4;
+
+ union { /* Parallel Input Select 5 (Base+0x1114) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS8:4;
+ vuint32_t IPS9:4;
+ vuint32_t IPS10:4;
+ vuint32_t IPS11:4;
+ vuint32_t IPS12:4;
+ vuint32_t IPS13:4;
+ vuint32_t IPS14:4;
+ vuint32_t IPS15:4;
+ } B;
+ } PISR5;
+
+ union { /* Parallel Input Select 6 (Base+0x1118) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS16:4;
+ vuint32_t IPS17:4;
+ vuint32_t IPS18:4;
+ vuint32_t IPS19:4;
+ vuint32_t IPS20:4;
+ vuint32_t IPS21:4;
+ vuint32_t IPS22:4;
+ vuint32_t IPS23:4;
+ } B;
+ } PISR6;
+
+ union { /* Parallel Input Select 7 (Base+0x111C) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS24:4;
+ vuint32_t IPS25:4;
+ vuint32_t IPS26:4;
+ vuint32_t IPS27:4;
+ vuint32_t IPS28:4;
+ vuint32_t IPS29:4;
+ vuint32_t IPS30:4;
+ vuint32_t IPS31:4;
+ } B;
+ } PISR7;
+
+ /* PISR group 3 (eMIOS 0 to DSPI 3) */
+
+ union { /* Parallel Input Select 8 (Base+0x1120) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS0:4;
+ vuint32_t IPS1:4;
+ vuint32_t IPS2:4;
+ vuint32_t IPS3:4;
+ vuint32_t IPS4:4;
+ vuint32_t IPS5:4;
+ vuint32_t IPS6:4;
+ vuint32_t IPS7:4;
+ } B;
+ } PISR8;
+
+ union { /* Parallel Input Select 9 (Base+0x1124) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS8:4;
+ vuint32_t IPS9:4;
+ vuint32_t IPS10:4;
+ vuint32_t IPS11:4;
+ vuint32_t IPS12:4;
+ vuint32_t IPS13:4;
+ vuint32_t IPS14:4;
+ vuint32_t IPS15:4;
+ } B;
+ } PISR9;
+
+ union { /* Parallel Input Select 10 (Base+0x1128) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS16:4;
+ vuint32_t IPS17:4;
+ vuint32_t IPS18:4;
+ vuint32_t IPS19:4;
+ vuint32_t IPS20:4;
+ vuint32_t IPS21:4;
+ vuint32_t IPS22:4;
+ vuint32_t IPS23:4;
+ } B;
+ } PISR10;
+
+ union { /* Parallel Input Select 11 (Base+0x112C) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS24:4;
+ vuint32_t IPS25:4;
+ vuint32_t IPS26:4;
+ vuint32_t IPS27:4;
+ vuint32_t IPS28:4;
+ vuint32_t IPS29:4;
+ vuint32_t IPS30:4;
+ vuint32_t IPS31:4;
+ } B;
+ } PISR11;
+
+ /* PISR group 4 (eMIOS 1 to DSPI 4) */
+
+ union { /* Parallel Input Select 12 (Base+0x1130) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS0:4;
+ vuint32_t IPS1:4;
+ vuint32_t IPS2:4;
+ vuint32_t IPS3:4;
+ vuint32_t IPS4:4;
+ vuint32_t IPS5:4;
+ vuint32_t IPS6:4;
+ vuint32_t IPS7:4;
+ } B;
+ } PISR12;
+
+ union { /* Parallel Input Select 13 (Base+0x1134) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS8:4;
+ vuint32_t IPS9:4;
+ vuint32_t IPS10:4;
+ vuint32_t IPS11:4;
+ vuint32_t IPS12:4;
+ vuint32_t IPS13:4;
+ vuint32_t IPS14:4;
+ vuint32_t IPS15:4;
+ } B;
+ } PISR13;
+
+ union { /* Parallel Input Select 14 (Base+0x1138) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS16:4;
+ vuint32_t IPS17:4;
+ vuint32_t IPS18:4;
+ vuint32_t IPS19:4;
+ vuint32_t IPS20:4;
+ vuint32_t IPS21:4;
+ vuint32_t IPS22:4;
+ vuint32_t IPS23:4;
+ } B;
+ } PISR14;
+
+ union { /* Parallel Input Select 15 (Base+0x113C) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPS24:4;
+ vuint32_t IPS25:4;
+ vuint32_t IPS26:4;
+ vuint32_t IPS27:4;
+ vuint32_t IPS28:4;
+ vuint32_t IPS29:4;
+ vuint32_t IPS30:4;
+ vuint32_t IPS31:4;
+ } B;
+ } PISR15;
+
+
+ vuint8_t SIU_reserved13[192]; /*Reserved 192 Bytes (Base+0x1140-0x11FF)*/
+
+ union { /* DSPI Input Select (Base+0x1200) */
+ vuint32_t R;
+ struct {
+ vuint32_t SINSEL0:2;
+ vuint32_t SSSSEL0:2;
+ vuint32_t SCKSEL0:2;
+ vuint32_t TRIGSEL0:2;
+ vuint32_t SINSEL1:2;
+ vuint32_t SSSSEL1:2;
+ vuint32_t SCKSEL1:2;
+ vuint32_t TRIGSEL1:2;
+ vuint32_t SINSEL2:2;
+ vuint32_t SSSSEL2:2;
+ vuint32_t SCKSEL2:2;
+ vuint32_t TRIGSEL2:2;
+ vuint32_t SINSEL3:2;
+ vuint32_t SSSSEL3:2;
+ vuint32_t SCKSEL3:2;
+ vuint32_t TRIGSEL3:2;
+ } B;
+ } DISR;
+
+}; /* end of SIU_tag */
+/****************************************************************************/
+/* MODULE : WKUP */
+/****************************************************************************/
+struct WKUP_tag{
+
+ union { /* NMI Status Flag (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1;
+ vuint32_t NOVF0:1;
+ vuint32_t :6;
+ vuint32_t NIF1:1;
+ vuint32_t NOVF1:1;
+ vuint32_t :22;
+ } B;
+ } NSR;
+
+ vuint8_t WKUP_reserved0[4]; /* Reserved 4 Bytes (Base+0x0004-0x0007) */
+
+ union { /* NMI Configuration (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK0:1;
+ vuint32_t NDSS0:2;
+ vuint32_t NWRE0:1;
+ vuint32_t :1;
+ vuint32_t NREE0:1;
+ vuint32_t NFEE0:1;
+ vuint32_t NFE0:1;
+ vuint32_t NLOCK1:1;
+ vuint32_t NDSS1:2;
+ vuint32_t NWRE1:1;
+ vuint32_t :1;
+ vuint32_t NREE1:1;
+ vuint32_t NFEE1:1;
+ vuint32_t NFE1:1;
+ vuint32_t :16;
+ } B;
+ } NCR;
+
+ vuint8_t WKUP_reserved1[8]; /* Reserved 8 Bytes (Base+0x000C-0x0013) */
+
+ union { /* Wakeup/Interrup status flag (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t EIF:32;
+ } B;
+ } WISR;
+
+ union { /* Interrupt Request Enable (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE:32;
+ } B;
+ } IRER;
+
+ union { /* Wakeup Request Enable (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t WRE:32;
+ } B;
+ } WRER;
+
+ vuint8_t WKUP_reserved2[8]; /* Reserved 8 Bytes (Base+0x0020-0x0027) */
+
+ union { /* Wakeup/Interrupt Rising-Edge (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t IREE:32;
+ } B;
+ } WIREER;
+
+ union { /* Wakeup/Interrupt Falling-Edge (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE:32;
+ } B;
+ } WIFEER;
+
+ union { /* Wakeup/Interrupt Filter Enable (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t IFE:32;
+ } B;
+ } WIFER;
+
+ union { /* Wakeup/Interrupt Pullup Enable (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t IPUE:32;
+ } B;
+ } WIPUER; /* Wakeup/Interrupt Pullup Enable Register */
+
+ vuint8_t WKUP_reserved3[16328]; /* Reserved 16328 (Base+0x0038-0x3FFF) */
+
+}; /* end of WKUP_tag */
+/****************************************************************************/
+/* MODULE : EMIOS */
+/****************************************************************************/
+
+struct EMIOS_CHANNEL_tag{
+
+ union { /* Channel A Data (UCn Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t A:16;
+ } B;
+ } CADR;
+
+ union { /* Channel B Data (UCn Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t B:16;
+ } B;
+ } CBDR;
+
+ union { /* Channel Counter (UCn Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t C:16;
+ } B;
+ } CCNTR;
+
+ union { /* Channel Control (UCn Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t FREN:1;
+ vuint32_t :3;
+ vuint32_t UCPRE:2;
+ vuint32_t UCPEN:1;
+ vuint32_t DMA:1;
+ vuint32_t :1;
+ vuint32_t IF:4;
+ vuint32_t FCK:1;
+ vuint32_t FEN:1;
+ vuint32_t :3;
+ vuint32_t FORCMA:1;
+ vuint32_t FORCMB:1;
+ vuint32_t :1;
+ vuint32_t BSL:2;
+ vuint32_t EDSEL:1;
+ vuint32_t EDPOL:1;
+ vuint32_t MODE:7;
+ } B;
+ } CCR;
+
+ union { /* Channel Status (UCn Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t OVR:1;
+ vuint32_t :15;
+ vuint32_t OVFL:1;
+ vuint32_t :12;
+ vuint32_t UCIN:1;
+ vuint32_t UCOUT:1;
+ vuint32_t FLAG:1;
+ } B;
+ } CSR;
+
+ union { /* Alternate Channel A Data (UCn Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t ALTA:16;
+ } B;
+ } ALTCADR;
+
+ vuint8_t EMIOS_CHANNEL_reserved0[8]; /* (UCn Base + (0x0018-0x001F) */
+
+}; /* end of EMIOS_CHANNEL_tag */
+
+
+struct EMIOS_tag{
+
+ union { /* Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t GTBE:1;
+ vuint32_t :1;
+ vuint32_t GPREN:1;
+ vuint32_t :10;
+ vuint32_t GPRE:8;
+ vuint32_t :8;
+ } B;
+ } MCR;
+
+ union { /* Global Flag (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t F31:1;
+ vuint32_t F30:1;
+ vuint32_t F29:1;
+ vuint32_t F28:1;
+ vuint32_t F27:1;
+ vuint32_t F26:1;
+ vuint32_t F25:1;
+ vuint32_t F24:1;
+ vuint32_t F23:1;
+ vuint32_t F22:1;
+ vuint32_t F21:1;
+ vuint32_t F20:1;
+ vuint32_t F19:1;
+ vuint32_t F18:1;
+ vuint32_t F17:1;
+ vuint32_t F16:1;
+ vuint32_t F15:1;
+ vuint32_t F14:1;
+ vuint32_t F13:1;
+ vuint32_t F12:1;
+ vuint32_t F11:1;
+ vuint32_t F10:1;
+ vuint32_t F9:1;
+ vuint32_t F8:1;
+ vuint32_t F7:1;
+ vuint32_t F6:1;
+ vuint32_t F5:1;
+ vuint32_t F4:1;
+ vuint32_t F3:1;
+ vuint32_t F2:1;
+ vuint32_t F1:1;
+ vuint32_t F0:1;
+ } B;
+ } GFR;
+
+ union { /* Output Update Disable (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t OU31:1;
+ vuint32_t OU30:1;
+ vuint32_t OU29:1;
+ vuint32_t OU28:1;
+ vuint32_t OU27:1;
+ vuint32_t OU26:1;
+ vuint32_t OU25:1;
+ vuint32_t OU24:1;
+ vuint32_t OU23:1;
+ vuint32_t OU22:1;
+ vuint32_t OU21:1;
+ vuint32_t OU20:1;
+ vuint32_t OU19:1;
+ vuint32_t OU18:1;
+ vuint32_t OU17:1;
+ vuint32_t OU16:1;
+ vuint32_t OU15:1;
+ vuint32_t OU14:1;
+ vuint32_t OU13:1;
+ vuint32_t OU12:1;
+ vuint32_t OU11:1;
+ vuint32_t OU10:1;
+ vuint32_t OU9:1;
+ vuint32_t OU8:1;
+ vuint32_t OU7:1;
+ vuint32_t OU6:1;
+ vuint32_t OU5:1;
+ vuint32_t OU4:1;
+ vuint32_t OU3:1;
+ vuint32_t OU2:1;
+ vuint32_t OU1:1;
+ vuint32_t OU0:1;
+ } B;
+ } OUDR;
+
+ union { /* Disable Channel (Base+0x000F) */
+ vuint32_t R;
+ struct {
+ vuint32_t CHDIS31:1;
+ vuint32_t CHDIS30:1;
+ vuint32_t CHDIS29:1;
+ vuint32_t CHDIS28:1;
+ vuint32_t CHDIS27:1;
+ vuint32_t CHDIS26:1;
+ vuint32_t CHDIS25:1;
+ vuint32_t CHDIS24:1;
+ vuint32_t CHDIS23:1;
+ vuint32_t CHDIS22:1;
+ vuint32_t CHDIS21:1;
+ vuint32_t CHDIS20:1;
+ vuint32_t CHDIS19:1;
+ vuint32_t CHDIS18:1;
+ vuint32_t CHDIS17:1;
+ vuint32_t CHDIS16:1;
+ vuint32_t CHDIS15:1;
+ vuint32_t CHDIS14:1;
+ vuint32_t CHDIS13:1;
+ vuint32_t CHDIS12:1;
+ vuint32_t CHDIS11:1;
+ vuint32_t CHDIS10:1;
+ vuint32_t CHDIS9:1;
+ vuint32_t CHDIS8:1;
+ vuint32_t CHDIS7:1;
+ vuint32_t CHDIS6:1;
+ vuint32_t CHDIS5:1;
+ vuint32_t CHDIS4:1;
+ vuint32_t CHDIS3:1;
+ vuint32_t CHDIS2:1;
+ vuint32_t CHDIS1:1;
+ vuint32_t CHDIS0:1;
+ } B;
+ } UCDIS;
+
+ vuint8_t EMIOS_reserved0[16]; /* Reserved 16 Bytes (Base+0x0010-0x001F) */
+
+ struct EMIOS_CHANNEL_tag CH[32]; /* Add in 32 unified channels */
+
+ vuint8_t EMIOS_reserved1[3040]; /* 3040 bytes (Base+0x0420-0x0FFF) */
+
+}; /* end of EMIOS_tag */
+/****************************************************************************/
+/* MODULE : SSCM */
+/****************************************************************************/
+struct SSCM_tag{
+
+ union { /* Status (Base+0x0000) */
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t CER:1;
+ vuint16_t :1;
+ vuint16_t Z4_NXEN:1;
+ vuint16_t Z0_NXEN:1;
+ vuint16_t PUB:1;
+ vuint16_t SEC:1;
+ vuint16_t :1;
+ vuint16_t BMODE:3;
+ vuint16_t VLE:1;
+ vuint16_t :4;
+ } B;
+ } STATUS;
+
+ union { /* System Memory Configuration (Base+0x002) */
+ vuint16_t R;
+ struct {
+ vuint16_t JPIN:10;
+ vuint16_t ILVD:1;
+ vuint16_t MREV:4;
+ vuint16_t DVLD:1;
+ } B;
+ } MEMCONFIG;
+
+ vuint8_t SSCM_reserved0[2]; /* Reserved 2 bytes (Base+0x0004-0x0005) */
+
+ union { /* Error Configuration (Base+0x0006) */
+ vuint16_t R;
+ struct {
+ vuint16_t :14;
+ vuint16_t PAE:1;
+ vuint16_t RAE:1;
+ } B;
+ } ERROR;
+
+ union { /* Debug Status Port (Base+0x0008) */
+ vuint16_t R;
+ struct {
+ vuint16_t :13;
+ vuint16_t DEBUG_MODE:3;
+ } B;
+ } DEBUGPORT;
+
+ vuint8_t SSCM_reserved1[2]; /* Reserved 2 bytes (Base+0x000A-0x000B) */
+
+ union { /* Password Comparison High Word (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32;
+ } B;
+ } PWCMPH;
+
+ union { /* Password Comparison Low Word (Base+0x0010)*/
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32;
+ } B;
+ } PWCMPL;
+
+ vuint8_t SSCM_reserved2[4]; /* Reserved 4 bytes (Base+0x0014-0x0017) */
+
+ union { /* DPM Boot (Base+0x0018)*/
+ vuint32_t R;
+ struct {
+ vuint32_t PBOOT:30;
+ vuint32_t DVLE:1;
+ vuint32_t :1;
+ } B;
+ } DPMBOOT;
+
+ union { /* DPM Boot Key (Base+0x001C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t KEY:16;
+ } B;
+ } DPMKEY;
+
+ union { /* User option status (Base+0x0020)*/
+ vuint32_t R;
+ struct {
+ vuint32_t UOPT:32;
+ } B;
+ } UOPS;
+
+ vuint8_t SSCM_reserved3[4]; /* Reserved 4 bytes (Base+0x0024-0x0027) */
+
+ union { /* Processor Start Address (Base+0x0028)*/
+ vuint32_t R;
+ struct {
+ vuint32_t SADR:32;
+ } B;
+ } PSA;
+
+ union { /* Code Length (Base+0x002C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t CL:32;
+ } B;
+ } CLEN;
+
+
+
+}; /* end of SSCM_tag */
+/****************************************************************************/
+/* MODULE : ME */
+/****************************************************************************/
+struct ME_tag{
+
+ union { /* Global Status (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t S_CURRENTMODE:4;
+ vuint32_t S_MTRANS:1;
+ vuint32_t :1; /* vuint32_t S_DC:1; (Not on B3M) */
+ vuint32_t :2;
+ vuint32_t S_PDO:1;
+ vuint32_t :2;
+ vuint32_t S_MVR:1;
+ vuint32_t S_DFLA:2;
+ vuint32_t S_CFLA:2;
+ vuint32_t :9;
+ vuint32_t S_FMPLL:1;
+ vuint32_t S_FXOSC:1;
+ vuint32_t S_FIRC:1;
+ vuint32_t S_SYSCLK:4;
+ } B;
+ } GS;
+
+ union { /* Mode Control (Base+0x004) */
+ vuint32_t R;
+ struct {
+ vuint32_t TARGET_MODE:4;
+ vuint32_t :12;
+ vuint32_t KEY:16;
+ } B;
+ } MCTL;
+
+ union { /* Mode Enable (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RESET_DEST:1;
+ vuint32_t :1;
+ vuint32_t STANDBY:1;
+ vuint32_t :2;
+ vuint32_t STOP:1;
+ vuint32_t :1;
+ vuint32_t HALT:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } MER;
+
+ union { /* Interrupt Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t I_ICONF:1;
+ vuint32_t I_IMODE:1;
+ vuint32_t I_SAFE:1;
+ vuint32_t I_MTC:1;
+ } B;
+ } IS;
+
+ union { /* Interrupt Mask (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :27;
+ vuint32_t M_ICONF_CU:1;
+ vuint32_t M_ICONF:1;
+ vuint32_t M_IMODE:1;
+ vuint32_t M_SAFE:1;
+ vuint32_t M_MTC:1;
+ } B;
+ } IM;
+
+ union { /* Invalid Mode Transition Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :27;
+ vuint32_t S_MTI:1;
+ vuint32_t S_MRI:1;
+ vuint32_t S_DMA:1;
+ vuint32_t S_NMA:1;
+ vuint32_t S_SEA:1;
+ } B;
+ } IMTS;
+
+ union { /* Debug Mode Transition Status (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t PREVIOUS_MODE:4;
+ vuint32_t :4;
+ vuint32_t MPH_BUSY:1;
+ vuint32_t :2;
+ vuint32_t PMC_PROG:1;
+ vuint32_t CORE_DBG:1;
+ vuint32_t :2;
+ vuint32_t SMR:1;
+ vuint32_t :1;
+ vuint32_t VREG_CSRC_SC:1;
+ vuint32_t CSRC_CSRC_SC:1;
+ vuint32_t FIRC_SC:1;
+ vuint32_t SCSRC_SC:1;
+ vuint32_t SYSCLK_SW:1;
+ vuint32_t DFLASH_SC:1;
+ vuint32_t CFLASH_SC:1;
+ vuint32_t CDP_PRPH_0_143:1;
+ vuint32_t :3;
+ vuint32_t CDP_PRPH_96_127:1;
+ vuint32_t CDP_PRPH_64_95:1;
+ vuint32_t CDP_PRPH_32_63:1;
+ vuint32_t CDP_PRPH_0_31:1;
+ } B;
+ } DMTS;
+
+ vuint8_t ME_reserved0[4]; /* reserved 4 bytes (Base+0x001C-0x001F) */
+
+ union { /* Reset Mode Configuration (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RESET;
+
+ union { /* Test Mode Configuration (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } TEST;
+
+ union { /* Safe Mode Configuration (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } SAFE;
+
+ union { /* DRUN Mode Configuration (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } DRUN;
+
+ union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } RUN[4];
+
+ union { /* HALT Mode Configuration (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } HALT;
+
+ vuint8_t ME_reserved1[4]; /* reserved 4 bytes (Base+0x0044-0x0047) */
+
+ union { /* STOP Mode Configuration (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STOP;
+
+ vuint8_t ME_reserved2[8]; /* reserved 8 bytes (Base+0x004C-0x0053) */
+
+ union { /* STANDBY Mode Configuration (Base+0x0054) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t PDO:1;
+ vuint32_t :2;
+ vuint32_t MVRON:1;
+ vuint32_t DFLAON:2;
+ vuint32_t CFLAON:2;
+ vuint32_t :9;
+ vuint32_t FMPLLON:1;
+ vuint32_t FXOSC0ON:1;
+ vuint32_t FIRCON:1;
+ vuint32_t SYSCLK:4;
+ } B;
+ } STANDBY;
+
+ vuint8_t ME_reserved3[8]; /* reserved 8 bytes (Base+0x0058-0x005F) */
+
+ union {
+ vuint32_t R;
+ struct { /* Peripheral Status 0 (Base+0x0060) */
+ vuint32_t :7;
+ vuint32_t S_FLEXRAY:1;
+ vuint32_t S_DMA_CH_MUX:1;
+ vuint32_t :1;
+ vuint32_t S_FLEXCAN5:1;
+ vuint32_t S_FLEXCAN4:1;
+ vuint32_t S_FLEXCAN3:1;
+ vuint32_t S_FLEXCAN2:1;
+ vuint32_t S_FLEXCAN1:1;
+ vuint32_t S_FLEXCAN0:1;
+ vuint32_t :2;
+ vuint32_t S_LINFLEX9:1;
+ vuint32_t S_LINFLEX8:1;
+ vuint32_t S_DSPI7:1;
+ vuint32_t S_DSPI6:1;
+ vuint32_t S_DSPI5:1;
+ vuint32_t S_DSPI4:1;
+ vuint32_t S_DSPI3:1;
+ vuint32_t S_DSPI2:1;
+ vuint32_t S_DSPI1:1;
+ vuint32_t S_DSPI0:1;
+ vuint32_t :4;
+ } B;
+ } PS0;
+
+ union { /* Peripheral Status 1 (Base+0x0064)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t S_CANSAMPLER:1;
+ vuint32_t :2;
+ vuint32_t S_CTUL:1;
+ vuint32_t :1;
+ vuint32_t S_LINFLEX7:1;
+ vuint32_t S_LINFLEX6:1;
+ vuint32_t S_LINFLEX5:1;
+ vuint32_t S_LINFLEX4:1;
+ vuint32_t S_LINFLEX3:1;
+ vuint32_t S_LINFLEX2:1;
+ vuint32_t S_LINFLEX1:1;
+ vuint32_t S_LINFLEX0:1;
+ vuint32_t :3;
+ vuint32_t S_I2C:1;
+ vuint32_t :10;
+ vuint32_t S_ADC1:1;
+ vuint32_t S_ADC0:1;
+ } B;
+ } PS1;
+
+ union { /* Peripheral Status 2 (Base+0x0068) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t S_PIT_RTI:1;
+ vuint32_t S_RTC_API:1;
+ vuint32_t :16;
+ vuint32_t S_EMIOS1:1;
+ vuint32_t S_EMIOS0:1;
+ vuint32_t :2;
+ vuint32_t S_WKUP:1; /* Also called S_WKPU on B3M RM */
+ vuint32_t S_SIUL:1;
+ vuint32_t :4;
+ } B;
+ } PS2;
+
+ union { /* Peripheral Status 3 (Base+0x006C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t S_CMU:1;
+ vuint32_t :8;
+ } B;
+ } PS3;
+
+ vuint8_t ME_reserved4[16]; /* reserved 16 bytes (Base+0x0070-0x007F) */
+
+ union { /* RUN Peripheral Config 0..7 (+0x0080-009C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :24;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RESET:1;
+ } B;
+ } RUNPC[8];
+
+ union { /* Low Pwr Periph Config 0..7 (+0x00A0-0x00BC) */
+ vuint32_t R;
+ struct {
+ vuint32_t :18;
+ vuint32_t STANDBY:1;
+ vuint32_t :2;
+ vuint32_t STOP:1;
+ vuint32_t :1;
+ vuint32_t HALT:1;
+ vuint32_t :8;
+ } B;
+ } LPPC[8];
+
+
+ /* Note on PCTL registers: There are only some PCTL implemented in */
+ /* Bolero 3M. In order to make the PCTL easily addressable, these */
+ /* are defined as an array (ie ME.PCTL[x].R). This means you have */
+ /* to be careful when addressing these registers in order not to */
+ /* access a PCTL that is not implemented. Following are available: */
+ /* 104, 92, 91, 73, 72, 69, 68, 60, 57, 44, 33, 32, 24, 23, 21-16, 13-4*/
+
+ union { /* Peripheral Control 0..143 (+0x00C0-0x0128) */
+ vuint8_t R;
+ struct {
+ vuint8_t :1;
+ vuint8_t DBG_F:1;
+ vuint8_t LP_CFG:3;
+ vuint8_t RUN_CFG:3;
+ } B;
+ } PCTL[105];
+
+}; /* end of ME_tag */
+/****************************************************************************/
+/* MODULE : CGM */
+/****************************************************************************/
+struct CGM_tag{
+
+
+ /*
+
+ The "CGM" has fairly wide coverage and essentially includes everything in
+
+ chapter 3 of the Bolero 3M Reference Manual:
+
+
+
+ Base Address | Clock Sources
+
+ -----------------------------
+
+ 0xC3FE0000 | FXOSC_CTL
+
+ 0xC3FE0040 | SXOSC_CTL
+
+ 0xC3FE0060 | FIRC_CTL
+
+ 0xC3FE0080 | SIRC_CTL
+
+ 0xC3FE00A0 | FMPLL
+
+ 0xC3FE00C0 | CGM Block 1
+
+ 0xC3FE0100 | CMU
+
+ 0xC3FE0120 | CGM Block 2
+
+
+
+ In this header file, "Base" referrs to the 1st address, 0xC3FE_0000
+
+ */
+ /* FXOSC - 0xC3FE_0000*/
+ union { /* Fast OSC Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t :7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t :2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t:7;
+ } B;
+ } FXOSC_CTL;
+
+
+ /* Reserved Space between end of FXOSC and start SXOSC */
+ vuint8_t CGM_reserved0[60]; /* Reserved 60 bytes (Base+0x0004-0x003F) */
+
+
+ /* SXOSC - 0xC3FE_0040*/
+ union { /* Slow Osc Control (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1;
+ vuint32_t :7;
+ vuint32_t EOCV:8;
+ vuint32_t M_OSC:1;
+ vuint32_t :2;
+ vuint32_t OSCDIV:5;
+ vuint32_t I_OSC:1;
+ vuint32_t :5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1;
+ } B;
+ } SXOSC_CTL;
+
+
+ /* Reserved space between end of SXOSC and start of FIRC */
+ vuint8_t CGM_reserved1[28]; /*Reserved 28 bytes (Base+0x0044-0x005F) */
+
+
+ /* FIRC - 0x3CFE_0060 */
+ union { /* Fast IRC Control (Base+0x0060) */
+ vuint32_t R;
+ struct {
+ vuint32_t :10;
+ vuint32_t RCTRIM:6;
+ vuint32_t :3;
+ vuint32_t RCDIV:5;
+ vuint32_t :8;
+ } B;
+ } FIRC_CTL;
+
+
+ /* Reserved space between end of FIRC and start of SIRC */
+ vuint8_t CGM_reserved2[28]; /*Reserved 28 bytes (Base+0x0064-0x007F) */
+
+
+ /* SIRC - 0x3FE_0080 */
+ union { /* Slow IRC Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :11;
+ vuint32_t SIRCTRIM:5;
+ vuint32_t :3;
+ vuint32_t SIRCDIV:5;
+ vuint32_t :3;
+ vuint32_t S_SIRC:1;
+ vuint32_t :3;
+ vuint32_t SIRCON_STDBY:1;
+ } B;
+ } SIRC_CTL;
+
+
+ /* Reserved space between end of SIRC and start of FMPLL */
+ vuint8_t CGM_reserved3[28]; /*Reserved 28 bytes (Base+0x0084-0x009F) */
+
+
+ /* FMPLL - 0xC3FE_00A0 */
+ union { /* FMPLL Control (Base+0x00A0) */
+ vuint32_t R;
+ struct {
+ vuint32_t :2;
+ vuint32_t IDF:4;
+ vuint32_t ODF:2;
+ vuint32_t :1;
+ vuint32_t NDIV:7;
+ vuint32_t :7;
+ vuint32_t EN_PLL_SW:1;
+ vuint32_t MODE:1;
+ vuint32_t UNLOCK_ONCE:1;
+ vuint32_t :1;
+ vuint32_t I_LOCK:1;
+ vuint32_t S_LOCK:1;
+ vuint32_t PLL_FAIL_MASK:1;
+ vuint32_t PLL_FAIL_FLAG:1;
+ vuint32_t :1;
+ } B;
+ } FMPLL_CR;
+
+ union { /* FMPLL Modulation (Base+0x00A4) */
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1;
+ vuint32_t :1;
+ vuint32_t SPRD_SEL:1;
+ vuint32_t MOD_PERIOD:13;
+ vuint32_t FM_EN:1;
+ vuint32_t INC_STEP:15;
+ } B;
+ } FMPLL_MR;
+
+
+ /* Reserved space between end of FMPLL and start of CGM Block 1 */
+ vuint8_t CGM_reserved4[24]; /*Reserved 24 bytes (Base+0x00A8-0x00BF) */
+
+
+ /* CGM Block 1 - 0xC3FE_00C0 */
+ union { /* CMU Z0 Clock Divider Config (Base+0x00C0) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t DIV:1;
+ } B;
+ } Z0_DCR;
+
+ vuint8_t CGM_reserved5[31]; /*Reserved 31 bytes (Base+0x00C1-0x00DF) */
+
+ union { /* CMU FEC Clock Divider Config (Base+0x00E0) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t DIV:1;
+ } B;
+ } FEC_DCR;
+
+
+ /* Reserved space between end of CGM Block1 and start of CMU */
+ vuint8_t CGM_reserved6[31]; /*Reserved 31 bytes (Base+0x00E1-0x00FF) */
+
+
+ /* CMU - 0xC3FE_0100 */
+ union { /* CMU Control Status (Base+0x0100) */
+ vuint32_t R;
+ struct {
+ vuint32_t :8;
+ vuint32_t SFM:1;
+ vuint32_t :13;
+ vuint32_t CLKSEL1:2;
+ vuint32_t :5;
+ vuint32_t RCDIV:2;
+ vuint32_t CME_A:1;
+ } B;
+ } CMU_CSR;
+
+ union { /* CMU Frequency Display (Base+0x0104) */
+ vuint32_t R;
+ struct {
+ vuint32_t :12;
+ vuint32_t FD:20;
+ } B;
+ } CMU_FDR;
+
+ union { /* CMU High Freq Reference FMPLL (Base+0x0108) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t HFREF:12;
+ } B;
+ } CMU_HFREFR;
+
+ union { /* CMU Low Freq Reference FMPLL (Base+0x010C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t LFREF:12;
+ } B;
+ } CMU_LFREFR;
+
+ union { /* CMU Interrupt Status (Base+0x0110) */
+ vuint32_t R;
+ struct {
+ vuint32_t :29;
+ vuint32_t FHHI:1;
+ vuint32_t FLLI:1;
+ vuint32_t OLRI:1;
+ } B;
+ } CMU_ISR;
+
+
+ /* Note about CMU_IMR: On Bolero 3M this register will always read as 0 */
+ /* Commented out register definition is below but this register should */
+ /* not be accessed in Bolero 3M */
+
+ /* Reserved space where IMR was previously positioned */
+ vuint8_t CGM_reserved7[4]; /*Reserved 4 bytes (Base+0x0114-0x0117) */
+
+ /*union { Interrupt Mask Register Removed from Bolero3M (Read 0)
+
+ vuint32_t R;
+
+ struct {
+
+ vuint32_t :32;
+
+ } B;
+
+ } CMU_IMR; */
+ union { /* CMU Measurement Duration (Base+0x0118) */
+ vuint32_t R;
+ struct {
+ vuint32_t :12;
+ vuint32_t MD:20;
+ } B;
+ } CMU_MDR;
+
+
+ /* Reserved space between end of CMU and start of CGM Block 2 */
+ vuint8_t CGM_reserved8[4]; /*Reserved 4 bytes (Base+0x011C-0x011F) */
+
+
+ /* CGM - 0xC3FE0120 */
+ union { /* CGM Flash Clock Divider Config (Base+0x0120) */
+ vuint8_t R;
+ struct {
+ vuint8_t :7;
+ vuint8_t DIV:1;
+ } B;
+ } FLASH_DCR;
+
+ vuint8_t CGM_reserved9[591]; /*Reserved 591 bytes (Base+0x0121-0x036F) */
+
+ union { /* GCM Output Clock Enable (Base+0x0370) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t EN:1;
+ } B;
+ } OC_EN;
+
+ union { /* CGM Output Clock Division Sel (Base+0x0374) */
+ vuint8_t R;
+ struct {
+ vuint8_t :2;
+ vuint8_t SELDIV:2;
+ vuint8_t SELCTL:4;
+ } B;
+ } OCDS_SC;
+
+ vuint8_t CGM_reserved10[3]; /*Reserved 3 bytes (Base+0x0375-0x0377) */
+
+ union { /* CGM System Clock Select Status (Base+0x0378) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t SELSTAT:4;
+ vuint32_t :24;
+ } B;
+ } SC_SS;
+
+ union { /* CGM Sys Clk Div Config0 (Base+0x037C) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE0:1;
+ vuint8_t :3;
+ vuint8_t DIV0:4;
+ } B;
+ } SC_DC0;
+
+ union { /* CGM Sys Clk Div Config1 (Base+0x037D) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE1:1;
+ vuint8_t :3;
+ vuint8_t DIV1:4;
+ } B;
+ } SC_DC1;
+
+ union { /* CGM Sys Clk Div Config1 (Base+0x037E) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE2:1;
+ vuint8_t :3;
+ vuint8_t DIV2:4;
+ } B;
+ } SC_DC2;
+
+ vuint8_t CGM_reserved11[1]; /*Reserved 1 byte (Base+0x037F) */
+
+ union { /* CGM Aux Clock0 Select Control (+0x0380-0x383) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t SELCTL:4;
+ vuint32_t :24;
+ } B;
+ } AC0_SC;
+
+ vuint8_t CGM_reserved12[4]; /*Reserved 4 bytes (Base+0x0384-0x0387) */
+
+ union { /* CGM Aux Clock1 Select Control (Base+0x0388) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t SELCTL:4;
+ vuint32_t :24;
+ } B;
+ } AC1_SC;
+
+ union { /* CGM Aux Clock1 Divider 0 Config (Base+0x038C) */
+ vuint8_t R;
+ struct {
+ vuint8_t DE0:1;
+ vuint8_t :3;
+ vuint8_t DIV0:4;
+ } B;
+ } AC1_DC0;
+
+}; /* end of CGM_tag */
+/****************************************************************************/
+/* MODULE : RGM */
+/****************************************************************************/
+struct RGM_tag{
+
+ union { /* Functional Event Status (Base+0x0000) */
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1;
+ vuint16_t F_ST_NCF:1;
+ vuint16_t F_ST_CF:1;
+ vuint16_t F_ST_DONE:1;
+ vuint16_t :1;
+ vuint16_t F_Z4CORE:1;
+ vuint16_t :1;
+ vuint16_t F_FLASH:1;
+ vuint16_t F_LVD45:1;
+ vuint16_t F_CMU_FHL:1;
+ vuint16_t F_CMU_OLR:1;
+ vuint16_t F_FMPLL:1;
+ vuint16_t F_CHKSTOP:1;
+ vuint16_t F_SOFT_FUNC:1;
+ vuint16_t F_Z0CORE:1;
+ vuint16_t F_JTAG:1;
+ } B;
+ } FES;
+
+ union { /* Destructive Event Status (Base+0x0002) */
+ vuint16_t R;
+ struct {
+ vuint16_t F_POR:1;
+ vuint16_t F_SOFT_DEST:1;
+ vuint16_t :10;
+ vuint16_t F_LVD27:1;
+ vuint16_t F_SWT:1;
+ vuint16_t F_LVD12_PD1:1;
+ vuint16_t F_LVD12_PD0:1;
+ } B;
+ } DES;
+
+ union { /* Functional Event Reset Disable (+0x0004) */
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1;
+ vuint16_t D_ST_NCF:1;
+ vuint16_t D_ST_CF:1;
+ vuint16_t D_ST_DONE:1;
+ vuint16_t :1;
+ vuint16_t D_Z4CORE:1;
+ vuint16_t :1;
+ vuint16_t D_FLASH:1;
+ vuint16_t D_LVD45:1;
+ vuint16_t D_CMU_FHL:1;
+ vuint16_t D_CMU_OLR:1;
+ vuint16_t D_FMPLL:1;
+ vuint16_t D_CHKSTOP:1;
+ vuint16_t D_SOFT_FUNC:1;
+ vuint16_t D_Z0CORE:1;
+ vuint16_t D_JTAG:1;
+ } B;
+ } FERD;
+
+ union { /* Destructive Event Reset Disable (Base+0x0006)*/
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t D_SOFT_DEST:1;
+ vuint16_t :10;
+ vuint16_t D_LVD27:1;
+ vuint16_t D_SWT:1;
+ vuint16_t D_LVD12_PD1:1;
+ vuint16_t D_LVD12_PD0:1;
+ } B;
+ } DERD;
+
+ vuint8_t RGM_reserved0[8]; /*Reserved 8 bytes (Base+0x008-0x000F) */
+
+ union { /* Functional Event Alt Request (Base+0x0010) */
+ vuint16_t R;
+ struct {
+ vuint16_t :1;
+ vuint16_t AR_ST_NCF:1;
+ vuint16_t AR_ST_CF:1;
+ vuint16_t :2;
+ vuint16_t AR_Z4CORE:1;
+ vuint16_t :2;
+ vuint16_t AR_LVD45:1;
+ vuint16_t AR_CMU_FHL:1;
+ vuint16_t AR_CMU_OLR:1;
+ vuint16_t AR_FMPLL:1;
+ vuint16_t :2;
+ vuint16_t AR_Z0CORE:1;
+ vuint16_t AR_JTAG:1;
+ } B;
+ } FEAR;
+
+ vuint8_t RGM_reserved1[6]; /*Reserved 6 bytes (Base+0x0012-0x0017) */
+
+ union { /* Functional Event Short Sequence (+0x0018) */
+ vuint16_t R;
+ struct {
+ vuint16_t SS_EXR:1;
+ vuint16_t :2;
+ vuint16_t SS_ST_DONE:1;
+ vuint16_t :1;
+ vuint16_t SS_Z4CORE:1;
+ vuint16_t :1;
+ vuint16_t SS_FLASH:1;
+ vuint16_t SS_LVD45:1;
+ vuint16_t SS_CMU_FHL:1;
+ vuint16_t SS_CMU_OLR:1;
+ vuint16_t SS_FMPLL:1;
+ vuint16_t SS_CHKSTOP:1;
+ vuint16_t SS_SOFT_FUNC:1;
+ vuint16_t SS_Z0CORE:1;
+ vuint16_t SS_JTAG:1;
+ } B;
+ } FESS;
+
+ union { /* STANDBY reset sequence (Base+0x001A) */
+ vuint16_t R;
+ struct {
+ vuint16_t :7;
+ vuint16_t SB_CPU:1;
+ vuint16_t BOOT_FROM_BKP_RAM:1;
+ vuint16_t :7;
+ } B;
+ } STDBY;
+
+ union { /* Functional Bidirectional Reset En (+0x001C) */
+ vuint16_t R;
+ struct {
+ vuint16_t BE_EXR:1;
+ vuint16_t :2;
+ vuint16_t BE_ST_DONE:1;
+ vuint16_t :1;
+ vuint16_t BE_Z4CORE:1;
+ vuint16_t :1;
+ vuint16_t BE_FLASH:1;
+ vuint16_t BE_LVD45:1;
+ vuint16_t BE_CMU_FHL:1;
+ vuint16_t BE_CMU_OLR:1;
+ vuint16_t BE_FMPLL:1;
+ vuint16_t BE_CHKSTOP:1;
+ vuint16_t BE_SOFT_FUNC:1;
+ vuint16_t BE_Z0CORE:1;
+ vuint16_t BE_JTAG:1;
+ } B;
+ } FBRE;
+
+}; /* end of RGM_tag */
+/****************************************************************************/
+/* MODULE : PCU */
+/****************************************************************************/
+struct PCU_tag{
+
+ union { /* PCU Power domain 0-3 config (+0x0000-0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :18;
+ vuint32_t STBY:1;
+ vuint32_t :2;
+ vuint32_t STOP:1;
+ vuint32_t :1;
+ vuint32_t HALT:1;
+ vuint32_t RUN3:1;
+ vuint32_t RUN2:1;
+ vuint32_t RUN1:1;
+ vuint32_t RUN0:1;
+ vuint32_t DRUN:1;
+ vuint32_t SAFE:1;
+ vuint32_t TEST:1;
+ vuint32_t RST:1;
+ } B;
+ } PCONF[4];
+
+ vuint8_t PCU_reserved0[48]; /* Reserved 48 bytes (Base+0x0010-0x003F) */
+
+ union { /* PCU Power Domain Status (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t :28;
+ vuint32_t PD3:1;
+ vuint32_t PD2:1;
+ vuint32_t PD1:1;
+ vuint32_t PD0:1;
+ } B;
+ } PSTAT;
+
+ vuint8_t PCU_reserved1[60]; /* Reserved 60 bytes (Base+0x0044-0x007F) */
+
+
+ /* Following registers are from Voltage Regulators chapter of RM */
+
+ union { /* PCU Voltage Regulator Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t MASK_LVDHV5:1;
+ } B;
+ } VREG_CTL; /* Changed from VCTL for consistency with other regs here */
+
+ union { /* PCU PDMODE (Base+0x0084) */
+ vuint32_t R;
+ struct {
+ vuint32_t :15;
+ vuint32_t PORPU:1;
+ vuint32_t :15;
+ vuint32_t PDMODE:1;
+ } B;
+ } VREG_PDMODE;
+
+
+}; /* end of PCU_tag */
+/****************************************************************************/
+/* MODULE : RTC/API */
+/****************************************************************************/
+struct RTC_tag{
+
+ union { /* RTC Supervisor Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t SUPV:1;
+ vuint32_t :31;
+ } B;
+ } RTCSUPV ;
+
+ union { /* RTC Control (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t CNTEN:1;
+ vuint32_t RTCIE:1;
+ vuint32_t FRZEN:1;
+ vuint32_t ROVREN:1;
+ vuint32_t RTCVAL:12;
+ vuint32_t APIEN:1;
+ vuint32_t APIIE:1;
+ vuint32_t CLKSEL:2;
+ vuint32_t DIV512EN:1;
+ vuint32_t DIV32EN:1;
+ vuint32_t APIVAL:10;
+ } B;
+ } RTCC;
+
+ union { /* RTC Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :2;
+ vuint32_t RTCF:1;
+ vuint32_t :15;
+ vuint32_t APIF:1;
+ vuint32_t :2;
+ vuint32_t ROVRF:1;
+ vuint32_t :10;
+ } B;
+ } RTCS;
+
+ union { /* RTC Counter (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t RTCCNT:32;
+ } B;
+ } RTCCNT;
+
+}; /* end of RTC_tag */
+/****************************************************************************/
+/* MODULE : pit */
+/****************************************************************************/
+struct PIT_tag {
+
+ union { /* PIT Module Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t MDIS_RTI:1;
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ } B;
+ } PITMCR;
+
+ vuint8_t PIT_reserved0[236]; /* Reserved 236 Bytes (Base+0x0004-0x00EF) */
+
+
+ /* RTI Config Registers (Base + 0x00F0-0x00FF) */
+ struct {
+
+ union { /* RTI Timer Load Value (Offset+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union { /* RTI Current Timer Value (Offset+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union { /* RTI Timer Control (Offset+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union { /* RTI Timer Flag (Offset+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+
+ }RTI; /* End of RTI registers */
+
+
+ /* PIT Timer Channels 0..7 (Base+0x0100-0x017C) */
+ struct {
+
+ union { /* PIT Timer Load Value (Offset+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32;
+ } B;
+ } LDVAL;
+
+ union { /* PIT Current Timer Value (Offset+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32;
+ } B;
+ } CVAL;
+
+ union { /* PIT Timer Control (Offset+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :30;
+ vuint32_t TIE:1;
+ vuint32_t TEN:1;
+ } B;
+ } TCTRL;
+
+ union { /* PIT Timer Flag (Offset+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t TIF:1;
+ } B;
+ } TFLG;
+
+ }CH[8]; /* End of PIT Timer Channels */
+
+}; /* end of PIT_tag */
+/****************************************************************************/
+/* MODULE : STCU (Self-Test Control Unit) */
+/****************************************************************************/
+struct STCU_tag {
+
+ union { /* STCU Run (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t RUN:1;
+ } B;
+ } RUN;
+
+ vuint8_t STCU_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* STCU SK Code (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t SKC:32;
+ } B;
+ } SKC;
+
+ union { /* STCU Config (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :1;
+ vuint32_t PTR:7;
+ vuint32_t :20;
+ vuint32_t CLK_CFG:4;
+ } B;
+ } CFG;
+
+ union { /* STCU Watchdog Granularity (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :29;
+ vuint32_t GMBIST:3;
+ } B;
+ } WDGG;
+
+ union { /* STCU CRC Expected Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t CRCE:32;
+ } B;
+ } CRCE;
+
+ union { /* STCU CRC Read Status (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t CRCR:32;
+ } B;
+ } CRCR;
+
+ union { /* STCU Error (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t WDTOSFM:1;
+ vuint32_t CRCSSFM:1;
+ vuint32_t ENGESFM:1;
+ vuint32_t INVPSFM:1;
+ vuint32_t :4;
+ vuint32_t WDTOCFM:1;
+ vuint32_t CRCSCFM:1;
+ vuint32_t ENGECFM:1;
+ vuint32_t INVPCFM:1;
+ vuint32_t :5;
+ vuint32_t CFSF:1;
+ vuint32_t NCFSF:1;
+ vuint32_t SIRSF:1;
+ vuint32_t :4;
+ vuint32_t WDTO:1;
+ vuint32_t CRCS:1;
+ vuint32_t ENGE:1;
+ vuint32_t INVP:1;
+ } B;
+ } ERR;
+
+ union { /* STCU Error Key (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t ERR_SK:32;
+ } B;
+ } ERRK;
+
+ vuint8_t STCU_reserved1[24]; /* Reserved 24 bytes (Base+0x0024-0x003B) */
+
+ union { /* STCU MBIST Status Low (Base+0x003C) */
+ vuint32_t R;
+ struct {
+ vuint32_t MBS31:1;
+ vuint32_t MBS30:1;
+ vuint32_t MBS29:1;
+ vuint32_t MBS28:1;
+ vuint32_t MBS27:1;
+ vuint32_t MBS26:1;
+ vuint32_t MBS25:1;
+ vuint32_t MBS24:1;
+ vuint32_t MBS23:1;
+ vuint32_t MBS22:1;
+ vuint32_t MBS21:1;
+ vuint32_t MBS20:1;
+ vuint32_t MBS19:1;
+ vuint32_t MBS18:1;
+ vuint32_t MBS17:1;
+ vuint32_t MBS16:1;
+ vuint32_t MBS15:1;
+ vuint32_t MBS14:1;
+ vuint32_t MBS13:1;
+ vuint32_t MBS12:1;
+ vuint32_t MBS11:1;
+ vuint32_t MBS10:1;
+ vuint32_t MBS9:1;
+ vuint32_t MBS8:1;
+ vuint32_t MBS7:1;
+ vuint32_t MBS6:1;
+ vuint32_t MBS5:1;
+ vuint32_t MBS4:1;
+ vuint32_t MBS3:1;
+ vuint32_t MBS2:1;
+ vuint32_t MBS1:1;
+ vuint32_t MBS0:1;
+ } B;
+ } MBSL;
+
+ union { /* STCU MBIST Status High (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t MBS40:1;
+ vuint32_t MBS39:1;
+ vuint32_t MBS38:1;
+ vuint32_t MBS37:1;
+ vuint32_t MBS36:1;
+ vuint32_t MBS35:1;
+ vuint32_t MBS34:1;
+ vuint32_t MBS33:1;
+ vuint32_t MBS32:1;
+ } B;
+ } MBSH;
+
+ union { /* STCU MBIST End Flag Low (Base+0x0044) */
+ vuint32_t R;
+ struct {
+ vuint32_t MBE31:1;
+ vuint32_t MBE30:1;
+ vuint32_t MBE29:1;
+ vuint32_t MBE28:1;
+ vuint32_t MBE27:1;
+ vuint32_t MBE26:1;
+ vuint32_t MBE25:1;
+ vuint32_t MBE24:1;
+ vuint32_t MBE23:1;
+ vuint32_t MBE22:1;
+ vuint32_t MBE21:1;
+ vuint32_t MBE20:1;
+ vuint32_t MBE19:1;
+ vuint32_t MBE18:1;
+ vuint32_t MBE17:1;
+ vuint32_t MBE16:1;
+ vuint32_t MBE15:1;
+ vuint32_t MBE14:1;
+ vuint32_t MBE13:1;
+ vuint32_t MBE12:1;
+ vuint32_t MBE11:1;
+ vuint32_t MBE10:1;
+ vuint32_t MBE9:1;
+ vuint32_t MBE8:1;
+ vuint32_t MBE7:1;
+ vuint32_t MBE6:1;
+ vuint32_t MBE5:1;
+ vuint32_t MBE4:1;
+ vuint32_t MBE3:1;
+ vuint32_t MBE2:1;
+ vuint32_t MBE1:1;
+ vuint32_t MBE0:1;
+ } B;
+ } MBEL;
+
+ union { /* STCU MBIST End Flag High (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t MBE40:1;
+ vuint32_t MBE39:1;
+ vuint32_t MBE38:1;
+ vuint32_t MBE37:1;
+ vuint32_t MBE36:1;
+ vuint32_t MBE35:1;
+ vuint32_t MBE34:1;
+ vuint32_t MBE33:1;
+ vuint32_t MBE32:1;
+ } B;
+ } MBEH;
+
+ union { /* STCU MBIST Status End Key (Base+0x004C) */
+ vuint32_t R;
+ struct {
+ vuint32_t MBSEK:32;
+ } B;
+ } MBSEK;
+
+ union { /* STCU MBIST Critical FM Low (Base+0x0050) */
+ vuint32_t R;
+ struct {
+ vuint32_t MBCFM31:1;
+ vuint32_t MBCFM30:1;
+ vuint32_t MBCFM29:1;
+ vuint32_t MBCFM28:1;
+ vuint32_t MBCFM27:1;
+ vuint32_t MBCFM26:1;
+ vuint32_t MBCFM25:1;
+ vuint32_t MBCFM24:1;
+ vuint32_t MBCFM23:1;
+ vuint32_t MBCFM22:1;
+ vuint32_t MBCFM21:1;
+ vuint32_t MBCFM20:1;
+ vuint32_t MBCFM19:1;
+ vuint32_t MBCFM18:1;
+ vuint32_t MBCFM17:1;
+ vuint32_t MBCFM16:1;
+ vuint32_t MBCFM15:1;
+ vuint32_t MBCFM14:1;
+ vuint32_t MBCFM13:1;
+ vuint32_t MBCFM12:1;
+ vuint32_t MBCFM11:1;
+ vuint32_t MBCFM10:1;
+ vuint32_t MBCFM9:1;
+ vuint32_t MBCFM8:1;
+ vuint32_t MBCFM7:1;
+ vuint32_t MBCFM6:1;
+ vuint32_t MBCFM5:1;
+ vuint32_t MBCFM4:1;
+ vuint32_t MBCFM3:1;
+ vuint32_t MBCFM2:1;
+ vuint32_t MBCFM1:1;
+ vuint32_t MBCFM0:1;
+ } B;
+ } MBCFML;
+
+ union { /* STCU MBIST Critical FM High (Base+0x0054) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t MBCFM40:1;
+ vuint32_t MBCFM39:1;
+ vuint32_t MBCFM38:1;
+ vuint32_t MBCFM37:1;
+ vuint32_t MBCFM36:1;
+ vuint32_t MBCFM35:1;
+ vuint32_t MBCFM34:1;
+ vuint32_t MBCFM33:1;
+ vuint32_t MBCFM32:1;
+ } B;
+ } MBCFMH;
+
+ union { /* STCU MBIST Stay-In-Reset FM Low (Base+0x0058)*/
+ vuint32_t R;
+ struct {
+ vuint32_t MBSFM31:1;
+ vuint32_t MBSFM30:1;
+ vuint32_t MBSFM29:1;
+ vuint32_t MBSFM28:1;
+ vuint32_t MBSFM27:1;
+ vuint32_t MBSFM26:1;
+ vuint32_t MBSFM25:1;
+ vuint32_t MBSFM24:1;
+ vuint32_t MBSFM23:1;
+ vuint32_t MBSFM22:1;
+ vuint32_t MBSFM21:1;
+ vuint32_t MBSFM20:1;
+ vuint32_t MBSFM19:1;
+ vuint32_t MBSFM18:1;
+ vuint32_t MBSFM17:1;
+ vuint32_t MBSFM16:1;
+ vuint32_t MBSFM15:1;
+ vuint32_t MBSFM14:1;
+ vuint32_t MBSFM13:1;
+ vuint32_t MBSFM12:1;
+ vuint32_t MBSFM11:1;
+ vuint32_t MBSFM10:1;
+ vuint32_t MBSFM9:1;
+ vuint32_t MBSFM8:1;
+ vuint32_t MBSFM7:1;
+ vuint32_t MBSFM6:1;
+ vuint32_t MBSFM5:1;
+ vuint32_t MBSFM4:1;
+ vuint32_t MBSFM3:1;
+ vuint32_t MBSFM2:1;
+ vuint32_t MBSFM1:1;
+ vuint32_t MBSFM0:1;
+ } B;
+ } MBSFML;
+
+ union { /* STCU MBIST Stay-In-Reset FM High (Base+0x005C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t MBSFM40:1;
+ vuint32_t MBSFM39:1;
+ vuint32_t MBSFM38:1;
+ vuint32_t MBSFM37:1;
+ vuint32_t MBSFM36:1;
+ vuint32_t MBSFM35:1;
+ vuint32_t MBSFM34:1;
+ vuint32_t MBSFM33:1;
+ vuint32_t MBSFM32:1;
+ } B;
+ } MBSFMH;
+
+ union { /* STCU MBIST FM Key (Base+0x0060) */
+ vuint32_t R;
+ struct {
+ vuint32_t MBFMK:32;
+ } B;
+ } MBFMK;
+
+ vuint8_t STCU_reserved2[668]; /*Reserved 668 bytes (Base+0x0064-0x02FF) */
+
+ union { /* STCU MBIST Comtrol (Base+0x0300) */
+ vuint32_t R;
+ struct {
+ vuint32_t :1;
+ vuint32_t PTR:7;
+ vuint32_t :2;
+ vuint32_t MB_TIME:6;
+ vuint32_t :16;
+ } B;
+ } MBCTRL[41];
+
+
+}; /* end of STCU_tag */
+/****************************************************************************/
+/* MODULE : ADC0 (10 Bit) */
+/* CH[0..15], CH[32..95] */
+/****************************************************************************/
+struct ADC0_tag {
+
+ union { /* ADC0 Main Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t EDGLEV:1;
+ vuint32_t TRGEN:1;
+ vuint32_t EDGE:1;
+ vuint32_t XSTRTEN:1;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:9;
+ vuint32_t ABORT_CHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:2;
+ vuint32_t:2;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR;
+
+ union { /* ADC0 Main Status (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:2;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR;
+
+ vuint8_t ADC0_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
+
+ union { /* ADC0 Interrupt Status (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ //vuint32_t OFFCANCOVR:1;
+ //vuint32_t EOFFSET:1;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR;
+
+ union { /* ADC0 Channel Pending 0 (Base+0x0014) */
+ vuint32_t R; /* (For precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR0;
+
+ union { /* ADC0 Channel Pending 1 (Base+0x0018) */
+ vuint32_t R; /* (For standard Channels) */
+ struct {
+ vuint32_t EOC_CH63:1;
+ vuint32_t EOC_CH62:1;
+ vuint32_t EOC_CH61:1;
+ vuint32_t EOC_CH60:1;
+ vuint32_t EOC_CH59:1;
+ vuint32_t EOC_CH58:1;
+ vuint32_t EOC_CH57:1;
+ vuint32_t EOC_CH56:1;
+ vuint32_t EOC_CH55:1;
+ vuint32_t EOC_CH54:1;
+ vuint32_t EOC_CH53:1;
+ vuint32_t EOC_CH52:1;
+ vuint32_t EOC_CH51:1;
+ vuint32_t EOC_CH50:1;
+ vuint32_t EOC_CH49:1;
+ vuint32_t EOC_CH48:1;
+ vuint32_t EOC_CH47:1;
+ vuint32_t EOC_CH46:1;
+ vuint32_t EOC_CH45:1;
+ vuint32_t EOC_CH44:1;
+ vuint32_t EOC_CH43:1;
+ vuint32_t EOC_CH42:1;
+ vuint32_t EOC_CH41:1;
+ vuint32_t EOC_CH40:1;
+ vuint32_t EOC_CH39:1;
+ vuint32_t EOC_CH38:1;
+ vuint32_t EOC_CH37:1;
+ vuint32_t EOC_CH36:1;
+ vuint32_t EOC_CH35:1;
+ vuint32_t EOC_CH34:1;
+ vuint32_t EOC_CH33:1;
+ vuint32_t EOC_CH32:1;
+ } B;
+ } CE0CFR1;
+
+ union { /* ADC0 Channel Pending 2 (Base+0x001C) */
+ vuint32_t R; /* (For external mux'd Channels) */
+ struct {
+ vuint32_t EOC_CH95:1;
+ vuint32_t EOC_CH94:1;
+ vuint32_t EOC_CH93:1;
+ vuint32_t EOC_CH92:1;
+ vuint32_t EOC_CH91:1;
+ vuint32_t EOC_CH90:1;
+ vuint32_t EOC_CH89:1;
+ vuint32_t EOC_CH88:1;
+ vuint32_t EOC_CH87:1;
+ vuint32_t EOC_CH86:1;
+ vuint32_t EOC_CH85:1;
+ vuint32_t EOC_CH84:1;
+ vuint32_t EOC_CH83:1;
+ vuint32_t EOC_CH82:1;
+ vuint32_t EOC_CH81:1;
+ vuint32_t EOC_CH80:1;
+ vuint32_t EOC_CH79:1;
+ vuint32_t EOC_CH78:1;
+ vuint32_t EOC_CH77:1;
+ vuint32_t EOC_CH76:1;
+ vuint32_t EOC_CH75:1;
+ vuint32_t EOC_CH74:1;
+ vuint32_t EOC_CH73:1;
+ vuint32_t EOC_CH72:1;
+ vuint32_t EOC_CH71:1;
+ vuint32_t EOC_CH70:1;
+ vuint32_t EOC_CH69:1;
+ vuint32_t EOC_CH68:1;
+ vuint32_t EOC_CH67:1;
+ vuint32_t EOC_CH66:1;
+ vuint32_t EOC_CH65:1;
+ vuint32_t EOC_CH64:1;
+ } B;
+ } CE0CFR2;
+
+ union { /* ADC0 Interrupt Mask (Base+0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR;
+
+ union { /* ADC0 Channel Interrupt Mask 0 (Base+0x0024) */
+ vuint32_t R; /* (For Precision Channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0;
+
+ union { /* ADC0 Channel Interrupt Mask 1 (+0x0028) */
+ vuint32_t R; /* (For Standard Channels) */
+ struct {
+ vuint32_t CIM63:1;
+ vuint32_t CIM62:1;
+ vuint32_t CIM61:1;
+ vuint32_t CIM60:1;
+ vuint32_t CIM59:1;
+ vuint32_t CIM58:1;
+ vuint32_t CIM57:1;
+ vuint32_t CIM56:1;
+ vuint32_t CIM55:1;
+ vuint32_t CIM54:1;
+ vuint32_t CIM53:1;
+ vuint32_t CIM52:1;
+ vuint32_t CIM51:1;
+ vuint32_t CIM50:1;
+ vuint32_t CIM49:1;
+ vuint32_t CIM48:1;
+ vuint32_t CIM47:1;
+ vuint32_t CIM46:1;
+ vuint32_t CIM45:1;
+ vuint32_t CIM44:1;
+ vuint32_t CIM43:1;
+ vuint32_t CIM42:1;
+ vuint32_t CIM41:1;
+ vuint32_t CIM40:1;
+ vuint32_t CIM39:1;
+ vuint32_t CIM38:1;
+ vuint32_t CIM37:1;
+ vuint32_t CIM36:1;
+ vuint32_t CIM35:1;
+ vuint32_t CIM34:1;
+ vuint32_t CIM33:1;
+ vuint32_t CIM32:1;
+ } B;
+ } CIMR1;
+
+ union { /* ADC0 Channel Interrupt Mask 2 (+0x002C) */
+ vuint32_t R; /* (For PExternal Mux'd Channels) */
+ struct {
+ vuint32_t CIM95:1;
+ vuint32_t CIM94:1;
+ vuint32_t CIM93:1;
+ vuint32_t CIM92:1;
+ vuint32_t CIM91:1;
+ vuint32_t CIM90:1;
+ vuint32_t CIM89:1;
+ vuint32_t CIM88:1;
+ vuint32_t CIM87:1;
+ vuint32_t CIM86:1;
+ vuint32_t CIM85:1;
+ vuint32_t CIM84:1;
+ vuint32_t CIM83:1;
+ vuint32_t CIM82:1;
+ vuint32_t CIM81:1;
+ vuint32_t CIM80:1;
+ vuint32_t CIM79:1;
+ vuint32_t CIM78:1;
+ vuint32_t CIM77:1;
+ vuint32_t CIM76:1;
+ vuint32_t CIM75:1;
+ vuint32_t CIM74:1;
+ vuint32_t CIM73:1;
+ vuint32_t CIM72:1;
+ vuint32_t CIM71:1;
+ vuint32_t CIM70:1;
+ vuint32_t CIM69:1;
+ vuint32_t CIM68:1;
+ vuint32_t CIM67:1;
+ vuint32_t CIM66:1;
+ vuint32_t CIM65:1;
+ vuint32_t CIM64:1;
+ } B;
+ } CIMR2;
+
+ union { /* ADC0 Watchdog Threshold Interrupt Status (+0x0030)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t WDG5H:1;
+ vuint32_t WDG5L:1;
+ vuint32_t WDG4H:1;
+ vuint32_t WDG4L:1;
+ vuint32_t WDG3H:1;
+ vuint32_t WDG3L:1;
+ vuint32_t WDG2H:1;
+ vuint32_t WDG2L:1;
+ vuint32_t WDG1H:1;
+ vuint32_t WDG1L:1;
+ vuint32_t WDG0H:1;
+ vuint32_t WDG0L:1;
+ } B;
+ } WTISR;
+
+ union { /* ADC0 Watchdog Threshold Interrupt Mask (+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t MSKWDG5H:1;
+ vuint32_t MSKWDG5L:1;
+ vuint32_t MSKWDG4H:1;
+ vuint32_t MSKWDG4L:1;
+ vuint32_t MSKWDG3H:1;
+ vuint32_t MSKWDG3L:1;
+ vuint32_t MSKWDG2H:1;
+ vuint32_t MSKWDG2L:1;
+ vuint32_t MSKWDG1H:1;
+ vuint32_t MSKWDG1L:1;
+ vuint32_t MSKWDG0H:1;
+ vuint32_t MSKWDG0L:1;
+ } B;
+ } WTIMR;
+
+ vuint8_t ADC0_reserved1[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
+
+ union { /* ADC0 DMA Enable (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE;
+
+ union { /* ADC0 DMA Channel Select 0 (Base+0x0044) */
+ vuint32_t R; /* (for precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0;
+
+ union { /* ADC0 DMA Channel Select 1 (Base+0x0048) */
+ vuint32_t R; /* (for standard channels) */
+ struct {
+ vuint32_t DMA63:1;
+ vuint32_t DMA62:1;
+ vuint32_t DMA61:1;
+ vuint32_t DMA60:1;
+ vuint32_t DMA59:1;
+ vuint32_t DMA58:1;
+ vuint32_t DMA57:1;
+ vuint32_t DMA56:1;
+ vuint32_t DMA55:1;
+ vuint32_t DMA54:1;
+ vuint32_t DMA53:1;
+ vuint32_t DMA52:1;
+ vuint32_t DMA51:1;
+ vuint32_t DMA50:1;
+ vuint32_t DMA49:1;
+ vuint32_t DMA48:1;
+ vuint32_t DMA47:1;
+ vuint32_t DMA46:1;
+ vuint32_t DMA45:1;
+ vuint32_t DMA44:1;
+ vuint32_t DMA43:1;
+ vuint32_t DMA42:1;
+ vuint32_t DMA41:1;
+ vuint32_t DMA40:1;
+ vuint32_t DMA39:1;
+ vuint32_t DMA38:1;
+ vuint32_t DMA37:1;
+ vuint32_t DMA36:1;
+ vuint32_t DMA35:1;
+ vuint32_t DMA34:1;
+ vuint32_t DMA33:1;
+ vuint32_t DMA32:1;
+ } B;
+ } DMAR1;
+
+ union { /* ADC0 DMA Channel Select 2 (Base+0x004C) */
+ vuint32_t R; /* (for external mux'd channels) */
+ struct {
+ vuint32_t DMA95:1;
+ vuint32_t DMA94:1;
+ vuint32_t DMA93:1;
+ vuint32_t DMA92:1;
+ vuint32_t DMA91:1;
+ vuint32_t DMA90:1;
+ vuint32_t DMA89:1;
+ vuint32_t DMA88:1;
+ vuint32_t DMA87:1;
+ vuint32_t DMA86:1;
+ vuint32_t DMA85:1;
+ vuint32_t DMA84:1;
+ vuint32_t DMA83:1;
+ vuint32_t DMA82:1;
+ vuint32_t DMA81:1;
+ vuint32_t DMA80:1;
+ vuint32_t DMA79:1;
+ vuint32_t DMA78:1;
+ vuint32_t DMA77:1;
+ vuint32_t DMA76:1;
+ vuint32_t DMA75:1;
+ vuint32_t DMA74:1;
+ vuint32_t DMA73:1;
+ vuint32_t DMA72:1;
+ vuint32_t DMA71:1;
+ vuint32_t DMA70:1;
+ vuint32_t DMA69:1;
+ vuint32_t DMA68:1;
+ vuint32_t DMA67:1;
+ vuint32_t DMA66:1;
+ vuint32_t DMA65:1;
+ vuint32_t DMA64:1;
+ } B;
+ } DMAR2;
+
+ vuint8_t ADC0_reserved2[16]; /* Reserved 16 bytes (Base+0x0050-0x005F) */
+
+ /* Note the threshold registers are split [0..3] then [4..5]. For this */
+ /* reason thay are NOT implemented as an array in order to maintain */
+ /* concistency through all THRHLR registers */
+
+ union { /* ADC0 Threshold 0 (Base+0x0060) */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR0;
+
+ union { /* ADC0 Threshold 1 (Base+0x0064) */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR1;
+
+ union { /* ADC0 Threshold 2 (Base+0x0068) */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR2;
+
+ union { /* ADC0 Threshold 3 (Base+0x006C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR3;
+
+ vuint8_t ADC0_reserved3[16]; /* Reserved 16 bytes (Base+0x0070-0x007F) */
+
+ union { /* ADC0 Presampling Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR;
+
+ union { /* ADC0 Presampling 0 (Base+0x0084) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0;
+
+ union { /* ADC0 Presampling 1 (Base+0x0088) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t PRES63:1;
+ vuint32_t PRES62:1;
+ vuint32_t PRES61:1;
+ vuint32_t PRES60:1;
+ vuint32_t PRES59:1;
+ vuint32_t PRES58:1;
+ vuint32_t PRES57:1;
+ vuint32_t PRES56:1;
+ vuint32_t PRES55:1;
+ vuint32_t PRES54:1;
+ vuint32_t PRES53:1;
+ vuint32_t PRES52:1;
+ vuint32_t PRES51:1;
+ vuint32_t PRES50:1;
+ vuint32_t PRES49:1;
+ vuint32_t PRES48:1;
+ vuint32_t PRES47:1;
+ vuint32_t PRES46:1;
+ vuint32_t PRES45:1;
+ vuint32_t PRES44:1;
+ vuint32_t PRES43:1;
+ vuint32_t PRES42:1;
+ vuint32_t PRES41:1;
+ vuint32_t PRES40:1;
+ vuint32_t PRES39:1;
+ vuint32_t PRES38:1;
+ vuint32_t PRES37:1;
+ vuint32_t PRES36:1;
+ vuint32_t PRES35:1;
+ vuint32_t PRES34:1;
+ vuint32_t PRES33:1;
+ vuint32_t PRES32:1;
+ } B;
+ } PSR1;
+
+ union { /* ADC0 Presampling 2 (Base+0x008C) */
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t PRES95:1;
+ vuint32_t PRES94:1;
+ vuint32_t PRES93:1;
+ vuint32_t PRES92:1;
+ vuint32_t PRES91:1;
+ vuint32_t PRES90:1;
+ vuint32_t PRES89:1;
+ vuint32_t PRES88:1;
+ vuint32_t PRES87:1;
+ vuint32_t PRES86:1;
+ vuint32_t PRES85:1;
+ vuint32_t PRES84:1;
+ vuint32_t PRES83:1;
+ vuint32_t PRES82:1;
+ vuint32_t PRES81:1;
+ vuint32_t PRES80:1;
+ vuint32_t PRES79:1;
+ vuint32_t PRES78:1;
+ vuint32_t PRES77:1;
+ vuint32_t PRES76:1;
+ vuint32_t PRES75:1;
+ vuint32_t PRES74:1;
+ vuint32_t PRES73:1;
+ vuint32_t PRES72:1;
+ vuint32_t PRES71:1;
+ vuint32_t PRES70:1;
+ vuint32_t PRES69:1;
+ vuint32_t PRES68:1;
+ vuint32_t PRES67:1;
+ vuint32_t PRES66:1;
+ vuint32_t PRES65:1;
+ vuint32_t PRES64:1;
+ } B;
+ } PSR2;
+
+ vuint8_t ADC0_reserved4[4]; /* Reserved 4 bytes (Base+0x0090-0x0093) */
+
+ /* Note the following CTR registers are NOT implemented as an array to */
+ /* try and maintain some concistency through the header file */
+ /* (The registers are however identical) */
+
+ union { /* ADC0 Conversion Timing 0 (Base+0x0094) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2;
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0;
+
+ union { /* ADC0 Conversion Timing 1 (Base+0x0098) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2;
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1;
+
+ union { /* ADC0 Conversion Timing 2 (Base+0x009C) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2;
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR2;
+
+ vuint8_t ADC0_reserved5[4]; /* Reserved 4 bytes (Base+0x00A0-0x00A3) */
+
+ union { /* ADC0 Normal Conversion Mask 0 (Base+0x00A4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0;
+
+ union { /* ADC0 Normal Conversion Mask 1 (Base+0x00A8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t CH63:1;
+ vuint32_t CH62:1;
+ vuint32_t CH61:1;
+ vuint32_t CH60:1;
+ vuint32_t CH59:1;
+ vuint32_t CH58:1;
+ vuint32_t CH57:1;
+ vuint32_t CH56:1;
+ vuint32_t CH55:1;
+ vuint32_t CH54:1;
+ vuint32_t CH53:1;
+ vuint32_t CH52:1;
+ vuint32_t CH51:1;
+ vuint32_t CH50:1;
+ vuint32_t CH49:1;
+ vuint32_t CH48:1;
+ vuint32_t CH47:1;
+ vuint32_t CH46:1;
+ vuint32_t CH45:1;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } NCMR1;
+
+ union { /* ADC0 Normal Conversion Mask 2 (Base+0x00AC) */
+ vuint32_t R; /* (For external mux'd channels) */
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } NCMR2;
+
+ vuint8_t ADC0_reserved6[4]; /* Reserved 4 bytes (Base+0x00B0-0x00B3) */
+
+ union { /* ADC0 Injected Conversion Mask0 (Base+0x00B4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0;
+
+ union { /* ADC0 Injected Conversion Mask1 (Base+0x00B8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t CH63:1;
+ vuint32_t CH62:1;
+ vuint32_t CH61:1;
+ vuint32_t CH60:1;
+ vuint32_t CH59:1;
+ vuint32_t CH58:1;
+ vuint32_t CH57:1;
+ vuint32_t CH56:1;
+ vuint32_t CH55:1;
+ vuint32_t CH54:1;
+ vuint32_t CH53:1;
+ vuint32_t CH52:1;
+ vuint32_t CH51:1;
+ vuint32_t CH50:1;
+ vuint32_t CH49:1;
+ vuint32_t CH48:1;
+ vuint32_t CH47:1;
+ vuint32_t CH46:1;
+ vuint32_t CH45:1;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } JCMR1;
+
+ union { /* ADC0 Injected Conversion Mask2 (Base+0x00BC) */
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t CH95:1;
+ vuint32_t CH94:1;
+ vuint32_t CH93:1;
+ vuint32_t CH92:1;
+ vuint32_t CH91:1;
+ vuint32_t CH90:1;
+ vuint32_t CH89:1;
+ vuint32_t CH88:1;
+ vuint32_t CH87:1;
+ vuint32_t CH86:1;
+ vuint32_t CH85:1;
+ vuint32_t CH84:1;
+ vuint32_t CH83:1;
+ vuint32_t CH82:1;
+ vuint32_t CH81:1;
+ vuint32_t CH80:1;
+ vuint32_t CH79:1;
+ vuint32_t CH78:1;
+ vuint32_t CH77:1;
+ vuint32_t CH76:1;
+ vuint32_t CH75:1;
+ vuint32_t CH74:1;
+ vuint32_t CH73:1;
+ vuint32_t CH72:1;
+ vuint32_t CH71:1;
+ vuint32_t CH70:1;
+ vuint32_t CH69:1;
+ vuint32_t CH68:1;
+ vuint32_t CH67:1;
+ vuint32_t CH66:1;
+ vuint32_t CH65:1;
+ vuint32_t CH64:1;
+ } B;
+ } JCMR2;
+
+ vuint8_t ADC0_reserved7[4]; /* Reserved 4 bytes (Base+0x00C0-0x00C3) */
+
+ union { /* ADC0 Decode Signals Delay (Base+0x00C4) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t DSD:12;
+ } B;
+ } DSDR;
+
+ union { /* ADC0 Power-Down exit Delay (Base+0x00C8) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8;
+ } B;
+ } PDEDR;
+
+ vuint8_t ADC0_reserved8[52]; /* Reserved 52 bytes (Base+0x00CC-0x00FF) */
+
+ union { /* ADC0 Channel 0-95 Data (Base+0x0100-0x027C) */
+ vuint32_t R; /* Note CDR[16..31] are reserved */
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:6;
+ vuint32_t CDATA:10;
+ } B;
+ } CDR[96];
+
+ union { /* ADC0 Threshold 4 (Base+0x0280) */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR4;
+
+ union { /* ADC0 Threshold 5 (Base+0x0284) */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10;
+ vuint32_t:6;
+ vuint32_t THRL:10;
+ } B;
+ } THRHLR5;
+
+ vuint8_t ADC0_reserved10[40]; /* Reserved 40 bytes (Base+0x0288-0x02AF) */
+
+ union { /* ADC0 Channel Watchdog Select 0 (Base+0x02B0) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH7:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH6:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH5:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH4:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH3:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH2:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH1:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH0:3;
+ } B;
+ } CWSELR0;
+
+ union { /* ADC0 Channel Watchdog Select 1 (Base+0x02B4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH15:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH14:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH13:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH12:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH11:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH10:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH9:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH8:3;
+ } B;
+ } CWSELR1;
+
+ vuint8_t ADC0_reserved11[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
+
+ union { /* ADC0 Channel Watchdog Select 4 (Base+0x02C0) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH39:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH38:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH37:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH36:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH35:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH34:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH33:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH32:3;
+ } B;
+ } CWSELR4;
+
+ union { /* ADC0 Channel Watchdog Select 5 (Base+0x02C4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH47:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH46:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH45:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH44:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH43:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH42:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH41:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH40:3;
+ } B;
+ } CWSELR5;
+
+ union { /* ADC0 Channel Watchdog Select 6 (Base+0x02C8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH55:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH54:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH53:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH52:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH51:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH50:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH49:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH48:3;
+ } B;
+ } CWSELR6;
+
+ union { /* ADC0 Channel Watchdog Select 7 (Base+0x02CC) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH63:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH62:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH61:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH60:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH59:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH58:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH57:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH56:3;
+ } B;
+ } CWSELR7;
+
+ union { /* ADC0 Channel Watchdog Select 8 (Base+0x02D0) */
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH71:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH70:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH69:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH68:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH67:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH66:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH65:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH64:3;
+ } B;
+ } CWSELR8;
+
+ union { /* ADC0 Channel Watchdog Select 9 (Base+0x02D4) */
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH79:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH78:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH77:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH76:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH75:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH74:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH73:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH72:3;
+ } B;
+ } CWSELR9;
+
+ union { /* ADC0 Channel Watchdog Select 10 (Base+0x02D8)*/
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH87:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH86:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH85:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH84:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH83:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH82:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH81:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH80:3;
+ } B;
+ } CWSELR10;
+
+ union { /* ADC0 Channel Watchdog Select 11 (Base+0x02DC)*/
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t:1;
+ vuint32_t WSEL_CH95:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH94:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH93:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH92:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH91:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH90:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH89:3;
+ vuint32_t:1;
+ vuint32_t WSEL_CH88:3;
+ } B;
+ } CWSELR11;
+
+ union { /* ADC0 Channel Watchdog Enable0 (Base++0x02E0) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR0;
+
+ union { /* ADC0 Channel Watchdog Enable1 (Base++0x02E4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t CWEN63:1;
+ vuint32_t CWEN62:1;
+ vuint32_t CWEN61:1;
+ vuint32_t CWEN60:1;
+ vuint32_t CWEN59:1;
+ vuint32_t CWEN58:1;
+ vuint32_t CWEN57:1;
+ vuint32_t CWEN56:1;
+ vuint32_t CWEN55:1;
+ vuint32_t CWEN54:1;
+ vuint32_t CWEN53:1;
+ vuint32_t CWEN52:1;
+ vuint32_t CWEN51:1;
+ vuint32_t CWEN50:1;
+ vuint32_t CWEN49:1;
+ vuint32_t CWEN48:1;
+ vuint32_t CWEN47:1;
+ vuint32_t CWEN46:1;
+ vuint32_t CWEN45:1;
+ vuint32_t CWEN44:1;
+ vuint32_t CWEN43:1;
+ vuint32_t CWEN42:1;
+ vuint32_t CWEN41:1;
+ vuint32_t CWEN40:1;
+ vuint32_t CWEN39:1;
+ vuint32_t CWEN38:1;
+ vuint32_t CWEN37:1;
+ vuint32_t CWEN36:1;
+ vuint32_t CWEN35:1;
+ vuint32_t CWEN34:1;
+ vuint32_t CWEN33:1;
+ vuint32_t CWEN32:1;
+ } B;
+ } CWENR1;
+
+ union { /* ADC0 Channel Watchdog Enable2 (Base++0x02E8) */
+ vuint32_t R; /* (external mux'd channels) */
+ struct {
+ vuint32_t CWEN95:1;
+ vuint32_t CWEN94:1;
+ vuint32_t CWEN93:1;
+ vuint32_t CWEN92:1;
+ vuint32_t CWEN91:1;
+ vuint32_t CWEN90:1;
+ vuint32_t CWEN89:1;
+ vuint32_t CWEN88:1;
+ vuint32_t CWEN87:1;
+ vuint32_t CWEN86:1;
+ vuint32_t CWEN85:1;
+ vuint32_t CWEN84:1;
+ vuint32_t CWEN83:1;
+ vuint32_t CWEN82:1;
+ vuint32_t CWEN81:1;
+ vuint32_t CWEN80:1;
+ vuint32_t CWEN79:1;
+ vuint32_t CWEN78:1;
+ vuint32_t CWEN77:1;
+ vuint32_t CWEN76:1;
+ vuint32_t CWEN75:1;
+ vuint32_t CWEN74:1;
+ vuint32_t CWEN73:1;
+ vuint32_t CWEN72:1;
+ vuint32_t CWEN71:1;
+ vuint32_t CWEN70:1;
+ vuint32_t CWEN69:1;
+ vuint32_t CWEN68:1;
+ vuint32_t CWEN67:1;
+ vuint32_t CWEN66:1;
+ vuint32_t CWEN65:1;
+ vuint32_t CWEN64:1;
+ } B;
+ } CWENR2;
+
+ vuint8_t ADC0_reserved12[4]; /* Reserved 4 bytes (Base+0x02EC-0x02EF) */
+
+ union { /* ADC0 Watchdog out of range 0 (Base+0x02F0) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t AWOR_CH15:1;
+ vuint32_t AWOR_CH14:1;
+ vuint32_t AWOR_CH13:1;
+ vuint32_t AWOR_CH12:1;
+ vuint32_t AWOR_CH11:1;
+ vuint32_t AWOR_CH10:1;
+ vuint32_t AWOR_CH9:1;
+ vuint32_t AWOR_CH8:1;
+ vuint32_t AWOR_CH7:1;
+ vuint32_t AWOR_CH6:1;
+ vuint32_t AWOR_CH5:1;
+ vuint32_t AWOR_CH4:1;
+ vuint32_t AWOR_CH3:1;
+ vuint32_t AWOR_CH2:1;
+ vuint32_t AWOR_CH1:1;
+ vuint32_t AWOR_CH0:1;
+ } B;
+ } AWORR0;
+
+ union { /* ADC0 Watchdog out of range 1 (Base+0x02F4) */
+ vuint32_t R;
+ struct {
+ vuint32_t AWORR_CH63:1;
+ vuint32_t AWORR_CH62:1;
+ vuint32_t AWORR_CH61:1;
+ vuint32_t AWOR_CH60:1;
+ vuint32_t AWOR_CH59:1;
+ vuint32_t AWOR_CH58:1;
+ vuint32_t AWOR_CH57:1;
+ vuint32_t AWOR_CH56:1;
+ vuint32_t AWOR_CH55:1;
+ vuint32_t AWOR_CH54:1;
+ vuint32_t AWOR_CH53:1;
+ vuint32_t AWOR_CH52:1;
+ vuint32_t AWOR_CH51:1;
+ vuint32_t AWOR_CH50:1;
+ vuint32_t AWOR_CH49:1;
+ vuint32_t AWOR_CH48:1;
+ vuint32_t AWOR_CH47:1;
+ vuint32_t AWOR_CH46:1;
+ vuint32_t AWOR_CH45:1;
+ vuint32_t AWOR_CH44:1;
+ vuint32_t AWOR_CH43:1;
+ vuint32_t AWOR_CH42:1;
+ vuint32_t AWOR_CH41:1;
+ vuint32_t AWOR_CH40:1;
+ vuint32_t AWOR_CH39:1;
+ vuint32_t AWOR_CH38:1;
+ vuint32_t AWOR_CH37:1;
+ vuint32_t AWOR_CH36:1;
+ vuint32_t AWOR_CH35:1;
+ vuint32_t AWOR_CH34:1;
+ vuint32_t AWOR_CH33:1;
+ vuint32_t AWOR_CH32:1;
+ } B;
+ } AWORR1;
+
+ union { /* ADC0 Watchdog out of range 2 (Base+0x02F8) */
+ vuint32_t R;
+ struct {
+ vuint32_t AWOR_CH95:1;
+ vuint32_t AWOR_CH94:1;
+ vuint32_t AWOR_CH93:1;
+ vuint32_t AWOR_CH92:1;
+ vuint32_t AWOR_CH91:1;
+ vuint32_t AWOR_CH90:1;
+ vuint32_t AWOR_CH89:1;
+ vuint32_t AWOR_CH88:1;
+ vuint32_t AWOR_CH87:1;
+ vuint32_t AWOR_CH86:1;
+ vuint32_t AWOR_CH85:1;
+ vuint32_t AWOR_CH84:1;
+ vuint32_t AWOR_CH83:1;
+ vuint32_t AWOR_CH82:1;
+ vuint32_t AWOR_CH81:1;
+ vuint32_t AWOR_CH80:1;
+ vuint32_t AWOR_CH79:1;
+ vuint32_t AWOR_CH78:1;
+ vuint32_t AWOR_CH77:1;
+ vuint32_t AWOR_CH76:1;
+ vuint32_t AWOR_CH75:1;
+ vuint32_t AWOR_CH74:1;
+ vuint32_t AWOR_CH73:1;
+ vuint32_t AWOR_CH72:1;
+ vuint32_t AWOR_CH71:1;
+ vuint32_t AWOR_CH70:1;
+ vuint32_t AWOR_CH69:1;
+ vuint32_t AWOR_CH68:1;
+ vuint32_t AWOR_CH67:1;
+ vuint32_t AWOR_CH66:1;
+ vuint32_t AWOR_CH65:1;
+ vuint32_t AWOR_CH64:1;
+ } B;
+ } AWORR2;
+
+ vuint8_t ADC0_reserved13[4]; /* Reserved 4 bytes (Base+0x02FC-0x02FF) */
+
+}; /* end of ADC0_tag */
+/****************************************************************************/
+/* MODULE : ADC1 (12 Bit) */
+/* CH[0..15], CH[32..44] */
+/****************************************************************************/
+struct ADC1_tag {
+
+ union { /* ADC1 Main Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1;
+ vuint32_t WLSIDE:1;
+ vuint32_t MODE:1;
+ vuint32_t:4;
+ vuint32_t NSTART:1;
+ vuint32_t:1;
+ vuint32_t JTRGEN:1;
+ vuint32_t JEDGE:1;
+ vuint32_t JSTART:1;
+ vuint32_t:2;
+ vuint32_t CTUEN:1;
+ vuint32_t:9;
+ vuint32_t ABORT_CHAIN:1;
+ vuint32_t ABORT:1;
+ vuint32_t ACKO:1;
+ vuint32_t:4;
+ vuint32_t PWDN:1;
+ } B;
+ } MCR;
+
+ union { /* ADC1 Main Status (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1;
+ vuint32_t JABORT:1;
+ vuint32_t:2;
+ vuint32_t JSTART:1;
+ vuint32_t:3;
+ vuint32_t CTUSTART:1;
+ vuint32_t CHADDR:7;
+ vuint32_t:3;
+ vuint32_t ACKO:1;
+ vuint32_t:2;
+ vuint32_t ADCSTATUS:3;
+ } B;
+ } MSR;
+
+ vuint8_t ADC1_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
+
+ union { /* ADC1 Interrupt Status (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t EOCTU:1;
+ vuint32_t JEOC:1;
+ vuint32_t JECH:1;
+ vuint32_t EOC:1;
+ vuint32_t ECH:1;
+ } B;
+ } ISR;
+
+ union { /* ADC1 Channel Pending 0 (Base+0x0014) */
+ vuint32_t R; /* (For precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t EOC_CH15:1;
+ vuint32_t EOC_CH14:1;
+ vuint32_t EOC_CH13:1;
+ vuint32_t EOC_CH12:1;
+ vuint32_t EOC_CH11:1;
+ vuint32_t EOC_CH10:1;
+ vuint32_t EOC_CH9:1;
+ vuint32_t EOC_CH8:1;
+ vuint32_t EOC_CH7:1;
+ vuint32_t EOC_CH6:1;
+ vuint32_t EOC_CH5:1;
+ vuint32_t EOC_CH4:1;
+ vuint32_t EOC_CH3:1;
+ vuint32_t EOC_CH2:1;
+ vuint32_t EOC_CH1:1;
+ vuint32_t EOC_CH0:1;
+ } B;
+ } CE0CFR0;
+
+ union { /* ADC1 Channel Pending 1 (Base+0x0018) */
+ vuint32_t R; /* (For standard Channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t EOC_CH44:1;
+ vuint32_t EOC_CH43:1;
+ vuint32_t EOC_CH42:1;
+ vuint32_t EOC_CH41:1;
+ vuint32_t EOC_CH40:1;
+ vuint32_t EOC_CH39:1;
+ vuint32_t EOC_CH38:1;
+ vuint32_t EOC_CH37:1;
+ vuint32_t EOC_CH36:1;
+ vuint32_t EOC_CH35:1;
+ vuint32_t EOC_CH34:1;
+ vuint32_t EOC_CH33:1;
+ vuint32_t EOC_CH32:1;
+ } B;
+ } CE0CFR1;
+
+ vuint8_t ADC1_reserved1[4]; /* Reserved 4 bytes (Base+0x001C-0x001F) */
+
+ union { /* ADC1 Interrupt Mask (Base+0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t MSKEOCTU:1;
+ vuint32_t MSKJEOC:1;
+ vuint32_t MSKJECH:1;
+ vuint32_t MSKEOC:1;
+ vuint32_t MSKECH:1;
+ } B;
+ } IMR;
+
+ union { /* ADC1 Channel Interrupt Mask 0 (Base+0x0024) */
+ vuint32_t R; /* (For Precision Channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t CIM15:1;
+ vuint32_t CIM14:1;
+ vuint32_t CIM13:1;
+ vuint32_t CIM12:1;
+ vuint32_t CIM11:1;
+ vuint32_t CIM10:1;
+ vuint32_t CIM9:1;
+ vuint32_t CIM8:1;
+ vuint32_t CIM7:1;
+ vuint32_t CIM6:1;
+ vuint32_t CIM5:1;
+ vuint32_t CIM4:1;
+ vuint32_t CIM3:1;
+ vuint32_t CIM2:1;
+ vuint32_t CIM1:1;
+ vuint32_t CIM0:1;
+ } B;
+ } CIMR0;
+
+ union { /* ADC1 Channel Interrupt Mask 1 (+0x0028) */
+ vuint32_t R; /* (For Standard Channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t CIM44:1;
+ vuint32_t CIM43:1;
+ vuint32_t CIM42:1;
+ vuint32_t CIM41:1;
+ vuint32_t CIM40:1;
+ vuint32_t CIM39:1;
+ vuint32_t CIM38:1;
+ vuint32_t CIM37:1;
+ vuint32_t CIM36:1;
+ vuint32_t CIM35:1;
+ vuint32_t CIM34:1;
+ vuint32_t CIM33:1;
+ vuint32_t CIM32:1;
+ } B;
+ } CIMR1;
+
+ vuint8_t ADC1_reserved2[4]; /* Reserved 4 bytes (Base+0x002C-0x002F) */
+
+ union { /* ADC1 Watchdog Threshold Interrupt Status (+0x0030)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t WDG2H:1;
+ vuint32_t WDG2L:1;
+ vuint32_t WDG1H:1;
+ vuint32_t WDG1L:1;
+ vuint32_t WDG0H:1;
+ vuint32_t WDG0L:1;
+ } B;
+ } WTISR;
+
+ union { /* ADC1 Watchdog Threshold Interrupt Mask (+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t MSKWDG2H:1;
+ vuint32_t MSKWDG2L:1;
+ vuint32_t MSKWDG1H:1;
+ vuint32_t MSKWDG1L:1;
+ vuint32_t MSKWDG0H:1;
+ vuint32_t MSKWDG0L:1;
+ } B;
+ } WTIMR;
+
+ vuint8_t ADC1_reserved3[8]; /* Reserved 8 bytes (Base+0x0038-0x003F) */
+
+ union { /* ADC1 DMA Enable (Base+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1;
+ vuint32_t DMAEN:1;
+ } B;
+ } DMAE;
+
+ union { /* ADC1 DMA Channel Select 0 (Base+0x0044) */
+ vuint32_t R; /* (for precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t DMA15:1;
+ vuint32_t DMA14:1;
+ vuint32_t DMA13:1;
+ vuint32_t DMA12:1;
+ vuint32_t DMA11:1;
+ vuint32_t DMA10:1;
+ vuint32_t DMA9:1;
+ vuint32_t DMA8:1;
+ vuint32_t DMA7:1;
+ vuint32_t DMA6:1;
+ vuint32_t DMA5:1;
+ vuint32_t DMA4:1;
+ vuint32_t DMA3:1;
+ vuint32_t DMA2:1;
+ vuint32_t DMA1:1;
+ vuint32_t DMA0:1;
+ } B;
+ } DMAR0;
+
+ union { /* ADC1 DMA Channel Select 1 (Base+0x0048) */
+ vuint32_t R; /* (for standard channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t DMA44:1;
+ vuint32_t DMA43:1;
+ vuint32_t DMA42:1;
+ vuint32_t DMA41:1;
+ vuint32_t DMA40:1;
+ vuint32_t DMA39:1;
+ vuint32_t DMA38:1;
+ vuint32_t DMA37:1;
+ vuint32_t DMA36:1;
+ vuint32_t DMA35:1;
+ vuint32_t DMA34:1;
+ vuint32_t DMA33:1;
+ vuint32_t DMA32:1;
+ } B;
+ } DMAR1;
+
+ vuint8_t ADC1_reserved4[20]; /* Reserved 20 bytes (Base+0x004C-0x005F) */
+
+ /* Note the threshold registers are not implemented as an array for */
+ /* concistency with ADC0 header section */
+
+ union { /* ADC1 Threshold 0 (Base+0x0060) */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR0;
+
+ union { /* ADC1 Threshold 1 (Base+0x0064) */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR1;
+
+ union { /* ADC1 Threshold 2 (Base+0x0068) */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12;
+ vuint32_t:4;
+ vuint32_t THRL:12;
+ } B;
+ } THRHLR2;
+
+ vuint8_t ADC1_reserved5[20]; /* Reserved 20 bytes (Base+0x006C-0x007F) */
+
+ union { /* ADC1 Presampling Control (Base+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2;
+ vuint32_t PREVAL1:2;
+ vuint32_t PREVAL0:2;
+ vuint32_t PRECONV:1;
+ } B;
+ } PSCR;
+
+ union { /* ADC1 Presampling 0 (Base+0x0084) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t PRES15:1;
+ vuint32_t PRES14:1;
+ vuint32_t PRES13:1;
+ vuint32_t PRES12:1;
+ vuint32_t PRES11:1;
+ vuint32_t PRES10:1;
+ vuint32_t PRES9:1;
+ vuint32_t PRES8:1;
+ vuint32_t PRES7:1;
+ vuint32_t PRES6:1;
+ vuint32_t PRES5:1;
+ vuint32_t PRES4:1;
+ vuint32_t PRES3:1;
+ vuint32_t PRES2:1;
+ vuint32_t PRES1:1;
+ vuint32_t PRES0:1;
+ } B;
+ } PSR0;
+
+ union { /* ADC1 Presampling 1 (Base+0x0088) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t PRES44:1;
+ vuint32_t PRES43:1;
+ vuint32_t PRES42:1;
+ vuint32_t PRES41:1;
+ vuint32_t PRES40:1;
+ vuint32_t PRES39:1;
+ vuint32_t PRES38:1;
+ vuint32_t PRES37:1;
+ vuint32_t PRES36:1;
+ vuint32_t PRES35:1;
+ vuint32_t PRES34:1;
+ vuint32_t PRES33:1;
+ vuint32_t PRES32:1;
+ } B;
+ } PSR1;
+
+ vuint8_t ADC1_reserved6[8]; /* Reserved 8 bytes (Base+0x008C-0x0093) */
+
+ /* Note the following CTR registers are NOT implemented as an array to */
+ /* try and maintain some concistency through the header file */
+ /* (The registers are however identical) */
+
+ union { /* ADC1 Conversion Timing 0 (Base+0x0094) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2;
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR0;
+
+ union { /* ADC1 Conversion Timing 1 (Base+0x0098) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1;
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2;
+ vuint32_t:1;
+ vuint32_t INPCMP:2;
+ vuint32_t:1;
+ vuint32_t INPSAMP:8;
+ } B;
+ } CTR1;
+
+ vuint8_t ADC1_reserved7[8]; /* Reserved 8 bytes (Base+0x009C-0x00A3) */
+
+ union { /* ADC1 Normal Conversion Mask 0 (Base+0x00A4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } NCMR0;
+
+ union { /* ADC1 Normal Conversion Mask 1 (Base+0x00A8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:19;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } NCMR1;
+
+ vuint8_t ADC1_reserved8[8]; /* Reserved 8 bytes (Base+0x00AC-0x00B3) */
+
+ union { /* ADC1 Injected Conversion Mask0 (Base+0x00B4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CH15:1;
+ vuint32_t CH14:1;
+ vuint32_t CH13:1;
+ vuint32_t CH12:1;
+ vuint32_t CH11:1;
+ vuint32_t CH10:1;
+ vuint32_t CH9:1;
+ vuint32_t CH8:1;
+ vuint32_t CH7:1;
+ vuint32_t CH6:1;
+ vuint32_t CH5:1;
+ vuint32_t CH4:1;
+ vuint32_t CH3:1;
+ vuint32_t CH2:1;
+ vuint32_t CH1:1;
+ vuint32_t CH0:1;
+ } B;
+ } JCMR0;
+
+ union { /* ADC1 Injected Conversion Mask1 (Base+0x00B8) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t :19;
+ vuint32_t CH44:1;
+ vuint32_t CH43:1;
+ vuint32_t CH42:1;
+ vuint32_t CH41:1;
+ vuint32_t CH40:1;
+ vuint32_t CH39:1;
+ vuint32_t CH38:1;
+ vuint32_t CH37:1;
+ vuint32_t CH36:1;
+ vuint32_t CH35:1;
+ vuint32_t CH34:1;
+ vuint32_t CH33:1;
+ vuint32_t CH32:1;
+ } B;
+ } JCMR1;
+
+ vuint8_t ADC1_reserved9[68]; /* Reserved 68 bytes (Base+0x00BC-0x00FF) */
+
+ union { /* ADC1 Channel 0-44 Data (Base+0x0100-0x01B0) */
+ vuint32_t R; /* Note CDR[16..31] are reserved */
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1;
+ vuint32_t OVERW:1;
+ vuint32_t RESULT:2;
+ vuint32_t:4;
+ vuint32_t CDATA:12;
+ } B;
+ } CDR[45];
+
+ vuint8_t ADC1_reserved10[252]; /* Reserved 252 bytes (Base+0x01B4-0x002AF) */
+
+ union { /* ADC1 Channel Watchdog Select 0 (Base+0x02B0) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:2;
+ vuint32_t WSEL_CH7:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH6:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH5:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH4:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH3:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH2:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH1:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH0:2;
+ } B;
+ } CWSELR0;
+
+ union { /* ADC1 Channel Watchdog Select 1 (Base+0x02B4) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t:2;
+ vuint32_t WSEL_CH15:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH14:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH13:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH12:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH11:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH10:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH9:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH8:2;
+ } B;
+ } CWSELR1;
+
+ vuint8_t ADC1_reserved11[8]; /* Reserved 8 bytes (Base+0x02B8-0x02BF) */
+
+ union { /* ADC1 Channel Watchdog Select 4 (Base+0x02C0) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:2;
+ vuint32_t WSEL_CH39:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH38:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH37:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH36:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH35:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH34:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH33:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH32:2;
+ } B;
+ } CWSELR4;
+
+ union { /* ADC1 Channel Watchdog Select 5 (Base+0x02C4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t:14;
+ vuint32_t WSEL_CH44:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH43:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH42:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH41:2;
+ vuint32_t:2;
+ vuint32_t WSEL_CH40:2;
+ } B;
+ } CWSELR5;
+
+ vuint8_t ADC1_reserved12[24]; /* Reserved 24 bytes (Base+0x02C8-0x02DF) */
+
+ union { /* ADC1 Channel Watchdog Enable0 (Base++0x02E0) */
+ vuint32_t R; /* (precision channels) */
+ struct {
+ vuint32_t :16;
+ vuint32_t CWEN15:1;
+ vuint32_t CWEN14:1;
+ vuint32_t CWEN13:1;
+ vuint32_t CWEN12:1;
+ vuint32_t CWEN11:1;
+ vuint32_t CWEN10:1;
+ vuint32_t CWEN9:1;
+ vuint32_t CWEN8:1;
+ vuint32_t CWEN7:1;
+ vuint32_t CWEN6:1;
+ vuint32_t CWEN5:1;
+ vuint32_t CWEN4:1;
+ vuint32_t CWEN3:1;
+ vuint32_t CWEN2:1;
+ vuint32_t CWEN1:1;
+ vuint32_t CWEN0:1;
+ } B;
+ } CWENR0;
+
+ union { /* ADC1 Channel Watchdog Enable1 (Base++0x02E4) */
+ vuint32_t R; /* (standard channels) */
+ struct {
+ vuint32_t :19;
+ vuint32_t CWEN44:1;
+ vuint32_t CWEN43:1;
+ vuint32_t CWEN42:1;
+ vuint32_t CWEN41:1;
+ vuint32_t CWEN40:1;
+ vuint32_t CWEN39:1;
+ vuint32_t CWEN38:1;
+ vuint32_t CWEN37:1;
+ vuint32_t CWEN36:1;
+ vuint32_t CWEN35:1;
+ vuint32_t CWEN34:1;
+ vuint32_t CWEN33:1;
+ vuint32_t CWEN32:1;
+ } B;
+ } CWENR1;
+
+ vuint8_t ADC1_reserved13[8]; /* Reserved 8 bytes (Base+0x02E8-0x02EF) */
+
+ union { /* ADC1 Watchdog out of range 0 (Base+0x02F0) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t AWOR_CH15:1;
+ vuint32_t AWOR_CH14:1;
+ vuint32_t AWOR_CH13:1;
+ vuint32_t AWOR_CH12:1;
+ vuint32_t AWOR_CH11:1;
+ vuint32_t AWOR_CH10:1;
+ vuint32_t AWOR_CH9:1;
+ vuint32_t AWOR_CH8:1;
+ vuint32_t AWOR_CH7:1;
+ vuint32_t AWOR_CH6:1;
+ vuint32_t AWOR_CH5:1;
+ vuint32_t AWOR_CH4:1;
+ vuint32_t AWOR_CH3:1;
+ vuint32_t AWOR_CH2:1;
+ vuint32_t AWOR_CH1:1;
+ vuint32_t AWOR_CH0:1;
+ } B;
+ } AWORR0;
+
+ union { /* ADC1 Watchdog out of range 1 (Base+0x02F4) */
+ vuint32_t R;
+ struct {
+ vuint32_t :19;
+ vuint32_t AWOR_CH44:1;
+ vuint32_t AWOR_CH43:1;
+ vuint32_t AWOR_CH42:1;
+ vuint32_t AWOR_CH41:1;
+ vuint32_t AWOR_CH40:1;
+ vuint32_t AWOR_CH39:1;
+ vuint32_t AWOR_CH38:1;
+ vuint32_t AWOR_CH37:1;
+ vuint32_t AWOR_CH36:1;
+ vuint32_t AWOR_CH35:1;
+ vuint32_t AWOR_CH34:1;
+ vuint32_t AWOR_CH33:1;
+ vuint32_t AWOR_CH32:1;
+ } B;
+ } AWORR1;
+
+ vuint8_t ADC1_reserved14[8]; /* Reserved 8 bytes (Base+0x02F8-0x02FF) */
+
+}; /* end of ADC1_tag */
+/****************************************************************************/
+/* MODULE : I2C */
+/****************************************************************************/
+struct I2C_tag{
+
+ union { /* I2C Bus Address (Base+0x0000) */
+ vuint8_t R;
+ struct {
+ vuint8_t ADR:7;
+ vuint8_t :1;
+ } B;
+ } IBAD;
+
+ union { /* I2C Bus Frequency Divider (Base+0x0001) */
+ vuint8_t R;
+ struct {
+ vuint8_t IBC:8;
+ } B;
+ } IBFD;
+
+ union { /* I2C Bus Control (Base+0x0002) */
+ vuint8_t R;
+ struct {
+ vuint8_t MDIS:1;
+ vuint8_t IBIE:1;
+ vuint8_t MS:1;
+ vuint8_t TX:1;
+ vuint8_t NOACK:1;
+ vuint8_t RSTA:1;
+ vuint8_t DMAEN:1;
+ vuint8_t IBDOZE:1;
+ } B;
+ } IBCR;
+
+ union { /* I2C Bus Status (Base+0x0003) */
+ vuint8_t R;
+ struct {
+ vuint8_t TCF:1;
+ vuint8_t IAAS:1;
+ vuint8_t IBB:1;
+ vuint8_t IBAL:1;
+ vuint8_t :1;
+ vuint8_t SRW:1;
+ vuint8_t IBIF:1;
+ vuint8_t RXAK:1;
+ } B;
+ } IBSR;
+
+ union { /* I2C Bus Data I/O (Base+0x0004) */
+ vuint8_t R;
+ struct {
+ vuint8_t DATA:8;
+ } B;
+ } IBDR;
+
+ union { /* I2C Interrupt Configuration (Base+0x0005) */
+ vuint8_t R;
+ struct {
+ vuint8_t BIIE:1;
+ vuint8_t :7;
+ } B;
+ } IBIC;
+
+ vuint8_t I2C_reserved0[16378]; /* Reserved 16378 (Base+0x0006-0x3FFF) */
+
+}; /* end of i2c_tag */
+/****************************************************************************/
+/* MODULE : LINFLEX (Master/Slave with DMA) */
+/****************************************************************************/
+
+struct LINFLEX_MS_tag {
+
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CCD:1;
+ vuint32_t CFD:1;
+ vuint32_t LASE:1;
+ vuint32_t AWUM:1;
+ vuint32_t MBL:4;
+ vuint32_t BF:1;
+ vuint32_t SFTM:1;
+ vuint32_t LBKM:1;
+ vuint32_t MME:1;
+ vuint32_t SBDT:1;
+ vuint32_t RBLM:1;
+ vuint32_t SLEEP:1;
+ vuint32_t INIT:1;
+ } B;
+ } LINCR1;
+
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZIE:1;
+ vuint32_t OCIE:1;
+ vuint32_t BEIE:1;
+ vuint32_t CEIE:1;
+ vuint32_t HEIE:1;
+ vuint32_t:2;
+ vuint32_t FEIE:1;
+ vuint32_t BOIE:1;
+ vuint32_t LSIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t DBFIE:1;
+ vuint32_t DBEIE:1;
+ vuint32_t DRIE:1;
+ vuint32_t DTIE:1;
+ vuint32_t HRIE:1;
+ } B;
+ } LINIER;
+
+ union { /* LINFLEX LIN Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t LINS:4;
+ vuint32_t:2;
+ vuint32_t RMB:1;
+ vuint32_t:1;
+ vuint32_t RBSY:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t DBFF:1;
+ vuint32_t DBEF:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t HRF:1;
+ } B;
+ } LINSR;
+
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t BEF:1;
+ vuint32_t CEF:1;
+ vuint32_t SFEF:1;
+ vuint32_t BDEF:1;
+ vuint32_t IDPEF:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t:6;
+ vuint32_t NF:1;
+ } B;
+ } LINESR;
+
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TDFL:3;
+ vuint32_t RDFL:3;
+ vuint32_t RFBM:1;
+ vuint32_t TFBM:1;
+ vuint32_t WL1:1;
+ vuint32_t PC1:1;
+ vuint32_t RXEN:1;
+ vuint32_t TXEN:1;
+ vuint32_t PC0:1;
+ vuint32_t PCE:1;
+ vuint32_t WL0:1;
+ vuint32_t UART:1;
+ } B;
+ } UARTCR;
+
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
+ vuint32_t RMB:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t:2;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t NF:1;
+ } B;
+ } UARTSR;
+
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t:5;
+ vuint32_t LTOM:1;
+ vuint32_t IOT:1;
+ vuint32_t TOCE:1;
+ vuint32_t CNT:8;
+ } B;
+ } LINTCSR;
+
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t OC2:8;
+ vuint32_t OC1:8;
+ } B;
+ } LINOCR;
+
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t RTO:4;
+ vuint32_t:1;
+ vuint32_t HTO:7;
+ } B;
+ } LINTOCR;
+
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DIV_F:4;
+ } B;
+ } LINFBRR;
+
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t:19;
+ vuint32_t DIV_M:13;
+ } B;
+ } LINIBRR;
+
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t CF:8;
+ } B;
+ } LINCFR;
+
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t IOBE:1;
+ vuint32_t IOPE:1;
+ vuint32_t WURQ:1;
+ vuint32_t DDRQ:1;
+ vuint32_t DTRQ:1;
+ vuint32_t ABRQ:1;
+ vuint32_t HTRQ:1;
+ vuint32_t:8;
+ } B;
+ } LINCR2;
+
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } BIDR;
+
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL;
+
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM;
+
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FACT:8;
+ } B;
+ } IFER;
+
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFMI:4;
+ } B;
+ } IFMI;
+
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFM:4;
+ } B;
+ } IFMR;
+
+ union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } IFCR[16];
+
+ union { /* LINFLEX Global Counter (+0x008C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t TDFBM:1;
+ vuint32_t RDFBM:1;
+ vuint32_t TDLIS:1;
+ vuint32_t RDLIS:1;
+ vuint32_t STOP:1;
+ vuint32_t SR:1;
+ } B;
+ } GCR;
+
+ union { /* LINFLEX UART preset timeout (+0x0090) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t PTO:12;
+ } B;
+ } UARTPTO;
+
+ union { /* LINFLEX UART current timeout (+0x0094) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t CTO:12;
+ } B;
+ } UARTCTO;
+
+ union { /* LINFLEX DMA Tx Enable (+0x0098) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DTE15:1;
+ vuint32_t DTE14:1;
+ vuint32_t DTE13:1;
+ vuint32_t DTE12:1;
+ vuint32_t DTE11:1;
+ vuint32_t DTE10:1;
+ vuint32_t DTE9:1;
+ vuint32_t DTE8:1;
+ vuint32_t DTE7:1;
+ vuint32_t DTE6:1;
+ vuint32_t DTE5:1;
+ vuint32_t DTE4:1;
+ vuint32_t DTE3:1;
+ vuint32_t DTE2:1;
+ vuint32_t DTE1:1;
+ vuint32_t DTE0:1;
+ } B;
+ } DMATXE;
+
+ union { /* LINFLEX DMA RX Enable (+0x009C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DRE15:1;
+ vuint32_t DRE14:1;
+ vuint32_t DRE13:1;
+ vuint32_t DRE12:1;
+ vuint32_t DRE11:1;
+ vuint32_t DRE10:1;
+ vuint32_t DRE9:1;
+ vuint32_t DRE8:1;
+ vuint32_t DRE7:1;
+ vuint32_t DRE6:1;
+ vuint32_t DRE5:1;
+ vuint32_t DRE4:1;
+ vuint32_t DRE3:1;
+ vuint32_t DRE2:1;
+ vuint32_t DRE1:1;
+ vuint32_t DRE0:1;
+ } B;
+ } DMARXE;
+
+
+
+}; /* end of LINFLEX_tag */
+/****************************************************************************/
+/* MODULE : LINFLEX (Master with DMA) */
+/****************************************************************************/
+
+struct LINFLEX_M_tag {
+
+ union { /* LINFLEX LIN Control 1 (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CCD:1;
+ vuint32_t CFD:1;
+ vuint32_t LASE:1;
+ vuint32_t AWUM:1;
+ vuint32_t MBL:4;
+ vuint32_t BF:1;
+ vuint32_t SFTM:1;
+ vuint32_t LBKM:1;
+ vuint32_t MME:1;
+ vuint32_t SBDT:1;
+ vuint32_t RBLM:1;
+ vuint32_t SLEEP:1;
+ vuint32_t INIT:1;
+ } B;
+ } LINCR1;
+
+ union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZIE:1;
+ vuint32_t OCIE:1;
+ vuint32_t BEIE:1;
+ vuint32_t CEIE:1;
+ vuint32_t HEIE:1;
+ vuint32_t:2;
+ vuint32_t FEIE:1;
+ vuint32_t BOIE:1;
+ vuint32_t LSIE:1;
+ vuint32_t WUIE:1;
+ vuint32_t DBFIE:1;
+ vuint32_t DBEIE:1;
+ vuint32_t DRIE:1;
+ vuint32_t DTIE:1;
+ vuint32_t HRIE:1;
+ } B;
+ } LINIER;
+
+ union { /* LINFLEX LIN Status (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t LINS:4;
+ vuint32_t:2;
+ vuint32_t RMB:1;
+ vuint32_t:1;
+ vuint32_t RBSY:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t DBFF:1;
+ vuint32_t DBEF:1;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t HRF:1;
+ } B;
+ } LINSR;
+
+ union { /* LINFLEX LIN Error Status (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t BEF:1;
+ vuint32_t CEF:1;
+ vuint32_t SFEF:1;
+ vuint32_t BDEF:1;
+ vuint32_t IDPEF:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t:6;
+ vuint32_t NF:1;
+ } B;
+ } LINESR;
+
+ union { /* LINFLEX UART Mode Control (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TDFL:3;
+ vuint32_t RDFL:3;
+ vuint32_t RFBM:1;
+ vuint32_t TFBM:1;
+ vuint32_t WL1:1;
+ vuint32_t PC1:1;
+ vuint32_t RXEN:1;
+ vuint32_t TXEN:1;
+ vuint32_t PC0:1;
+ vuint32_t PCE:1;
+ vuint32_t WL0:1;
+ vuint32_t UART:1;
+ } B;
+ } UARTCR;
+
+ union { /* LINFLEX UART Mode Status (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t SZF:1;
+ vuint32_t OCF:1;
+ vuint32_t PE:4; /*Can check all 4 RX'd bytes at once with array*/
+ vuint32_t RMB:1;
+ vuint32_t FEF:1;
+ vuint32_t BOF:1;
+ vuint32_t RPS:1;
+ vuint32_t WUF:1;
+ vuint32_t:2;
+ vuint32_t DRF:1;
+ vuint32_t DTF:1;
+ vuint32_t NF:1;
+ } B;
+ } UARTSR;
+
+ union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t:5;
+ vuint32_t LTOM:1;
+ vuint32_t IOT:1;
+ vuint32_t TOCE:1;
+ vuint32_t CNT:8;
+ } B;
+ } LINTCSR;
+
+ union { /* LINFLEX LIN Output Compare (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t OC2:8;
+ vuint32_t OC1:8;
+ } B;
+ } LINOCR;
+
+ union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :20;
+ vuint32_t RTO:4;
+ vuint32_t:1;
+ vuint32_t HTO:7;
+ } B;
+ } LINTOCR;
+
+ union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t DIV_F:4;
+ } B;
+ } LINFBRR;
+
+ union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t:19;
+ vuint32_t DIV_M:13;
+ } B;
+ } LINIBRR;
+
+ union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t CF:8;
+ } B;
+ } LINCFR;
+
+ union { /* LINFLEX LIN Control 2 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t IOBE:1;
+ vuint32_t IOPE:1;
+ vuint32_t WURQ:1;
+ vuint32_t DDRQ:1;
+ vuint32_t DTRQ:1;
+ vuint32_t ABRQ:1;
+ vuint32_t HTRQ:1;
+ vuint32_t:8;
+ } B;
+ } LINCR2;
+
+ union { /* LINFLEX Buffer Identifier (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6;
+ vuint32_t DIR:1;
+ vuint32_t CCS:1;
+ vuint32_t:2;
+ vuint32_t ID:6;
+ } B;
+ } BIDR;
+
+ union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8;
+ vuint32_t DATA2:8;
+ vuint32_t DATA1:8;
+ vuint32_t DATA0:8;
+ } B;
+ } BDRL;
+
+ union { /* LINFLEX Buffer Data MSB (Base+0x003C */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8;
+ vuint32_t DATA6:8;
+ vuint32_t DATA5:8;
+ vuint32_t DATA4:8;
+ } B;
+ } BDRM;
+
+ union { /* LINFLEX Identifier Filter Enable (+0x0040) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FACT:8;
+ } B;
+ } IFER;
+
+ union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFMI:4;
+ } B;
+ } IFMI;
+
+ union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFM:4;
+ } B;
+ } IFMR;
+
+ /* ---------------- */
+ /* For Master-Only LINFLEX, this is where the memory map changes! */
+ /* ---------------- */
+
+ union { /* LINFLEX Global Counter (+0x004C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t TDFBM:1;
+ vuint32_t RDFBM:1;
+ vuint32_t TDLIS:1;
+ vuint32_t RDLIS:1;
+ vuint32_t STOP:1;
+ vuint32_t SR:1;
+ } B;
+ } GCR;
+
+ union { /* LINFLEX UART preset timeout (+0x0050) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t PTO:12;
+ } B;
+ } UARTPTO;
+
+ union { /* LINFLEX UART current timeout (+0x0054) */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t CTO:12;
+ } B;
+ } UARTCTO;
+
+ union { /* LINFLEX DMA Tx Enable (+0x0058) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DTE15:1;
+ vuint32_t DTE14:1;
+ vuint32_t DTE13:1;
+ vuint32_t DTE12:1;
+ vuint32_t DTE11:1;
+ vuint32_t DTE10:1;
+ vuint32_t DTE9:1;
+ vuint32_t DTE8:1;
+ vuint32_t DTE7:1;
+ vuint32_t DTE6:1;
+ vuint32_t DTE5:1;
+ vuint32_t DTE4:1;
+ vuint32_t DTE3:1;
+ vuint32_t DTE2:1;
+ vuint32_t DTE1:1;
+ vuint32_t DTE0:1;
+ } B;
+ } DMATXE;
+
+ union { /* LINFLEX DMA RX Enable (+0x005C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DRE15:1;
+ vuint32_t DRE14:1;
+ vuint32_t DRE13:1;
+ vuint32_t DRE12:1;
+ vuint32_t DRE11:1;
+ vuint32_t DRE10:1;
+ vuint32_t DRE9:1;
+ vuint32_t DRE8:1;
+ vuint32_t DRE7:1;
+ vuint32_t DRE6:1;
+ vuint32_t DRE5:1;
+ vuint32_t DRE4:1;
+ vuint32_t DRE3:1;
+ vuint32_t DRE2:1;
+ vuint32_t DRE1:1;
+ vuint32_t DRE0:1;
+ } B;
+ } DMARXE;
+
+
+
+}; /* end of LINFLEX_tag */
+/****************************************************************************/
+/* MODULE : CTU Lite */
+/****************************************************************************/
+struct CTU_tag{
+
+ vuint8_t CTU_reserved[48]; /* Reserved 48 bytes (Base+0x0000-0x002F) */
+
+ union { /* Event Config 0..63 (Base+0x0030-0x012C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TM:1;
+ vuint32_t CLR_FLAG:1;
+ vuint32_t :5;
+ vuint32_t ADC_SEL:1;
+ vuint32_t :1;
+ vuint32_t CHANNEL_VALUE:7;
+ } B;
+ } EVTCFGR[64];
+
+
+}; /* end of CTU_tag */
+/****************************************************************************/
+/* MODULE : CANSP */
+/****************************************************************************/
+struct CANSP_tag{
+
+ union { /* CANSP Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RX_COMPLETE:1;
+ vuint32_t BUSY:1;
+ vuint32_t ACTIVE_CK:1;
+ vuint32_t :3;
+ vuint32_t MODE:1;
+ vuint32_t CAN_RX_SEL:3;
+ vuint32_t BRP:5;
+ vuint32_t CAN_SMPLR_EN:1;
+ } B;
+ } CR;
+
+ union { /* CANSP Sample 0..11 (Base+0x0000-0x0030)*/
+ vuint32_t R;
+ } SR[12];
+
+}; /* end of CANSP_tag */
+/****************************************************************************/
+/* MODULE : XBAR */
+/****************************************************************************/
+struct XBAR_tag{
+
+ union { /* XBAR Master Priority Slave Port 0 (+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR_7:3;
+ vuint32_t:1;
+ vuint32_t MSTR_6:3;
+ vuint32_t:1;
+ vuint32_t MSTR_5:3;
+ vuint32_t:1;
+ vuint32_t MSTR_4:3;
+ vuint32_t:1;
+ vuint32_t MSTR_3:3;
+ vuint32_t:1;
+ vuint32_t MSTR_2:3;
+ vuint32_t:1;
+ vuint32_t MSTR_1:3;
+ vuint32_t:1;
+ vuint32_t MSTR_0:3;
+ } B;
+ } MPR0;
+
+ vuint8_t XBAR_reserved0[12]; /* Reserved 12 bytes (Base+0x0004-0x000F)*/
+
+ union { /* XBAR General Purpose Control Slave 0 (+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1;
+ vuint32_t:6;
+ vuint32_t HPE7:1;
+ vuint32_t HPE6:1;
+ vuint32_t HPE5:1;
+ vuint32_t HPE4:1;
+ vuint32_t HPE3:1;
+ vuint32_t HPE2:1;
+ vuint32_t HPE1:1;
+ vuint32_t HPE0:1;
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR0;
+
+ vuint8_t XBAR_reserved1[236]; /*Reserved 236 bytes (Base+0x0014-0x00FF)*/
+
+ union { /* XBAR Master Priority Slave Port 1 (+0x0100) */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR_7:3;
+ vuint32_t:1;
+ vuint32_t MSTR_6:3;
+ vuint32_t:1;
+ vuint32_t MSTR_5:3;
+ vuint32_t:1;
+ vuint32_t MSTR_4:3;
+ vuint32_t:1;
+ vuint32_t MSTR_3:3;
+ vuint32_t:1;
+ vuint32_t MSTR_2:3;
+ vuint32_t:1;
+ vuint32_t MSTR_1:3;
+ vuint32_t:1;
+ vuint32_t MSTR_0:3;
+ } B;
+ } MPR1;
+
+ vuint8_t XBAR_reserved2[12]; /* Reserved 12 bytes (Base+0x0104-0x010F)*/
+
+ union { /* XBAR General Purpose Control Slave 1 (+0x0110) */
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1;
+ vuint32_t:6;
+ vuint32_t HPE7:1;
+ vuint32_t HPE6:1;
+ vuint32_t HPE5:1;
+ vuint32_t HPE4:1;
+ vuint32_t HPE3:1;
+ vuint32_t HPE2:1;
+ vuint32_t HPE1:1;
+ vuint32_t HPE0:1;
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR1;
+
+ vuint8_t XBAR_reserved3[236]; /*Reserved 236 bytes (Base+0x0114-0x01FF)*/
+
+ union { /* XBAR Master Priority Slave Port 2 (+0x0200) */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR_7:3;
+ vuint32_t:1;
+ vuint32_t MSTR_6:3;
+ vuint32_t:1;
+ vuint32_t MSTR_5:3;
+ vuint32_t:1;
+ vuint32_t MSTR_4:3;
+ vuint32_t:1;
+ vuint32_t MSTR_3:3;
+ vuint32_t:1;
+ vuint32_t MSTR_2:3;
+ vuint32_t:1;
+ vuint32_t MSTR_1:3;
+ vuint32_t:1;
+ vuint32_t MSTR_0:3;
+ } B;
+ } MPR2;
+
+ vuint8_t XBAR_reserved4[12]; /* Reserved 12 bytes (Base+0x0204-0x020F)*/
+
+ union { /* XBAR General Purpose Control Slave 2 (+0x0210) */
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1;
+ vuint32_t:6;
+ vuint32_t HPE7:1;
+ vuint32_t HPE6:1;
+ vuint32_t HPE5:1;
+ vuint32_t HPE4:1;
+ vuint32_t HPE3:1;
+ vuint32_t HPE2:1;
+ vuint32_t HPE1:1;
+ vuint32_t HPE0:1;
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR2;
+
+ vuint8_t XBAR_reserved5[236]; /*Reserved 236 bytes (Base+0x0214-0x02FF)*/
+
+ union { /* XBAR Master Priority Slave Port 3 (+0x0300) */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR_7:3;
+ vuint32_t:1;
+ vuint32_t MSTR_6:3;
+ vuint32_t:1;
+ vuint32_t MSTR_5:3;
+ vuint32_t:1;
+ vuint32_t MSTR_4:3;
+ vuint32_t:1;
+ vuint32_t MSTR_3:3;
+ vuint32_t:1;
+ vuint32_t MSTR_2:3;
+ vuint32_t:1;
+ vuint32_t MSTR_1:3;
+ vuint32_t:1;
+ vuint32_t MSTR_0:3;
+ } B;
+ } MPR3;
+
+ vuint8_t XBAR_reserved6[12]; /* Reserved 12 bytes (Base+0x0304-0x030F)*/
+
+ union { /* XBAR General Purpose Control Slave 3 (+0x0310) */
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1;
+ vuint32_t:6;
+ vuint32_t HPE7:1;
+ vuint32_t HPE6:1;
+ vuint32_t HPE5:1;
+ vuint32_t HPE4:1;
+ vuint32_t HPE3:1;
+ vuint32_t HPE2:1;
+ vuint32_t HPE1:1;
+ vuint32_t HPE0:1;
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR3;
+
+ vuint8_t XBAR_reserved7[1004]; /*Reserved 1004 bytes (Base+0x0314-0x06FF)*/
+
+ union { /* XBAR Master Priority Slave Port 7 (+0x0700) */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR_7:3;
+ vuint32_t:1;
+ vuint32_t MSTR_6:3;
+ vuint32_t:1;
+ vuint32_t MSTR_5:3;
+ vuint32_t:1;
+ vuint32_t MSTR_4:3;
+ vuint32_t:1;
+ vuint32_t MSTR_3:3;
+ vuint32_t:1;
+ vuint32_t MSTR_2:3;
+ vuint32_t:1;
+ vuint32_t MSTR_1:3;
+ vuint32_t:1;
+ vuint32_t MSTR_0:3;
+ } B;
+ } MPR7;
+
+ vuint8_t XBAR_reserved8[12]; /* Reserved 12 bytes (Base+0x0704-0x070F)*/
+
+ union { /* XBAR General Purpose Control Slave 7 (+0x0710) */
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1;
+ vuint32_t HLP:1;
+ vuint32_t:6;
+ vuint32_t HPE7:1;
+ vuint32_t HPE6:1;
+ vuint32_t HPE5:1;
+ vuint32_t HPE4:1;
+ vuint32_t HPE3:1;
+ vuint32_t HPE2:1;
+ vuint32_t HPE1:1;
+ vuint32_t HPE0:1;
+ vuint32_t:6;
+ vuint32_t ARB:2;
+ vuint32_t:2;
+ vuint32_t PCTL:2;
+ vuint32_t:1;
+ vuint32_t PARK:3;
+ } B;
+ } SGPCR7;
+
+ vuint8_t XBAR_reserved9[236]; /*Reserved 236 bytes (Base+0x0714-0x07FF)*/
+
+ union { /* XBAR General Purpose Control Master 0 (+0x0800) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR0;
+
+ vuint8_t XBAR_reserved10[252]; /*Reserved 252 bytes (Base+0x0804-0x08FF)*/
+
+ union { /* XBAR General Purpose Control Master 1 (+0x0900) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR1;
+
+ vuint8_t XBAR_reserved11[252]; /*Reserved 252 bytes (Base+0x0904-0x09FF)*/
+
+ union { /* XBAR General Purpose Control Master 2 (+0x0A00) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR2;
+
+ vuint8_t XBAR_reserved12[252]; /*Reserved 252 bytes (Base+0x0A04-0x0AFF)*/
+
+ union { /* XBAR General Purpose Control Master 3 (+0x0B00) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR3;
+
+ vuint8_t XBAR_reserved13[252]; /*Reserved 252 bytes (Base+0x0B04-0x0BFF)*/
+
+ union { /* XBAR General Purpose Control Master 4 (+0x0C00) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR4;
+
+ vuint8_t XBAR_reserved14[252]; /*Reserved 252 bytes (Base+0x0C04-0x0CFF)*/
+
+ union { /* XBAR General Purpose Control Master 5 (+0x0D00) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR5;
+
+ vuint8_t XBAR_reserved15[252]; /*Reserved 252 bytes (Base+0x0D04-0x0DFF)*/
+
+ union { /* XBAR General Purpose Control Master 6 (+0x0E00) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR6;
+
+ vuint8_t XBAR_reserved16[252]; /*Reserved 252 bytes (Base+0x0E04-0x0EFF)*/
+
+ union { /* XBAR General Purpose Control Master 7 (+0x0F00) */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3;
+ } B;
+ } MGPCR7;
+
+
+}; /* end of XBAR_tag */
+/****************************************************************************/
+/* MODULE : MPU (Memory Protection Unit) */
+/****************************************************************************/
+struct MPU_tag {
+
+ union { /* Control/Error Status (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t SPERR:8;
+ vuint32_t :4;
+ vuint32_t HRL:4;
+ vuint32_t NSP:4;
+ vuint32_t NGRD:4;
+ vuint32_t :7;
+ vuint32_t VLD:1;
+ } B;
+ } CESR;
+
+ vuint8_t MPU_reserved0[12]; /* Reserved 12 Bytes (Base+0x0004-0x000F) */
+
+
+ union { /* Error Address Slave Port0 (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR0;
+
+ union { /* Error Detail Slave Port0 (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR0;
+
+
+ union { /* Error Address Slave Port1 (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR1;
+
+ union { /* Error Detail Slave Port1 (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR1;
+
+
+ union { /* Error Address Slave Port2 (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR2;
+
+ union { /* Error Detail Slave Port2 (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR2;
+
+
+ union { /* Error Address Slave Port3 (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR3;
+
+ union { /* Error Detail Slave Port3 (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR3;
+
+
+ union { /* Error Address Slave Port4 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32;
+ } B;
+ } EAR4;
+
+ union { /* Error Detail Slave Port4 (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16;
+ vuint32_t EPID:8;
+ vuint32_t EMN:4;
+ vuint32_t EATTR:3;
+ vuint32_t ERW:1;
+ } B;
+ } EDR4;
+
+ vuint8_t MPU_reserved1[968]; /* Reserved 968 Bytes (Base+0x0038-0x03FF) */
+
+ struct { /* Region Descriptor 0..15 (Base+0x0400-0x04F0) */
+
+ union { /* - Word 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27;
+ vuint32_t :5;
+ } B;
+ } WORD0;
+
+ union { /* - Word 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27;
+ vuint32_t :5;
+ } B;
+ } WORD1;
+
+ union { /* - Word 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } WORD2;
+
+ union { /* - Word 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8;
+ vuint32_t PIDMASK:8;
+ vuint32_t :15;
+ vuint32_t VLD:1;
+ } B;
+ } WORD3;
+
+ }RGD[16]; /* End of Region Descriptor Structure) */
+
+ vuint8_t MPU_reserved2[768]; /* Reserved 768 Bytes (Base+0x0500-0x07FF) */
+
+ union { /* Region Descriptor Alt 0..15 (0x0800-0x083F) */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1;
+ vuint32_t M7WE:1;
+ vuint32_t M6RE:1;
+ vuint32_t M6WE:1;
+ vuint32_t M5RE:1;
+ vuint32_t M5WE:1;
+ vuint32_t M4RE:1;
+ vuint32_t M4WE:1;
+ vuint32_t M3PE:1;
+ vuint32_t M3SM:2;
+ vuint32_t M3UM:3;
+ vuint32_t M2PE:1;
+ vuint32_t M2SM:2;
+ vuint32_t M2UM:3;
+ vuint32_t M1PE:1;
+ vuint32_t M1SM:2;
+ vuint32_t M1UM:3;
+ vuint32_t M0PE:1;
+ vuint32_t M0SM:2;
+ vuint32_t M0UM:3;
+ } B;
+ } RGDAAC[16];
+
+ vuint8_t MPU_reserved3[14242]; /* Reserved 14242 Bytes (+0x0840-0x03FFF) */
+
+}; /* end of MPU_tag */
+/****************************************************************************/
+/* MODULE : CSE (Cryptographic Security Engine) */
+/****************************************************************************/
+struct CSE_tag {
+
+ union { /* CSE Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t DIV:8;
+ vuint32_t :4;
+ vuint32_t MDIS:1;
+ vuint32_t SUS:1;
+ vuint32_t :1; /* vuint32_t DRE:1; removed RevD */
+ vuint32_t CIE:1;
+ } B;
+ } CR;
+
+ union { /* CSE Status (Read Only) (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :23;
+ vuint32_t EX:1;
+ vuint32_t IDB:1;
+ vuint32_t EDB:1;
+ vuint32_t RIN:1;
+ vuint32_t BOK:1;
+ vuint32_t BFN:1;
+ vuint32_t BIN:1;
+ vuint32_t SB:1;
+ vuint32_t BSY:1;
+ } B;
+ } SR;
+
+ union { /* CSE Interrupt (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t CIF:1;
+ } B;
+ } IR;
+
+ union { /* CSE Error Code (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :27;
+ vuint32_t EC:5;
+ } B;
+ } ECR;
+
+ vuint8_t CSE_reserved0[13]; /* Reserved 13 Bytes (Base+0x0010-0x001C) */
+
+ union { /* CSE Command (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :27;
+ vuint32_t CMD:5;
+ } B;
+ } CMD;
+
+
+ /*-- Note parameter registers cannot be array since no P0 (SHE spec) --*/
+
+ union { /* CSE Paramter 1 (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARM:32;
+ } B;
+ } P1;
+
+ union { /* CSE Paramter 2 (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARM:32;
+ } B;
+ } P2;
+
+ union { /* CSE Paramter 3 (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARM:32;
+ } B;
+ } P3;
+
+ union { /* CSE Paramter 4 (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARM:32;
+ } B;
+ } P4;
+
+ union { /* CSE Paramter 5 (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t PARM:32;
+ } B;
+ } P5;
+
+ vuint8_t CSE_reserved1[16328]; /* Reserved 16328 Bytes (0x0038-0x3FFF) */
+
+}; /* end of CSE_tag */
+/****************************************************************************/
+/* MODULE : SEMA4 (Semaphores) */
+/****************************************************************************/
+ struct SEMA4_tag {
+
+ union { /* Gate 0..15 (Base+0x0000-0x000F) */
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t GTFSM:2;
+ } B;
+ } GATE[16];
+
+ vuint8_t SEMA4_reserved0[48]; /* Reserved 48 Bytes (Base+0x0010-0x003F) */
+
+ union { /* CP0 IRQ Notification enable (Base+0x0040) */
+ vuint16_t R;
+ struct {
+ vuint16_t INE0:1;
+ vuint16_t INE1:1;
+ vuint16_t INE2:1;
+ vuint16_t INE3:1;
+ vuint16_t INE4:1;
+ vuint16_t INE5:1;
+ vuint16_t INE6:1;
+ vuint16_t INE7:1;
+ vuint16_t INE8:1;
+ vuint16_t INE9:1;
+ vuint16_t INE10:1;
+ vuint16_t INE11:1;
+ vuint16_t INE12:1;
+ vuint16_t INE13:1;
+ vuint16_t INE14:1;
+ vuint16_t INE15:1;
+ } B;
+ } CP0INE;
+
+ vuint8_t SEMA4_reserved1[6]; /* Reserved 6 Bytes (Base+0x0042-0x0047) */
+
+ union { /* CP1 IRQ Notification enable (Base+0x0048) */
+ vuint16_t R;
+ struct {
+ vuint16_t INE0:1;
+ vuint16_t INE1:1;
+ vuint16_t INE2:1;
+ vuint16_t INE3:1;
+ vuint16_t INE4:1;
+ vuint16_t INE5:1;
+ vuint16_t INE6:1;
+ vuint16_t INE7:1;
+ vuint16_t INE8:1;
+ vuint16_t INE9:1;
+ vuint16_t INE10:1;
+ vuint16_t INE11:1;
+ vuint16_t INE12:1;
+ vuint16_t INE13:1;
+ vuint16_t INE14:1;
+ vuint16_t INE15:1;
+ } B;
+ } CP1INE;
+
+ vuint8_t SEMA4_reserved2[54]; /* Reserved 54 Bytes (Base+0x004A-0x007F) */
+
+ union { /* CP0 IRQ Notification (Base+0x0080) */
+ vuint16_t R;
+ struct {
+ vuint16_t GN0:1;
+ vuint16_t GN1:1;
+ vuint16_t GN2:1;
+ vuint16_t GN3:1;
+ vuint16_t GN4:1;
+ vuint16_t GN5:1;
+ vuint16_t GN6:1;
+ vuint16_t GN7:1;
+ vuint16_t GN8:1;
+ vuint16_t GN9:1;
+ vuint16_t GN10:1;
+ vuint16_t GN11:1;
+ vuint16_t GN12:1;
+ vuint16_t GN13:1;
+ vuint16_t GN14:1;
+ vuint16_t GN15:1;
+ } B;
+ } CP0NTF;
+
+ vuint8_t SEMA4_reserved3[6]; /* Reserved 6 Bytes (Base+0x0082-0x0087) */
+
+ union { /* CP1 IRQ Notification (Base+0x0088) */
+ vuint16_t R;
+ struct {
+ vuint16_t GN0:1;
+ vuint16_t GN1:1;
+ vuint16_t GN2:1;
+ vuint16_t GN3:1;
+ vuint16_t GN4:1;
+ vuint16_t GN5:1;
+ vuint16_t GN6:1;
+ vuint16_t GN7:1;
+ vuint16_t GN8:1;
+ vuint16_t GN9:1;
+ vuint16_t GN10:1;
+ vuint16_t GN11:1;
+ vuint16_t GN12:1;
+ vuint16_t GN13:1;
+ vuint16_t GN14:1;
+ vuint16_t GN15:1;
+ } B;
+ } CP1NTF;
+
+ vuint8_t SEMA4_reserved4[118]; /* Reserved 118 Bytes (+0x008A-0x00FF) */
+
+ union { /* Reset gate (Base+0x0100) */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t RSTGSM:2;
+ vuint16_t:1;
+ vuint16_t RSTGMS:3;
+ vuint16_t RSTGTN:8;
+ } B;
+ } RSTGT;
+
+ vuint8_t SEMA4_reserved5[2]; /* Reserved 2 Bytes (Base+0x0102-0x0103) */
+
+ union {
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t RSTNSM:2;
+ vuint16_t:1;
+ vuint16_t RSTNMS:3;
+ vuint16_t RSTNTN:8;
+ } B;
+ } RSTNTF;
+
+ vuint8_t SEMA4_reserved6[16122]; /* Reserved 16122 (Base+0x0106-0x3FFF) */
+
+ }; /* end of SEMA4_tag */
+/****************************************************************************/
+/* MODULE : SWT */
+/****************************************************************************/
+struct SWT_tag{
+
+ union { /* SWT Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1;
+ vuint32_t MAP1:1;
+ vuint32_t MAP2:1;
+ vuint32_t MAP3:1;
+ vuint32_t MAP4:1;
+ vuint32_t MAP5:1;
+ vuint32_t MAP6:1;
+ vuint32_t MAP7:1;
+ vuint32_t :14;
+ vuint32_t KEY:1;
+ vuint32_t RIA:1;
+ vuint32_t WND:1;
+ vuint32_t ITR:1;
+ vuint32_t HLK:1;
+ vuint32_t SLK:1;
+ vuint32_t CSL:1;
+ vuint32_t STP:1;
+ vuint32_t FRZ:1;
+ vuint32_t WEN:1;
+ } B;
+ } CR;
+
+ union { /* SWT Interrupt (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t TIF:1;
+ } B;
+ } IR;
+
+ union { /* SWT Time-Out (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32;
+ } B;
+ } TO;
+
+ union { /* SWT Window (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32;
+ } B;
+ } WN;
+
+ union { /* SWT Service (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t WSC:16;
+ } B;
+ } SR;
+
+ union { /* SWT Counter Output (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32;
+ } B;
+ } CO;
+
+ union { /* SWT Service Key (Base+0x0018) */
+ vuint32_t R; /* New for Bolero 3M */
+ struct {
+ vuint32_t :16;
+ vuint32_t SK:16;
+ } B;
+ } SK;
+
+}; /* end of SWT_tag */
+/****************************************************************************/
+/* MODULE : STM */
+/****************************************************************************/
+ struct STM_CHANNEL_tag{
+
+ union { /* STM Channel Control 0..3 */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t CEN:1;
+ } B;
+ } CCR;
+
+ union { /* STM Channel Interrupt 0..3 */
+ vuint32_t R;
+ struct {
+ vuint32_t :31;
+ vuint32_t CIF:1;
+ } B;
+ } CIR;
+
+ union { /* STM Channel Compare 0..3 */
+ vuint32_t R;
+ struct {
+ vuint32_t CMP:32;
+ } B;
+ } CMP;
+
+ vuint8_t STM_CHANNEL_reserved[4]; /* Reserved 4 bytes between ch reg's */
+
+ }; /* end of STM_CHANNEL_tag */
+
+
+struct STM_tag{
+
+ union { /* STM Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t CPS:8;
+ vuint32_t :6;
+ vuint32_t FRZ:1;
+ vuint32_t TEN:1;
+ } B;
+ } CR;
+
+ union { /* STM Count (Base+0x0004) */
+ vuint32_t R;
+ } CNT;
+
+ vuint8_t STM_reserved0[8]; /* Reserved 8 bytes (Base+0x0008-0x000F) */
+
+ struct STM_CHANNEL_tag CH[4]; /*STM Channels 0..3 (Base+0x0010-0x0048) */
+
+}; /* end of STM_tag */
+/****************************************************************************/
+/* MODULE : ECSM */
+/****************************************************************************/
+struct ECSM_tag{
+
+ union { /* ECSM Processor Core Type (Base+0x0000) */
+ vuint16_t R;
+ } PCT;
+
+ union { /* ECSM Revision (Base+0x0002) */
+ vuint16_t R;
+ } REV;
+
+ vuint8_t ECSM_reserved0[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* ECSM IPS Module Configuration (Base+0x0008) */
+ vuint32_t R;
+ } IMC;
+
+ vuint8_t ECSM_reserved1[19]; /* Reserved 19 bytes (Base+0x000C-0x001E) */
+
+ union { /* ECSM Miscellaneous Interrupt (Base+0x001F) */
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1;
+ vuint8_t FB0SI:1;
+ vuint8_t FB1AI:1;
+ vuint8_t FB1SI:1;
+ vuint8_t :4;
+ } B;
+ } MIR;
+
+ vuint8_t ECSM_reserved3[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
+
+ union { /*ECSM Miscellaneous User-Defined Control (+0x0024)*/
+ vuint32_t R;
+ struct {
+ vuint32_t XBAR_ARB:1;
+ vuint32_t RAM_WS:1;
+ vuint32_t :19;
+ vuint32_t MUDCR:11;
+ } B;
+ } MUDCR;
+
+ vuint8_t ECSM_reserved4[27]; /* Reserved 27 bytes (Base+0x0028-0x0042) */
+
+ union { /* ECSM ECC Configuration (Base+0x0043) */
+ vuint8_t R;
+ struct {
+ vuint8_t :2;
+ vuint8_t ER1BR:1;
+ vuint8_t EF1BR:1;
+ vuint8_t :2;
+ vuint8_t ERNCR:1;
+ vuint8_t EFNCR:1;
+ } B;
+ } ECR;
+
+ vuint8_t ECSM_reserved5[3]; /* Reserved 3 bytes (Base+0x0044-0x0046) */
+
+ union { /* ECSM ECC Status (Base+0x0047) */
+ vuint8_t R;
+ struct {
+ vuint8_t :2;
+ vuint8_t R1BC:1;
+ vuint8_t F1BC:1;
+ vuint8_t :2;
+ vuint8_t RNCE:1;
+ vuint8_t FNCE:1;
+ } B;
+ } ESR;
+
+ vuint8_t ECSM_reserved6[2]; /* Reserved 2 bytes (Base+0x0048-0x0049) */
+
+ union { /* ECSM ECC Error Generation (Base+0x004A) */
+ vuint16_t R;
+ struct {
+ vuint16_t :2;
+ vuint16_t FRC1BI:1;
+ vuint16_t FR11BI:1;
+ vuint16_t :2;
+ vuint16_t FRCNCI:1;
+ vuint16_t FR1NCI:1;
+ vuint16_t :1;
+ vuint16_t ERRBIT:7;
+ } B;
+ } EEGR;
+
+ vuint8_t ECSM_reserved7[4]; /* Reserved 4 bytes (Base+0x004C-0x004F) */
+
+ union { /* ECSM Flash ECC Address(Base+0x0050) */
+ vuint32_t R;
+ } FEAR;
+
+ vuint8_t ECSM_reserved8[2]; /* Reserved 2 bytes (Base+0x0054-0x0055) */
+
+ union { /* ECSM Flash ECC Master Number (Base+0x0056) */
+ vuint8_t R;
+ struct {
+ vuint8_t :4;
+ vuint8_t FEMR:4;
+ } B;
+ } FEMR;
+
+ union { /* ECSM Flash ECC Attributes (Base+0x0057) */
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } FEAT;
+
+ vuint8_t ECSM_reserved9[4]; /* Reserved 4 bytes (Base+0x0058-0x005B) */
+
+ union { /* ECSM Flash ECC Data (Base+0x005C) */
+ vuint32_t R;
+ } FEDR;
+
+ union { /* ECSM RAM ECC Address (Base+0x0060) */
+ vuint32_t R;
+ } REAR;
+
+ vuint8_t ECSM_reserved10[1]; /* Reserved 1 bytes (Base+0x0064) */
+
+ union { /* ECSM RAM ECC Address (Base+0x0065) */
+ vuint8_t R;
+ } RESR;
+
+ union { /* ECSM RAM ECC Master Number (Base+0x0066) */
+ vuint8_t R;
+ struct {
+ vuint8_t :4;
+ vuint8_t REMR:4;
+ } B;
+ } REMR;
+
+ union { /* ECSM RAM ECC Attributes (Base+0x0067) */
+ vuint8_t R;
+ struct {
+ vuint8_t WRITE:1;
+ vuint8_t SIZE:3;
+ vuint8_t PROTECTION:4;
+ } B;
+ } REAT;
+
+ vuint8_t ECSM_reserved11[4]; /* Reserved 4 bytes (Base+0x0068-0x006B) */
+
+ union { /* ECSM RAM ECC Data (Base+0x006C) */
+ vuint32_t R;
+ } REDR;
+
+}; /* end of ECSM_tag */
+/****************************************************************************/
+/* MODULE : eDMA */
+/****************************************************************************/
+
+ /* There are 4 different TCD structures which should be used based on */
+ /* how the DMA is configured as below. CAUTION - Do not mix TCD's */
+ /* */
+ /* Channel Linking Minor Loop Mapping Addressing TCD */
+ /* OFF OFF XBAR.TCD[x] */
+ /* OFF ON XBAR.ML_TCD[x] */
+ /* ON OFF XBAR.CL_TCD[X] */
+ /* ON ON XBAR.MLCL_TCD[X] */
+ /* */
+
+
+ /* (1) - Standard TCD (Channel Linking OFF, Minor Loop mapping OFF */
+ struct EDMA_TCD_STD_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t NBYTES; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITER:15; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITER:15; /* Starting major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* End of Standard TCD tag */
+
+
+
+ /* (2) - ML_TCD (Channel Linking OFF, Minor Loop mapping Enabled */
+ /* (EMLM = 1) */
+ struct EDMA_TCD_MLMIRROR_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t SMLOE:1; /* Source minor loop offset enabled */
+ vuint32_t DMLOE:1; /* Destination minor loop offset enable */
+ vuint32_t MLOFF:20; /* Minor loop offset */
+ vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITER:15; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITER:15; /* Starting major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* End of EDMA_TCD_MLMIRROR_tag */
+
+
+
+ /* (3) - CL_TCD (Channel Linking Enabled, Minor Loop mapping OFF */
+ /* (CITERE_LINK = BITERE_LINK = 1) */
+ struct EDMA_TCD_CHLINK_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t NBYTES; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITERLINKCH:6; /* Link channel number */
+ vuint16_t CITER:9; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITERLINKCH:6; /* Link channel number */
+ vuint16_t BITER:9; /* Starting Major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* end of EDMA_TCD_CHLINK_tag */
+
+
+
+ /* (4) - CL_TCD (Channel Linking Enabled, Minor Loop mapping Enabled */
+ /* (CITERE_LINK = BITERE_LINK = 1, EMLM = 1) */
+ struct EDMA_TCD_MLMIRROR_CHLINK_tag {
+
+ vuint32_t SADDR; /* Source address */
+
+ vuint16_t SMOD:5; /* Source address modulo */
+ vuint16_t SSIZE:3; /* Source data transfer size */
+ vuint16_t DMOD:5; /* Destination address modulo */
+ vuint16_t DSIZE:3; /* Destination data transfer size */
+ vint16_t SOFF; /* Source address signed offset */
+
+ vuint32_t SMLOE:1; /* Source minor loop offset enabled */
+ vuint32_t DMLOE:1; /* Destination minor loop offset enable */
+ vuint32_t MLOFF:20; /* Minor loop offset */
+ vuint32_t NBYTES:10; /* Inner "minor" byte transfer count */
+
+ vint32_t SLAST; /* Last source address adjustment */
+
+ vuint32_t DADDR; /* Destination address */
+
+ vuint16_t CITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t CITERLINKCH:6; /* Link channel number */
+ vuint16_t CITER:9; /* Current Major iteration count */
+ vint16_t DOFF; /* Destination address signed offset */
+
+ vint32_t DLAST_SGA; /* Last desitination address adjustment */
+
+ vuint16_t BITERE_LINK:1; /* Enable ch-to-ch link on minor complete */
+ vuint16_t BITERLINKCH:6; /* Link channel number */
+ vuint16_t BITER:9; /* Starting Major iteration count */
+ vuint16_t BWC:2; /* Bandwidth & Priority Elevation control */
+ vuint16_t MAJORLINKCH:6; /* Link channel number */
+ vuint16_t DONE:1; /* Channel done */
+ vuint16_t ACTIVE:1; /* Channel active */
+ vuint16_t MAJORE_LINK:1; /* Enable ch-to-ch link on major complete */
+ vuint16_t E_SG:1; /* Enable scatter/gather processing */
+ vuint16_t D_REQ:1; /* Disable hardware request (ERQRL bit) */
+ vuint16_t INT_HALF:1; /* interrupt on Major loop half complete */
+ vuint16_t INT_MAJ:1; /* interrupt on major loop complete */
+ vuint16_t START:1; /* Chanel start */
+
+ }; /* end of EDMA_TCD_MLMIRROR_CHLINK_tag */
+
+
+
+
+struct EDMA_tag {
+
+ union { /* Control (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t CX:1;
+ vuint32_t ECX:1;
+ vuint32_t:2; /* vuint32_t GRP3PRI:2; (Not implemented B3M) */
+ vuint32_t:2; /* vuint32_t GRP2PRI:2; (Not implemented B3M) */
+ vuint32_t:2; /* vuint32_t GRP1PRI:2; (Not implemented B3M) */
+ vuint32_t GRP0PRI:2;
+ vuint32_t EMLM:1;
+ vuint32_t CLM:1;
+ vuint32_t HALT:1;
+ vuint32_t HOE:1;
+ vuint32_t ERGA:1;
+ vuint32_t ERCA:1;
+ vuint32_t EDBG:1;
+ vuint32_t EBW:1;
+ } B;
+ } CR;
+
+ union { /* Error Status (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1;
+ vuint32_t:14;
+ vuint32_t:1; /* vuint32_t ECX:1; (Not implemented B3M) */
+ vuint32_t:1; /* vuint32_t GPE:1; (Not implemented B3M) */
+ vuint32_t CPE:1;
+ vuint32_t ERRCHN:6;
+ vuint32_t SAE:1;
+ vuint32_t SOE:1;
+ vuint32_t DAE:1;
+ vuint32_t DOE:1;
+ vuint32_t NCE:1;
+ vuint32_t SGE:1;
+ vuint32_t SBE:1;
+ vuint32_t DBE:1;
+ } B;
+ } ESR;
+
+ vuint8_t eDMA_reserved0[4]; /* Reserved 4 bytes (Base+0x0008-0x000B) */
+
+ union { /* Enable Request Low Ch31..0 (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ31:1;
+ vuint32_t ERQ30:1;
+ vuint32_t ERQ29:1;
+ vuint32_t ERQ28:1;
+ vuint32_t ERQ27:1;
+ vuint32_t ERQ26:1;
+ vuint32_t ERQ25:1;
+ vuint32_t ERQ24:1;
+ vuint32_t ERQ23:1;
+ vuint32_t ERQ22:1;
+ vuint32_t ERQ21:1;
+ vuint32_t ERQ20:1;
+ vuint32_t ERQ19:1;
+ vuint32_t ERQ18:1;
+ vuint32_t ERQ17:1;
+ vuint32_t ERQ16:1;
+ vuint32_t ERQ15:1;
+ vuint32_t ERQ14:1;
+ vuint32_t ERQ13:1;
+ vuint32_t ERQ12:1;
+ vuint32_t ERQ11:1;
+ vuint32_t ERQ10:1;
+ vuint32_t ERQ09:1;
+ vuint32_t ERQ08:1;
+ vuint32_t ERQ07:1;
+ vuint32_t ERQ06:1;
+ vuint32_t ERQ05:1;
+ vuint32_t ERQ04:1;
+ vuint32_t ERQ03:1;
+ vuint32_t ERQ02:1;
+ vuint32_t ERQ01:1;
+ vuint32_t ERQ00:1;
+ } B;
+ } ERQRL;
+
+ vuint8_t eDMA_reserved1[4]; /* Reserved 4 bytes (Base+0x0010-0x0013) */
+
+ union { /* nable Error Interrupt Low (Base+0x0014) */
+ vuint16_t R;
+ struct {
+ vuint32_t EEI31:1;
+ vuint32_t EEI30:1;
+ vuint32_t EEI29:1;
+ vuint32_t EEI28:1;
+ vuint32_t EEI27:1;
+ vuint32_t EEI26:1;
+ vuint32_t EEI25:1;
+ vuint32_t EEI24:1;
+ vuint32_t EEI23:1;
+ vuint32_t EEI22:1;
+ vuint32_t EEI21:1;
+ vuint32_t EEI20:1;
+ vuint32_t EEI19:1;
+ vuint32_t EEI18:1;
+ vuint32_t EEI17:1;
+ vuint32_t EEI16:1;
+ vuint32_t EEI15:1;
+ vuint32_t EEI14:1;
+ vuint32_t EEI13:1;
+ vuint32_t EEI12:1;
+ vuint32_t EEI11:1;
+ vuint32_t EEI10:1;
+ vuint32_t EEI09:1;
+ vuint32_t EEI08:1;
+ vuint32_t EEI07:1;
+ vuint32_t EEI06:1;
+ vuint32_t EEI05:1;
+ vuint32_t EEI04:1;
+ vuint32_t EEI03:1;
+ vuint32_t EEI02:1;
+ vuint32_t EEI01:1;
+ vuint32_t EEI00:1;
+ } B;
+ } EEIRL;
+
+ union { /* DMA Set Enable Request (Base+0x0018) */
+ vuint8_t R;
+ struct {
+ vuint8_t NOP:1;
+ vuint8_t SERQ:7;
+ } B;
+ } SERQR;
+
+ union { /* DMA Clear Enable Request (Base+0x0019) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1; /* vuint8_t NOP:1; */
+ vuint8_t CERQ:7;
+ } B;
+ } CERQR;
+
+ union { /* DMA Set Enable Error Interrupt (Base+0x001A) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1; /* vuint8_t NOP:1; */
+ vuint8_t SEEI:7;
+ } B;
+ } SEEIR;
+
+ union { /* DMA Clr Enable Error Interrupt (Base+0x001B) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CEEI:7;
+ } B;
+ } CEEIR;
+
+ union { /* DMA Clear Interrupt Request (Base+0x001C) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1; /* vuint8_t NOP:1; */
+ vuint8_t CINT:7;
+ } B;
+ } CIRQR;
+
+ union { /* DMA Clear error (Base+0x001D) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1; /* vuint8_t NOP:1; */
+ vuint8_t CERR:7;
+ } B;
+ } CERR;
+
+ union { /* DMA Set Start Bit (Base+0x001E) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1; /* vuint8_t NOP:1; */
+ vuint8_t SSB:7;
+ } B;
+ } SSBR;
+
+ union { /* DMA Clear Done Status Bit (Base+0x001F) */
+ vuint8_t R;
+ struct {
+ vuint8_t:1; /* vuint8_t NOP:1; */
+ vuint8_t CDSB:7;
+ } B;
+ } CDSBR;
+
+ vuint8_t eDMA_reserved2[4]; /* Reserved 4 bytes (Base+0x0020-0x0023) */
+
+ union { /* DMA Interrupt Req Low Ch31..0 (+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t INT31:1;
+ vuint32_t INT30:1;
+ vuint32_t INT29:1;
+ vuint32_t INT28:1;
+ vuint32_t INT27:1;
+ vuint32_t INT26:1;
+ vuint32_t INT25:1;
+ vuint32_t INT24:1;
+ vuint32_t INT23:1;
+ vuint32_t INT22:1;
+ vuint32_t INT21:1;
+ vuint32_t INT20:1;
+ vuint32_t INT19:1;
+ vuint32_t INT18:1;
+ vuint32_t INT17:1;
+ vuint32_t INT16:1;
+ vuint32_t INT15:1;
+ vuint32_t INT14:1;
+ vuint32_t INT13:1;
+ vuint32_t INT12:1;
+ vuint32_t INT11:1;
+ vuint32_t INT10:1;
+ vuint32_t INT09:1;
+ vuint32_t INT08:1;
+ vuint32_t INT07:1;
+ vuint32_t INT06:1;
+ vuint32_t INT05:1;
+ vuint32_t INT04:1;
+ vuint32_t INT03:1;
+ vuint32_t INT02:1;
+ vuint32_t INT01:1;
+ vuint32_t INT00:1;
+ } B;
+ } IRQRL;
+
+ vuint8_t eDMA_reserved3[4]; /* Reserved 4 bytes (Base+0x0028-0x002B) */
+
+ union { /* DMA Error Low Ch31..0 (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t ERR31:1;
+ vuint32_t ERR30:1;
+ vuint32_t ERR29:1;
+ vuint32_t ERR28:1;
+ vuint32_t ERR27:1;
+ vuint32_t ERR26:1;
+ vuint32_t ERR25:1;
+ vuint32_t ERR24:1;
+ vuint32_t ERR23:1;
+ vuint32_t ERR22:1;
+ vuint32_t ERR21:1;
+ vuint32_t ERR20:1;
+ vuint32_t ERR19:1;
+ vuint32_t ERR18:1;
+ vuint32_t ERR17:1;
+ vuint32_t ERR16:1;
+ vuint32_t ERR15:1;
+ vuint32_t ERR14:1;
+ vuint32_t ERR13:1;
+ vuint32_t ERR12:1;
+ vuint32_t ERR11:1;
+ vuint32_t ERR10:1;
+ vuint32_t ERR09:1;
+ vuint32_t ERR08:1;
+ vuint32_t ERR07:1;
+ vuint32_t ERR06:1;
+ vuint32_t ERR05:1;
+ vuint32_t ERR04:1;
+ vuint32_t ERR03:1;
+ vuint32_t ERR02:1;
+ vuint32_t ERR01:1;
+ vuint32_t ERR00:1;
+ } B;
+ } ERL;
+
+ vuint8_t eDMA_reserved4[4]; /* Reserved 4 bytes (Base+0x0030-0x0033) */
+
+ union { /* DMA Hardware Request Stat Low (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t HRS31:1;
+ vuint32_t HRS30:1;
+ vuint32_t HRS29:1;
+ vuint32_t HRS28:1;
+ vuint32_t HRS27:1;
+ vuint32_t HRS26:1;
+ vuint32_t HRS25:1;
+ vuint32_t HRS24:1;
+ vuint32_t HRS23:1;
+ vuint32_t HRS22:1;
+ vuint32_t HRS21:1;
+ vuint32_t HRS20:1;
+ vuint32_t HRS19:1;
+ vuint32_t HRS18:1;
+ vuint32_t HRS17:1;
+ vuint32_t HRS16:1;
+ vuint32_t HRS15:1;
+ vuint32_t HRS14:1;
+ vuint32_t HRS13:1;
+ vuint32_t HRS12:1;
+ vuint32_t HRS11:1;
+ vuint32_t HRS10:1;
+ vuint32_t HRS09:1;
+ vuint32_t HRS08:1;
+ vuint32_t HRS07:1;
+ vuint32_t HRS06:1;
+ vuint32_t HRS05:1;
+ vuint32_t HRS04:1;
+ vuint32_t HRS03:1;
+ vuint32_t HRS02:1;
+ vuint32_t HRS01:1;
+ vuint32_t HRS00:1;
+ } B;
+ } HRSL;
+
+ vuint8_t eDMA_reserved5[200]; /* Reserved 200 bytes (Base+0x0038-0x00FF)*/
+
+ union { /* Channel n Priority (Base+0x0100-0x011F) */
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1;
+ vuint8_t DPA:1;
+ vuint8_t GRPPRI:2;
+ vuint8_t CHPRI:4;
+ } B;
+ } CPR[32];
+
+ vuint8_t eDMA_reserved6[3808]; /* Reserved 3808 bytes (+0x0120-0x0FFF) */
+
+
+ union { /* 4 different TCD definitions depending on operating mode */
+
+ /* Default TCD (Channel Linking and Minor Loop Maping disabled) */
+ struct EDMA_TCD_STD_tag TCD[32];
+
+ /* ML_TCD (Channel Linking disabled, Minor Loop Mapping enabled) */
+ struct EDMA_TCD_MLMIRROR_tag ML_TCD[32];
+
+ /* CL_TCD (Channel Linking enabled, Minor Loop Mapping disabled) */
+ struct EDMA_TCD_CHLINK_tag CL_TCD[32];
+
+ /* MLCL_TCD (Channel Linking enabled, Minor Loop Mapping enabled) */
+ struct EDMA_TCD_MLMIRROR_CHLINK_tag MLCL_TCD[32];
+ };
+
+}; /* end of EDMA_tag */
+/*************************************************************************/
+/* MODULE : INTC */
+/*************************************************************************/
+
+struct INTC_tag {
+
+ union { /* INTC Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t VTES_PRC1:1;
+ vuint32_t:4;
+ vuint32_t HVEN_PRC1:1;
+ vuint32_t:2;
+ vuint32_t VTES_PRC0:1;
+ vuint32_t:4;
+ vuint32_t HVEN_PRC0:1;
+ } B;
+ } MCR;
+
+ vuint8_t INTC_reserved0[4]; /* reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* INTC Current Priority Proc0 (Z4) (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR_PRC0;
+
+ union { /* INTC Current Priority Proc1 (Z0) (Base+0x000C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4;
+ } B;
+ } CPR_PRC1;
+
+ union { /* INTC Interrupt Acknowledge Proc0 (Z4) (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA_PRC0:21;
+ vuint32_t INTVEC_PRC0:9;
+ vuint32_t:2;
+ } B;
+ } IACKR_PRC0;
+
+ union { /* INTC Interrupt Acknowledge Proc1 (Z0) (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA_PRC1:21;
+ vuint32_t INTVEC_PRC1:9;
+ vuint32_t:2;
+ } B;
+ } IACKR_PRC1;
+
+ union { /* INTC End Of Interrupt Proc0 (Z4) (Base+0x0018) */
+ vuint32_t R;
+ /* CHIBIOS FIX
+ struct {
+ vuint32_t:32;
+ } B;*/
+ } EOIR_PRC0;
+
+ union { /* INTC End Of Interrupt Proc1 (Z0) (Base+0x001C) */
+ vuint32_t R;
+ /* CHIBIOS FIX
+ struct {
+ vuint32_t:32;
+ } B;*/
+ } EOIR_PRC1;
+
+ union { /* INTC Software Set/Clear Interrupt0-7 (+0x0020-0x0027) */
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1;
+ vuint8_t CLR:1;
+ } B;
+ } SSCIR[8];
+
+ vuint8_t INTC_reserved1[24]; /* Reserved 24 bytes (Base+0x0028-0x003F) */
+
+ union { /* INTC Priority Select (Base+0x0040-0x0157) */
+ vuint8_t R;
+ struct {
+ vuint8_t PRC_SEL:2;
+ vuint8_t:2;
+ vuint8_t PRI:4;
+ } B;
+ } PSR[279];
+
+}; /* end of INTC_tag */
+/****************************************************************************/
+/* MODULE : FEC (Fast Ethernet Controller) */
+/****************************************************************************/
+struct FEC_tag {
+
+ vuint8_t FEC_reserved0[4100]; /*Reserved 4100 bytes (Base+0x0000-0x0103)*/
+
+ union { /* FEC Interrupt Event (Base+0x1004) */
+ vuint32_t R;
+ struct {
+ vuint32_t HBERR:1;
+ vuint32_t BABR:1;
+ vuint32_t BABT:1;
+ vuint32_t GRA:1;
+ vuint32_t TXF:1;
+ vuint32_t TXB:1;
+ vuint32_t RXF:1;
+ vuint32_t RXB:1;
+ vuint32_t MII:1;
+ vuint32_t EBERR:1;
+ vuint32_t LC:1;
+ vuint32_t RL:1;
+ vuint32_t UN:1;
+ vuint32_t:19;
+ } B;
+ } EIR;
+
+ union { /* Interrupt Mask (Base+0x1008) */
+ vuint32_t R;
+ struct {
+ vuint32_t HBERR:1;
+ vuint32_t BABR:1;
+ vuint32_t BABT:1;
+ vuint32_t GRA:1;
+ vuint32_t TXF:1;
+ vuint32_t TXB:1;
+ vuint32_t RXF:1;
+ vuint32_t RXB:1;
+ vuint32_t MII:1;
+ vuint32_t EBERR:1;
+ vuint32_t LC:1;
+ vuint32_t RL:1;
+ vuint32_t UN:1;
+ vuint32_t:19;
+ } B;
+ } EIMR;
+
+ vuint8_t FEC_reserved1[4]; /* Reserved 4 Bytes (Base+0x100C-0x100F) */
+
+ union { /* FEC Receive Descriptor Active (Base+0x1010) */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t R_DES_ACTIVE:1;
+ vuint32_t:24;
+ } B;
+ } RDAR;
+
+ union { /* FEC TX Descriptor Active (Base+0x1014) */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t X_DES_ACTIVE:1;
+ vuint32_t:24;
+ } B;
+ } TDAR;
+
+ vuint8_t FEC_reserved2[12]; /* Reserved 12 Bytes (Base+0x1018-0x1023) */
+
+ union { /* FEC Ethernet Control (Base+0x1024) */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t ETHER_EN:1;
+ vuint32_t RESET:1;
+ } B;
+ } ECR;
+
+ vuint8_t FEC_reserved3[24]; /* Reserved 24 Bytes (Base+0x1028-0x103F) */
+
+ union { /* FEC Management Frame (Base+0x1040) */
+ vuint32_t R;
+ struct {
+ vuint32_t ST:2;
+ vuint32_t OP:2;
+ vuint32_t PA:5;
+ vuint32_t RA:5;
+ vuint32_t TA:2;
+ vuint32_t DATA:16;
+ } B;
+ } MDATA;
+
+ union { /* FEC MII Speed Control (Base+0x1044) */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DIS_PREAMBLE:1;
+ vuint32_t MII_SPEED:6;
+ vuint32_t:1;
+ } B;
+ } MSCR;
+
+ vuint8_t FEC_reserved4[28]; /* Reserved 28 Bytes (Base+0x1048-0x1063) */
+
+ union { /* FEC MIB Control (Base+0x1064) */
+ vuint32_t R;
+ struct {
+ vuint32_t MIB_DISABLE:1;
+ vuint32_t MIB_IDLE:1;
+ vuint32_t:30;
+ } B;
+ } MIBC;
+
+ vuint8_t FEC_reserved5[28]; /* Reserved 28 Bytes (Base+0x1068-0x1083) */
+
+ union { /* FEC Receive Control (Base+0x1084) */
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t MAX_FL:11;
+ vuint32_t:10;
+ vuint32_t FCE:1;
+ vuint32_t BC_REJ:1;
+ vuint32_t PROM:1;
+ vuint32_t MII_MODE:1;
+ vuint32_t DRT:1;
+ vuint32_t LOOP:1;
+ } B;
+ } RCR;
+
+ vuint8_t FEC_reserved6[60]; /* Reserved 60 Bytes (Base+0x1088-0x10C3) */
+
+ union { /* FEC Transmit Control (Base+0x10C4) */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t RFC_PAUSE:1;
+ vuint32_t TFC_PAUSE:1;
+ vuint32_t FDEN:1;
+ vuint32_t HBC:1;
+ vuint32_t GTS:1;
+ } B;
+ } TCR;
+
+ vuint8_t FEC_reserved7[28]; /* Reserved 28 Bytes (Base+0x10C8-0x10E3) */
+
+ union { /* FEC Physical Address Low (Base+0x10E4) */
+ vuint32_t R;
+ struct {
+ vuint32_t PADDR1:32;
+ } B;
+ } PALR;
+
+ union { /* FEC Physical Address High (Base+0x10E8) */
+ vuint32_t R;
+ struct {
+ vuint32_t PADDR2:16;
+ vuint32_t TYPE:16;
+ } B;
+ } PAUR;
+
+ union { /* Opcode/Pause Duration (Base+0x10EC) */
+ vuint32_t R;
+ struct {
+ vuint32_t OPCODE:16;
+ vuint32_t PAUSE_DUR:16;
+ } B;
+ } OPD;
+
+ vuint8_t FEC_reserved8[40]; /* Reserved 40 Bytes (Base+0x10F0-0x1117) */
+
+ union { /*FEC Descriptor Individual Upper Addr (+0x1118)*/
+ vuint32_t R;
+ struct {
+ vuint32_t IADDR1:32;
+ } B;
+ } IAUR;
+
+ union { /*FEC Descriptor Individual Lower Addr (+0x111C)*/
+ vuint32_t R;
+ struct {
+ vuint32_t IADDR2:32;
+ } B;
+ } IALR;
+
+ union { /* FEC Descriptor Group Upper Addr (Base+0x1120)*/
+ vuint32_t R;
+ struct {
+ vuint32_t GADDR1:32;
+ } B;
+ } GAUR;
+
+ union { /* FEC Descriptor Group Lower Addr (Base+0x1124)*/
+ vuint32_t R;
+ struct {
+ vuint32_t GADDR2:32;
+ } B;
+ } GALR;
+
+ vuint8_t FEC_reserved9[28]; /* Reserved 28 Bytes (Base+0x1128-0x1143) */
+
+ union { /* FEC FIFO Transmit FIFO Watermark (+0x1144) */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t X_WMRK:2;
+ } B;
+ } TFWR;
+
+ vuint8_t FEC_reserved10[4]; /* Reserved 4 Bytes (Base+0x1148-0x114B) */
+
+ union { /* FEC FIFO Receive Bound (Base+0x114C) */
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t R_BOUND:8;
+ vuint32_t:2;
+ } B;
+ } FRBR;
+
+ union { /* FEC FIFO Receive FIFO Start (Base+0x1150) */
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t R_FSTART:8;
+ vuint32_t:2;
+ } B;
+ } FRSR;
+
+ vuint8_t FEC_reserved11[44]; /* Reserved 44 Bytes (Base+0x1154-0x117F) */
+
+ union { /* FEC Receive Descriptor Ring Start (+0x1180) */
+ vuint32_t R;
+ struct {
+ vuint32_t R_DES_START:30;
+ vuint32_t:2;
+ } B;
+ } ERDSR;
+
+ union { /* FEC Transmit Descriptor Ring Start (+0x1184) */
+ vuint32_t R;
+ struct {
+ vuint32_t X_DES_START:30;
+ vuint32_t:2;
+ } B;
+ } ETDSR;
+
+ union { /* FEC Max Receive Buffer Size (Base+0x1188) */
+ vuint32_t R;
+ struct {
+ vuint32_t:21;
+ vuint32_t R_BUF_SIZE:7;
+ vuint32_t:4;
+ } B;
+ } EMRBR;
+
+ vuint8_t FEC_reserved12[116]; /*Reserved 116 Bytes (Base+0x118C-0x11FF) */
+
+
+ /* --- FEC MIB Counters Registers Below (Base+0x12000) --- */
+
+ union { /* MIB Count frames not counted correctly (Base+0x1200)*/
+ vuint32_t R;
+ } RMON_T_DROP;
+
+ union { /* MIB RMON Tx packet count (Base+0x1204) */
+ vuint32_t R;
+ } RMON_T_PACKETS;
+
+ union { /* MIB RMON Tx Broadcast Packets (Base+0x1208) */
+ vuint32_t R;
+ } RMON_T_BC_PKT;
+
+ union { /* MIB RMON Tx Multicast Packets (Base+0x120C) */
+ vuint32_t R;
+ } RMON_T_MC_PKT;
+
+ union { /* MIB RMON Tx Packets w CRC/Align err (+0x1210)*/
+ vuint32_t R;
+ } RMON_T_CRC_ALIGN;
+
+ union { /* MIB RMON Tx Packets < 64 bytes, good crc (+0x1214)*/
+ vuint32_t R;
+ } RMON_T_UNDERSIZE;
+
+ union { /* RMON Tx Packets > MAX_FL bytes, good crc (+0x1218) */
+ vuint32_t R;
+ } RMON_T_OVERSIZE;
+
+ union { /* MIB RMON Tx Packets < 64 bytes, bad crc (+0x121C) */
+ vuint32_t R;
+ } RMON_T_FRAG;
+
+ union { /* MIB RMON Tx Packets > MAX_FL bytes, bad crc (+0x1220) */
+ vuint32_t R;
+ } RMON_T_JAB;
+
+ union { /* MIB RMON Tx collision count (Base+0x1224)*/
+ vuint32_t R;
+ } RMON_T_COL;
+
+ union { /* MIB RMON Tx 64 byte packets (Base+0x1228) */
+ vuint32_t R;
+ } RMON_T_P64;
+
+ union { /* MIB RMON Tx 65 to 127 byte packets (+0x122C) */
+ vuint32_t R;
+ } RMON_T_P65TO127;
+
+ union { /* MIB RMON Tx 128 to 255 byte packets (+0x1230)*/
+ vuint32_t R;
+ } RMON_T_P128TO255;
+
+ union { /* MIB RMON Tx 256 to 511 byte packets (+0x1234)*/
+ vuint32_t R;
+ } RMON_T_P256TO511;
+
+ union { /* MIB RMON Tx 512 to 1023 byte packets (+0x1238)*/
+ vuint32_t R;
+ } RMON_T_P512TO1023;
+
+ union { /* MIB RMON Tx 1024 to 2047 byte packets (+0x123C)*/
+ vuint32_t R;
+ } RMON_T_P1024TO2047;
+
+ union { /* MIB RMON Tx packets w > 2048 bytes (+0x1240) */
+ vuint32_t R;
+ } RMON_T_P_GTE2048;
+
+ union { /* MIB RMON Tx Octets (Base+0x1244) */
+ vuint32_t R;
+ } RMON_T_OCTETS;
+
+ union { /* MIB Count of frames not counted correct (+0x1248)*/
+ vuint32_t R;
+ } IEEE_T_DROP;
+
+ union { /* MIB Frames Transmitted OK (Base+124C) */
+ vuint32_t R;
+ } IEEE_T_FRAME_OK;
+
+ union { /* MIB Frames Tx'd with Single Collision (+0x1250)*/
+ vuint32_t R;
+ } IEEE_T_1COL;
+
+ union { /* MIB Frames Tx'd with mult Collision (+0x1254)*/
+ vuint32_t R;
+ } IEEE_T_MCOL;
+
+ union { /* MIB Frames Tx'd after Deferral Delay (+0x1258)*/
+ vuint32_t R;
+ } IEEE_T_DEF;
+
+ union { /* MIB Frames Tx'd with Late Collision (+0x125C)*/
+ vuint32_t R;
+ } IEEE_T_LCOL;
+
+ union { /* MIB Frames Tx'd with Excessive Collisions (+0x1260)*/
+ vuint32_t R;
+ } IEEE_T_EXCOL;
+
+ union { /* MIB Frames Tx'd with Tx FIFO Underrun (+0x1264)*/
+ vuint32_t R;
+ } IEEE_T_MACERR;
+
+ union { /* MIB Frames Tx'd with Carrier Sense Error (+0x1268) */
+ vuint32_t R;
+ } IEEE_T_CSERR;
+
+ union { /* MIB Frames Tx'd with SQE Error (Base+0x126C) */
+ vuint32_t R;
+ } IEEE_T_SQE;
+
+ union { /* MIB Flow Control Pause frames tx'd (+0x1270) */
+ vuint32_t R;
+ } IEEE_T_FDXFC;
+
+ union { /* MIB Octet count for Frames Tx'd w/o Error (+0x1274)*/
+ vuint32_t R;
+ } IEEE_T_OCTETS_OK;
+
+ vuint8_t FEC_reserved13[8]; /*Reserved 12 Bytes (Base+0x1278-0x127F) */
+
+ union { /* MIB RMON # frames not counted correct (+0x1280) */
+ vuint32_t R;
+ } RMON_R_DROP;
+
+ union { /* MIB RMON Rx packet count (Base+0x1284) */
+ vuint32_t R;
+ } RMON_R_PACKETS;
+
+ union { /* MIB RMON Rx Broadcast Packets (Base+0x1288) */
+ vuint32_t R;
+ } RMON_R_BC_PKT;
+
+ union { /* MIB RMON Rx Multicast Packets (Base+0x128C) */
+ vuint32_t R;
+ } RMON_R_MC_PKT;
+
+ union { /* MIB RMON Rx Packets w CRC/Align error (+0x1290)*/
+ vuint32_t R;
+ } RMON_R_CRC_ALIGN;
+
+ union { /* MIB RMON Rx Packets < 64 bytes, good crc (+0x1294)*/
+ vuint32_t R;
+ } RMON_R_UNDERSIZE;
+
+ union { /* MIB RMON Rx Packets > MAX_FL bytes, good crc (+0x1298)*/
+ vuint32_t R;
+ } RMON_R_OVERSIZE;
+
+ union { /* MIB RMON Rx Packets < 64 bytes, bad crc (+0x129C)*/
+ vuint32_t R;
+ } RMON_R_FRAG;
+
+ union { /* MIB RMON Rx Packets > MAX_FL bytes, bad crc (0x12A0)*/
+ vuint32_t R;
+ } RMON_R_JAB;
+
+ vuint8_t FEC_reserved14[4]; /*Reserved 4 Bytes (Base+0x12A4-0x12A7) */
+
+ union { /* MIB RMON Rx 64 byte packets (Base+0x12A8) */
+ vuint32_t R;
+ } RMON_R_P64;
+
+ union { /* MIB RMON Rx 65 to 127 byte packets (+0x12AC) */
+ vuint32_t R;
+ } RMON_R_P65TO127;
+
+ union { /* MIB RMON Rx 128 to 255 byte packets (+0x12B0)*/
+ vuint32_t R;
+ } RMON_R_P128TO255;
+
+ union { /* MIB RMON Rx 256 to 511 byte packets (+0x12B4)*/
+ vuint32_t R;
+ } RMON_R_P256TO511;
+
+ union { /* MIB RMON Rx 512 to 1023 byte packets (+0x12B8)*/
+ vuint32_t R;
+ } RMON_R_P512TO1023;
+
+ union { /* MIB RMON Rx 1024 to 2047 byte packets (+0x12BC)*/
+ vuint32_t R;
+ } RMON_R_P1024TO2047;
+
+ union { /* MIB RMON Rx packets w > 2048 bytes (+0x12C0) */
+ vuint32_t R;
+ } RMON_R_P_GTE2048;
+
+ union { /* MIB RMON Rx Octets (Base+0x12C4) */
+ vuint32_t R;
+ } RMON_R_OCTETS;
+
+ union { /* MIB Count of frames not counted correctly (+0x12C8)*/
+ vuint32_t R;
+ } IEEE_R_DROP;
+
+ union { /* MIB Frames Received OK (Base+0x12CC) */
+ vuint32_t R;
+ } IEEE_R_FRAME_OK;
+
+ union { /* MIB Frames Received with CRC Error (+0x12D0) */
+ vuint32_t R;
+ } IEEE_R_CRC;
+
+ union { /* MIB Frames Received Alignment Error (+0x12D4)*/
+ vuint32_t R;
+ } IEEE_R_ALIGN;
+
+ union { /* MIB Receive Fifo Overflow count (+0x12D8) */
+ vuint32_t R;
+ } IEEE_R_MACERR;
+
+ union { /* MIB Flow Control Pause frames Rx'd (+0x12DC) */
+ vuint32_t R;
+ } IEEE_R_FDXFC;
+
+ union { /* MIB Octet count for Frames Rcvd w/o Error (+0x12E0)*/
+ vuint32_t R;
+ } IEEE_R_OCTETS_OK;
+
+
+}; /* end of FEC_tag */
+/****************************************************************************/
+/* MODULE : DSPI */
+/****************************************************************************/
+struct DSPI_tag{
+
+ union { /* DSPI Module Configuraiton (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1;
+ vuint32_t CONT_SCKE:1;
+ vuint32_t DCONF:2;
+ vuint32_t FRZ:1;
+ vuint32_t MTFE:1;
+ vuint32_t PCSSE:1;
+ vuint32_t ROOE:1;
+ vuint32_t :2; /* Chip selects 6,7 not bonded out on B3M */
+ vuint32_t PCSIS5:1;
+ vuint32_t PCSIS4:1;
+ vuint32_t PCSIS3:1;
+ vuint32_t PCSIS2:1;
+ vuint32_t PCSIS1:1;
+ vuint32_t PCSIS0:1;
+ vuint32_t :1;
+ vuint32_t MDIS:1;
+ vuint32_t DIS_TXF:1;
+ vuint32_t DIS_RXF:1;
+ vuint32_t CLR_TXF:1;
+ vuint32_t CLR_RXF:1;
+ vuint32_t SMPL_PT:2;
+ vuint32_t :6;
+ vuint32_t PES:1;
+ vuint32_t HALT:1;
+ } B;
+ } MCR;
+
+ vuint8_t DSPI_reserved00[4]; /* Reserved 4 bytes (Base+0x0004-0x0007) */
+
+ union { /* DSPI Transfer Count (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t TCNT:16;
+ vuint32_t :16;
+ } B;
+ } TCR;
+
+ union { /* DSPI Clock & Tranfer Attrib 0-5 (+0x000C-0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1;
+ vuint32_t FMSZ:4;
+ vuint32_t CPOL:1;
+ vuint32_t CPHA:1;
+ vuint32_t LSBFE:1;
+ vuint32_t PCSSCK:2;
+ vuint32_t PASC:2;
+ vuint32_t PDT:2;
+ vuint32_t PBR:2;
+ vuint32_t CSSCK:4;
+ vuint32_t ASC:4;
+ vuint32_t DT:4;
+ vuint32_t BR:4;
+ } B;
+ } CTAR[6];
+
+ vuint8_t DSPI_reserved0[8]; /* Reserved 8 bytes (Base+0x0024-0x002B) */
+
+ union { /* DSPI Status (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1;
+ vuint32_t TXRXS:1;
+ vuint32_t :1;
+ vuint32_t EOQF:1;
+ vuint32_t TFUF:1;
+ vuint32_t :1;
+ vuint32_t TFFF:1;
+ vuint32_t :2;
+ vuint32_t DPEF:1; /* New on Bolero 3M */
+ vuint32_t SPEF:1; /* New on Bolero 3M */
+ vuint32_t DDIF:1; /* New on Bolero 3M */
+ vuint32_t RFOF:1;
+ vuint32_t :1;
+ vuint32_t RFDF:1;
+ vuint32_t :1;
+ vuint32_t TXCTR:4;
+ vuint32_t TXNXTPTR:4;
+ vuint32_t RXCTR:4;
+ vuint32_t POPNXTPTR:4;
+ } B;
+ } SR;
+
+ union { /* DSPI DMA/Int Request Select & Enable (+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t TCFRE:1;
+ vuint32_t :2;
+ vuint32_t EOQFRE:1;
+ vuint32_t TFUFRE:1;
+ vuint32_t :1;
+ vuint32_t TFFFRE:1;
+ vuint32_t TFFFDIRS:1;
+ vuint32_t :1;
+ vuint32_t DPEFRE:1; /* New on Bolero 3M */
+ vuint32_t SPEFRE:1; /* New on Bolero 3M */
+ vuint32_t DDIFRE:1; /* New on Bolero 3M */
+ vuint32_t RFOFRE:1;
+ vuint32_t :1;
+ vuint32_t RFDFRE:1;
+ vuint32_t RFDFDIRS:1;
+ vuint32_t :16;
+ } B;
+ } RSER;
+
+ union { /* DSPI Push TX FIFO (Base+0x0034) */
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1;
+ vuint32_t CTAS:3;
+ vuint32_t EOQ:1;
+ vuint32_t CTCNT:1;
+ vuint32_t PE:1; /* New on Bolero 3M */
+ vuint32_t PP:1; /* New on Bolero 3M */
+ vuint32_t :2; /* PCS 7..6 not implemented on B3M */
+ vuint32_t PCS5:1;
+ vuint32_t PCS4:1;
+ vuint32_t PCS3:1;
+ vuint32_t PCS2:1;
+ vuint32_t PCS1:1;
+ vuint32_t PCS0:1;
+ vuint32_t TXDATA:16;
+ } B;
+ } PUSHR;
+
+ union { /* DSPI Pop RX FIFO (Base+0x0038) */
+ vuint32_t R;
+ struct {
+ vuint32_t RXDATA:32; /* Changed t0 32-bit data on B3M */
+ } B;
+ } POPR;
+
+ union { /* DSPI Transmit FIFO 0-3 (Base+0x003C-0x0048)*/
+ vuint32_t R;
+ struct { /* This is MASTER mode config for B3M */
+ vuint32_t TXCMD:16; /* replace with TXDATA for B3M slave mode*/
+ vuint32_t TXDATA:16;
+ } B;
+ } TXFR[4];
+
+ vuint8_t DSPI_reserved1[48]; /* Reserved 48 bytes (Base+0x004C-0x007B) */
+
+ union { /* DSPI Receive FIFO 0-3 (Base+0x007C-0x0088) */
+ vuint32_t R;
+ struct {
+ vuint32_t RXDATA:32; /* Changed to 32-bit data on B3M */
+ } B;
+ } RXFR[4];
+
+ vuint8_t DSPI_reserved2[48]; /* Reserved 48 bytes (Base+0x008C-0x00BB) */
+
+ union { /* DSPI DSI Configuration (Base+0x00BC) */
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1;
+ vuint32_t FMSZ4:1; /* New on Bolero 3M */
+ vuint32_t MTOCNT:6;
+ vuint32_t :3;
+ vuint32_t TSBC:1; /* New on Bolero 3M */
+ vuint32_t TXSS:1;
+ vuint32_t TPOL:1;
+ vuint32_t TRRE:1;
+ vuint32_t CID:1;
+ vuint32_t DCONT:1;
+ vuint32_t DSICTAS:3;
+ vuint32_t DMS:1; /* New on Bolero 3M */
+ vuint32_t PES:1; /* New on Bolero 3M */
+ vuint32_t PE:1; /* New on Bolero 3M */
+ vuint32_t PP:1; /* New on Bolero 3M */
+ vuint32_t :2; /* PCS 7..6 not implemented on B3M */
+ vuint32_t DPCS5:1;
+ vuint32_t DPCS4:1;
+ vuint32_t DPCS3:1;
+ vuint32_t DPCS2:1;
+ vuint32_t DPCS1:1;
+ vuint32_t DPCS0:1;
+ } B;
+ } DSICR;
+
+ union { /* DSPI DSI Serialization Data (Base+0x00C0) */
+ vuint32_t R;
+ struct {
+ vuint32_t SER_DATA:32; /* Changed to 32-bit data on B3M */
+ } B;
+ } SDR;
+
+ union { /* DSPI ALT DSI Serialization Data (Base+0x00C4) */
+ vuint32_t R;
+ struct {
+ vuint32_t ASER_DATA:32; /* Changed to 32-bit data on B3M */
+ } B;
+ } ASDR;
+
+ union { /* DSPI DSI Transmit Comparison (Base+0x00C8) */
+ vuint32_t R;
+ struct {
+ vuint32_t COMP_DATA:32; /* Changed to 32-bit data on B3M */
+ } B;
+ } COMPR;
+
+ union { /* DSPI DSI Deserialization Data (Base+0x00CC) */
+ vuint32_t R;
+ struct {
+ vuint32_t DESER_DATA:32; /* Changed to 32-bit data on B3M */
+ } B;
+ } DDR;
+
+ union { /* DSPI DSI Configuration 1 (Base+0x00D0) */
+ vuint32_t R; /* NB this reg was missing from 1.5M header! */
+ struct {
+ vuint32_t :3;
+ vuint32_t TSBCNT:5;
+ vuint32_t :6;
+ vuint32_t DSE1:1;
+ vuint32_t DSE0:1;
+ vuint32_t :8;
+ vuint32_t :1; /* vuint32_t DPCS1_7:1; (Not implemented on B3m)*/
+ vuint32_t :1; /* vuint32_t DPCS1_6:1; (Not implemented on B3m)*/
+ vuint32_t DPCS1_5:1;
+ vuint32_t DPCS1_4:1;
+ vuint32_t DPCS1_3:1;
+ vuint32_t DPCS1_2:1;
+ vuint32_t DPCS1_1:1;
+ vuint32_t DPCS1_0:1;
+ } B;
+ } DSICR1;
+
+ union { /* DSPI DSI Serialisation Source (Base+0x00D4) */
+ vuint32_t R;
+ struct {
+ vuint32_t SS:32; /* All bits avail for B3M */
+ } B;
+ } SSR;
+
+ vuint8_t DSPI_reserved4[16]; /* Reserved 16 bytes (Base+0x00D8-0x00E7) */
+
+ union { /* DSPI DSI Deserialised Data Interrupt Mask (+0x00E8) */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:32; /* 32-bit for B3M */
+ } B;
+ } DIMR;
+
+ union { /* DSPI DSI Deserialised Data Poloarity Int (+0x00E8) */
+ vuint32_t R;
+ struct {
+ vuint32_t DP:32; /* 32-bit for B3M */
+ } B;
+ } DPIR;
+
+}; /* end of DSPI_tag */
+/****************************************************************************/
+/* MODULE : FlexCAN */
+/****************************************************************************/
+struct FLEXCAN_BUF_t{
+
+ union { /* FLEXCAN MBx Control & Status (Offset+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :4;
+ vuint32_t CODE:4;
+ vuint32_t :1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union { /* FLEXCAN MBx Identifier (Offset+0x0084) */
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union { /* FLEXCAN MBx Data 0..7 (Offset+0x0088) */
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } DATA;
+
+}; /* end of FLEXCAN_BUF_t */
+
+
+struct FLEXCAN_RXFIFO_t{ /* RxFIFO Configuration */
+
+ union { /* RxFIFO Control & Status (Offset+0x0080) */
+ vuint32_t R;
+ struct {
+ vuint32_t :9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union { /* RxFIFO Identifier (Offset+0x0084) */
+ vuint32_t R;
+ struct {
+ vuint32_t :3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union { /* RxFIFO Data 0..7 (Offset+0x0088) */
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } DATA;
+
+ vuint8_t FLEXCAN_RX_reserved0[80]; /* Reserved 80 bytes (+0x0090-0x00DF)*/
+
+ union { /* RxFIFO ID Table 0..7 (+0x00E0-0x00FC) */
+ vuint32_t R;
+ } IDTABLE[8];
+
+}; /* end of FLEXCAN_RXFIFO_t */
+
+
+struct FLEXCAN_tag{
+
+ union { /* FLEXCAN Module Configuration (Base+0x0000) */
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLFWAK:1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t DOZE:1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t :2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t :2;
+ vuint32_t IDAM:2;
+ vuint32_t :2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR;
+
+ union { /* FLEXCAN Control (Base+0x0004) */
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t :2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR;
+
+ union { /* FLEXCAN Free Running Timer (Base+0x0008) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t TIMER:16;
+ } B;
+ } TIMER;
+
+ vuint8_t FLEXCAN_reserved0[4]; /* reserved 4 bytes (Base+0x000C-0x000F) */
+
+ union { /* FLEXCAN RX Global Mask (Base+0x0010) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK;
+
+ /* --- Following 2 registers are included for legacy purposes only --- */
+
+ union { /* FLEXCAN RX 14 Mask (Base+0x0014) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK;
+
+ union { /* FLEXCAN RX 15 Mask (Base+0x0018) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK;
+
+ /* --- */
+
+ union { /* FLEXCAN Error Counter (Base+0x001C) */
+ vuint32_t R;
+ struct {
+ vuint32_t :16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR;
+
+ union { /* FLEXCAN Error & Status (Base+0x0020) */
+ vuint32_t R;
+ struct {
+ vuint32_t :14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t :1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAKINT:1;
+ } B;
+ } ESR;
+
+ union { /* FLEXCAN Interruput Masks H (Base+0x0024) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH;
+
+ union { /* FLEXCAN Interruput Masks L (Base+0x0028) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL;
+
+ union { /* FLEXCAN Interruput Flag H (Base+0x002C) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH;
+
+ union { /* FLEXCAN Interruput Flag l (Base+0x0030) */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interruput Flag Register */
+
+ vuint8_t FLEXCAN_reserved1[76]; /*Reserved 76 bytes (Base+0x0034-0x007F)*/
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUF_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_t RXFIFO; */
+ /*struct FLEXCAN_BUF_t BUF[56]; */
+/****************************************************************************/
+
+ vuint8_t FLEXCAN_reserved2[1024]; /*Reserved 1024 (Base+0x0480-0x087F)*/
+
+ union { /* FLEXCAN RX Individual Mask (Base+0x0880-0x097F) */
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64];
+
+}; /* end of FLEXCAN_tag */
+/****************************************************************************/
+/* MODULE : DMAMUX */
+/****************************************************************************/
+struct DMAMUX_tag {
+
+ union { /* DMAMUX Channel Configuration (Base+0x0000-0x000F) */
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1;
+ vuint8_t TRIG:1;
+ vuint8_t SOURCE:6;
+ } B;
+ } CHCONFIG[32];
+
+}; /* end of DMAMUX_tag */
+/******************************************************************
+| defines and macros (scope: module-local)
+|-----------------------------------------------------------------*/
+/* Define instances of modules (in address order) */
+
+#define CFLASH_0 (*(volatile struct CFLASH_tag *) 0xC3F88000UL)
+#define DFLASH (*(volatile struct DFLASH_tag *) 0xC3F8C000UL)
+#define SIU (*(volatile struct SIU_tag *) 0xC3F90000UL)
+#define WKUP (*(volatile struct WKUP_tag *) 0xC3F94000UL)
+#define EMIOS_0 (*(volatile struct EMIOS_tag *) 0xC3FA0000UL)
+#define EMIOS_1 (*(volatile struct EMIOS_tag *) 0xC3FA4000UL)
+#define CFLASH_1 (*(volatile struct CFLASH_tag *) 0xC3FB0000UL)
+#define SSCM (*(volatile struct SSCM_tag *) 0xC3FD8000UL)
+#define ME (*(volatile struct ME_tag *) 0xC3FDC000UL)
+#define CGM (*(volatile struct CGM_tag *) 0xC3FE0000UL)
+#define RGM (*(volatile struct RGM_tag *) 0xC3FE4000UL)
+#define PCU (*(volatile struct PCU_tag *) 0xC3FE8000UL)
+#define RTC (*(volatile struct RTC_tag *) 0xC3FEC000UL)
+#define PIT (*(volatile struct PIT_tag *) 0xC3FF0000UL)
+#define STCU (*(volatile struct STCU_tag *) 0xC3FF4000UL)
+#define ADC_0 (*(volatile struct ADC0_tag *) 0xFFE00000UL)
+#define ADC_1 (*(volatile struct ADC1_tag *) 0xFFE04000UL)
+#define I2C (*(volatile struct I2C_tag *) 0xFFE30000UL)
+#define LINFLEX_0 (*(volatile struct LINFLEX_MS_tag *) 0xFFE40000UL)
+#define LINFLEX_1 (*(volatile struct LINFLEX_M_tag *) 0xFFE44000UL)
+#define LINFLEX_2 (*(volatile struct LINFLEX_M_tag *) 0xFFE48000UL)
+#define LINFLEX_3 (*(volatile struct LINFLEX_M_tag *) 0xFFE4C000UL)
+#define LINFLEX_4 (*(volatile struct LINFLEX_M_tag *) 0xFFE50000UL)
+#define LINFLEX_5 (*(volatile struct LINFLEX_M_tag *) 0xFFE54000UL)
+#define LINFLEX_6 (*(volatile struct LINFLEX_M_tag *) 0xFFE58000UL)
+#define LINFLEX_7 (*(volatile struct LINFLEX_M_tag *) 0xFFE5C000UL)
+#define CTU (*(volatile struct CTU_tag *) 0xFFE64000UL)
+#define CANSP (*(volatile struct CANSP_tag *) 0xFFE70000UL)
+#define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL)
+#define MPU (*(volatile struct MPU_tag *) 0xFFF10000UL)
+#define CSE (*(volatile struct CSE_tag *) 0xFFF1C000UL)
+#define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF24000UL)
+#define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
+#define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
+#define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
+#define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
+#define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
+#define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL)
+#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFF90000UL)
+#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFF94000UL)
+#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFFF98000UL)
+#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFFF9C000UL)
+#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFFA0000UL)
+#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFFFA4000UL)
+#define DSPI_6 (*(volatile struct DSPI_tag *) 0xFFFA8000UL)
+#define DSPI_7 (*(volatile struct DSPI_tag *) 0xFFFAC000UL)
+#define LINFLEX_8 (*(volatile struct LINFLEX_M_tag *) 0xFFFB0000UL)
+#define LINFLEX_9 (*(volatile struct LINFLEX_M_tag *) 0xFFFB4000UL)
+#define CAN_0 (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
+#define CAN_1 (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
+#define CAN_2 (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
+#define CAN_3 (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
+#define CAN_4 (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
+#define CAN_5 (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
+#define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
+
+// Flexray is NOT added to this header. Expected use is that Flexray is used with drivers.
+
+
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/* End of file */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/cfg/mcuconf.h.ftl b/os/hal/ports/SPC5/SPC56ELxx/cfg/mcuconf.h.ftl new file mode 100644 index 000000000..b4c02206e --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/cfg/mcuconf.h.ftl @@ -0,0 +1,272 @@ +[#ftl]
+[@pp.dropOutputFile /]
+[@pp.changeOutputFile name="mcuconf.h" /]
+/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _MCUCONF_H_
+#define _MCUCONF_H_
+
+/*
+ * SPC56ELxx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 1...15 Lowest...Highest.
+ * DMA priorities:
+ * 0...15 Highest...Lowest.
+ */
+
+#define SPC56ELxx_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define SPC5_NO_INIT ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
+#define SPC5_ALLOW_OVERCLOCK ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
+#define SPC5_DISABLE_WATCHDOG ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
+#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_${conf.instance.initialization_settings.fmpll0_settings.clock_source.value[0]}
+#define SPC5_FMPLL0_IDF_VALUE ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
+#define SPC5_FMPLL0_NDIV_VALUE ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL0_ODF ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
+#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_${conf.instance.initialization_settings.fmpll1_settings.clock_source.value[0]}
+#define SPC5_FMPLL1_IDF_VALUE ${conf.instance.initialization_settings.fmpll1_settings.idf_value.value[0]}
+#define SPC5_FMPLL1_NDIV_VALUE ${conf.instance.initialization_settings.fmpll1_settings.ndiv_value.value[0]}
+#define SPC5_FMPLL1_ODF ${conf.instance.initialization_settings.fmpll1_settings.odf_value.value[0]}
+#define SPC5_SYSCLK_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.system_clock_divider.value[0]}
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux0_clock_source.value[0]}
+#define SPC5_MCONTROL_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.motor_control_clock_divider.value[0]}
+#define SPC5_SWG_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.swg_clock_divider.value[0]}
+#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux1_clock_source.value[0]}
+#define SPC5_FLEXRAY_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.flexray_clock_divider.value[0]}
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux2_clock_source.value[0]}
+#define SPC5_FLEXCAN_DIVIDER_VALUE ${conf.instance.initialization_settings.clocks.flexcan_clock_divider.value[0]}
+#define SPC5_CLOCK_FAILURE_HOOK() ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
+
+/*
+ * EDMA driver settings.
+ */
+#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP1PRI(1) | \
+ EDMA_CR_GRP0PRI(0) | \
+ EDMA_CR_EMLM | \
+ EDMA_CR_ERGA)
+#define SPC5_EDMA_GROUP0_PRIORITIES [#rt/]
+[#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
+ [#if channel_has_next]
+${channel.value[0]}, [#rt/]
+ [#else]
+${channel.value[0]}
+ [/#if]
+[/#list]
+#define SPC5_EDMA_ERROR_IRQ_PRIO 12
+#define SPC5_EDMA_ERROR_HANDLER() osalSysHalt("DMA failure")
+
+/*
+ * PWM driver system settings.
+ */
+[#assign pwm0_all_sm = conf.instance.flexpwm_settings.synchronized_flexpwm0.value[0]?upper_case /]
+[#assign pwm1_all_sm = conf.instance.flexpwm_settings.synchronized_flexpwm1.value[0]?upper_case /]
+#define SPC5_PWM0_USE_SYNC_SMOD ${pwm0_all_sm}
+#define SPC5_PWM1_USE_SYNC_SMOD ${pwm1_all_sm}
+#define SPC5_PWM_USE_SMOD0 ${conf.instance.flexpwm_settings.flexpwm0_sm0.value[0]?upper_case}
+[#if pwm0_all_sm == "FALSE"]
+#define SPC5_PWM_USE_SMOD1 ${conf.instance.flexpwm_settings.flexpwm0_sm1.value[0]?upper_case}
+#define SPC5_PWM_USE_SMOD2 ${conf.instance.flexpwm_settings.flexpwm0_sm2.value[0]?upper_case}
+#define SPC5_PWM_USE_SMOD3 ${conf.instance.flexpwm_settings.flexpwm0_sm3.value[0]?upper_case}
+[#else]
+#define SPC5_PWM_USE_SMOD1 TRUE
+#define SPC5_PWM_USE_SMOD2 TRUE
+#define SPC5_PWM_USE_SMOD3 TRUE
+[/#if]
+#define SPC5_PWM_SMOD0_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm0.value[0]}
+#define SPC5_PWM_SMOD1_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm1.value[0]}
+#define SPC5_PWM_SMOD2_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm2.value[0]}
+#define SPC5_PWM_SMOD3_PRIORITY ${conf.instance.irq_priority_settings.flexpwm0_sm3.value[0]}
+
+#define SPC5_PWM_USE_SMOD4 ${conf.instance.flexpwm_settings.flexpwm1_sm0.value[0]?upper_case}
+[#if pwm1_all_sm == "FALSE"]
+#define SPC5_PWM_USE_SMOD5 ${conf.instance.flexpwm_settings.flexpwm1_sm1.value[0]?upper_case}
+#define SPC5_PWM_USE_SMOD6 ${conf.instance.flexpwm_settings.flexpwm1_sm2.value[0]?upper_case}
+#define SPC5_PWM_USE_SMOD7 ${conf.instance.flexpwm_settings.flexpwm1_sm3.value[0]?upper_case}
+[#else]
+#define SPC5_PWM_USE_SMOD5 TRUE
+#define SPC5_PWM_USE_SMOD6 TRUE
+#define SPC5_PWM_USE_SMOD7 TRUE
+[/#if]
+#define SPC5_PWM_SMOD4_PRIORITY ${conf.instance.irq_priority_settings.flexpwm1_sm0.value[0]}
+#define SPC5_PWM_SMOD5_PRIORITY ${conf.instance.irq_priority_settings.flexpwm1_sm1.value[0]}
+#define SPC5_PWM_SMOD6_PRIORITY ${conf.instance.irq_priority_settings.flexpwm1_sm2.value[0]}
+#define SPC5_PWM_SMOD7_PRIORITY ${conf.instance.irq_priority_settings.flexpwm1_sm3.value[0]}
+
+/*
+ * ICU driver system settings.
+ */
+#define SPC5_ICU_USE_SMOD0 ${conf.instance.etimer_settings.etimer0_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD1 ${conf.instance.etimer_settings.etimer0_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD2 ${conf.instance.etimer_settings.etimer0_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD3 ${conf.instance.etimer_settings.etimer0_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD4 ${conf.instance.etimer_settings.etimer0_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD5 ${conf.instance.etimer_settings.etimer0_ch5.value[0]?upper_case}
+#define SPC5_ICU_ETIMER0_PRIORITY ${conf.instance.irq_priority_settings.etimer0.value[0]}
+
+#define SPC5_ICU_USE_SMOD6 ${conf.instance.etimer_settings.etimer1_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD7 ${conf.instance.etimer_settings.etimer1_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD8 ${conf.instance.etimer_settings.etimer1_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD9 ${conf.instance.etimer_settings.etimer1_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD10 ${conf.instance.etimer_settings.etimer1_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD11 ${conf.instance.etimer_settings.etimer1_ch5.value[0]?upper_case}
+#define SPC5_ICU_ETIMER1_PRIORITY ${conf.instance.irq_priority_settings.etimer1.value[0]}
+
+#define SPC5_ICU_USE_SMOD12 ${conf.instance.etimer_settings.etimer2_ch0.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD13 ${conf.instance.etimer_settings.etimer2_ch1.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD14 ${conf.instance.etimer_settings.etimer2_ch2.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD15 ${conf.instance.etimer_settings.etimer2_ch3.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD16 ${conf.instance.etimer_settings.etimer2_ch4.value[0]?upper_case}
+#define SPC5_ICU_USE_SMOD17 ${conf.instance.etimer_settings.etimer2_ch5.value[0]?upper_case}
+#define SPC5_ICU_ETIMER2_PRIORITY ${conf.instance.irq_priority_settings.etimer2.value[0]}
+
+/*
+ * SERIAL driver system settings.
+ */
+#define SPC5_SERIAL_USE_LINFLEX0 ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_USE_LINFLEX1 ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
+#define SPC5_SERIAL_LINFLEX0_PRIORITY ${conf.instance.irq_priority_settings.linflex0.value[0]}
+#define SPC5_SERIAL_LINFLEX1_PRIORITY ${conf.instance.irq_priority_settings.linflex1.value[0]}
+
+/*
+ * SPI driver system settings.
+ */
+#define SPC5_SPI_USE_DSPI0 ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI1 ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
+#define SPC5_SPI_USE_DSPI2 ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
+#define SPC5_SPI_DMA_MODE SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
+[#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
+[#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
+[#assign s6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs6[0].@index[0]?trim?number] /]
+[#assign s7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs7[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI0_MCR (0${s0 + s1 + s2 + s3 + s4 + s5 + s6 + s7})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI1_MCR (0${s0 + s1 + s2 + s3})
+[#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
+[#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
+[#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
+[#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
+#define SPC5_SPI_DSPI2_MCR (0${s0 + s1 + s2 + s3})
+#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
+#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
+#define SPC5_SPI_DSPI0_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
+#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
+#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
+#define SPC5_SPI_DSPI1_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
+#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
+#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
+#define SPC5_SPI_DSPI2_RX_DMA_CH_ID ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
+#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DSPI0_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_0.value[0]}
+#define SPC5_SPI_DSPI1_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_1.value[0]}
+#define SPC5_SPI_DSPI2_IRQ_PRIO ${conf.instance.irq_priority_settings.dspi_2.value[0]}
+#define SPC5_SPI_DMA_ERROR_HOOK(spip) ${conf.instance.dspi_settings.dma_error_hook.value[0]}
+
+/*
+ * CAN driver system settings.
+ */
+#define SPC5_CAN_USE_FILTERS ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
+
+#define SPC5_CAN_USE_FLEXCAN0 ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan0.value[0]}
+#define SPC5_CAN_NUM_RX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
+#define SPC5_CAN_NUM_TX_MAILBOXES ${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
+#define SPC5_CAN_FLEXCAN0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN1 ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan1.value[0]}
+#define SPC5_CAN_FLEXCAN1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#define SPC5_CAN_USE_FLEXCAN2 ${conf.instance.flexcan_settings.flexcan2.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_USE_EXT_CLK ${conf.instance.flexcan_settings.flexcan2_use_external_clock.value[0]?upper_case}
+#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY ${conf.instance.irq_priority_settings.flexcan2.value[0]}
+#define SPC5_CAN_FLEXCAN2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_CAN_FLEXCAN2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+/*
+* ADC driver system settings.
+*/
+[#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+
+[#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
+ [#assign dma_mode = "SPC5_ADC_DMA_ON"]
+[#else]
+ [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
+[/#if]
+
+#define SPC5_ADC_DMA_MODE ${dma_mode}
+
+#define SPC5_ADC_USE_ADC0 ${conf.instance.adc_settings.adc0.value[0]?upper_case}
+#define SPC5_ADC_ADC0_CLK_FREQUENCY ${clk_f0}
+#define SPC5_ADC_ADC0_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC0_WD_PRIORITY ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_EOC_PRIORITY SPC5_ADC_ADC0_WD_PRIORITY
+#define SPC5_ADC_ADC0_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
+#define SPC5_ADC_ADC0_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc0.value[0]}
+#define SPC5_ADC_ADC0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+[#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
+ [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[#else]
+ [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
+[/#if]
+#define SPC5_ADC_USE_ADC1 ${conf.instance.adc_settings.adc1.value[0]?upper_case}
+#define SPC5_ADC_ADC1_CLK_FREQUENCY ${clk_f1}
+#define SPC5_ADC_ADC1_AUTO_CLOCK_OFF ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
+#define SPC5_ADC_ADC1_WD_PRIORITY ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_EOC_PRIORITY SPC5_ADC_ADC1_WD_PRIORITY
+#define SPC5_ADC_ADC1_DMA_CH_ID ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
+#define SPC5_ADC_ADC1_DMA_IRQ_PRIO ${conf.instance.irq_priority_settings.adc1.value[0]}
+#define SPC5_ADC_ADC1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
+ SPC5_ME_PCTL_LP(2))
+#define SPC5_ADC_ADC1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
+ SPC5_ME_PCTL_LP(0))
+
+#endif /* _MCUCONF_H_ */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/hal_lld.c b/os/hal/ports/SPC5/SPC56ELxx/hal_lld.c new file mode 100644 index 000000000..ff7356dc0 --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/hal_lld.c @@ -0,0 +1,306 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/hal_lld.c
+ * @brief SPC56ELxx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+ uint32_t n;
+
+ /* The system is switched to the RUN0 mode, the default for normal
+ operations.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Decrementer timer initialized for system tick use, note, it is
+ initialized here because in the OSAL layer the system clock frequency
+ is not yet known.*/
+ n = halSPCGetSystemClock() / OSAL_ST_FREQUENCY;
+ asm volatile ("mtspr 22, %[n] \t\n" /* Init. DEC register. */
+ "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/
+ "e_lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */
+ "mtspr 340, %%r3" /* TCR register. */
+ : : [n] "r" (n) : "r3");
+
+ /* TB counter enabled for debug and measurements.*/
+ asm volatile ("e_li %%r3, 0x4000 \t\n" /* TBEN bit. */
+ "mtspr 1008, %%r3" /* HID0 register. */
+ : : : "r3");
+
+ /* EDMA initialization.*/
+ edmaInit();
+}
+
+/**
+ * @brief SPC56ELxx early initialization.
+ * @note All the involved constants come from the file @p board.h and
+ * @p hal_lld.h
+ * @note This function must be invoked only after the system reset.
+ *
+ * @special
+ */
+void spc_clock_init(void) {
+
+ /* Waiting for IRC stabilization before attempting anything else.*/
+ while (!ME.GS.B.S_IRCOSC)
+ ;
+
+#if !SPC5_NO_INIT
+
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* Enabling peripheral bridges to allow any operation.*/
+ AIPS.MPROT.R = 0x77777777;
+ AIPS.PACR0_7.R = 0;
+ AIPS.PACR8_15.R = 0;
+ AIPS.PACR16_23.R = 0;
+ AIPS.PACR24_31.R = 0;
+ AIPS.OPACR0_7.R = 0;
+ AIPS.OPACR8_15.R = 0;
+ AIPS.OPACR16_23.R = 0;
+ AIPS.OPACR24_31.R = 0;
+ AIPS.OPACR32_39.R = 0;
+ AIPS.OPACR40_47.R = 0;
+ AIPS.OPACR48_55.R = 0;
+ AIPS.OPACR56_63.R = 0;
+ AIPS.OPACR64_71.R = 0;
+ AIPS.OPACR72_79.R = 0;
+ AIPS.OPACR80_87.R = 0;
+ AIPS.OPACR88_95.R = 0;
+
+ /* SSCM initialization. Setting up the most restrictive handling of
+ invalid accesses to peripherals.*/
+ SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+
+ /* FCCU CF errors clearing.*/
+ FCCU.CFK.R = 0x618B7A50;
+ FCCU.CFS[0].R = 0xFFFFFFFF;
+ while (FCCU.CTRL.B.OPS != 3)
+ ;
+ FCCU.CFK.R = 0x618B7A50;
+ FCCU.CFS[1].R = 0xFFFFFFFF;
+ while (FCCU.CTRL.B.OPS != 3)
+ ;
+
+ /* FCCU NCF errors clearing.*/
+ FCCU.NCFK.R = 0xAB3498FE;
+ FCCU.NCFS[0].R = 0xFFFFFFFF;
+ while (FCCU.CTRL.B.OPS != 3)
+ ;
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
+ /* The system must be in DRUN mode on entry, if this is not the case then
+ it is considered a serious anomaly.*/
+ if (ME.GS.B.S_CURRENT_MODE != SPC5_RUNMODE_DRUN) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#if defined(SPC5_OSC_BYPASS)
+ /* If the board is equipped with an oscillator instead of a crystal then the
+ bypass must be activated.*/
+ CGM.OSC_CTL.B.OSCBYP = TRUE;
+#endif /* SPC5_OSC_BYPASS */
+
+ /* Setting the various dividers and source selectors.*/
+ CGM.SC_DC0.R = SPC5_CGM_SC_DC0;
+ CGM.AC0_DC0_3.R = SPC5_CGM_AC0_DC0 | SPC5_CGM_AC0_DC1;
+ CGM.AC0_SC.R = SPC5_AUX0CLK_SRC;
+ CGM.AC1_DC0_3.R = SPC5_CGM_AC1_DC0;
+ CGM.AC1_SC.R = SPC5_AUX1CLK_SRC;
+ CGM.AC2_DC0_3.R = SPC5_CGM_AC2_DC0;
+ CGM.AC2_SC.R = SPC5_AUX2CLK_SRC;
+ CGM.AC3_SC.R = SPC5_FMPLL0_CLK_SRC;
+ CGM.AC4_SC.R = SPC5_FMPLL1_CLK_SRC;
+
+ /* Enables the XOSC in order to check its functionality before proceeding
+ with the initialization.*/
+ ME.DRUN.R = SPC5_ME_MC_SYSCLK_IRC | SPC5_ME_MC_IRCON | SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_FLAON_NORMAL | SPC5_ME_MC_MVRON;
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Initialization of the FMPLLs settings.
+ TODO: Add settings for the MR registers.*/
+ CGM.FMPLL[0].CR.R = SPC5_FMPLL0_ODF |
+ ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL0_NDIV_VALUE << 16);
+ CGM.FMPLL[0].MR.R = 0;
+ CGM.FMPLL[1].CR.R = SPC5_FMPLL1_ODF |
+ ((SPC5_FMPLL1_IDF_VALUE - 1) << 26) |
+ (SPC5_FMPLL1_NDIV_VALUE << 16);
+ CGM.FMPLL[1].MR.R = 0;
+
+ /* Run modes initialization, note writes to the MC registers are verified
+ by a protection mechanism, the operation success is verified at the
+ end of the sequence.*/
+ ME.IS.R = 8; /* Resetting I_ICONF status.*/
+ ME.MER.R = SPC5_ME_ME_BITS; /* Enabled run modes. */
+ ME.SAFE.R = SPC5_ME_SAFE_MC_BITS; /* SAFE run mode. */
+ ME.DRUN.R = SPC5_ME_DRUN_MC_BITS; /* DRUN run mode. */
+ ME.RUN[0].R = SPC5_ME_RUN0_MC_BITS; /* RUN0 run mode. */
+ ME.RUN[1].R = SPC5_ME_RUN1_MC_BITS; /* RUN1 run mode. */
+ ME.RUN[2].R = SPC5_ME_RUN2_MC_BITS; /* RUN2 run mode. */
+ ME.RUN[3].R = SPC5_ME_RUN3_MC_BITS; /* RUN0 run mode. */
+ ME.HALT0.R = SPC5_ME_HALT0_MC_BITS; /* HALT0 run mode. */
+ ME.STOP0.R = SPC5_ME_STOP0_MC_BITS; /* STOP0 run mode. */
+ if (ME.IS.B.I_ICONF) {
+ /* Configuration rejected.*/
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+ /* Peripherals run and low power modes initialization.*/
+ ME.RUNPC[0].R = SPC5_ME_RUN_PC0_BITS;
+ ME.RUNPC[1].R = SPC5_ME_RUN_PC1_BITS;
+ ME.RUNPC[2].R = SPC5_ME_RUN_PC2_BITS;
+ ME.RUNPC[3].R = SPC5_ME_RUN_PC3_BITS;
+ ME.RUNPC[4].R = SPC5_ME_RUN_PC4_BITS;
+ ME.RUNPC[5].R = SPC5_ME_RUN_PC5_BITS;
+ ME.RUNPC[6].R = SPC5_ME_RUN_PC6_BITS;
+ ME.RUNPC[7].R = SPC5_ME_RUN_PC7_BITS;
+ ME.LPPC[0].R = SPC5_ME_LP_PC0_BITS;
+ ME.LPPC[1].R = SPC5_ME_LP_PC1_BITS;
+ ME.LPPC[2].R = SPC5_ME_LP_PC2_BITS;
+ ME.LPPC[3].R = SPC5_ME_LP_PC3_BITS;
+ ME.LPPC[4].R = SPC5_ME_LP_PC4_BITS;
+ ME.LPPC[5].R = SPC5_ME_LP_PC5_BITS;
+ ME.LPPC[6].R = SPC5_ME_LP_PC6_BITS;
+ ME.LPPC[7].R = SPC5_ME_LP_PC7_BITS;
+
+ /* CFLASH settings initialized for a maximum clock of 120MHz.*/
+ CFLASH.PFCR0.B.B02_APC = 3;
+ CFLASH.PFCR0.B.B02_WWSC = 3;
+ CFLASH.PFCR0.B.B02_RWSC = 3;
+
+ /* Switches again to DRUN mode (current mode) in order to update the
+ settings.*/
+ if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == OSAL_FAILED) {
+ SPC5_CLOCK_FAILURE_HOOK();
+ }
+
+#endif /* !SPC5_NO_INIT */
+}
+
+/**
+ * @brief Switches the system to the specified run mode.
+ *
+ * @param[in] mode one of the possible run modes
+ *
+ * @return The operation status.
+ * @retval OSAL_SUCCESS if the switch operation has been completed.
+ * @retval OSAL_FAILED if the switch operation failed.
+ */
+bool halSPCSetRunMode(spc5_runmode_t mode) {
+
+ /* Clearing status register bits I_IMODE(4) and I_IMTC(1).*/
+ ME.IS.R = 5;
+
+ /* Starts a transition process.*/
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+
+ /* Waits for the mode switch or an error condition.*/
+ while (TRUE) {
+ uint32_t r = ME.IS.R;
+ if (r & 1)
+ return OSAL_SUCCESS;
+ if (r & 4)
+ return OSAL_FAILED;
+ }
+}
+
+/**
+ * @brief Changes the clock mode of a peripheral.
+ *
+ * @param[in] n index of the @p PCTL register
+ * @param[in] pctl new value for the @p PCTL register
+ *
+ * @notapi
+ */
+void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) {
+ uint32_t mode;
+
+ ME.PCTL[n].R = pctl;
+ mode = ME.MCTL.B.TARGET_MODE;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY;
+ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY_INV;
+}
+
+#if !SPC5_NO_INIT || defined(__DOXYGEN__)
+/**
+ * @brief Returns the system clock under the current run mode.
+ *
+ * @return The system clock in Hertz.
+ */
+uint32_t halSPCGetSystemClock(void) {
+ uint32_t sysclk;
+
+ sysclk = ME.GS.B.S_SYSCLK;
+ switch (sysclk) {
+ case SPC5_ME_GS_SYSCLK_IRC:
+ return SPC5_IRC_CLK;
+ case SPC5_ME_GS_SYSCLK_XOSC:
+ return SPC5_XOSC_CLK;
+ case SPC5_ME_GS_SYSCLK_FMPLL0:
+ return SPC5_FMPLL0_CLK;
+ default:
+ return 0;
+ }
+}
+#endif /* !SPC5_NO_INIT */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/hal_lld.h b/os/hal/ports/SPC5/SPC56ELxx/hal_lld.h new file mode 100644 index 000000000..100d1ef01 --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/hal_lld.h @@ -0,0 +1,1000 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/hal_lld.h
+ * @brief SPC56ELxx HAL subsystem low level driver header.
+ * @pre This module requires the following macros to be defined in the
+ * @p board.h file:
+ * - SPC5_XOSC_CLK.
+ * - SPC5_OSC_BYPASS (optionally).
+ * .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H
+#define HAL_LLD_H
+
+#include "registers.h"
+#include "spc5_registry.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS TRUE
+
+/**
+ * @name Platform identification
+ * @{
+ */
+#define PLATFORM_NAME "SPC56ELxx Chassis and Safety"
+/** @} */
+
+/**
+ * @name Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief Maximum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MAX 40000000
+
+/**
+ * @brief Minimum XOSC clock frequency.
+ */
+#define SPC5_XOSC_CLK_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MIN 4000000
+
+/**
+ * @brief Maximum FMPLLs input clock frequency.
+ */
+#define SPC5_FMPLLIN_MAX 40000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MAX 512000000
+
+/**
+ * @brief Maximum FMPLLs VCO clock frequency.
+ */
+#define SPC5_FMPLLVCO_MIN 256000000
+
+/**
+ * @brief Maximum FMPLL0 output clock frequency.
+ */
+#define SPC5_FMPLL0_CLK_MAX 120000000
+
+/**
+ * @brief Maximum FMPLL1 output clock frequency.
+ */
+#define SPC5_FMPLL1_CLK_MAX 120000000
+
+/**
+ * @brief Maximum FMPLL1 1D1 output clock frequency.
+ */
+#define SPC5_FMPLL1_1D1_CLK_MAX 80000000
+/** @} */
+
+/**
+ * @name Internal clock sources
+ * @{
+ */
+#define SPC5_IRC_CLK 16000000 /**< Internal RC oscillator.*/
+/** @} */
+
+/**
+ * @name FMPLLs register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_SRC_IRC (0U << 24)
+#define SPC5_FMPLL_SRC_XOSC (1U << 24)
+/** @} */
+
+/**
+ * @name FMPLL_CR register bits definitions
+ * @{
+ */
+#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
+#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
+#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
+#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
+/** @} */
+
+/**
+ * @name Clock selectors used in the various GCM SC registers
+ * @{
+ */
+#define SPC5_CGM_SS_MASK (15U << 24)
+#define SPC5_CGM_SS_IRC (0U << 24)
+#define SPC5_CGM_SS_XOSC (2U << 24)
+#define SPC5_CGM_SS_FMPLL0 (4U << 24)
+#define SPC5_CGM_SS_FMPLL1 (5U << 24)
+#define SPC5_CGM_SS_FMPLL1_1D1 (8U << 24)
+/** @} */
+
+/**
+ * @name ME_GS register bits definitions
+ * @{
+ */
+#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
+#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
+#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
+/** @} */
+
+/**
+ * @name ME_ME register bits definitions
+ * @{
+ */
+#define SPC5_ME_ME_RESET (1U << 0)
+#define SPC5_ME_ME_SAFE (1U << 2)
+#define SPC5_ME_ME_DRUN (1U << 3)
+#define SPC5_ME_ME_RUN0 (1U << 4)
+#define SPC5_ME_ME_RUN1 (1U << 5)
+#define SPC5_ME_ME_RUN2 (1U << 6)
+#define SPC5_ME_ME_RUN3 (1U << 7)
+#define SPC5_ME_ME_HALT0 (1U << 8)
+#define SPC5_ME_ME_STOP0 (1U << 10)
+/** @} */
+
+/**
+ * @name ME_xxx_MC registers bits definitions
+ * @{
+ */
+#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
+#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
+#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
+#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
+#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
+#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
+#define SPC5_ME_MC_IRCON (1U << 4)
+#define SPC5_ME_MC_XOSC0ON (1U << 5)
+#define SPC5_ME_MC_PLL0ON (1U << 6)
+#define SPC5_ME_MC_PLL1ON (1U << 7)
+#define SPC5_ME_MC_FLAON_MASK ((3U << 16) | (3U << 18))
+#define SPC5_ME_MC_FLAON(n) (((n) << 16) | ((n) << 18))
+#define SPC5_ME_MC_FLAON_PD ((1U << 16) | (1U << 18))
+#define SPC5_ME_MC_FLAON_LP ((2U << 16) | (2U << 18))
+#define SPC5_ME_MC_FLAON_NORMAL ((3U << 16) | (3U << 18))
+#define SPC5_ME_MC_MVRON (1U << 20)
+#define SPC5_ME_MC_PDO (1U << 23)
+/** @} */
+
+/**
+ * @name ME_MCTL register bits definitions
+ * @{
+ */
+#define SPC5_ME_MCTL_KEY 0x5AF0U
+#define SPC5_ME_MCTL_KEY_INV 0xA50FU
+#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
+#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
+/** @} */
+
+/**
+ * @name ME_RUN_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_RUN_PC_SAFE (1U << 2)
+#define SPC5_ME_RUN_PC_DRUN (1U << 3)
+#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
+#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
+#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
+#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
+/** @} */
+
+/**
+ * @name ME_LP_PCx registers bits definitions
+ * @{
+ */
+#define SPC5_ME_LP_PC_HALT0 (1U << 8)
+#define SPC5_ME_LP_PC_STOP0 (1U << 10)
+/** @} */
+
+/**
+ * @name ME_PCTL registers bits definitions
+ * @{
+ */
+#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
+#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
+#define SPC5_ME_PCTL_LP_MASK (7U << 3)
+#define SPC5_ME_PCTL_LP(n) ((n) << 3)
+#define SPC5_ME_PCTL_DBG (1U << 6)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Disables the clocks initialization in the HAL.
+ */
+#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
+#define SPC5_NO_INIT FALSE
+#endif
+
+/**
+ * @brief Disables the overclock checks.
+ */
+#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
+#define SPC5_ALLOW_OVERCLOCK FALSE
+#endif
+
+/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
+ * @brief FMPLL0 Clock source.
+ */
+#if !defined(SPC5_FMPLL0_CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_CLK_SRC SPC5_FMPLL_SRC_XOSC
+#endif
+
+/**
+ * @brief FMPLL0 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL0 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_NDIV_VALUE 60
+#endif
+
+/**
+ * @brief FMPLL0 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief FMPLL1 Clock source.
+ */
+#if !defined(SPC5_FMPLL1_CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_CLK_SRC SPC5_FMPLL_SRC_XOSC
+#endif
+
+/**
+ * @brief FMPLL1 IDF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL1_IDF_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_IDF_VALUE 5
+#endif
+
+/**
+ * @brief FMPLL1 NDIV divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL1_NDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_NDIV_VALUE 60
+#endif
+
+/**
+ * @brief FMPLL1 ODF divider value.
+ * @note The default value is calculated for XOSC=40MHz and PHI=120MHz.
+ */
+#if !defined(SPC5_FMPLL1_ODF) || defined(__DOXYGEN__)
+#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
+#endif
+
+/**
+ * @brief System clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_SYSCLK_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_SYSCLK_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX0 clock source.
+ */
+#if !defined(SPC5_AUX0CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief Motor Control clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_MCONTROL_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_MCONTROL_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief SWG clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_SWG_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_SWG_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX1 clock source.
+ * @note Used by Flexray.
+ */
+#if !defined(SPC5_AUX1CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX1CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief Flexray clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_FLEXRAY_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FLEXRAY_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief AUX2 clock source.
+ * @note Used by FlexCAN.
+ */
+#if !defined(SPC5_AUX2CLK_SRC) || defined(__DOXYGEN__)
+#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
+#endif
+
+/**
+ * @brief FlexCAN clock divider value.
+ * @note Zero means disabled clock.
+ */
+#if !defined(SPC5_FLEXCAN_DIVIDER_VALUE) || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_DIVIDER_VALUE 2
+#endif
+
+/**
+ * @brief Active run modes in ME_ME register.
+ * @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
+ * is no need to specify them.
+ */
+#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
+ SPC5_ME_ME_RUN2 | \
+ SPC5_ME_ME_RUN3 | \
+ SPC5_ME_ME_HALT0 | \
+ SPC5_ME_ME_STOP0)
+#endif
+
+/**
+ * @brief SAFE mode settings.
+ */
+#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
+#endif
+
+/**
+ * @brief DRUN mode settings.
+ */
+#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN0 mode settings.
+ */
+#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN1 mode settings.
+ */
+#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN2 mode settings.
+ */
+#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief RUN3 mode settings.
+ */
+#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief HALT0 mode settings.
+ */
+#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief STOP0 mode settings.
+ */
+#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
+ SPC5_ME_MC_IRCON | \
+ SPC5_ME_MC_XOSC0ON | \
+ SPC5_ME_MC_PLL0ON | \
+ SPC5_ME_MC_PLL1ON | \
+ SPC5_ME_MC_FLAON_NORMAL | \
+ SPC5_ME_MC_MVRON)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (run mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (run mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_SAFE | \
+ SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (run mode).
+ * @note Do not change this setting, it is expected to be the "only during
+ * normal run" mode.
+ */
+#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
+ SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (run mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
+ SPC5_ME_RUN_PC_RUN1 | \
+ SPC5_ME_RUN_PC_RUN2 | \
+ SPC5_ME_RUN_PC_RUN3)
+#endif
+
+/**
+ * @brief Peripheral mode 0 (low power mode).
+ * @note Do not change this setting, it is expected to be the "never run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC0_BITS 0
+#endif
+
+/**
+ * @brief Peripheral mode 1 (low power mode).
+ * @note Do not change this setting, it is expected to be the "always run"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 2 (low power mode).
+ * @note Do not change this setting, it is expected to be the "halt only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
+#endif
+
+/**
+ * @brief Peripheral mode 3 (low power mode).
+ * @note Do not change this setting, it is expected to be the "stop only"
+ * mode.
+ */
+#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 4 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 5 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 6 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Peripheral mode 7 (low power mode).
+ * @note Not defined, available to application-specific modes.
+ */
+#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
+#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
+ SPC5_ME_LP_PC_STOP0)
+#endif
+
+/**
+ * @brief Clock initialization failure hook.
+ * @note The default is to stop the system and let the RTC restart it.
+ * @note The hook code must not return.
+ */
+#if !defined(SPC5_CLOCK_FAILURE_HOOK) || defined(__DOXYGEN__)
+#define SPC5_CLOCK_FAILURE_HOOK() osalSysHalt("clock failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(SPC56ELxx_MCUCONF)
+#error "Using a wrong mcuconf.h file, SPC56ELxx_MCUCONF not defined"
+#endif
+
+/* Check on the XOSC frequency.*/
+#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
+ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
+#error "invalid SPC5_XOSC_CLK value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/
+#if SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_IRC
+#define SPC5_FMPLL0_INPUT_CLK SPC5_IRC_CLK
+#elif SPC5_FMPLL0_CLK_SRC == SPC5_FMPLL_SRC_XOSC
+#define SPC5_FMPLL0_INPUT_CLK SPC5_XOSC_CLK
+#else
+#error "invalid SPC5_FMPLL0_CLK_SRC value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_IDF_VALUE.*/
+#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
+#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL0_ODF.*/
+#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL0_ODF_VALUE 2
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL0_ODF_VALUE 4
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL0_ODF_VALUE 8
+#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL0_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL0_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL0_VCO_CLK \
+ ((SPC5_FMPLL0_INPUT_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
+
+/* Check on FMPLL0 VCO output.*/
+#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL0_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL0_CLK clock point.
+ */
+#define SPC5_FMPLL0_CLK \
+ (SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
+
+/* Check on SPC5_FMPLL0_CLK.*/
+#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
+#endif
+
+/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/
+#if SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_IRC
+#define SPC5_FMPLL1_INPUT_CLK SPC5_IRC_CLK
+#elif SPC5_FMPLL1_CLK_SRC == SPC5_FMPLL_SRC_XOSC
+#define SPC5_FMPLL1_INPUT_CLK SPC5_XOSC_CLK
+#else
+#error "invalid SPC5_FMPLL1_CLK_SRC value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_IDF_VALUE.*/
+#if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)
+#error "invalid SPC5_FMPLL1_IDF_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_NDIV_VALUE.*/
+#if (SPC5_FMPLL1_NDIV_VALUE < 32) || (SPC5_FMPLL1_NDIV_VALUE > 96)
+#error "invalid SPC5_FMPLL1_NDIV_VALUE value specified"
+#endif
+
+/* Check on SPC5_FMPLL1_ODF.*/
+#if (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV2)
+#define SPC5_FMPLL1_ODF_VALUE 2
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV4)
+#define SPC5_FMPLL1_ODF_VALUE 4
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV8)
+#define SPC5_FMPLL1_ODF_VALUE 8
+#elif (SPC5_FMPLL1_ODF == SPC5_FMPLL_ODF_DIV16)
+#define SPC5_FMPLL1_ODF_VALUE 16
+#else
+#error "invalid SPC5_FMPLL1_ODF value specified"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_VCO_CLK clock point.
+ */
+#define SPC5_FMPLL1_VCO_CLK \
+ ((SPC5_FMPLL1_INPUT_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)
+
+/* Check on FMPLL1 VCO output.*/
+#if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
+ (SPC5_FMPLL1_VCO_CLK > SPC5_FMPLLVCO_MAX)
+#error "SPC5_FMPLL1_VCO_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
+#endif
+
+/**
+ * @brief SPC5_FMPLL1_CLK clock point.
+ */
+#define SPC5_FMPLL1_CLK \
+ (SPC5_FMPLL1_VCO_CLK / SPC5_FMPLL1_ODF_VALUE)
+
+/**
+ * @brief SPC5_FMPLL1_1D1_CLK clock point.
+ */
+#define SPC5_FMPLL1_1D1_CLK \
+ (SPC5_FMPLL1_VCO_CLK / 6)
+
+/* Check on SPC5_FMPLL1_CLK.*/
+#if (SPC5_FMPLL1_CLK > SPC5_FMPLL1_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
+#error "SPC5_FMPLL1_CLK outside acceptable range (0...SPC5_FMPLL1_CLK_MAX)"
+#endif
+
+/* Check on the system divider settings.*/
+#if SPC5_SYSCLK_DIVIDER_VALUE == 0
+#define SPC5_CGM_SC_DC0 0
+#elif (SPC5_SYSCLK_DIVIDER_VALUE >= 1) && (SPC5_SYSCLK_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_SC_DC0 (0x80 | (SPC5_SYSCLK_DIVIDER_VALUE - 1))
+#else
+#error "invalid SPC5_SYSCLK_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief AUX0 clock point.
+ */
+#if (SPC5_AUX0CLK_SRC == SPC5_CGM_SS_IRC) || defined(__DOXYGEN__)
+#define SPC5_AUX0_CLK SPC5_IRC_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_XOSC
+#define SPC5_AUX0_CLK SPC5_XOSC_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL0
+#define SPC5_AUX0_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX0_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX0CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
+#define SPC5_AUX0_CLK SPC5_FMPLL1_1D1_CLK
+#else
+#error "invalid SPC5_AUX0CLK_SRC value specified"
+#endif
+
+/* Check on the AUX0 divider 0 settings.*/
+#if SPC5_MCONTROL_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC0_DC0 0
+#elif (SPC5_MCONTROL_DIVIDER_VALUE >= 1) && (SPC5_MCONTROL_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC0_DC0 ((0x80U | (SPC5_MCONTROL_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_MCONTROL_DIVIDER_VALUE value specified"
+#endif
+
+/* Check on the AUX0 divider 1 settings.*/
+#if SPC5_SWG_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC0_DC1 0
+#elif (SPC5_SWG_DIVIDER_VALUE >= 1) && (SPC5_SWG_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC0_DC1 ((0x80U | (SPC5_SWG_DIVIDER_VALUE - 1)) << 16)
+#else
+#error "invalid SPC5_SWG_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief Motor Control clock point.
+ */
+#if (SPC5_MCONTROL_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_MCONTROL_CLK (SPC5_AUX0_CLK / SPC5_MCONTROL_DIVIDER_VALUE)
+#else
+#define SPC5_MCONTROL_CLK 0
+#endif
+
+/**
+ * @brief SWG clock point.
+ */
+#if (SPC5_SWG_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_SWG_CLK (SPC5_AUX0_CLK / SPC5_SWG_DIVIDER_VALUE)
+#else
+#define SPC5_SWG_CLK 0
+#endif
+
+/**
+ * @brief AUX1 clock point.
+ */
+#if (SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL0) || defined(__DOXYGEN__)
+#define SPC5_AUX1_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX1_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX1CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
+#define SPC5_AUX1_CLK SPC5_FMPLL1_1D1_CLK
+#else
+#error "invalid SPC5_AUX1CLK_SRC value specified"
+#endif
+
+/* Check on the AUX1 divider 0 settings.*/
+#if SPC5_FLEXRAY_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC1_DC0 0
+#elif (SPC5_FLEXRAY_DIVIDER_VALUE >= 1) && (SPC5_FLEXRAY_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC1_DC0 ((0x80U | (SPC5_FLEXRAY_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_FLEXRAY_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief Flexray clock point.
+ */
+#if (SPC5_FLEXRAY_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_FLEXRAY_CLK (SPC5_AUX2_CLK / SPC5_FLEXRAY_DIVIDER_VALUE)
+#else
+#define SPC5_FLEXRAY_CLK 0
+#endif
+
+/**
+ * @brief AUX2 clock point.
+ */
+#if (SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL0) || defined(__DOXYGEN__)
+#define SPC5_AUX2_CLK SPC5_FMPLL0_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1
+#define SPC5_AUX2_CLK SPC5_FMPLL1_CLK
+#elif SPC5_AUX2CLK_SRC == SPC5_CGM_SS_FMPLL1_1D1
+#define SPC5_AUX2_CLK SPC5_FMPLL1_1D1_CLK
+#else
+#error "invalid SPC5_AUX2CLK_SRC value specified"
+#endif
+
+/* Check on the AUX2 divider 0 settings.*/
+#if SPC5_FLEXCAN_DIVIDER_VALUE == 0
+#define SPC5_CGM_AC2_DC0 0
+#elif (SPC5_FLEXCAN_DIVIDER_VALUE >= 1) && (SPC5_FLEXCAN_DIVIDER_VALUE <= 16)
+#define SPC5_CGM_AC2_DC0 ((0x80U | (SPC5_FLEXCAN_DIVIDER_VALUE - 1)) << 24)
+#else
+#error "invalid SPC5_FLEXCAN_DIVIDER_VALUE value specified"
+#endif
+
+/**
+ * @brief FlexCAN clock point.
+ */
+#if (SPC5_FLEXCAN_DIVIDER_VALUE) != 0 || defined(__DOXYGEN)
+#define SPC5_FLEXCAN_CLK (SPC5_AUX2_CLK / SPC5_FLEXCAN_DIVIDER_VALUE)
+#else
+#define SPC5_FLEXCAN_CLK 0
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/**
+ * @brief Run modes.
+ */
+typedef enum {
+ SPC5_RUNMODE_SAFE = 2,
+ SPC5_RUNMODE_DRUN = 3,
+ SPC5_RUNMODE_RUN0 = 4,
+ SPC5_RUNMODE_RUN1 = 5,
+ SPC5_RUNMODE_RUN2 = 6,
+ SPC5_RUNMODE_RUN3 = 7,
+ SPC5_RUNMODE_HALT0 = 8,
+ SPC5_RUNMODE_STOP0 = 10
+} spc5_runmode_t;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Returns the current value of the system free running counter.
+ * @note This service is implemented by returning the content of the
+ * TBL register.
+ *
+ * @return The value of the system free running counter of
+ * type halrtcnt_t.
+ *
+ * @notapi
+ */
+static inline
+halrtcnt_t hal_lld_get_counter_value(void) {
+ halrtcnt_t cnt;
+
+ asm volatile ("mfspr %[cnt], 284" : [cnt] "=r" (cnt) : : );
+ return cnt;
+}
+
+/**
+ * @brief Realtime counter frequency.
+ *
+ * @return The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency() (halclock_t)halSPCGetSystemClock()
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#include "spc5_edma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void spc_clock_init(void);
+ bool halSPCSetRunMode(spc5_runmode_t mode);
+ void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
+#if !SPC5_NO_INIT
+ uint32_t halSPCGetSystemClock(void);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/platform.mk b/os/hal/ports/SPC5/SPC56ELxx/platform.mk new file mode 100644 index 000000000..72d862bd1 --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/platform.mk @@ -0,0 +1,21 @@ +# List of all the SPC56ELxx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/SPC5/SPC56ELxx/hal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1/spc5_edma.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1/hal_can_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eTimer_v1/hal_icu_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1/hal_pal_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexPWM_v1/hal_pwm_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1/hal_serial_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1/hal_spi_lld.c \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1/hal_st_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/SPC5/SPC56ELxx \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/EDMA_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexCAN_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/eTimer_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/SIUL_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/FlexPWM_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/LINFlex_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/DSPI_v1 \
+ ${CHIBIOS}/os/hal/ports/SPC5/SPC5xx/STM_v1
diff --git a/os/hal/ports/SPC5/SPC56ELxx/registers.h b/os/hal/ports/SPC5/SPC56ELxx/registers.h new file mode 100644 index 000000000..d78c3feb4 --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/registers.h @@ -0,0 +1,60 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file registers.h
+ * @brief Registers wrapper header.
+ *
+ * @addtogroup REGISTERS
+ * @{
+ */
+
+#ifndef REGISTERS_H
+#define REGISTERS_H
+
+#include "xpc56el.h"
+
+/*===========================================================================*/
+/* Module constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Module inline functions. */
+/*===========================================================================*/
+
+#endif /* REGISTERS_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/spc5_registry.h b/os/hal/ports/SPC5/SPC56ELxx/spc5_registry.h new file mode 100644 index 000000000..9c0ab167d --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/spc5_registry.h @@ -0,0 +1,433 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/spc5_registry.h
+ * @brief SPC56ELxx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef SPC5_REGISTRY_H
+#define SPC5_REGISTRY_H
+
+/*===========================================================================*/
+/* Platform capabilities. */
+/*===========================================================================*/
+
+/**
+ * @name SPC56ELxx capabilities
+ * @{
+ */
+/* eDMA attributes.*/
+#define SPC5_HAS_EDMA TRUE
+#define SPC5_EDMA_NCHANNELS 16
+#define SPC5_EDMA_HAS_MUX TRUE
+
+/* DSPI attribures.*/
+#define SPC5_HAS_DSPI0 TRUE
+#define SPC5_HAS_DSPI1 TRUE
+#define SPC5_HAS_DSPI2 TRUE
+#define SPC5_HAS_DSPI3 FALSE
+#define SPC5_HAS_DSPI4 FALSE
+#define SPC5_HAS_DSPI5 FALSE
+#define SPC5_HAS_DSPI6 FALSE
+#define SPC5_HAS_DSPI7 FALSE
+#define SPC5_DSPI_FIFO_DEPTH 5
+#define SPC5_DSPI0_PCTL 4
+#define SPC5_DSPI1_PCTL 5
+#define SPC5_DSPI2_PCTL 6
+#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
+#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI0_RX_DMA_DEV_ID 2
+#define SPC5_DSPI1_TX1_DMA_DEV_ID 3
+#define SPC5_DSPI1_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI1_RX_DMA_DEV_ID 4
+#define SPC5_DSPI2_TX1_DMA_DEV_ID 5
+#define SPC5_DSPI2_TX2_DMA_DEV_ID 0
+#define SPC5_DSPI2_RX_DMA_DEV_ID 6
+#define SPC5_DSPI0_TFFF_HANDLER vector76
+#define SPC5_DSPI0_TFFF_NUMBER 76
+#define SPC5_DSPI0_RFDF_HANDLER vector78
+#define SPC5_DSPI0_RFDF_NUMBER 78
+#define SPC5_DSPI1_TFFF_HANDLER vector96
+#define SPC5_DSPI1_TFFF_NUMBER 96
+#define SPC5_DSPI1_RFDF_HANDLER vector98
+#define SPC5_DSPI1_RFDF_NUMBER 98
+#define SPC5_DSPI2_TFFF_HANDLER vector116
+#define SPC5_DSPI2_TFFF_NUMBER 116
+#define SPC5_DSPI2_RFDF_HANDLER vector118
+#define SPC5_DSPI2_RFDF_NUMBER 118
+#define SPC5_DSPI0_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_START_PCTL)
+#define SPC5_DSPI0_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI0_PCTL, SPC5_SPI_DSPI0_STOP_PCTL)
+#define SPC5_DSPI1_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_START_PCTL)
+#define SPC5_DSPI1_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI1_PCTL, SPC5_SPI_DSPI1_STOP_PCTL)
+#define SPC5_DSPI2_ENABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_START_PCTL)
+#define SPC5_DSPI2_DISABLE_CLOCK() \
+ halSPCSetPeripheralClockMode(SPC5_DSPI2_PCTL, SPC5_SPI_DSPI2_STOP_PCTL)
+
+/* LINFlex attributes.*/
+#define SPC5_HAS_LINFLEX0 TRUE
+#define SPC5_LINFLEX0_PCTL 48
+#define SPC5_LINFLEX0_RXI_HANDLER vector79
+#define SPC5_LINFLEX0_TXI_HANDLER vector80
+#define SPC5_LINFLEX0_ERR_HANDLER vector81
+#define SPC5_LINFLEX0_RXI_NUMBER 79
+#define SPC5_LINFLEX0_TXI_NUMBER 80
+#define SPC5_LINFLEX0_ERR_NUMBER 81
+#define SPC5_LINFLEX0_CLK (halSPCGetSystemClock() / \
+ SPC5_SYSCLK_DIVIDER_VALUE)
+
+#define SPC5_HAS_LINFLEX1 TRUE
+#define SPC5_LINFLEX1_PCTL 49
+#define SPC5_LINFLEX1_RXI_HANDLER vector99
+#define SPC5_LINFLEX1_TXI_HANDLER vector100
+#define SPC5_LINFLEX1_ERR_HANDLER vector101
+#define SPC5_LINFLEX1_RXI_NUMBER 99
+#define SPC5_LINFLEX1_TXI_NUMBER 100
+#define SPC5_LINFLEX1_ERR_NUMBER 101
+#define SPC5_LINFLEX1_CLK (halSPCGetSystemClock() / \
+ SPC5_SYSCLK_DIVIDER_VALUE)
+
+#define SPC5_HAS_LINFLEX2 FALSE
+#define SPC5_HAS_LINFLEX3 FALSE
+#define SPC5_HAS_LINFLEX4 FALSE
+#define SPC5_HAS_LINFLEX5 FALSE
+#define SPC5_HAS_LINFLEX6 FALSE
+#define SPC5_HAS_LINFLEX7 FALSE
+#define SPC5_HAS_LINFLEX8 FALSE
+#define SPC5_HAS_LINFLEX9 FALSE
+
+/* SIUL attributes.*/
+#define SPC5_HAS_SIUL TRUE
+#define SPC5_SIUL_NUM_PORTS 8
+#define SPC5_SIUL_NUM_PCRS 133
+#define SPC5_SIUL_NUM_PADSELS 44
+/** @} */
+
+/* FlexPWM attributes.*/
+#define SPC5_HAS_FLEXPWM0 TRUE
+#define SPC5_FLEXPWM0_PCTL 41
+#define SPC5_FLEXPWM0_RF0_HANDLER vector179
+#define SPC5_FLEXPWM0_COF0_HANDLER vector180
+#define SPC5_FLEXPWM0_CAF0_HANDLER vector181
+#define SPC5_FLEXPWM0_RF1_HANDLER vector182
+#define SPC5_FLEXPWM0_COF1_HANDLER vector183
+#define SPC5_FLEXPWM0_CAF1_HANDLER vector184
+#define SPC5_FLEXPWM0_RF2_HANDLER vector185
+#define SPC5_FLEXPWM0_COF2_HANDLER vector186
+#define SPC5_FLEXPWM0_CAF2_HANDLER vector187
+#define SPC5_FLEXPWM0_RF3_HANDLER vector188
+#define SPC5_FLEXPWM0_COF3_HANDLER vector189
+#define SPC5_FLEXPWM0_CAF3_HANDLER vector190
+#define SPC5_FLEXPWM0_FFLAG_HANDLER vector191
+#define SPC5_FLEXPWM0_REF_HANDLER vector192
+#define SPC5_FLEXPWM0_RF0_NUMBER 179
+#define SPC5_FLEXPWM0_COF0_NUMBER 180
+#define SPC5_FLEXPWM0_CAF0_NUMBER 181
+#define SPC5_FLEXPWM0_RF1_NUMBER 182
+#define SPC5_FLEXPWM0_COF1_NUMBER 183
+#define SPC5_FLEXPWM0_CAF1_NUMBER 184
+#define SPC5_FLEXPWM0_RF2_NUMBER 185
+#define SPC5_FLEXPWM0_COF2_NUMBER 186
+#define SPC5_FLEXPWM0_CAF2_NUMBER 187
+#define SPC5_FLEXPWM0_RF3_NUMBER 188
+#define SPC5_FLEXPWM0_COF3_NUMBER 189
+#define SPC5_FLEXPWM0_CAF3_NUMBER 190
+#define SPC5_FLEXPWM0_FFLAG_NUMBER 191
+#define SPC5_FLEXPWM0_REF_NUMBER 192
+#define SPC5_FLEXPWM0_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_FLEXPWM1 TRUE
+#define SPC5_FLEXPWM1_PCTL 42
+#define SPC5_FLEXPWM1_RF0_HANDLER vector233
+#define SPC5_FLEXPWM1_COF0_HANDLER vector234
+#define SPC5_FLEXPWM1_CAF0_HANDLER vector235
+#define SPC5_FLEXPWM1_RF1_HANDLER vector236
+#define SPC5_FLEXPWM1_COF1_HANDLER vector237
+#define SPC5_FLEXPWM1_CAF1_HANDLER vector238
+#define SPC5_FLEXPWM1_RF2_HANDLER vector239
+#define SPC5_FLEXPWM1_COF2_HANDLER vector240
+#define SPC5_FLEXPWM1_CAF2_HANDLER vector241
+#define SPC5_FLEXPWM1_RF3_HANDLER vector242
+#define SPC5_FLEXPWM1_COF3_HANDLER vector243
+#define SPC5_FLEXPWM1_CAF3_HANDLER vector244
+#define SPC5_FLEXPWM1_FFLAG_HANDLER vector245
+#define SPC5_FLEXPWM1_REF_HANDLER vector246
+#define SPC5_FLEXPWM1_RF0_NUMBER 233
+#define SPC5_FLEXPWM1_COF0_NUMBER 234
+#define SPC5_FLEXPWM1_CAF0_NUMBER 235
+#define SPC5_FLEXPWM1_RF1_NUMBER 236
+#define SPC5_FLEXPWM1_COF1_NUMBER 237
+#define SPC5_FLEXPWM1_CAF1_NUMBER 238
+#define SPC5_FLEXPWM1_RF2_NUMBER 239
+#define SPC5_FLEXPWM1_COF2_NUMBER 240
+#define SPC5_FLEXPWM1_CAF2_NUMBER 241
+#define SPC5_FLEXPWM1_RF3_NUMBER 242
+#define SPC5_FLEXPWM1_COF3_NUMBER 243
+#define SPC5_FLEXPWM1_CAF3_NUMBER 244
+#define SPC5_FLEXPWM1_FFLAG_NUMBER 245
+#define SPC5_FLEXPWM1_REF_NUMBER 246
+#define SPC5_FLEXPWM1_CLK SPC5_MCONTROL_CLK
+
+/* eTimer attributes.*/
+#define SPC5_HAS_ETIMER0 TRUE
+#define SPC5_ETIMER0_PCTL 38
+#define SPC5_ETIMER0_TC0IR_HANDLER vector157
+#define SPC5_ETIMER0_TC1IR_HANDLER vector158
+#define SPC5_ETIMER0_TC2IR_HANDLER vector159
+#define SPC5_ETIMER0_TC3IR_HANDLER vector160
+#define SPC5_ETIMER0_TC4IR_HANDLER vector161
+#define SPC5_ETIMER0_TC5IR_HANDLER vector162
+#define SPC5_ETIMER0_WTIF_HANDLER vector165
+#define SPC5_ETIMER0_RCF_HANDLER vector167
+#define SPC5_ETIMER0_TC0IR_NUMBER 157
+#define SPC5_ETIMER0_TC1IR_NUMBER 158
+#define SPC5_ETIMER0_TC2IR_NUMBER 159
+#define SPC5_ETIMER0_TC3IR_NUMBER 160
+#define SPC5_ETIMER0_TC4IR_NUMBER 161
+#define SPC5_ETIMER0_TC5IR_NUMBER 162
+#define SPC5_ETIMER0_WTIF_NUMBER 165
+#define SPC5_ETIMER0_RCF_NUMBER 167
+#define SPC5_ETIMER0_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_ETIMER1 TRUE
+#define SPC5_ETIMER1_PCTL 39
+#define SPC5_ETIMER1_TC0IR_HANDLER vector168
+#define SPC5_ETIMER1_TC1IR_HANDLER vector169
+#define SPC5_ETIMER1_TC2IR_HANDLER vector170
+#define SPC5_ETIMER1_TC3IR_HANDLER vector171
+#define SPC5_ETIMER1_TC4IR_HANDLER vector172
+#define SPC5_ETIMER1_TC5IR_HANDLER vector173
+#define SPC5_ETIMER1_RCF_HANDLER vector178
+#define SPC5_ETIMER1_TC0IR_NUMBER 168
+#define SPC5_ETIMER1_TC1IR_NUMBER 169
+#define SPC5_ETIMER1_TC2IR_NUMBER 170
+#define SPC5_ETIMER1_TC3IR_NUMBER 171
+#define SPC5_ETIMER1_TC4IR_NUMBER 172
+#define SPC5_ETIMER1_TC5IR_NUMBER 173
+#define SPC5_ETIMER1_RCF_NUMBER 178
+#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_ETIMER2 TRUE
+#define SPC5_ETIMER2_PCTL 40
+#define SPC5_ETIMER2_TC0IR_HANDLER vector222
+#define SPC5_ETIMER2_TC1IR_HANDLER vector223
+#define SPC5_ETIMER2_TC2IR_HANDLER vector224
+#define SPC5_ETIMER2_TC3IR_HANDLER vector225
+#define SPC5_ETIMER2_TC4IR_HANDLER vector226
+#define SPC5_ETIMER2_TC5IR_HANDLER vector227
+#define SPC5_ETIMER2_RCF_HANDLER vector232
+#define SPC5_ETIMER2_TC0IR_NUMBER 222
+#define SPC5_ETIMER2_TC1IR_NUMBER 223
+#define SPC5_ETIMER2_TC2IR_NUMBER 224
+#define SPC5_ETIMER2_TC3IR_NUMBER 225
+#define SPC5_ETIMER2_TC4IR_NUMBER 226
+#define SPC5_ETIMER2_TC5IR_NUMBER 227
+#define SPC5_ETIMER2_RCF_NUMBER 232
+#define SPC5_ETIMER2_CLK SPC5_MCONTROL_CLK
+
+#define SPC5_HAS_ETIMER3 FALSE
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 32
+#define SPC5_FLEXCAN0_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_START_PCTL);
+#define SPC5_FLEXCAN0_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL, SPC5_CAN_FLEXCAN0_STOP_PCTL);
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 32
+#define SPC5_FLEXCAN1_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_HANDLER vector87
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_NUMBER 87
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
+#define SPC5_FLEXCAN1_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_START_PCTL);
+#define SPC5_FLEXCAN1_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL, SPC5_CAN_FLEXCAN1_STOP_PCTL);
+
+#if defined(_SPC56EL70L5_) || defined(_SPC564L70L5_) || defined(_SPC564L70L3_)
+#define SPC5_HAS_FLEXCAN2 TRUE
+#else
+#define SPC5_HAS_FLEXCAN2 FALSE
+#endif
+#define SPC5_FLEXCAN2_PCTL 18
+#define SPC5_FLEXCAN2_MB 32
+#define SPC5_FLEXCAN2_SHARED_IRQ TRUE
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_WAK_HANDLER vector107
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_WAK_NUMBER 107
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
+#define SPC5_FLEXCAN2_ENABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_START_PCTL);
+#define SPC5_FLEXCAN2_DISABLE_CLOCK() halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL, SPC5_CAN_FLEXCAN2_STOP_PCTL);
+
+/* ADC attributes.*/
+#define SPC5_ADC_HAS_TRC FALSE
+
+#define SPC5_HAS_ADC0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC0_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_NCMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR4 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR5 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR6 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR7 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR8 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR9 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR10 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR11 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR12 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR13 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR14 TRUE
+#define SPC5_ADC_ADC0_HAS_THRHLR15 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWENR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC0_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL4 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL5 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC0_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CIMR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CIMR2 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC0_HAS_CEOCFR1 FALSE
+#define SPC5_ADC_ADC0_HAS_CEOCFR2 FALSE
+#define SPC5_ADC0_PCTL 32
+#define SPC5_ADC0_DMA_DEV_ID 20
+#define SPC5_ADC0_EOC_HANDLER vector62
+#define SPC5_ADC0_EOC_NUMBER 62
+#define SPC5_ADC0_WD_HANDLER vector64
+#define SPC5_ADC0_WD_NUMBER 64
+
+#define SPC5_HAS_ADC1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR1 TRUE
+#define SPC5_ADC_ADC1_HAS_CTR2 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_NCMR1 FALSE
+#define SPC5_ADC_ADC1_HAS_NCMR2 FALSE
+#define SPC5_ADC_ADC1_HAS_THRHLR0 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR1 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR2 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR3 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR4 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR5 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR6 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR7 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR8 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR9 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR10 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR11 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR12 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR13 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR14 TRUE
+#define SPC5_ADC_ADC1_HAS_THRHLR15 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWENR1 FALSE
+#define SPC5_ADC_ADC1_HAS_CWENR2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL0 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL1 TRUE
+#define SPC5_ADC_ADC1_HAS_CWSEL2 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL3 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL4 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL5 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL6 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL7 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL8 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL9 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL10 FALSE
+#define SPC5_ADC_ADC1_HAS_CWSEL11 FALSE
+#define SPC5_ADC_ADC1_HAS_CIMR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CIMR1 FALSE
+#define SPC5_ADC_ADC1_HAS_CIMR2 FALSE
+#define SPC5_ADC_ADC1_HAS_CEOCFR0 TRUE
+#define SPC5_ADC_ADC1_HAS_CEOCFR1 FALSE
+#define SPC5_ADC_ADC1_HAS_CEOCFR2 FALSE
+#define SPC5_ADC1_PCTL 33
+#define SPC5_ADC1_DMA_DEV_ID 21
+#define SPC5_ADC1_EOC_HANDLER vector82
+#define SPC5_ADC1_EOC_NUMBER 82
+#define SPC5_ADC1_WD_HANDLER vector84
+#define SPC5_ADC1_WD_NUMBER 84
+/** @} */
+
+#endif /* SPC5_REGISTRY_H */
+
+/** @} */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/typedefs.h b/os/hal/ports/SPC5/SPC56ELxx/typedefs.h new file mode 100644 index 000000000..18113da7b --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/typedefs.h @@ -0,0 +1,38 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file SPC56ELxx/typedefs.h
+ * @brief Dummy typedefs file.
+ */
+
+#ifndef _TYPEDEFS_H_
+#define _TYPEDEFS_H_
+
+#include <stdint.h>
+
+/*
+ * Derived generic types.
+ */
+typedef volatile int8_t vint8_t; /**< Volatile signed 8 bits. */
+typedef volatile uint8_t vuint8_t; /**< Volatile unsigned 8 bits. */
+typedef volatile int16_t vint16_t; /**< Volatile signed 16 bits. */
+typedef volatile uint16_t vuint16_t; /**< Volatile unsigned 16 bits. */
+typedef volatile int32_t vint32_t; /**< Volatile signed 32 bits. */
+typedef volatile uint32_t vuint32_t; /**< Volatile unsigned 32 bits. */
+typedef volatile uint64_t vuint64_t; /**< Volatile unsigned 64 bits. */
+
+#endif /* _TYPEDEFS_H_ */
diff --git a/os/hal/ports/SPC5/SPC56ELxx/xpc56el.h b/os/hal/ports/SPC5/SPC56ELxx/xpc56el.h new file mode 100644 index 000000000..5d9dfefcc --- /dev/null +++ b/os/hal/ports/SPC5/SPC56ELxx/xpc56el.h @@ -0,0 +1,20796 @@ +/****************************************************************************\
+ * PROJECT : MPC5643L
+ * FILE : mpc5643l.h
+ *
+ * DESCRIPTION : This is the header file describing the register
+ * set for the named projects.
+ *
+ * COPYRIGHT : (c) 2009, Freescale Semiconductor & ST Microelectronics
+ *
+ * VERSION : 1.01
+ * DATE : Thu Oct 8 13:53:51 CEST 2009
+ * AUTHOR : generated from IP-XACT database
+ * HISTORY : Preliminary release.
+\****************************************************************************/
+
+/* >>>> NOTE! this file is auto-generated please do not edit it! <<<< */
+
+/****************************************************************************\
+ * Example instantiation and use:
+ *
+ * <MODULE>.<REGISTER>.B.<BIT> = 1;
+ * <MODULE>.<REGISTER>.R = 0x10000000;
+ *
+\****************************************************************************/
+
+
+#ifndef _leopard_H_ /* prevents multiple inclusions of this file */
+#define _leopard_H_
+
+#include "typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+
+/* #define USE_FIELD_ALIASES_CFLASH */
+/* #define USE_FIELD_ALIASES_SIUL */
+/* #define USE_FIELD_ALIASES_SSCM */
+/* #define USE_FIELD_ALIASES_ME */
+/* #define USE_FIELD_ALIASES_RGM */
+/* #define USE_FIELD_ALIASES_ADC */
+/* #define USE_FIELD_ALIASES_CTU */
+/* #define USE_FIELD_ALIASES_mcTIMER */
+/* #define USE_FIELD_ALIASES_mcPWM */
+/* #define USE_FIELD_ALIASES_LINFLEX */
+/* #define USE_FIELD_ALIASES_SPP_MCM */
+/* #define USE_FIELD_ALIASES_INTC */
+/* #define USE_FIELD_ALIASES_DSPI */
+/* #define USE_FIELD_ALIASES_FLEXCAN */
+/* #define USE_FIELD_ALIASES_FR */
+
+/****************************************************************/
+/* */
+/* Global definitions and aliases */
+/* */
+/****************************************************************/
+
+/*
+ Platform blocks that are only accessible by the second core (core 1) when
+ the device is in DPM mode. The block definition is equivalent to the one
+ for the first core (core 0) and reuses the related block structure.
+
+ NOTE: the <block_name>_1 defines are the preferred method for programming
+ */
+#define AIPS_1 (*(volatile struct AIPS_tag*) 0x8FF00000UL)
+#define MAX_1 (*(volatile struct MAX_tag*) 0x8FF04000UL)
+#define MPU_1 (*(volatile struct MPU_tag*) 0x8FF10000UL)
+#define SEMA4_1 (*(volatile struct SEMA4_tag*) 0x8FF24000UL)
+#define SWT_1 (*(volatile struct SWT_tag*) 0x8FF38000UL)
+#define STM_1 (*(volatile struct STM_tag*) 0x8FF3C000UL)
+#define SPP_MCM_1 (*(volatile struct SPP_MCM_tag*) 0x8FF40000UL)
+#define SPP_DMA2_1 (*(volatile struct SPP_DMA2_tag*) 0x8FF44000UL)
+#define INTC_1 (*(volatile struct INTC_tag*) 0x8FF48000UL)
+
+/*
+ Platform blocks that are only accessible by the second core (core 1) when
+ the device is in DPM mode. The block definition is equivalent to the one
+ for the first core (core 0) and reuses the related block structure.
+
+ NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for
+ programming the corresponding blocks for new code instead.
+ */
+#define AIPS_DPM AIPS_1
+#define MAX_DPM MAX_1
+#define MPU_DPM MPU_1
+#define SEMA4_DPM SEMA4_1
+#define SWT_DPM SWT_1
+#define STM_DPM STM_1
+#define SPP_MCM_DPM SPP_MCM_1
+#define SPP_DMA2_DPM SPP_DMA2_1
+#define INTC_DPM INTC_1
+
+/* Aliases for Pictus Module names */
+#define CAN_0 FLEXCAN_A
+#define CAN_1 FLEXCAN_B
+#define CTU_0 CTU
+#define DFLASH CRC
+#define DMAMUX DMA_CH_MUX
+#define DSPI_0 DSPI_A
+#define DSPI_1 DSPI_B
+#define DSPI_2 DSPI_C
+#define EDMA SPP_DMA2
+#define ETIMER_0 mcTIMER0
+#define ETIMER_1 mcTIMER1
+#define FLEXPWM_0 mcPWM_A
+#define FLEXPWM_1 mcPWM_B
+#define LINFLEX_0 LINFLEX0
+#define LINFLEX_1 LINFLEX1
+#define MCM_ SPP_MCM
+#define PIT PIT_RTI
+#define SIU SIUL
+#define WKUP WKPU
+/****************************************************************/
+/* */
+/* Module: CFLASH_SHADOW */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers NVPWD... */
+
+ typedef union { /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PWD:32; /* PassWorD */
+ } B;
+ } CFLASH_SHADOW_NVPWD_32B_tag;
+
+
+ /* Register layout for all registers NVSCI... */
+
+ typedef union { /* NVSCI - Non Volatile System Censoring Information Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SC:16; /* Serial Censorship Control Word */
+ vuint32_t CW:16; /* Censorship Control Word */
+ } B;
+ } CFLASH_SHADOW_NVSCI_32B_tag;
+
+ typedef union { /* Non Volatile LML Default Value */
+ vuint32_t R;
+ } CFLASH_SHADOW_NVLML_32B_tag;
+
+ typedef union { /* Non Volatile HBL Default Value */
+ vuint32_t R;
+ } CFLASH_SHADOW_NVHBL_32B_tag;
+
+ typedef union { /* Non Volatile SLL Default Value */
+ vuint32_t R;
+ } CFLASH_SHADOW_NVSLL_32B_tag;
+
+
+ /* Register layout for all registers NVBIU... */
+
+ typedef union { /* Non Volatile Bus Interface Unit Register */
+ vuint32_t R;
+ struct {
+ vuint32_t BI:32; /* Bus interface Unit */
+ } B;
+ } CFLASH_SHADOW_NVBIU_32B_tag;
+
+ typedef union { /* NVUSRO - Non Volatile USeR Options Register */
+ vuint32_t R;
+ struct {
+ vuint32_t UO:32; /* User Options */
+ } B;
+ } CFLASH_SHADOW_NVUSRO_32B_tag;
+
+
+ typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag {
+
+ /* Non Volatile Bus Interface Unit Register */
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */
+ int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4];
+
+ } CFLASH_SHADOW_BIU_DEFAULTS_tag;
+
+
+ typedef struct CFLASH_SHADOW_struct_tag { /* start of CFLASH_SHADOW_tag */
+ int8_t CFLASH_SHADOW_reserved_0000_C[15832];
+ union {
+ /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
+ CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2]; /* offset: 0x3DD8 (0x0004 x 2) */
+
+ struct {
+ /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
+ CFLASH_SHADOW_NVPWD_32B_tag NVPWD0; /* offset: 0x3DD8 size: 32 bit */
+ CFLASH_SHADOW_NVPWD_32B_tag NVPWD1; /* offset: 0x3DDC size: 32 bit */
+ };
+
+ };
+ union {
+ /* NVSCI - Non Volatile System Censoring Information Register */
+ CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2]; /* offset: 0x3DE0 (0x0004 x 2) */
+
+ struct {
+ /* NVSCI - Non Volatile System Censoring Information Register */
+ CFLASH_SHADOW_NVSCI_32B_tag NVSCI0; /* offset: 0x3DE0 size: 32 bit */
+ CFLASH_SHADOW_NVSCI_32B_tag NVSCI1; /* offset: 0x3DE4 size: 32 bit */
+ };
+
+ };
+ /* Non Volatile LML Default Value */
+ CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3DEC[4];
+ /* Non Volatile HBL Default Value */
+ CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3DF4[4];
+ /* Non Volatile SLL Default Value */
+ CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3DFC_C[4];
+ union {
+ /* Register set BIU_DEFAULTS */
+ CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3]; /* offset: 0x3E00 (0x0008 x 3) */
+
+ struct {
+ /* Non Volatile Bus Interface Unit Register */
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU2; /* offset: 0x3E00 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3E04_I1[4];
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU3; /* offset: 0x3E08 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3E0C_I1[4];
+ CFLASH_SHADOW_NVBIU_32B_tag NVBIU4; /* offset: 0x3E10 size: 32 bit */
+ int8_t CFLASH_SHADOW_reserved_3E14_E1[4];
+ };
+
+ };
+ /* NVUSRO - Non Volatile USeR Options Register */
+ CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO; /* offset: 0x3E18 size: 32 bit */
+ } CFLASH_SHADOW_tag;
+
+
+#define CFLASH_SHADOW (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CFLASH */
+/* */
+/****************************************************************/
+
+ typedef union { /* MCR - Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t SIZE:3; /* Array Space Size */
+ vuint32_t:1;
+ vuint32_t LAS:3; /* Low Address Space */
+ vuint32_t:3;
+ vuint32_t MAS:1; /* Mid Address Space Configuration */
+ vuint32_t EER:1; /* ECC Event Error */
+ vuint32_t RWE:1; /* Read-while-Write Event Error */
+ vuint32_t SBC:1; /* Single Bit Correction */
+ vuint32_t:1;
+ vuint32_t PEAS:1; /* Program/Erase Access Space */
+ vuint32_t DONE:1; /* modify operation DONE */
+ vuint32_t PEG:1; /* Program/Erase Good */
+ vuint32_t:4;
+ vuint32_t PGM:1; /* Program Bit */
+ vuint32_t PSUS:1; /* Program Suspend */
+ vuint32_t ERS:1; /* Erase Bit */
+ vuint32_t ESUS:1; /* Erase Suspend */
+ vuint32_t EHV:1; /* Enable High Voltage */
+ } B;
+ } CFLASH_MCR_32B_tag;
+
+ typedef union { /* LML - Low/Mid Address Space Block Locking Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LME:1; /* Low/Mid Address Space Block Enable */
+ vuint32_t:10;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t SLOCK:1; /* Shadow Address Space Block Lock */
+#else
+ vuint32_t TSLK:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t MLOCK:2; /* Mid Address Space Block Lock */
+#else
+ vuint32_t MLK:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:6;
+ vuint32_t LLOCK:10; /* Low Address Space Block Lock */
+ } B;
+ } CFLASH_LML_32B_tag;
+
+ typedef union { /* HBL - High Address Space Block Locking Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HBE:1; /* High Address Space Block Enable */
+ vuint32_t:25;
+ vuint32_t HLOCK:6; /* High Address Space Block Lock */
+ } B;
+ } CFLASH_HBL_32B_tag;
+
+ typedef union { /* SLL - Secondary Low/Mid Address Space Block Locking Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SLE:1; /* Secondary Low/Mid Address Space Block Enable */
+ vuint32_t:10;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t SSLOCK:1; /* Secondary Shadow Address Space Block Lock */
+#else
+ vuint32_t STSLK:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t SMLOCK:2; /* Secondary Mid Address Space Block Lock */
+#else
+ vuint32_t SMK:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:6;
+ vuint32_t SLLOCK:10; /* Secondary Low Address Space Block Lock */
+ } B;
+ } CFLASH_SLL_32B_tag;
+
+ typedef union { /* LMS - Low/Mid Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t MSL:2; /* Mid Address Space Block Select */
+ vuint32_t:6;
+ vuint32_t LSL:10; /* Low Address Space Block Select */
+ } B;
+ } CFLASH_LMS_32B_tag;
+
+ typedef union { /* HBS - High Address Space Block Select Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t HSL:6; /* High Address Space Block Select */
+ } B;
+ } CFLASH_HBS_32B_tag;
+
+ typedef union { /* ADR - Address Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SAD:1; /* Shadow Address */
+ vuint32_t:10;
+ vuint32_t ADDR:18; /* Address */
+ vuint32_t:3;
+ } B;
+ } CFLASH_ADR_32B_tag;
+
+ typedef union { /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_APC:5; /* Bank0+2 Address Pipelining Control */
+#else
+ vuint32_t BK0_APC:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_WWSC:5; /* Bank0+2 Write Wait State Control */
+#else
+ vuint32_t BK0_WWSC:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_RWSC:5; /* Bank0+2 Read Wait State Control */
+#else
+ vuint32_t BK0_RWSC:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_RWWC2:1; /* Bank 0+2 Read While Write Control, bit 2 */
+#else
+ vuint32_t BK0_RWWC2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_RWWC1:1; /* Bank 0+2 Read While Write Control, bit 1 */
+#else
+ vuint32_t BK0_RWWC1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P1_BCFG:2; /* Bank0+2 Port 1 Page Buffer Configuration */
+#else
+ vuint32_t B0_P1_BCFG:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P1_DPFE:1; /* Bank0+2 Port 1 Data Prefetch Enable */
+#else
+ vuint32_t B0_P1_DPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P1_IPFE:1; /* Bank0+2 Port 1 Inst Prefetch Enable */
+#else
+ vuint32_t B0_P1_IPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P1_PFLM:2; /* Bank0+2 Port 1 Prefetch Limit */
+#else
+ vuint32_t B0_P1_PFLM:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P1_BFE:1; /* Bank0+2 Port 1 Buffer Enable */
+#else
+ vuint32_t B0_P1_BFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_RWWC0:1; /* Bank 0+2 Read While Write Control, bit 0 */
+#else
+ vuint32_t BK0_RWWC0:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P0_BCFG:2; /* Bank0+2 Port 0 Page Buffer Configuration */
+#else
+ vuint32_t B0_P0_BCFG:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P0_DPFE:1; /* Bank0+2 Port 0 Data Prefetch Enable */
+#else
+ vuint32_t B0_P0_DPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P0_IPFE:1; /* Bank0+2 Port 0 Inst Prefetch Enable */
+#else
+ vuint32_t B0_P0_IPFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P0_PFLM:2; /* Bank0+2 Port 0 Prefetch Limit */
+#else
+ vuint32_t B0_P0_PFLM:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B02_P0_BFE:1; /* Bank0+2 Port 0 Buffer Enable */
+#else
+ vuint32_t B0_P0_BFE:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } CFLASH_PFCR0_32B_tag;
+
+
+ /* Register layout for all registers BIU... */
+
+ typedef union { /* Bus Interface Unit Register */
+ vuint32_t R;
+ } CFLASH_BIU_32B_tag;
+
+ typedef union { /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t B1_APC:5; /* Bank 1 Address Pipelining Control */
+ vuint32_t B1_WWSC:5; /* Bank 1 Write Wait State Control */
+ vuint32_t B1_RWSC:5; /* Bank 1 Read Wait State Control */
+ vuint32_t B1_RWWC2:1; /* Bank1 Read While Write Control, bit 2 */
+ vuint32_t B1_RWWC1:1; /* Bank1 Read While Write Control, bit 1 */
+ vuint32_t:6;
+ vuint32_t B1_P1_BFE:1; /* Bank 1 Port 1 Buffer Enable */
+ vuint32_t B1_RWWC0:1; /* Bank1 Read While Write Control, bit 0 */
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1; /* Bank 1 Port 0 Buffer Enable */
+#else
+ vuint32_t BK1_APC:5;
+ vuint32_t BK1_WWSC:5;
+ vuint32_t BK1_RWSC:5;
+ vuint32_t BK1_RWWC2:1;
+ vuint32_t BK1_RWWC1:1;
+ vuint32_t:6;
+ vuint32_t B0_P1_BFE:1;
+ vuint32_t BK1_RWWC0:1;
+ vuint32_t:6;
+ vuint32_t B1_P0_BFE:1;
+#endif
+ } B;
+ } CFLASH_PFCR1_32B_tag;
+
+ typedef union { /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t ARBM:2; /* Arbitration Mode */
+ vuint32_t M7PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M6PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M5PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M4PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M3PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M2PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M1PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M0PFD:1; /* Master x Prefetch Disable */
+ vuint32_t M7AP:2; /* Master 7 Access Protection */
+ vuint32_t M6AP:2; /* Master 6 Access Protection */
+ vuint32_t M5AP:2; /* Master 5 Access Protection */
+ vuint32_t M4AP:2; /* Master 4 Access Protection */
+ vuint32_t M3AP:2; /* Master 3 Access Protection */
+ vuint32_t M2AP:2; /* Master 2 Access Protection */
+ vuint32_t M1AP:2; /* Master 1 Access Protection */
+ vuint32_t M0AP:2; /* Master 0 Access Protection */
+ } B;
+ } CFLASH_PFAPR_32B_tag;
+
+ typedef union { /* UT0 - User Test Register */
+ vuint32_t R;
+ struct {
+ vuint32_t UTE:1; /* User Test Enable */
+ vuint32_t SBCE:1; /* Single Bit Correction Enable */
+ vuint32_t:6;
+ vuint32_t DSI:8; /* Data Syndrome Input */
+ vuint32_t:10;
+ vuint32_t MRE:1; /* Margin Read Enable */
+ vuint32_t MRV:1; /* Margin Read Value */
+ vuint32_t EIE:1; /* ECC Data Input Enable */
+ vuint32_t AIS:1; /* Array Integrity Sequence */
+ vuint32_t AIE:1; /* Array Integrity Enable */
+ vuint32_t AID:1; /* Array Integrity Done */
+ } B;
+ } CFLASH_UT0_32B_tag;
+
+ typedef union { /* UT1 - User Test Register */
+ vuint32_t R;
+ } CFLASH_UT1_32B_tag;
+
+ typedef union { /* UT2 - User Test Register */
+ vuint32_t R;
+ } CFLASH_UT2_32B_tag;
+
+
+ /* Register layout for all registers UM... */
+
+ typedef union { /* UM - User Multiple Input Signature Register */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CFLASH
+ vuint32_t MISR:32; /* Multiple Input Signature */
+#else
+ vuint32_t MS:32; /* deprecated - please avoid */
+#endif
+ } B;
+ } CFLASH_UM_32B_tag;
+
+
+ /* Register layout for generated register(s) UT... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } CFLASH_UT_32B_tag;
+
+
+ /* Register layout for generated register(s) PFCR... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } CFLASH_PFCR_32B_tag;
+
+
+
+ typedef struct CFLASH_struct_tag { /* start of CFLASH_tag */
+ /* MCR - Module Configuration Register */
+ CFLASH_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
+ /* LML - Low/Mid Address Space Block Locking Register */
+ CFLASH_LML_32B_tag LML; /* offset: 0x0004 size: 32 bit */
+ /* HBL - High Address Space Block Locking Register */
+ CFLASH_HBL_32B_tag HBL; /* offset: 0x0008 size: 32 bit */
+ /* SLL - Secondary Low/Mid Address Space Block Locking Register */
+ CFLASH_SLL_32B_tag SLL; /* offset: 0x000C size: 32 bit */
+ /* LMS - Low/Mid Address Space Block Select Register */
+ CFLASH_LMS_32B_tag LMS; /* offset: 0x0010 size: 32 bit */
+ /* HBS - High Address Space Block Select Register */
+ CFLASH_HBS_32B_tag HBS; /* offset: 0x0014 size: 32 bit */
+ /* ADR - Address Register */
+ CFLASH_ADR_32B_tag ADR; /* offset: 0x0018 size: 32 bit */
+ union {
+ struct {
+ /* */
+ CFLASH_PFCR_32B_tag PFCR[2]; /* offset: 0x001C (0x0004 x 2) */
+ int8_t CFLASH_reserved_0024_E0[12];
+ };
+
+ /* Bus Interface Unit Register */
+ CFLASH_BIU_32B_tag BIU[5]; /* offset: 0x001C (0x0004 x 5) */
+
+ struct {
+ /* Bus Interface Unit Register */
+ CFLASH_BIU_32B_tag BIU0; /* offset: 0x001C size: 32 bit */
+ CFLASH_BIU_32B_tag BIU1; /* offset: 0x0020 size: 32 bit */
+ CFLASH_BIU_32B_tag BIU2; /* offset: 0x0024 size: 32 bit */
+ CFLASH_BIU_32B_tag BIU3; /* offset: 0x0028 size: 32 bit */
+ CFLASH_BIU_32B_tag BIU4; /* offset: 0x002C size: 32 bit */
+ };
+
+ struct {
+ int8_t CFLASH_reserved_001C_I3[8];
+ CFLASH_PFAPR_32B_tag FAPR; /* deprecated - please avoid */
+ int8_t CFLASH_reserved_0028_E3[8];
+ };
+
+ struct {
+ /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
+ CFLASH_PFCR0_32B_tag PFCR0; /* offset: 0x001C size: 32 bit */
+ /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
+ CFLASH_PFCR1_32B_tag PFCR1; /* offset: 0x0020 size: 32 bit */
+ /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
+ CFLASH_PFAPR_32B_tag PFAPR; /* offset: 0x0024 size: 32 bit */
+ int8_t CFLASH_reserved_0028_E4[8];
+ };
+
+ };
+ int8_t CFLASH_reserved_0030_C[12];
+ union {
+ CFLASH_UT_32B_tag UT[3]; /* offset: 0x003C (0x0004 x 3) */
+
+ struct {
+ /* UT0 - User Test Register */
+ CFLASH_UT0_32B_tag UT0; /* offset: 0x003C size: 32 bit */
+ /* UT1 - User Test Register */
+ CFLASH_UT1_32B_tag UT1; /* offset: 0x0040 size: 32 bit */
+ /* UT2 - User Test Register */
+ CFLASH_UT2_32B_tag UT2; /* offset: 0x0044 size: 32 bit */
+ };
+
+ };
+ union {
+ CFLASH_UM_32B_tag UMISR[5]; /* offset: 0x0048 (0x0004 x 5) */
+
+ /* UM - User Multiple Input Signature Register */
+ CFLASH_UM_32B_tag UM[5]; /* offset: 0x0048 (0x0004 x 5) */
+
+ struct {
+ /* UM - User Multiple Input Signature Register */
+ CFLASH_UM_32B_tag UM0; /* offset: 0x0048 size: 32 bit */
+ CFLASH_UM_32B_tag UM1; /* offset: 0x004C size: 32 bit */
+ CFLASH_UM_32B_tag UM2; /* offset: 0x0050 size: 32 bit */
+ CFLASH_UM_32B_tag UM3; /* offset: 0x0054 size: 32 bit */
+ CFLASH_UM_32B_tag UM4; /* offset: 0x0058 size: 32 bit */
+ };
+
+ };
+ } CFLASH_tag;
+
+
+#define CFLASH (*(volatile CFLASH_tag *) 0xC3F88000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SIUL */
+/* */
+/****************************************************************/
+
+ typedef union { /* MIDR1 - MCU ID Register #1 */
+ vuint32_t R;
+ struct {
+ vuint32_t PARTNUM:16; /* MCU Part Number */
+ vuint32_t CSP:1; /* CSP Package */
+ vuint32_t PKG:5; /* Package Settings */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_SIUL
+ vuint32_t MAJOR_MASK:4; /* Major Mask Revision */
+#else
+ vuint32_t MAJORMASK:4; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SIUL
+ vuint32_t MINOR_MASK:4; /* Minor Mask Revision */
+#else
+ vuint32_t MINORMASK:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SIUL_MIDR1_32B_tag;
+
+ typedef union { /* MIDR2 - MCU ID Register #2 */
+ vuint32_t R;
+ struct {
+ vuint32_t SF:1; /* Manufacturer */
+ vuint32_t FLASH_SIZE_1:4; /* Coarse Flash Memory Size */
+ vuint32_t FLASH_SIZE_2:4; /* Fine Flash Memory Size */
+ vuint32_t:7;
+#ifndef USE_FIELD_ALIASES_SIUL
+ vuint32_t PARTNUM2:8; /* MCU Part Number */
+#else
+ vuint32_t PARTNUM:8; /* deprecated name - please avoid */
+#endif
+ vuint32_t TBD:1; /* Optional Bit */
+ vuint32_t:2;
+ vuint32_t EE:1; /* Data Flash Present */
+ vuint32_t:3;
+ vuint32_t FR:1; /* Flexray Present */
+ } B;
+ } SIUL_MIDR2_32B_tag;
+
+ typedef union { /* ISR - Interrupt Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIF31:1; /* External Interrupt Status Flag */
+ vuint32_t EIF30:1; /* External Interrupt Status Flag */
+ vuint32_t EIF29:1; /* External Interrupt Status Flag */
+ vuint32_t EIF28:1; /* External Interrupt Status Flag */
+ vuint32_t EIF27:1; /* External Interrupt Status Flag */
+ vuint32_t EIF26:1; /* External Interrupt Status Flag */
+ vuint32_t EIF25:1; /* External Interrupt Status Flag */
+ vuint32_t EIF24:1; /* External Interrupt Status Flag */
+ vuint32_t EIF23:1; /* External Interrupt Status Flag */
+ vuint32_t EIF22:1; /* External Interrupt Status Flag */
+ vuint32_t EIF21:1; /* External Interrupt Status Flag */
+ vuint32_t EIF20:1; /* External Interrupt Status Flag */
+ vuint32_t EIF19:1; /* External Interrupt Status Flag */
+ vuint32_t EIF18:1; /* External Interrupt Status Flag */
+ vuint32_t EIF17:1; /* External Interrupt Status Flag */
+ vuint32_t EIF16:1; /* External Interrupt Status Flag */
+ vuint32_t EIF15:1; /* External Interrupt Status Flag */
+ vuint32_t EIF14:1; /* External Interrupt Status Flag */
+ vuint32_t EIF13:1; /* External Interrupt Status Flag */
+ vuint32_t EIF12:1; /* External Interrupt Status Flag */
+ vuint32_t EIF11:1; /* External Interrupt Status Flag */
+ vuint32_t EIF10:1; /* External Interrupt Status Flag */
+ vuint32_t EIF9:1; /* External Interrupt Status Flag */
+ vuint32_t EIF8:1; /* External Interrupt Status Flag */
+ vuint32_t EIF7:1; /* External Interrupt Status Flag */
+ vuint32_t EIF6:1; /* External Interrupt Status Flag */
+ vuint32_t EIF5:1; /* External Interrupt Status Flag */
+ vuint32_t EIF4:1; /* External Interrupt Status Flag */
+ vuint32_t EIF3:1; /* External Interrupt Status Flag */
+ vuint32_t EIF2:1; /* External Interrupt Status Flag */
+ vuint32_t EIF1:1; /* External Interrupt Status Flag */
+ vuint32_t EIF0:1; /* External Interrupt Status Flag */
+ } B;
+ } SIUL_ISR_32B_tag;
+
+ typedef union { /* IRER - Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE31:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE30:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE29:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE28:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE27:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE26:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE25:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE24:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE23:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE22:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE21:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE20:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE19:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE18:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE17:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE16:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE15:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE14:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE13:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE12:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE11:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE10:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE9:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE8:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE7:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE6:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE5:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE4:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE3:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE2:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE1:1; /* Enable External Interrupt Requests */
+ vuint32_t EIRE0:1; /* Enable External Interrupt Requests */
+ } B;
+ } SIUL_IRER_32B_tag;
+
+ typedef union { /* IREER - Interrupt Rising Edge Event Enable */
+ vuint32_t R;
+ struct {
+ vuint32_t IREE31:1; /* Enable rising-edge events */
+ vuint32_t IREE30:1; /* Enable rising-edge events */
+ vuint32_t IREE29:1; /* Enable rising-edge events */
+ vuint32_t IREE28:1; /* Enable rising-edge events */
+ vuint32_t IREE27:1; /* Enable rising-edge events */
+ vuint32_t IREE26:1; /* Enable rising-edge events */
+ vuint32_t IREE25:1; /* Enable rising-edge events */
+ vuint32_t IREE24:1; /* Enable rising-edge events */
+ vuint32_t IREE23:1; /* Enable rising-edge events */
+ vuint32_t IREE22:1; /* Enable rising-edge events */
+ vuint32_t IREE21:1; /* Enable rising-edge events */
+ vuint32_t IREE20:1; /* Enable rising-edge events */
+ vuint32_t IREE19:1; /* Enable rising-edge events */
+ vuint32_t IREE18:1; /* Enable rising-edge events */
+ vuint32_t IREE17:1; /* Enable rising-edge events */
+ vuint32_t IREE16:1; /* Enable rising-edge events */
+ vuint32_t IREE15:1; /* Enable rising-edge events */
+ vuint32_t IREE14:1; /* Enable rising-edge events */
+ vuint32_t IREE13:1; /* Enable rising-edge events */
+ vuint32_t IREE12:1; /* Enable rising-edge events */
+ vuint32_t IREE11:1; /* Enable rising-edge events */
+ vuint32_t IREE10:1; /* Enable rising-edge events */
+ vuint32_t IREE9:1; /* Enable rising-edge events */
+ vuint32_t IREE8:1; /* Enable rising-edge events */
+ vuint32_t IREE7:1; /* Enable rising-edge events */
+ vuint32_t IREE6:1; /* Enable rising-edge events */
+ vuint32_t IREE5:1; /* Enable rising-edge events */
+ vuint32_t IREE4:1; /* Enable rising-edge events */
+ vuint32_t IREE3:1; /* Enable rising-edge events */
+ vuint32_t IREE2:1; /* Enable rising-edge events */
+ vuint32_t IREE1:1; /* Enable rising-edge events */
+ vuint32_t IREE0:1; /* Enable rising-edge events */
+ } B;
+ } SIUL_IREER_32B_tag;
+
+ typedef union { /* IFEER - Interrupt Falling-Edge Event Enable */
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE31:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE30:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE29:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE28:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE27:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE26:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE25:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE24:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE23:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE22:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE21:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE20:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE19:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE18:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE17:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE16:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE15:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE14:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE13:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE12:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE11:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE10:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE9:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE8:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE7:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE6:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE5:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE4:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE3:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE2:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE1:1; /* Enable Falling Edge Events */
+ vuint32_t IFEE0:1; /* Enable Falling Edge Events */
+ } B;
+ } SIUL_IFEER_32B_tag;
+
+ typedef union { /* IFER Interrupt Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFE31:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE30:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE29:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE28:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE27:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE26:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE25:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE24:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE23:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE22:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE21:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE20:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE19:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE18:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE17:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE16:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE15:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE14:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE13:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE12:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE11:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE10:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE9:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE8:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE7:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE6:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE5:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE4:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE3:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE2:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE1:1; /* Enable Digital Glitch Filter */
+ vuint32_t IFE0:1; /* Enable Digital Glitch Filter */
+ } B;
+ } SIUL_IFER_32B_tag;
+
+
+ /* Register layout for all registers PCR... */
+
+ typedef union { /* PCR - Pad Configuration Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+#ifndef USE_FIELD_ALIASES_SIUL
+ vuint16_t SMC:1; /* Safe Mode Control */
+#else
+ vuint16_t SME:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t APC:1; /* Analog Pad Control */
+ vuint16_t:1;
+ vuint16_t PA:2; /* Pad Output Assignment */
+ vuint16_t OBE:1; /* Output Buffer Enable */
+ vuint16_t IBE:1; /* Input Buffer Enable */
+#ifndef USE_FIELD_ALIASES_SIUL
+ vuint16_t DSC:2; /* Drive Strength Control */
+#else
+ vuint16_t DCS:2; /* deprecated name - please avoid */
+#endif
+ vuint16_t ODE:1; /* Open Drain Output Enable */
+ vuint16_t HYS:1; /* Input Hysteresis */
+ vuint16_t SRC:2; /* Slew Rate Control */
+ vuint16_t WPE:1; /* Weak Pull Up/Down Enable */
+ vuint16_t WPS:1; /* Weak Pull Up/Down Select */
+ } B;
+ } SIUL_PCR_16B_tag;
+
+
+ /* Register layout for all registers PSMI... */
+
+ typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t PADSEL:4; /* Pad selection for pin */
+ } B;
+ } SIUL_PSMI_8B_tag;
+
+
+ /* Register layout for all registers PSMI... */
+
+ typedef union { /* PSMI - Pad Selection for Multiplexed Inputs */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t PADSEL0:4; /* Pad selection for pin */
+ vuint32_t:4;
+ vuint32_t PADSEL1:4; /* Pad selection for pin */
+ vuint32_t:4;
+ vuint32_t PADSEL2:4; /* Pad selection for pin */
+ vuint32_t:4;
+ vuint32_t PADSEL3:4; /* Pad selection for pin */
+ } B;
+ } SIUL_PSMI_32B_tag;
+
+
+ /* Register layout for all registers GPDO... */
+
+ typedef union { /* GPDO - GPIO Pad Data Output Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDO:1; /* Pad Data Out */
+ } B;
+ } SIUL_GPDO_8B_tag;
+
+
+ /* Register layout for all registers GPDO... */
+
+ typedef union { /* GPDO - GPIO Pad Data Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t PDO0:1; /* Pad Data Out */
+ vuint32_t:7;
+ vuint32_t PDO1:1; /* Pad Data Out */
+ vuint32_t:7;
+ vuint32_t PDO2:1; /* Pad Data Out */
+ vuint32_t:7;
+ vuint32_t PDO3:1; /* Pad Data Out */
+ } B;
+ } SIUL_GPDO_32B_tag;
+
+
+ /* Register layout for all registers GPDI... */
+
+ typedef union { /* GPDI - GPIO Pad Data Input Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:7;
+ vuint8_t PDI:1; /* Pad Data In */
+ } B;
+ } SIUL_GPDI_8B_tag;
+
+
+ /* Register layout for all registers GPDI... */
+
+ typedef union { /* GPDI - GPIO Pad Data Input Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t PDI0:1; /* Pad Data In */
+ vuint32_t:7;
+ vuint32_t PDI1:1; /* Pad Data In */
+ vuint32_t:7;
+ vuint32_t PDI2:1; /* Pad Data In */
+ vuint32_t:7;
+ vuint32_t PDI3:1; /* Pad Data In */
+ } B;
+ } SIUL_GPDI_32B_tag;
+
+
+ /* Register layout for all registers PGPDO... */
+
+ typedef union { /* PGPDO - Parallel GPIO Pad Data Out Register */
+ vuint16_t R;
+ } SIUL_PGPDO_16B_tag;
+
+
+ /* Register layout for all registers PGPDI... */
+
+ typedef union { /* PGPDI - Parallel GPIO Pad Data In Register */
+ vuint16_t R;
+ } SIUL_PGPDI_16B_tag;
+
+
+ /* Register layout for all registers MPGPDO... */
+
+ typedef union { /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MASK:16; /* Mask Field */
+ vuint32_t MPPDO:16; /* Masked Parallel Pad Data Out */
+ } B;
+ } SIUL_MPGPDO_32B_tag;
+
+
+ /* Register layout for all registers IFMC... */
+
+ typedef union { /* IFMC - Interrupt Filter Maximum Counter Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t MAXCNT:4; /* Maximum Interrupt Filter Counter Setting */
+ } B;
+ } SIUL_IFMC_32B_tag;
+
+ typedef union { /* IFCPR - Inerrupt Filter Clock Prescaler Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFCP:4; /* Interrupt Filter Clock Prescaler Setting */
+ } B;
+ } SIUL_IFCPR_32B_tag;
+
+
+
+ typedef struct SIUL_struct_tag { /* start of SIUL_tag */
+ int8_t SIUL_reserved_0000_C[4];
+ union {
+ SIUL_MIDR1_32B_tag MIDR; /* deprecated - please avoid */
+
+ /* MIDR1 - MCU ID Register #1 */
+ SIUL_MIDR1_32B_tag MIDR1; /* offset: 0x0004 size: 32 bit */
+
+ };
+ /* MIDR2 - MCU ID Register #2 */
+ SIUL_MIDR2_32B_tag MIDR2; /* offset: 0x0008 size: 32 bit */
+ int8_t SIUL_reserved_000C[8];
+ /* ISR - Interrupt Status Flag Register */
+ SIUL_ISR_32B_tag ISR; /* offset: 0x0014 size: 32 bit */
+ /* IRER - Interrupt Request Enable Register */
+ SIUL_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
+ int8_t SIUL_reserved_001C[12];
+ /* IREER - Interrupt Rising Edge Event Enable */
+ SIUL_IREER_32B_tag IREER; /* offset: 0x0028 size: 32 bit */
+ /* IFEER - Interrupt Falling-Edge Event Enable */
+ SIUL_IFEER_32B_tag IFEER; /* offset: 0x002C size: 32 bit */
+ /* IFER Interrupt Filter Enable Register */
+ SIUL_IFER_32B_tag IFER; /* offset: 0x0030 size: 32 bit */
+ int8_t SIUL_reserved_0034_C[12];
+ union {
+ /* PCR - Pad Configuration Register */
+ SIUL_PCR_16B_tag PCR[512]; /* offset: 0x0040 (0x0002 x 512) */
+
+ struct {
+ /* PCR - Pad Configuration Register */
+ SIUL_PCR_16B_tag PCR0; /* offset: 0x0040 size: 16 bit */
+ SIUL_PCR_16B_tag PCR1; /* offset: 0x0042 size: 16 bit */
+ SIUL_PCR_16B_tag PCR2; /* offset: 0x0044 size: 16 bit */
+ SIUL_PCR_16B_tag PCR3; /* offset: 0x0046 size: 16 bit */
+ SIUL_PCR_16B_tag PCR4; /* offset: 0x0048 size: 16 bit */
+ SIUL_PCR_16B_tag PCR5; /* offset: 0x004A size: 16 bit */
+ SIUL_PCR_16B_tag PCR6; /* offset: 0x004C size: 16 bit */
+ SIUL_PCR_16B_tag PCR7; /* offset: 0x004E size: 16 bit */
+ SIUL_PCR_16B_tag PCR8; /* offset: 0x0050 size: 16 bit */
+ SIUL_PCR_16B_tag PCR9; /* offset: 0x0052 size: 16 bit */
+ SIUL_PCR_16B_tag PCR10; /* offset: 0x0054 size: 16 bit */
+ SIUL_PCR_16B_tag PCR11; /* offset: 0x0056 size: 16 bit */
+ SIUL_PCR_16B_tag PCR12; /* offset: 0x0058 size: 16 bit */
+ SIUL_PCR_16B_tag PCR13; /* offset: 0x005A size: 16 bit */
+ SIUL_PCR_16B_tag PCR14; /* offset: 0x005C size: 16 bit */
+ SIUL_PCR_16B_tag PCR15; /* offset: 0x005E size: 16 bit */
+ SIUL_PCR_16B_tag PCR16; /* offset: 0x0060 size: 16 bit */
+ SIUL_PCR_16B_tag PCR17; /* offset: 0x0062 size: 16 bit */
+ SIUL_PCR_16B_tag PCR18; /* offset: 0x0064 size: 16 bit */
+ SIUL_PCR_16B_tag PCR19; /* offset: 0x0066 size: 16 bit */
+ SIUL_PCR_16B_tag PCR20; /* offset: 0x0068 size: 16 bit */
+ SIUL_PCR_16B_tag PCR21; /* offset: 0x006A size: 16 bit */
+ SIUL_PCR_16B_tag PCR22; /* offset: 0x006C size: 16 bit */
+ SIUL_PCR_16B_tag PCR23; /* offset: 0x006E size: 16 bit */
+ SIUL_PCR_16B_tag PCR24; /* offset: 0x0070 size: 16 bit */
+ SIUL_PCR_16B_tag PCR25; /* offset: 0x0072 size: 16 bit */
+ SIUL_PCR_16B_tag PCR26; /* offset: 0x0074 size: 16 bit */
+ SIUL_PCR_16B_tag PCR27; /* offset: 0x0076 size: 16 bit */
+ SIUL_PCR_16B_tag PCR28; /* offset: 0x0078 size: 16 bit */
+ SIUL_PCR_16B_tag PCR29; /* offset: 0x007A size: 16 bit */
+ SIUL_PCR_16B_tag PCR30; /* offset: 0x007C size: 16 bit */
+ SIUL_PCR_16B_tag PCR31; /* offset: 0x007E size: 16 bit */
+ SIUL_PCR_16B_tag PCR32; /* offset: 0x0080 size: 16 bit */
+ SIUL_PCR_16B_tag PCR33; /* offset: 0x0082 size: 16 bit */
+ SIUL_PCR_16B_tag PCR34; /* offset: 0x0084 size: 16 bit */
+ SIUL_PCR_16B_tag PCR35; /* offset: 0x0086 size: 16 bit */
+ SIUL_PCR_16B_tag PCR36; /* offset: 0x0088 size: 16 bit */
+ SIUL_PCR_16B_tag PCR37; /* offset: 0x008A size: 16 bit */
+ SIUL_PCR_16B_tag PCR38; /* offset: 0x008C size: 16 bit */
+ SIUL_PCR_16B_tag PCR39; /* offset: 0x008E size: 16 bit */
+ SIUL_PCR_16B_tag PCR40; /* offset: 0x0090 size: 16 bit */
+ SIUL_PCR_16B_tag PCR41; /* offset: 0x0092 size: 16 bit */
+ SIUL_PCR_16B_tag PCR42; /* offset: 0x0094 size: 16 bit */
+ SIUL_PCR_16B_tag PCR43; /* offset: 0x0096 size: 16 bit */
+ SIUL_PCR_16B_tag PCR44; /* offset: 0x0098 size: 16 bit */
+ SIUL_PCR_16B_tag PCR45; /* offset: 0x009A size: 16 bit */
+ SIUL_PCR_16B_tag PCR46; /* offset: 0x009C size: 16 bit */
+ SIUL_PCR_16B_tag PCR47; /* offset: 0x009E size: 16 bit */
+ SIUL_PCR_16B_tag PCR48; /* offset: 0x00A0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR49; /* offset: 0x00A2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR50; /* offset: 0x00A4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR51; /* offset: 0x00A6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR52; /* offset: 0x00A8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR53; /* offset: 0x00AA size: 16 bit */
+ SIUL_PCR_16B_tag PCR54; /* offset: 0x00AC size: 16 bit */
+ SIUL_PCR_16B_tag PCR55; /* offset: 0x00AE size: 16 bit */
+ SIUL_PCR_16B_tag PCR56; /* offset: 0x00B0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR57; /* offset: 0x00B2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR58; /* offset: 0x00B4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR59; /* offset: 0x00B6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR60; /* offset: 0x00B8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR61; /* offset: 0x00BA size: 16 bit */
+ SIUL_PCR_16B_tag PCR62; /* offset: 0x00BC size: 16 bit */
+ SIUL_PCR_16B_tag PCR63; /* offset: 0x00BE size: 16 bit */
+ SIUL_PCR_16B_tag PCR64; /* offset: 0x00C0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR65; /* offset: 0x00C2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR66; /* offset: 0x00C4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR67; /* offset: 0x00C6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR68; /* offset: 0x00C8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR69; /* offset: 0x00CA size: 16 bit */
+ SIUL_PCR_16B_tag PCR70; /* offset: 0x00CC size: 16 bit */
+ SIUL_PCR_16B_tag PCR71; /* offset: 0x00CE size: 16 bit */
+ SIUL_PCR_16B_tag PCR72; /* offset: 0x00D0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR73; /* offset: 0x00D2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR74; /* offset: 0x00D4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR75; /* offset: 0x00D6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR76; /* offset: 0x00D8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR77; /* offset: 0x00DA size: 16 bit */
+ SIUL_PCR_16B_tag PCR78; /* offset: 0x00DC size: 16 bit */
+ SIUL_PCR_16B_tag PCR79; /* offset: 0x00DE size: 16 bit */
+ SIUL_PCR_16B_tag PCR80; /* offset: 0x00E0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR81; /* offset: 0x00E2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR82; /* offset: 0x00E4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR83; /* offset: 0x00E6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR84; /* offset: 0x00E8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR85; /* offset: 0x00EA size: 16 bit */
+ SIUL_PCR_16B_tag PCR86; /* offset: 0x00EC size: 16 bit */
+ SIUL_PCR_16B_tag PCR87; /* offset: 0x00EE size: 16 bit */
+ SIUL_PCR_16B_tag PCR88; /* offset: 0x00F0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR89; /* offset: 0x00F2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR90; /* offset: 0x00F4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR91; /* offset: 0x00F6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR92; /* offset: 0x00F8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR93; /* offset: 0x00FA size: 16 bit */
+ SIUL_PCR_16B_tag PCR94; /* offset: 0x00FC size: 16 bit */
+ SIUL_PCR_16B_tag PCR95; /* offset: 0x00FE size: 16 bit */
+ SIUL_PCR_16B_tag PCR96; /* offset: 0x0100 size: 16 bit */
+ SIUL_PCR_16B_tag PCR97; /* offset: 0x0102 size: 16 bit */
+ SIUL_PCR_16B_tag PCR98; /* offset: 0x0104 size: 16 bit */
+ SIUL_PCR_16B_tag PCR99; /* offset: 0x0106 size: 16 bit */
+ SIUL_PCR_16B_tag PCR100; /* offset: 0x0108 size: 16 bit */
+ SIUL_PCR_16B_tag PCR101; /* offset: 0x010A size: 16 bit */
+ SIUL_PCR_16B_tag PCR102; /* offset: 0x010C size: 16 bit */
+ SIUL_PCR_16B_tag PCR103; /* offset: 0x010E size: 16 bit */
+ SIUL_PCR_16B_tag PCR104; /* offset: 0x0110 size: 16 bit */
+ SIUL_PCR_16B_tag PCR105; /* offset: 0x0112 size: 16 bit */
+ SIUL_PCR_16B_tag PCR106; /* offset: 0x0114 size: 16 bit */
+ SIUL_PCR_16B_tag PCR107; /* offset: 0x0116 size: 16 bit */
+ SIUL_PCR_16B_tag PCR108; /* offset: 0x0118 size: 16 bit */
+ SIUL_PCR_16B_tag PCR109; /* offset: 0x011A size: 16 bit */
+ SIUL_PCR_16B_tag PCR110; /* offset: 0x011C size: 16 bit */
+ SIUL_PCR_16B_tag PCR111; /* offset: 0x011E size: 16 bit */
+ SIUL_PCR_16B_tag PCR112; /* offset: 0x0120 size: 16 bit */
+ SIUL_PCR_16B_tag PCR113; /* offset: 0x0122 size: 16 bit */
+ SIUL_PCR_16B_tag PCR114; /* offset: 0x0124 size: 16 bit */
+ SIUL_PCR_16B_tag PCR115; /* offset: 0x0126 size: 16 bit */
+ SIUL_PCR_16B_tag PCR116; /* offset: 0x0128 size: 16 bit */
+ SIUL_PCR_16B_tag PCR117; /* offset: 0x012A size: 16 bit */
+ SIUL_PCR_16B_tag PCR118; /* offset: 0x012C size: 16 bit */
+ SIUL_PCR_16B_tag PCR119; /* offset: 0x012E size: 16 bit */
+ SIUL_PCR_16B_tag PCR120; /* offset: 0x0130 size: 16 bit */
+ SIUL_PCR_16B_tag PCR121; /* offset: 0x0132 size: 16 bit */
+ SIUL_PCR_16B_tag PCR122; /* offset: 0x0134 size: 16 bit */
+ SIUL_PCR_16B_tag PCR123; /* offset: 0x0136 size: 16 bit */
+ SIUL_PCR_16B_tag PCR124; /* offset: 0x0138 size: 16 bit */
+ SIUL_PCR_16B_tag PCR125; /* offset: 0x013A size: 16 bit */
+ SIUL_PCR_16B_tag PCR126; /* offset: 0x013C size: 16 bit */
+ SIUL_PCR_16B_tag PCR127; /* offset: 0x013E size: 16 bit */
+ SIUL_PCR_16B_tag PCR128; /* offset: 0x0140 size: 16 bit */
+ SIUL_PCR_16B_tag PCR129; /* offset: 0x0142 size: 16 bit */
+ SIUL_PCR_16B_tag PCR130; /* offset: 0x0144 size: 16 bit */
+ SIUL_PCR_16B_tag PCR131; /* offset: 0x0146 size: 16 bit */
+ SIUL_PCR_16B_tag PCR132; /* offset: 0x0148 size: 16 bit */
+ SIUL_PCR_16B_tag PCR133; /* offset: 0x014A size: 16 bit */
+ SIUL_PCR_16B_tag PCR134; /* offset: 0x014C size: 16 bit */
+ SIUL_PCR_16B_tag PCR135; /* offset: 0x014E size: 16 bit */
+ SIUL_PCR_16B_tag PCR136; /* offset: 0x0150 size: 16 bit */
+ SIUL_PCR_16B_tag PCR137; /* offset: 0x0152 size: 16 bit */
+ SIUL_PCR_16B_tag PCR138; /* offset: 0x0154 size: 16 bit */
+ SIUL_PCR_16B_tag PCR139; /* offset: 0x0156 size: 16 bit */
+ SIUL_PCR_16B_tag PCR140; /* offset: 0x0158 size: 16 bit */
+ SIUL_PCR_16B_tag PCR141; /* offset: 0x015A size: 16 bit */
+ SIUL_PCR_16B_tag PCR142; /* offset: 0x015C size: 16 bit */
+ SIUL_PCR_16B_tag PCR143; /* offset: 0x015E size: 16 bit */
+ SIUL_PCR_16B_tag PCR144; /* offset: 0x0160 size: 16 bit */
+ SIUL_PCR_16B_tag PCR145; /* offset: 0x0162 size: 16 bit */
+ SIUL_PCR_16B_tag PCR146; /* offset: 0x0164 size: 16 bit */
+ SIUL_PCR_16B_tag PCR147; /* offset: 0x0166 size: 16 bit */
+ SIUL_PCR_16B_tag PCR148; /* offset: 0x0168 size: 16 bit */
+ SIUL_PCR_16B_tag PCR149; /* offset: 0x016A size: 16 bit */
+ SIUL_PCR_16B_tag PCR150; /* offset: 0x016C size: 16 bit */
+ SIUL_PCR_16B_tag PCR151; /* offset: 0x016E size: 16 bit */
+ SIUL_PCR_16B_tag PCR152; /* offset: 0x0170 size: 16 bit */
+ SIUL_PCR_16B_tag PCR153; /* offset: 0x0172 size: 16 bit */
+ SIUL_PCR_16B_tag PCR154; /* offset: 0x0174 size: 16 bit */
+ SIUL_PCR_16B_tag PCR155; /* offset: 0x0176 size: 16 bit */
+ SIUL_PCR_16B_tag PCR156; /* offset: 0x0178 size: 16 bit */
+ SIUL_PCR_16B_tag PCR157; /* offset: 0x017A size: 16 bit */
+ SIUL_PCR_16B_tag PCR158; /* offset: 0x017C size: 16 bit */
+ SIUL_PCR_16B_tag PCR159; /* offset: 0x017E size: 16 bit */
+ SIUL_PCR_16B_tag PCR160; /* offset: 0x0180 size: 16 bit */
+ SIUL_PCR_16B_tag PCR161; /* offset: 0x0182 size: 16 bit */
+ SIUL_PCR_16B_tag PCR162; /* offset: 0x0184 size: 16 bit */
+ SIUL_PCR_16B_tag PCR163; /* offset: 0x0186 size: 16 bit */
+ SIUL_PCR_16B_tag PCR164; /* offset: 0x0188 size: 16 bit */
+ SIUL_PCR_16B_tag PCR165; /* offset: 0x018A size: 16 bit */
+ SIUL_PCR_16B_tag PCR166; /* offset: 0x018C size: 16 bit */
+ SIUL_PCR_16B_tag PCR167; /* offset: 0x018E size: 16 bit */
+ SIUL_PCR_16B_tag PCR168; /* offset: 0x0190 size: 16 bit */
+ SIUL_PCR_16B_tag PCR169; /* offset: 0x0192 size: 16 bit */
+ SIUL_PCR_16B_tag PCR170; /* offset: 0x0194 size: 16 bit */
+ SIUL_PCR_16B_tag PCR171; /* offset: 0x0196 size: 16 bit */
+ SIUL_PCR_16B_tag PCR172; /* offset: 0x0198 size: 16 bit */
+ SIUL_PCR_16B_tag PCR173; /* offset: 0x019A size: 16 bit */
+ SIUL_PCR_16B_tag PCR174; /* offset: 0x019C size: 16 bit */
+ SIUL_PCR_16B_tag PCR175; /* offset: 0x019E size: 16 bit */
+ SIUL_PCR_16B_tag PCR176; /* offset: 0x01A0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR177; /* offset: 0x01A2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR178; /* offset: 0x01A4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR179; /* offset: 0x01A6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR180; /* offset: 0x01A8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR181; /* offset: 0x01AA size: 16 bit */
+ SIUL_PCR_16B_tag PCR182; /* offset: 0x01AC size: 16 bit */
+ SIUL_PCR_16B_tag PCR183; /* offset: 0x01AE size: 16 bit */
+ SIUL_PCR_16B_tag PCR184; /* offset: 0x01B0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR185; /* offset: 0x01B2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR186; /* offset: 0x01B4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR187; /* offset: 0x01B6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR188; /* offset: 0x01B8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR189; /* offset: 0x01BA size: 16 bit */
+ SIUL_PCR_16B_tag PCR190; /* offset: 0x01BC size: 16 bit */
+ SIUL_PCR_16B_tag PCR191; /* offset: 0x01BE size: 16 bit */
+ SIUL_PCR_16B_tag PCR192; /* offset: 0x01C0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR193; /* offset: 0x01C2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR194; /* offset: 0x01C4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR195; /* offset: 0x01C6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR196; /* offset: 0x01C8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR197; /* offset: 0x01CA size: 16 bit */
+ SIUL_PCR_16B_tag PCR198; /* offset: 0x01CC size: 16 bit */
+ SIUL_PCR_16B_tag PCR199; /* offset: 0x01CE size: 16 bit */
+ SIUL_PCR_16B_tag PCR200; /* offset: 0x01D0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR201; /* offset: 0x01D2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR202; /* offset: 0x01D4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR203; /* offset: 0x01D6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR204; /* offset: 0x01D8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR205; /* offset: 0x01DA size: 16 bit */
+ SIUL_PCR_16B_tag PCR206; /* offset: 0x01DC size: 16 bit */
+ SIUL_PCR_16B_tag PCR207; /* offset: 0x01DE size: 16 bit */
+ SIUL_PCR_16B_tag PCR208; /* offset: 0x01E0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR209; /* offset: 0x01E2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR210; /* offset: 0x01E4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR211; /* offset: 0x01E6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR212; /* offset: 0x01E8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR213; /* offset: 0x01EA size: 16 bit */
+ SIUL_PCR_16B_tag PCR214; /* offset: 0x01EC size: 16 bit */
+ SIUL_PCR_16B_tag PCR215; /* offset: 0x01EE size: 16 bit */
+ SIUL_PCR_16B_tag PCR216; /* offset: 0x01F0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR217; /* offset: 0x01F2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR218; /* offset: 0x01F4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR219; /* offset: 0x01F6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR220; /* offset: 0x01F8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR221; /* offset: 0x01FA size: 16 bit */
+ SIUL_PCR_16B_tag PCR222; /* offset: 0x01FC size: 16 bit */
+ SIUL_PCR_16B_tag PCR223; /* offset: 0x01FE size: 16 bit */
+ SIUL_PCR_16B_tag PCR224; /* offset: 0x0200 size: 16 bit */
+ SIUL_PCR_16B_tag PCR225; /* offset: 0x0202 size: 16 bit */
+ SIUL_PCR_16B_tag PCR226; /* offset: 0x0204 size: 16 bit */
+ SIUL_PCR_16B_tag PCR227; /* offset: 0x0206 size: 16 bit */
+ SIUL_PCR_16B_tag PCR228; /* offset: 0x0208 size: 16 bit */
+ SIUL_PCR_16B_tag PCR229; /* offset: 0x020A size: 16 bit */
+ SIUL_PCR_16B_tag PCR230; /* offset: 0x020C size: 16 bit */
+ SIUL_PCR_16B_tag PCR231; /* offset: 0x020E size: 16 bit */
+ SIUL_PCR_16B_tag PCR232; /* offset: 0x0210 size: 16 bit */
+ SIUL_PCR_16B_tag PCR233; /* offset: 0x0212 size: 16 bit */
+ SIUL_PCR_16B_tag PCR234; /* offset: 0x0214 size: 16 bit */
+ SIUL_PCR_16B_tag PCR235; /* offset: 0x0216 size: 16 bit */
+ SIUL_PCR_16B_tag PCR236; /* offset: 0x0218 size: 16 bit */
+ SIUL_PCR_16B_tag PCR237; /* offset: 0x021A size: 16 bit */
+ SIUL_PCR_16B_tag PCR238; /* offset: 0x021C size: 16 bit */
+ SIUL_PCR_16B_tag PCR239; /* offset: 0x021E size: 16 bit */
+ SIUL_PCR_16B_tag PCR240; /* offset: 0x0220 size: 16 bit */
+ SIUL_PCR_16B_tag PCR241; /* offset: 0x0222 size: 16 bit */
+ SIUL_PCR_16B_tag PCR242; /* offset: 0x0224 size: 16 bit */
+ SIUL_PCR_16B_tag PCR243; /* offset: 0x0226 size: 16 bit */
+ SIUL_PCR_16B_tag PCR244; /* offset: 0x0228 size: 16 bit */
+ SIUL_PCR_16B_tag PCR245; /* offset: 0x022A size: 16 bit */
+ SIUL_PCR_16B_tag PCR246; /* offset: 0x022C size: 16 bit */
+ SIUL_PCR_16B_tag PCR247; /* offset: 0x022E size: 16 bit */
+ SIUL_PCR_16B_tag PCR248; /* offset: 0x0230 size: 16 bit */
+ SIUL_PCR_16B_tag PCR249; /* offset: 0x0232 size: 16 bit */
+ SIUL_PCR_16B_tag PCR250; /* offset: 0x0234 size: 16 bit */
+ SIUL_PCR_16B_tag PCR251; /* offset: 0x0236 size: 16 bit */
+ SIUL_PCR_16B_tag PCR252; /* offset: 0x0238 size: 16 bit */
+ SIUL_PCR_16B_tag PCR253; /* offset: 0x023A size: 16 bit */
+ SIUL_PCR_16B_tag PCR254; /* offset: 0x023C size: 16 bit */
+ SIUL_PCR_16B_tag PCR255; /* offset: 0x023E size: 16 bit */
+ SIUL_PCR_16B_tag PCR256; /* offset: 0x0240 size: 16 bit */
+ SIUL_PCR_16B_tag PCR257; /* offset: 0x0242 size: 16 bit */
+ SIUL_PCR_16B_tag PCR258; /* offset: 0x0244 size: 16 bit */
+ SIUL_PCR_16B_tag PCR259; /* offset: 0x0246 size: 16 bit */
+ SIUL_PCR_16B_tag PCR260; /* offset: 0x0248 size: 16 bit */
+ SIUL_PCR_16B_tag PCR261; /* offset: 0x024A size: 16 bit */
+ SIUL_PCR_16B_tag PCR262; /* offset: 0x024C size: 16 bit */
+ SIUL_PCR_16B_tag PCR263; /* offset: 0x024E size: 16 bit */
+ SIUL_PCR_16B_tag PCR264; /* offset: 0x0250 size: 16 bit */
+ SIUL_PCR_16B_tag PCR265; /* offset: 0x0252 size: 16 bit */
+ SIUL_PCR_16B_tag PCR266; /* offset: 0x0254 size: 16 bit */
+ SIUL_PCR_16B_tag PCR267; /* offset: 0x0256 size: 16 bit */
+ SIUL_PCR_16B_tag PCR268; /* offset: 0x0258 size: 16 bit */
+ SIUL_PCR_16B_tag PCR269; /* offset: 0x025A size: 16 bit */
+ SIUL_PCR_16B_tag PCR270; /* offset: 0x025C size: 16 bit */
+ SIUL_PCR_16B_tag PCR271; /* offset: 0x025E size: 16 bit */
+ SIUL_PCR_16B_tag PCR272; /* offset: 0x0260 size: 16 bit */
+ SIUL_PCR_16B_tag PCR273; /* offset: 0x0262 size: 16 bit */
+ SIUL_PCR_16B_tag PCR274; /* offset: 0x0264 size: 16 bit */
+ SIUL_PCR_16B_tag PCR275; /* offset: 0x0266 size: 16 bit */
+ SIUL_PCR_16B_tag PCR276; /* offset: 0x0268 size: 16 bit */
+ SIUL_PCR_16B_tag PCR277; /* offset: 0x026A size: 16 bit */
+ SIUL_PCR_16B_tag PCR278; /* offset: 0x026C size: 16 bit */
+ SIUL_PCR_16B_tag PCR279; /* offset: 0x026E size: 16 bit */
+ SIUL_PCR_16B_tag PCR280; /* offset: 0x0270 size: 16 bit */
+ SIUL_PCR_16B_tag PCR281; /* offset: 0x0272 size: 16 bit */
+ SIUL_PCR_16B_tag PCR282; /* offset: 0x0274 size: 16 bit */
+ SIUL_PCR_16B_tag PCR283; /* offset: 0x0276 size: 16 bit */
+ SIUL_PCR_16B_tag PCR284; /* offset: 0x0278 size: 16 bit */
+ SIUL_PCR_16B_tag PCR285; /* offset: 0x027A size: 16 bit */
+ SIUL_PCR_16B_tag PCR286; /* offset: 0x027C size: 16 bit */
+ SIUL_PCR_16B_tag PCR287; /* offset: 0x027E size: 16 bit */
+ SIUL_PCR_16B_tag PCR288; /* offset: 0x0280 size: 16 bit */
+ SIUL_PCR_16B_tag PCR289; /* offset: 0x0282 size: 16 bit */
+ SIUL_PCR_16B_tag PCR290; /* offset: 0x0284 size: 16 bit */
+ SIUL_PCR_16B_tag PCR291; /* offset: 0x0286 size: 16 bit */
+ SIUL_PCR_16B_tag PCR292; /* offset: 0x0288 size: 16 bit */
+ SIUL_PCR_16B_tag PCR293; /* offset: 0x028A size: 16 bit */
+ SIUL_PCR_16B_tag PCR294; /* offset: 0x028C size: 16 bit */
+ SIUL_PCR_16B_tag PCR295; /* offset: 0x028E size: 16 bit */
+ SIUL_PCR_16B_tag PCR296; /* offset: 0x0290 size: 16 bit */
+ SIUL_PCR_16B_tag PCR297; /* offset: 0x0292 size: 16 bit */
+ SIUL_PCR_16B_tag PCR298; /* offset: 0x0294 size: 16 bit */
+ SIUL_PCR_16B_tag PCR299; /* offset: 0x0296 size: 16 bit */
+ SIUL_PCR_16B_tag PCR300; /* offset: 0x0298 size: 16 bit */
+ SIUL_PCR_16B_tag PCR301; /* offset: 0x029A size: 16 bit */
+ SIUL_PCR_16B_tag PCR302; /* offset: 0x029C size: 16 bit */
+ SIUL_PCR_16B_tag PCR303; /* offset: 0x029E size: 16 bit */
+ SIUL_PCR_16B_tag PCR304; /* offset: 0x02A0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR305; /* offset: 0x02A2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR306; /* offset: 0x02A4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR307; /* offset: 0x02A6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR308; /* offset: 0x02A8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR309; /* offset: 0x02AA size: 16 bit */
+ SIUL_PCR_16B_tag PCR310; /* offset: 0x02AC size: 16 bit */
+ SIUL_PCR_16B_tag PCR311; /* offset: 0x02AE size: 16 bit */
+ SIUL_PCR_16B_tag PCR312; /* offset: 0x02B0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR313; /* offset: 0x02B2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR314; /* offset: 0x02B4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR315; /* offset: 0x02B6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR316; /* offset: 0x02B8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR317; /* offset: 0x02BA size: 16 bit */
+ SIUL_PCR_16B_tag PCR318; /* offset: 0x02BC size: 16 bit */
+ SIUL_PCR_16B_tag PCR319; /* offset: 0x02BE size: 16 bit */
+ SIUL_PCR_16B_tag PCR320; /* offset: 0x02C0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR321; /* offset: 0x02C2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR322; /* offset: 0x02C4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR323; /* offset: 0x02C6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR324; /* offset: 0x02C8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR325; /* offset: 0x02CA size: 16 bit */
+ SIUL_PCR_16B_tag PCR326; /* offset: 0x02CC size: 16 bit */
+ SIUL_PCR_16B_tag PCR327; /* offset: 0x02CE size: 16 bit */
+ SIUL_PCR_16B_tag PCR328; /* offset: 0x02D0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR329; /* offset: 0x02D2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR330; /* offset: 0x02D4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR331; /* offset: 0x02D6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR332; /* offset: 0x02D8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR333; /* offset: 0x02DA size: 16 bit */
+ SIUL_PCR_16B_tag PCR334; /* offset: 0x02DC size: 16 bit */
+ SIUL_PCR_16B_tag PCR335; /* offset: 0x02DE size: 16 bit */
+ SIUL_PCR_16B_tag PCR336; /* offset: 0x02E0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR337; /* offset: 0x02E2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR338; /* offset: 0x02E4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR339; /* offset: 0x02E6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR340; /* offset: 0x02E8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR341; /* offset: 0x02EA size: 16 bit */
+ SIUL_PCR_16B_tag PCR342; /* offset: 0x02EC size: 16 bit */
+ SIUL_PCR_16B_tag PCR343; /* offset: 0x02EE size: 16 bit */
+ SIUL_PCR_16B_tag PCR344; /* offset: 0x02F0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR345; /* offset: 0x02F2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR346; /* offset: 0x02F4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR347; /* offset: 0x02F6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR348; /* offset: 0x02F8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR349; /* offset: 0x02FA size: 16 bit */
+ SIUL_PCR_16B_tag PCR350; /* offset: 0x02FC size: 16 bit */
+ SIUL_PCR_16B_tag PCR351; /* offset: 0x02FE size: 16 bit */
+ SIUL_PCR_16B_tag PCR352; /* offset: 0x0300 size: 16 bit */
+ SIUL_PCR_16B_tag PCR353; /* offset: 0x0302 size: 16 bit */
+ SIUL_PCR_16B_tag PCR354; /* offset: 0x0304 size: 16 bit */
+ SIUL_PCR_16B_tag PCR355; /* offset: 0x0306 size: 16 bit */
+ SIUL_PCR_16B_tag PCR356; /* offset: 0x0308 size: 16 bit */
+ SIUL_PCR_16B_tag PCR357; /* offset: 0x030A size: 16 bit */
+ SIUL_PCR_16B_tag PCR358; /* offset: 0x030C size: 16 bit */
+ SIUL_PCR_16B_tag PCR359; /* offset: 0x030E size: 16 bit */
+ SIUL_PCR_16B_tag PCR360; /* offset: 0x0310 size: 16 bit */
+ SIUL_PCR_16B_tag PCR361; /* offset: 0x0312 size: 16 bit */
+ SIUL_PCR_16B_tag PCR362; /* offset: 0x0314 size: 16 bit */
+ SIUL_PCR_16B_tag PCR363; /* offset: 0x0316 size: 16 bit */
+ SIUL_PCR_16B_tag PCR364; /* offset: 0x0318 size: 16 bit */
+ SIUL_PCR_16B_tag PCR365; /* offset: 0x031A size: 16 bit */
+ SIUL_PCR_16B_tag PCR366; /* offset: 0x031C size: 16 bit */
+ SIUL_PCR_16B_tag PCR367; /* offset: 0x031E size: 16 bit */
+ SIUL_PCR_16B_tag PCR368; /* offset: 0x0320 size: 16 bit */
+ SIUL_PCR_16B_tag PCR369; /* offset: 0x0322 size: 16 bit */
+ SIUL_PCR_16B_tag PCR370; /* offset: 0x0324 size: 16 bit */
+ SIUL_PCR_16B_tag PCR371; /* offset: 0x0326 size: 16 bit */
+ SIUL_PCR_16B_tag PCR372; /* offset: 0x0328 size: 16 bit */
+ SIUL_PCR_16B_tag PCR373; /* offset: 0x032A size: 16 bit */
+ SIUL_PCR_16B_tag PCR374; /* offset: 0x032C size: 16 bit */
+ SIUL_PCR_16B_tag PCR375; /* offset: 0x032E size: 16 bit */
+ SIUL_PCR_16B_tag PCR376; /* offset: 0x0330 size: 16 bit */
+ SIUL_PCR_16B_tag PCR377; /* offset: 0x0332 size: 16 bit */
+ SIUL_PCR_16B_tag PCR378; /* offset: 0x0334 size: 16 bit */
+ SIUL_PCR_16B_tag PCR379; /* offset: 0x0336 size: 16 bit */
+ SIUL_PCR_16B_tag PCR380; /* offset: 0x0338 size: 16 bit */
+ SIUL_PCR_16B_tag PCR381; /* offset: 0x033A size: 16 bit */
+ SIUL_PCR_16B_tag PCR382; /* offset: 0x033C size: 16 bit */
+ SIUL_PCR_16B_tag PCR383; /* offset: 0x033E size: 16 bit */
+ SIUL_PCR_16B_tag PCR384; /* offset: 0x0340 size: 16 bit */
+ SIUL_PCR_16B_tag PCR385; /* offset: 0x0342 size: 16 bit */
+ SIUL_PCR_16B_tag PCR386; /* offset: 0x0344 size: 16 bit */
+ SIUL_PCR_16B_tag PCR387; /* offset: 0x0346 size: 16 bit */
+ SIUL_PCR_16B_tag PCR388; /* offset: 0x0348 size: 16 bit */
+ SIUL_PCR_16B_tag PCR389; /* offset: 0x034A size: 16 bit */
+ SIUL_PCR_16B_tag PCR390; /* offset: 0x034C size: 16 bit */
+ SIUL_PCR_16B_tag PCR391; /* offset: 0x034E size: 16 bit */
+ SIUL_PCR_16B_tag PCR392; /* offset: 0x0350 size: 16 bit */
+ SIUL_PCR_16B_tag PCR393; /* offset: 0x0352 size: 16 bit */
+ SIUL_PCR_16B_tag PCR394; /* offset: 0x0354 size: 16 bit */
+ SIUL_PCR_16B_tag PCR395; /* offset: 0x0356 size: 16 bit */
+ SIUL_PCR_16B_tag PCR396; /* offset: 0x0358 size: 16 bit */
+ SIUL_PCR_16B_tag PCR397; /* offset: 0x035A size: 16 bit */
+ SIUL_PCR_16B_tag PCR398; /* offset: 0x035C size: 16 bit */
+ SIUL_PCR_16B_tag PCR399; /* offset: 0x035E size: 16 bit */
+ SIUL_PCR_16B_tag PCR400; /* offset: 0x0360 size: 16 bit */
+ SIUL_PCR_16B_tag PCR401; /* offset: 0x0362 size: 16 bit */
+ SIUL_PCR_16B_tag PCR402; /* offset: 0x0364 size: 16 bit */
+ SIUL_PCR_16B_tag PCR403; /* offset: 0x0366 size: 16 bit */
+ SIUL_PCR_16B_tag PCR404; /* offset: 0x0368 size: 16 bit */
+ SIUL_PCR_16B_tag PCR405; /* offset: 0x036A size: 16 bit */
+ SIUL_PCR_16B_tag PCR406; /* offset: 0x036C size: 16 bit */
+ SIUL_PCR_16B_tag PCR407; /* offset: 0x036E size: 16 bit */
+ SIUL_PCR_16B_tag PCR408; /* offset: 0x0370 size: 16 bit */
+ SIUL_PCR_16B_tag PCR409; /* offset: 0x0372 size: 16 bit */
+ SIUL_PCR_16B_tag PCR410; /* offset: 0x0374 size: 16 bit */
+ SIUL_PCR_16B_tag PCR411; /* offset: 0x0376 size: 16 bit */
+ SIUL_PCR_16B_tag PCR412; /* offset: 0x0378 size: 16 bit */
+ SIUL_PCR_16B_tag PCR413; /* offset: 0x037A size: 16 bit */
+ SIUL_PCR_16B_tag PCR414; /* offset: 0x037C size: 16 bit */
+ SIUL_PCR_16B_tag PCR415; /* offset: 0x037E size: 16 bit */
+ SIUL_PCR_16B_tag PCR416; /* offset: 0x0380 size: 16 bit */
+ SIUL_PCR_16B_tag PCR417; /* offset: 0x0382 size: 16 bit */
+ SIUL_PCR_16B_tag PCR418; /* offset: 0x0384 size: 16 bit */
+ SIUL_PCR_16B_tag PCR419; /* offset: 0x0386 size: 16 bit */
+ SIUL_PCR_16B_tag PCR420; /* offset: 0x0388 size: 16 bit */
+ SIUL_PCR_16B_tag PCR421; /* offset: 0x038A size: 16 bit */
+ SIUL_PCR_16B_tag PCR422; /* offset: 0x038C size: 16 bit */
+ SIUL_PCR_16B_tag PCR423; /* offset: 0x038E size: 16 bit */
+ SIUL_PCR_16B_tag PCR424; /* offset: 0x0390 size: 16 bit */
+ SIUL_PCR_16B_tag PCR425; /* offset: 0x0392 size: 16 bit */
+ SIUL_PCR_16B_tag PCR426; /* offset: 0x0394 size: 16 bit */
+ SIUL_PCR_16B_tag PCR427; /* offset: 0x0396 size: 16 bit */
+ SIUL_PCR_16B_tag PCR428; /* offset: 0x0398 size: 16 bit */
+ SIUL_PCR_16B_tag PCR429; /* offset: 0x039A size: 16 bit */
+ SIUL_PCR_16B_tag PCR430; /* offset: 0x039C size: 16 bit */
+ SIUL_PCR_16B_tag PCR431; /* offset: 0x039E size: 16 bit */
+ SIUL_PCR_16B_tag PCR432; /* offset: 0x03A0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR433; /* offset: 0x03A2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR434; /* offset: 0x03A4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR435; /* offset: 0x03A6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR436; /* offset: 0x03A8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR437; /* offset: 0x03AA size: 16 bit */
+ SIUL_PCR_16B_tag PCR438; /* offset: 0x03AC size: 16 bit */
+ SIUL_PCR_16B_tag PCR439; /* offset: 0x03AE size: 16 bit */
+ SIUL_PCR_16B_tag PCR440; /* offset: 0x03B0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR441; /* offset: 0x03B2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR442; /* offset: 0x03B4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR443; /* offset: 0x03B6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR444; /* offset: 0x03B8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR445; /* offset: 0x03BA size: 16 bit */
+ SIUL_PCR_16B_tag PCR446; /* offset: 0x03BC size: 16 bit */
+ SIUL_PCR_16B_tag PCR447; /* offset: 0x03BE size: 16 bit */
+ SIUL_PCR_16B_tag PCR448; /* offset: 0x03C0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR449; /* offset: 0x03C2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR450; /* offset: 0x03C4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR451; /* offset: 0x03C6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR452; /* offset: 0x03C8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR453; /* offset: 0x03CA size: 16 bit */
+ SIUL_PCR_16B_tag PCR454; /* offset: 0x03CC size: 16 bit */
+ SIUL_PCR_16B_tag PCR455; /* offset: 0x03CE size: 16 bit */
+ SIUL_PCR_16B_tag PCR456; /* offset: 0x03D0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR457; /* offset: 0x03D2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR458; /* offset: 0x03D4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR459; /* offset: 0x03D6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR460; /* offset: 0x03D8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR461; /* offset: 0x03DA size: 16 bit */
+ SIUL_PCR_16B_tag PCR462; /* offset: 0x03DC size: 16 bit */
+ SIUL_PCR_16B_tag PCR463; /* offset: 0x03DE size: 16 bit */
+ SIUL_PCR_16B_tag PCR464; /* offset: 0x03E0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR465; /* offset: 0x03E2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR466; /* offset: 0x03E4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR467; /* offset: 0x03E6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR468; /* offset: 0x03E8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR469; /* offset: 0x03EA size: 16 bit */
+ SIUL_PCR_16B_tag PCR470; /* offset: 0x03EC size: 16 bit */
+ SIUL_PCR_16B_tag PCR471; /* offset: 0x03EE size: 16 bit */
+ SIUL_PCR_16B_tag PCR472; /* offset: 0x03F0 size: 16 bit */
+ SIUL_PCR_16B_tag PCR473; /* offset: 0x03F2 size: 16 bit */
+ SIUL_PCR_16B_tag PCR474; /* offset: 0x03F4 size: 16 bit */
+ SIUL_PCR_16B_tag PCR475; /* offset: 0x03F6 size: 16 bit */
+ SIUL_PCR_16B_tag PCR476; /* offset: 0x03F8 size: 16 bit */
+ SIUL_PCR_16B_tag PCR477; /* offset: 0x03FA size: 16 bit */
+ SIUL_PCR_16B_tag PCR478; /* offset: 0x03FC size: 16 bit */
+ SIUL_PCR_16B_tag PCR479; /* offset: 0x03FE size: 16 bit */
+ SIUL_PCR_16B_tag PCR480; /* offset: 0x0400 size: 16 bit */
+ SIUL_PCR_16B_tag PCR481; /* offset: 0x0402 size: 16 bit */
+ SIUL_PCR_16B_tag PCR482; /* offset: 0x0404 size: 16 bit */
+ SIUL_PCR_16B_tag PCR483; /* offset: 0x0406 size: 16 bit */
+ SIUL_PCR_16B_tag PCR484; /* offset: 0x0408 size: 16 bit */
+ SIUL_PCR_16B_tag PCR485; /* offset: 0x040A size: 16 bit */
+ SIUL_PCR_16B_tag PCR486; /* offset: 0x040C size: 16 bit */
+ SIUL_PCR_16B_tag PCR487; /* offset: 0x040E size: 16 bit */
+ SIUL_PCR_16B_tag PCR488; /* offset: 0x0410 size: 16 bit */
+ SIUL_PCR_16B_tag PCR489; /* offset: 0x0412 size: 16 bit */
+ SIUL_PCR_16B_tag PCR490; /* offset: 0x0414 size: 16 bit */
+ SIUL_PCR_16B_tag PCR491; /* offset: 0x0416 size: 16 bit */
+ SIUL_PCR_16B_tag PCR492; /* offset: 0x0418 size: 16 bit */
+ SIUL_PCR_16B_tag PCR493; /* offset: 0x041A size: 16 bit */
+ SIUL_PCR_16B_tag PCR494; /* offset: 0x041C size: 16 bit */
+ SIUL_PCR_16B_tag PCR495; /* offset: 0x041E size: 16 bit */
+ SIUL_PCR_16B_tag PCR496; /* offset: 0x0420 size: 16 bit */
+ SIUL_PCR_16B_tag PCR497; /* offset: 0x0422 size: 16 bit */
+ SIUL_PCR_16B_tag PCR498; /* offset: 0x0424 size: 16 bit */
+ SIUL_PCR_16B_tag PCR499; /* offset: 0x0426 size: 16 bit */
+ SIUL_PCR_16B_tag PCR500; /* offset: 0x0428 size: 16 bit */
+ SIUL_PCR_16B_tag PCR501; /* offset: 0x042A size: 16 bit */
+ SIUL_PCR_16B_tag PCR502; /* offset: 0x042C size: 16 bit */
+ SIUL_PCR_16B_tag PCR503; /* offset: 0x042E size: 16 bit */
+ SIUL_PCR_16B_tag PCR504; /* offset: 0x0430 size: 16 bit */
+ SIUL_PCR_16B_tag PCR505; /* offset: 0x0432 size: 16 bit */
+ SIUL_PCR_16B_tag PCR506; /* offset: 0x0434 size: 16 bit */
+ SIUL_PCR_16B_tag PCR507; /* offset: 0x0436 size: 16 bit */
+ SIUL_PCR_16B_tag PCR508; /* offset: 0x0438 size: 16 bit */
+ SIUL_PCR_16B_tag PCR509; /* offset: 0x043A size: 16 bit */
+ SIUL_PCR_16B_tag PCR510; /* offset: 0x043C size: 16 bit */
+ SIUL_PCR_16B_tag PCR511; /* offset: 0x043E size: 16 bit */
+ };
+
+ };
+ int8_t SIUL_reserved_0440_C[192];
+ union {
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_32B_tag PSMI_32B[64]; /* offset: 0x0500 (0x0004 x 64) */
+
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_8B_tag PSMI[256]; /* offset: 0x0500 (0x0001 x 256) */
+
+ struct {
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_32B_tag PSMI0_3; /* offset: 0x0500 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI4_7; /* offset: 0x0504 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI8_11; /* offset: 0x0508 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI12_15; /* offset: 0x050C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI16_19; /* offset: 0x0510 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI20_23; /* offset: 0x0514 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI24_27; /* offset: 0x0518 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI28_31; /* offset: 0x051C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI32_35; /* offset: 0x0520 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI36_39; /* offset: 0x0524 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI40_43; /* offset: 0x0528 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI44_47; /* offset: 0x052C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI48_51; /* offset: 0x0530 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI52_55; /* offset: 0x0534 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI56_59; /* offset: 0x0538 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI60_63; /* offset: 0x053C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI64_67; /* offset: 0x0540 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI68_71; /* offset: 0x0544 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI72_75; /* offset: 0x0548 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI76_79; /* offset: 0x054C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI80_83; /* offset: 0x0550 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI84_87; /* offset: 0x0554 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI88_91; /* offset: 0x0558 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI92_95; /* offset: 0x055C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI96_99; /* offset: 0x0560 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */
+ SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */
+ };
+
+ struct {
+ /* PSMI - Pad Selection for Multiplexed Inputs */
+ SIUL_PSMI_8B_tag PSMI0; /* offset: 0x0500 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI1; /* offset: 0x0501 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI2; /* offset: 0x0502 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI3; /* offset: 0x0503 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI4; /* offset: 0x0504 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI5; /* offset: 0x0505 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI6; /* offset: 0x0506 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI7; /* offset: 0x0507 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI8; /* offset: 0x0508 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI9; /* offset: 0x0509 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI10; /* offset: 0x050A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI11; /* offset: 0x050B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI12; /* offset: 0x050C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI13; /* offset: 0x050D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI14; /* offset: 0x050E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI15; /* offset: 0x050F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI16; /* offset: 0x0510 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI17; /* offset: 0x0511 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI18; /* offset: 0x0512 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI19; /* offset: 0x0513 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI20; /* offset: 0x0514 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI21; /* offset: 0x0515 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI22; /* offset: 0x0516 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI23; /* offset: 0x0517 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI24; /* offset: 0x0518 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI25; /* offset: 0x0519 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI26; /* offset: 0x051A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI27; /* offset: 0x051B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI28; /* offset: 0x051C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI29; /* offset: 0x051D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI30; /* offset: 0x051E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI31; /* offset: 0x051F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI32; /* offset: 0x0520 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI33; /* offset: 0x0521 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI34; /* offset: 0x0522 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI35; /* offset: 0x0523 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI36; /* offset: 0x0524 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI37; /* offset: 0x0525 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI38; /* offset: 0x0526 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI39; /* offset: 0x0527 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI40; /* offset: 0x0528 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI41; /* offset: 0x0529 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI42; /* offset: 0x052A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI43; /* offset: 0x052B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI44; /* offset: 0x052C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI45; /* offset: 0x052D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI46; /* offset: 0x052E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI47; /* offset: 0x052F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI48; /* offset: 0x0530 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI49; /* offset: 0x0531 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI50; /* offset: 0x0532 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI51; /* offset: 0x0533 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI52; /* offset: 0x0534 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI53; /* offset: 0x0535 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI54; /* offset: 0x0536 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI55; /* offset: 0x0537 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI56; /* offset: 0x0538 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI57; /* offset: 0x0539 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI58; /* offset: 0x053A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI59; /* offset: 0x053B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI60; /* offset: 0x053C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI61; /* offset: 0x053D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI62; /* offset: 0x053E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI63; /* offset: 0x053F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI64; /* offset: 0x0540 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI65; /* offset: 0x0541 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI66; /* offset: 0x0542 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI67; /* offset: 0x0543 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI68; /* offset: 0x0544 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI69; /* offset: 0x0545 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI70; /* offset: 0x0546 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI71; /* offset: 0x0547 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI72; /* offset: 0x0548 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI73; /* offset: 0x0549 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI74; /* offset: 0x054A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI75; /* offset: 0x054B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI76; /* offset: 0x054C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI77; /* offset: 0x054D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI78; /* offset: 0x054E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI79; /* offset: 0x054F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI80; /* offset: 0x0550 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI81; /* offset: 0x0551 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI82; /* offset: 0x0552 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI83; /* offset: 0x0553 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI84; /* offset: 0x0554 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI85; /* offset: 0x0555 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI86; /* offset: 0x0556 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI87; /* offset: 0x0557 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI88; /* offset: 0x0558 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI89; /* offset: 0x0559 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI90; /* offset: 0x055A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI91; /* offset: 0x055B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI92; /* offset: 0x055C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI93; /* offset: 0x055D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI94; /* offset: 0x055E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI95; /* offset: 0x055F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI96; /* offset: 0x0560 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI97; /* offset: 0x0561 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI98; /* offset: 0x0562 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI99; /* offset: 0x0563 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI100; /* offset: 0x0564 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI101; /* offset: 0x0565 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI102; /* offset: 0x0566 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI103; /* offset: 0x0567 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI104; /* offset: 0x0568 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI105; /* offset: 0x0569 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI106; /* offset: 0x056A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI107; /* offset: 0x056B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI108; /* offset: 0x056C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI109; /* offset: 0x056D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI110; /* offset: 0x056E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI111; /* offset: 0x056F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI112; /* offset: 0x0570 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI113; /* offset: 0x0571 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI114; /* offset: 0x0572 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI115; /* offset: 0x0573 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI116; /* offset: 0x0574 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI117; /* offset: 0x0575 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI118; /* offset: 0x0576 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI119; /* offset: 0x0577 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI120; /* offset: 0x0578 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI121; /* offset: 0x0579 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI122; /* offset: 0x057A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI123; /* offset: 0x057B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI124; /* offset: 0x057C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI125; /* offset: 0x057D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI126; /* offset: 0x057E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI127; /* offset: 0x057F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI128; /* offset: 0x0580 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI129; /* offset: 0x0581 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI130; /* offset: 0x0582 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI131; /* offset: 0x0583 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI132; /* offset: 0x0584 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI133; /* offset: 0x0585 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI134; /* offset: 0x0586 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI135; /* offset: 0x0587 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI136; /* offset: 0x0588 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI137; /* offset: 0x0589 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI138; /* offset: 0x058A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI139; /* offset: 0x058B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI140; /* offset: 0x058C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI141; /* offset: 0x058D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI142; /* offset: 0x058E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI143; /* offset: 0x058F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI144; /* offset: 0x0590 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI145; /* offset: 0x0591 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI146; /* offset: 0x0592 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI147; /* offset: 0x0593 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI148; /* offset: 0x0594 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI149; /* offset: 0x0595 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI150; /* offset: 0x0596 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI151; /* offset: 0x0597 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI152; /* offset: 0x0598 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI153; /* offset: 0x0599 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI154; /* offset: 0x059A size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI155; /* offset: 0x059B size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI156; /* offset: 0x059C size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI157; /* offset: 0x059D size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI158; /* offset: 0x059E size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI159; /* offset: 0x059F size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI160; /* offset: 0x05A0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI161; /* offset: 0x05A1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI162; /* offset: 0x05A2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI163; /* offset: 0x05A3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI164; /* offset: 0x05A4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI165; /* offset: 0x05A5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI166; /* offset: 0x05A6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI167; /* offset: 0x05A7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI168; /* offset: 0x05A8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI169; /* offset: 0x05A9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI170; /* offset: 0x05AA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI171; /* offset: 0x05AB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI172; /* offset: 0x05AC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI173; /* offset: 0x05AD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI174; /* offset: 0x05AE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI175; /* offset: 0x05AF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI176; /* offset: 0x05B0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI177; /* offset: 0x05B1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI178; /* offset: 0x05B2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI179; /* offset: 0x05B3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI180; /* offset: 0x05B4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI181; /* offset: 0x05B5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI182; /* offset: 0x05B6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI183; /* offset: 0x05B7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI184; /* offset: 0x05B8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI185; /* offset: 0x05B9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI186; /* offset: 0x05BA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI187; /* offset: 0x05BB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI188; /* offset: 0x05BC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI189; /* offset: 0x05BD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI190; /* offset: 0x05BE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI191; /* offset: 0x05BF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI192; /* offset: 0x05C0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI193; /* offset: 0x05C1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI194; /* offset: 0x05C2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI195; /* offset: 0x05C3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI196; /* offset: 0x05C4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI197; /* offset: 0x05C5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI198; /* offset: 0x05C6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI199; /* offset: 0x05C7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI200; /* offset: 0x05C8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI201; /* offset: 0x05C9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI202; /* offset: 0x05CA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI203; /* offset: 0x05CB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI204; /* offset: 0x05CC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI205; /* offset: 0x05CD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI206; /* offset: 0x05CE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI207; /* offset: 0x05CF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI208; /* offset: 0x05D0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI209; /* offset: 0x05D1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI210; /* offset: 0x05D2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI211; /* offset: 0x05D3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI212; /* offset: 0x05D4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI213; /* offset: 0x05D5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI214; /* offset: 0x05D6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI215; /* offset: 0x05D7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI216; /* offset: 0x05D8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI217; /* offset: 0x05D9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI218; /* offset: 0x05DA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI219; /* offset: 0x05DB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI220; /* offset: 0x05DC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI221; /* offset: 0x05DD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI222; /* offset: 0x05DE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI223; /* offset: 0x05DF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI224; /* offset: 0x05E0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI225; /* offset: 0x05E1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI226; /* offset: 0x05E2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI227; /* offset: 0x05E3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI228; /* offset: 0x05E4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI229; /* offset: 0x05E5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI230; /* offset: 0x05E6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI231; /* offset: 0x05E7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI232; /* offset: 0x05E8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI233; /* offset: 0x05E9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI234; /* offset: 0x05EA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI235; /* offset: 0x05EB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI236; /* offset: 0x05EC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI237; /* offset: 0x05ED size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI238; /* offset: 0x05EE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI239; /* offset: 0x05EF size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI240; /* offset: 0x05F0 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI241; /* offset: 0x05F1 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI242; /* offset: 0x05F2 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI243; /* offset: 0x05F3 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI244; /* offset: 0x05F4 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI245; /* offset: 0x05F5 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI246; /* offset: 0x05F6 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI247; /* offset: 0x05F7 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI248; /* offset: 0x05F8 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI249; /* offset: 0x05F9 size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI250; /* offset: 0x05FA size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI251; /* offset: 0x05FB size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI252; /* offset: 0x05FC size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI253; /* offset: 0x05FD size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI254; /* offset: 0x05FE size: 8 bit */
+ SIUL_PSMI_8B_tag PSMI255; /* offset: 0x05FF size: 8 bit */
+ };
+
+ };
+ union {
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600 (0x0004 x 128) */
+
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_8B_tag GPDO[512]; /* offset: 0x0600 (0x0001 x 512) */
+
+ struct {
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_32B_tag GPDO0_3; /* offset: 0x0600 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO4_7; /* offset: 0x0604 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO8_11; /* offset: 0x0608 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO12_15; /* offset: 0x060C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO16_19; /* offset: 0x0610 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO20_23; /* offset: 0x0614 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO24_27; /* offset: 0x0618 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO28_31; /* offset: 0x061C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO32_35; /* offset: 0x0620 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO36_39; /* offset: 0x0624 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO40_43; /* offset: 0x0628 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO44_47; /* offset: 0x062C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO48_51; /* offset: 0x0630 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO52_55; /* offset: 0x0634 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO56_59; /* offset: 0x0638 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO60_63; /* offset: 0x063C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO64_67; /* offset: 0x0640 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO68_71; /* offset: 0x0644 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO72_75; /* offset: 0x0648 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO76_79; /* offset: 0x064C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO80_83; /* offset: 0x0650 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO84_87; /* offset: 0x0654 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO88_91; /* offset: 0x0658 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO92_95; /* offset: 0x065C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO96_99; /* offset: 0x0660 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */
+ SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */
+ };
+
+ struct {
+ /* GPDO - GPIO Pad Data Output Register */
+ SIUL_GPDO_8B_tag GPDO0; /* offset: 0x0600 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO1; /* offset: 0x0601 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO2; /* offset: 0x0602 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO3; /* offset: 0x0603 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO4; /* offset: 0x0604 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO5; /* offset: 0x0605 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO6; /* offset: 0x0606 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO7; /* offset: 0x0607 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO8; /* offset: 0x0608 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO9; /* offset: 0x0609 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO10; /* offset: 0x060A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO11; /* offset: 0x060B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO12; /* offset: 0x060C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO13; /* offset: 0x060D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO14; /* offset: 0x060E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO15; /* offset: 0x060F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO16; /* offset: 0x0610 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO17; /* offset: 0x0611 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO18; /* offset: 0x0612 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO19; /* offset: 0x0613 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO20; /* offset: 0x0614 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO21; /* offset: 0x0615 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO22; /* offset: 0x0616 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO23; /* offset: 0x0617 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO24; /* offset: 0x0618 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO25; /* offset: 0x0619 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO26; /* offset: 0x061A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO27; /* offset: 0x061B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO28; /* offset: 0x061C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO29; /* offset: 0x061D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO30; /* offset: 0x061E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO31; /* offset: 0x061F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO32; /* offset: 0x0620 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO33; /* offset: 0x0621 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO34; /* offset: 0x0622 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO35; /* offset: 0x0623 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO36; /* offset: 0x0624 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO37; /* offset: 0x0625 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO38; /* offset: 0x0626 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO39; /* offset: 0x0627 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO40; /* offset: 0x0628 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO41; /* offset: 0x0629 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO42; /* offset: 0x062A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO43; /* offset: 0x062B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO44; /* offset: 0x062C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO45; /* offset: 0x062D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO46; /* offset: 0x062E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO47; /* offset: 0x062F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO48; /* offset: 0x0630 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO49; /* offset: 0x0631 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO50; /* offset: 0x0632 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO51; /* offset: 0x0633 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO52; /* offset: 0x0634 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO53; /* offset: 0x0635 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO54; /* offset: 0x0636 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO55; /* offset: 0x0637 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO56; /* offset: 0x0638 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO57; /* offset: 0x0639 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO58; /* offset: 0x063A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO59; /* offset: 0x063B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO60; /* offset: 0x063C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO61; /* offset: 0x063D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO62; /* offset: 0x063E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO63; /* offset: 0x063F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO64; /* offset: 0x0640 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO65; /* offset: 0x0641 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO66; /* offset: 0x0642 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO67; /* offset: 0x0643 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO68; /* offset: 0x0644 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO69; /* offset: 0x0645 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO70; /* offset: 0x0646 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO71; /* offset: 0x0647 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO72; /* offset: 0x0648 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO73; /* offset: 0x0649 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO74; /* offset: 0x064A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO75; /* offset: 0x064B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO76; /* offset: 0x064C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO77; /* offset: 0x064D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO78; /* offset: 0x064E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO79; /* offset: 0x064F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO80; /* offset: 0x0650 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO81; /* offset: 0x0651 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO82; /* offset: 0x0652 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO83; /* offset: 0x0653 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO84; /* offset: 0x0654 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO85; /* offset: 0x0655 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO86; /* offset: 0x0656 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO87; /* offset: 0x0657 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO88; /* offset: 0x0658 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO89; /* offset: 0x0659 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO90; /* offset: 0x065A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO91; /* offset: 0x065B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO92; /* offset: 0x065C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO93; /* offset: 0x065D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO94; /* offset: 0x065E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO95; /* offset: 0x065F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO96; /* offset: 0x0660 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO97; /* offset: 0x0661 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO98; /* offset: 0x0662 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO99; /* offset: 0x0663 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO100; /* offset: 0x0664 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO101; /* offset: 0x0665 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO102; /* offset: 0x0666 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO103; /* offset: 0x0667 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO104; /* offset: 0x0668 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO105; /* offset: 0x0669 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO106; /* offset: 0x066A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO107; /* offset: 0x066B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO108; /* offset: 0x066C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO109; /* offset: 0x066D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO110; /* offset: 0x066E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO111; /* offset: 0x066F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO112; /* offset: 0x0670 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO113; /* offset: 0x0671 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO114; /* offset: 0x0672 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO115; /* offset: 0x0673 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO116; /* offset: 0x0674 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO117; /* offset: 0x0675 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO118; /* offset: 0x0676 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO119; /* offset: 0x0677 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO120; /* offset: 0x0678 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO121; /* offset: 0x0679 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO122; /* offset: 0x067A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO123; /* offset: 0x067B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO124; /* offset: 0x067C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO125; /* offset: 0x067D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO126; /* offset: 0x067E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO127; /* offset: 0x067F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO128; /* offset: 0x0680 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO129; /* offset: 0x0681 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO130; /* offset: 0x0682 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO131; /* offset: 0x0683 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO132; /* offset: 0x0684 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO133; /* offset: 0x0685 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO134; /* offset: 0x0686 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO135; /* offset: 0x0687 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO136; /* offset: 0x0688 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO137; /* offset: 0x0689 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO138; /* offset: 0x068A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO139; /* offset: 0x068B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO140; /* offset: 0x068C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO141; /* offset: 0x068D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO142; /* offset: 0x068E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO143; /* offset: 0x068F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO144; /* offset: 0x0690 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO145; /* offset: 0x0691 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO146; /* offset: 0x0692 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO147; /* offset: 0x0693 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO148; /* offset: 0x0694 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO149; /* offset: 0x0695 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO150; /* offset: 0x0696 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO151; /* offset: 0x0697 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO152; /* offset: 0x0698 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO153; /* offset: 0x0699 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO154; /* offset: 0x069A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO155; /* offset: 0x069B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO156; /* offset: 0x069C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO157; /* offset: 0x069D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO158; /* offset: 0x069E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO159; /* offset: 0x069F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO160; /* offset: 0x06A0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO161; /* offset: 0x06A1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO162; /* offset: 0x06A2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO163; /* offset: 0x06A3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO164; /* offset: 0x06A4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO165; /* offset: 0x06A5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO166; /* offset: 0x06A6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO167; /* offset: 0x06A7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO168; /* offset: 0x06A8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO169; /* offset: 0x06A9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO170; /* offset: 0x06AA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO171; /* offset: 0x06AB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO172; /* offset: 0x06AC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO173; /* offset: 0x06AD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO174; /* offset: 0x06AE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO175; /* offset: 0x06AF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO176; /* offset: 0x06B0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO177; /* offset: 0x06B1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO178; /* offset: 0x06B2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO179; /* offset: 0x06B3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO180; /* offset: 0x06B4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO181; /* offset: 0x06B5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO182; /* offset: 0x06B6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO183; /* offset: 0x06B7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO184; /* offset: 0x06B8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO185; /* offset: 0x06B9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO186; /* offset: 0x06BA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO187; /* offset: 0x06BB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO188; /* offset: 0x06BC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO189; /* offset: 0x06BD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO190; /* offset: 0x06BE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO191; /* offset: 0x06BF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO192; /* offset: 0x06C0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO193; /* offset: 0x06C1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO194; /* offset: 0x06C2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO195; /* offset: 0x06C3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO196; /* offset: 0x06C4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO197; /* offset: 0x06C5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO198; /* offset: 0x06C6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO199; /* offset: 0x06C7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO200; /* offset: 0x06C8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO201; /* offset: 0x06C9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO202; /* offset: 0x06CA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO203; /* offset: 0x06CB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO204; /* offset: 0x06CC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO205; /* offset: 0x06CD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO206; /* offset: 0x06CE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO207; /* offset: 0x06CF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO208; /* offset: 0x06D0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO209; /* offset: 0x06D1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO210; /* offset: 0x06D2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO211; /* offset: 0x06D3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO212; /* offset: 0x06D4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO213; /* offset: 0x06D5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO214; /* offset: 0x06D6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO215; /* offset: 0x06D7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO216; /* offset: 0x06D8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO217; /* offset: 0x06D9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO218; /* offset: 0x06DA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO219; /* offset: 0x06DB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO220; /* offset: 0x06DC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO221; /* offset: 0x06DD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO222; /* offset: 0x06DE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO223; /* offset: 0x06DF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO224; /* offset: 0x06E0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO225; /* offset: 0x06E1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO226; /* offset: 0x06E2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO227; /* offset: 0x06E3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO228; /* offset: 0x06E4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO229; /* offset: 0x06E5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO230; /* offset: 0x06E6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO231; /* offset: 0x06E7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO232; /* offset: 0x06E8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO233; /* offset: 0x06E9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO234; /* offset: 0x06EA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO235; /* offset: 0x06EB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO236; /* offset: 0x06EC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO237; /* offset: 0x06ED size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO238; /* offset: 0x06EE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO239; /* offset: 0x06EF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO240; /* offset: 0x06F0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO241; /* offset: 0x06F1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO242; /* offset: 0x06F2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO243; /* offset: 0x06F3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO244; /* offset: 0x06F4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO245; /* offset: 0x06F5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO246; /* offset: 0x06F6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO247; /* offset: 0x06F7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO248; /* offset: 0x06F8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO249; /* offset: 0x06F9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO250; /* offset: 0x06FA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO251; /* offset: 0x06FB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO252; /* offset: 0x06FC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO253; /* offset: 0x06FD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO254; /* offset: 0x06FE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO255; /* offset: 0x06FF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO256; /* offset: 0x0700 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO257; /* offset: 0x0701 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO258; /* offset: 0x0702 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO259; /* offset: 0x0703 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO260; /* offset: 0x0704 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO261; /* offset: 0x0705 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO262; /* offset: 0x0706 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO263; /* offset: 0x0707 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO264; /* offset: 0x0708 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO265; /* offset: 0x0709 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO266; /* offset: 0x070A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO267; /* offset: 0x070B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO268; /* offset: 0x070C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO269; /* offset: 0x070D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO270; /* offset: 0x070E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO271; /* offset: 0x070F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO272; /* offset: 0x0710 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO273; /* offset: 0x0711 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO274; /* offset: 0x0712 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO275; /* offset: 0x0713 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO276; /* offset: 0x0714 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO277; /* offset: 0x0715 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO278; /* offset: 0x0716 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO279; /* offset: 0x0717 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO280; /* offset: 0x0718 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO281; /* offset: 0x0719 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO282; /* offset: 0x071A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO283; /* offset: 0x071B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO284; /* offset: 0x071C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO285; /* offset: 0x071D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO286; /* offset: 0x071E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO287; /* offset: 0x071F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO288; /* offset: 0x0720 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO289; /* offset: 0x0721 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO290; /* offset: 0x0722 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO291; /* offset: 0x0723 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO292; /* offset: 0x0724 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO293; /* offset: 0x0725 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO294; /* offset: 0x0726 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO295; /* offset: 0x0727 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO296; /* offset: 0x0728 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO297; /* offset: 0x0729 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO298; /* offset: 0x072A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO299; /* offset: 0x072B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO300; /* offset: 0x072C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO301; /* offset: 0x072D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO302; /* offset: 0x072E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO303; /* offset: 0x072F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO304; /* offset: 0x0730 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO305; /* offset: 0x0731 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO306; /* offset: 0x0732 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO307; /* offset: 0x0733 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO308; /* offset: 0x0734 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO309; /* offset: 0x0735 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO310; /* offset: 0x0736 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO311; /* offset: 0x0737 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO312; /* offset: 0x0738 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO313; /* offset: 0x0739 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO314; /* offset: 0x073A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO315; /* offset: 0x073B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO316; /* offset: 0x073C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO317; /* offset: 0x073D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO318; /* offset: 0x073E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO319; /* offset: 0x073F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO320; /* offset: 0x0740 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO321; /* offset: 0x0741 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO322; /* offset: 0x0742 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO323; /* offset: 0x0743 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO324; /* offset: 0x0744 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO325; /* offset: 0x0745 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO326; /* offset: 0x0746 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO327; /* offset: 0x0747 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO328; /* offset: 0x0748 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO329; /* offset: 0x0749 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO330; /* offset: 0x074A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO331; /* offset: 0x074B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO332; /* offset: 0x074C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO333; /* offset: 0x074D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO334; /* offset: 0x074E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO335; /* offset: 0x074F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO336; /* offset: 0x0750 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO337; /* offset: 0x0751 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO338; /* offset: 0x0752 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO339; /* offset: 0x0753 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO340; /* offset: 0x0754 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO341; /* offset: 0x0755 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO342; /* offset: 0x0756 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO343; /* offset: 0x0757 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO344; /* offset: 0x0758 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO345; /* offset: 0x0759 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO346; /* offset: 0x075A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO347; /* offset: 0x075B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO348; /* offset: 0x075C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO349; /* offset: 0x075D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO350; /* offset: 0x075E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO351; /* offset: 0x075F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO352; /* offset: 0x0760 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO353; /* offset: 0x0761 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO354; /* offset: 0x0762 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO355; /* offset: 0x0763 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO356; /* offset: 0x0764 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO357; /* offset: 0x0765 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO358; /* offset: 0x0766 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO359; /* offset: 0x0767 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO360; /* offset: 0x0768 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO361; /* offset: 0x0769 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO362; /* offset: 0x076A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO363; /* offset: 0x076B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO364; /* offset: 0x076C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO365; /* offset: 0x076D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO366; /* offset: 0x076E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO367; /* offset: 0x076F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO368; /* offset: 0x0770 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO369; /* offset: 0x0771 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO370; /* offset: 0x0772 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO371; /* offset: 0x0773 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO372; /* offset: 0x0774 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO373; /* offset: 0x0775 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO374; /* offset: 0x0776 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO375; /* offset: 0x0777 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO376; /* offset: 0x0778 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO377; /* offset: 0x0779 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO378; /* offset: 0x077A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO379; /* offset: 0x077B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO380; /* offset: 0x077C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO381; /* offset: 0x077D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO382; /* offset: 0x077E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO383; /* offset: 0x077F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO384; /* offset: 0x0780 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO385; /* offset: 0x0781 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO386; /* offset: 0x0782 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO387; /* offset: 0x0783 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO388; /* offset: 0x0784 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO389; /* offset: 0x0785 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO390; /* offset: 0x0786 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO391; /* offset: 0x0787 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO392; /* offset: 0x0788 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO393; /* offset: 0x0789 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO394; /* offset: 0x078A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO395; /* offset: 0x078B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO396; /* offset: 0x078C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO397; /* offset: 0x078D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO398; /* offset: 0x078E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO399; /* offset: 0x078F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO400; /* offset: 0x0790 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO401; /* offset: 0x0791 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO402; /* offset: 0x0792 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO403; /* offset: 0x0793 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO404; /* offset: 0x0794 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO405; /* offset: 0x0795 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO406; /* offset: 0x0796 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO407; /* offset: 0x0797 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO408; /* offset: 0x0798 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO409; /* offset: 0x0799 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO410; /* offset: 0x079A size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO411; /* offset: 0x079B size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO412; /* offset: 0x079C size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO413; /* offset: 0x079D size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO414; /* offset: 0x079E size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO415; /* offset: 0x079F size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO416; /* offset: 0x07A0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO417; /* offset: 0x07A1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO418; /* offset: 0x07A2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO419; /* offset: 0x07A3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO420; /* offset: 0x07A4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO421; /* offset: 0x07A5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO422; /* offset: 0x07A6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO423; /* offset: 0x07A7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO424; /* offset: 0x07A8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO425; /* offset: 0x07A9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO426; /* offset: 0x07AA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO427; /* offset: 0x07AB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO428; /* offset: 0x07AC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO429; /* offset: 0x07AD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO430; /* offset: 0x07AE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO431; /* offset: 0x07AF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO432; /* offset: 0x07B0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO433; /* offset: 0x07B1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO434; /* offset: 0x07B2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO435; /* offset: 0x07B3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO436; /* offset: 0x07B4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO437; /* offset: 0x07B5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO438; /* offset: 0x07B6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO439; /* offset: 0x07B7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO440; /* offset: 0x07B8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO441; /* offset: 0x07B9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO442; /* offset: 0x07BA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO443; /* offset: 0x07BB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO444; /* offset: 0x07BC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO445; /* offset: 0x07BD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO446; /* offset: 0x07BE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO447; /* offset: 0x07BF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO448; /* offset: 0x07C0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO449; /* offset: 0x07C1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO450; /* offset: 0x07C2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO451; /* offset: 0x07C3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO452; /* offset: 0x07C4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO453; /* offset: 0x07C5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO454; /* offset: 0x07C6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO455; /* offset: 0x07C7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO456; /* offset: 0x07C8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO457; /* offset: 0x07C9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO458; /* offset: 0x07CA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO459; /* offset: 0x07CB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO460; /* offset: 0x07CC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO461; /* offset: 0x07CD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO462; /* offset: 0x07CE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO463; /* offset: 0x07CF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO464; /* offset: 0x07D0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO465; /* offset: 0x07D1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO466; /* offset: 0x07D2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO467; /* offset: 0x07D3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO468; /* offset: 0x07D4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO469; /* offset: 0x07D5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO470; /* offset: 0x07D6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO471; /* offset: 0x07D7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO472; /* offset: 0x07D8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO473; /* offset: 0x07D9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO474; /* offset: 0x07DA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO475; /* offset: 0x07DB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO476; /* offset: 0x07DC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO477; /* offset: 0x07DD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO478; /* offset: 0x07DE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO479; /* offset: 0x07DF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO480; /* offset: 0x07E0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO481; /* offset: 0x07E1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO482; /* offset: 0x07E2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO483; /* offset: 0x07E3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO484; /* offset: 0x07E4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO485; /* offset: 0x07E5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO486; /* offset: 0x07E6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO487; /* offset: 0x07E7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO488; /* offset: 0x07E8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO489; /* offset: 0x07E9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO490; /* offset: 0x07EA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO491; /* offset: 0x07EB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO492; /* offset: 0x07EC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO493; /* offset: 0x07ED size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO494; /* offset: 0x07EE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO495; /* offset: 0x07EF size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO496; /* offset: 0x07F0 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO497; /* offset: 0x07F1 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO498; /* offset: 0x07F2 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO499; /* offset: 0x07F3 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO500; /* offset: 0x07F4 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO501; /* offset: 0x07F5 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO502; /* offset: 0x07F6 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO503; /* offset: 0x07F7 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO504; /* offset: 0x07F8 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO505; /* offset: 0x07F9 size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO506; /* offset: 0x07FA size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO507; /* offset: 0x07FB size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO508; /* offset: 0x07FC size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO509; /* offset: 0x07FD size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO510; /* offset: 0x07FE size: 8 bit */
+ SIUL_GPDO_8B_tag GPDO511; /* offset: 0x07FF size: 8 bit */
+ };
+
+ };
+ union {
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800 (0x0004 x 128) */
+
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_8B_tag GPDI[512]; /* offset: 0x0800 (0x0001 x 512) */
+
+ struct {
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_32B_tag GPDI0_3; /* offset: 0x0800 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI4_7; /* offset: 0x0804 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI8_11; /* offset: 0x0808 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI12_15; /* offset: 0x080C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI16_19; /* offset: 0x0810 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI20_23; /* offset: 0x0814 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI24_27; /* offset: 0x0818 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI28_31; /* offset: 0x081C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI32_35; /* offset: 0x0820 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI36_39; /* offset: 0x0824 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI40_43; /* offset: 0x0828 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI44_47; /* offset: 0x082C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI48_51; /* offset: 0x0830 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI52_55; /* offset: 0x0834 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI56_59; /* offset: 0x0838 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI60_63; /* offset: 0x083C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI64_67; /* offset: 0x0840 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI68_71; /* offset: 0x0844 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI72_75; /* offset: 0x0848 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI76_79; /* offset: 0x084C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI80_83; /* offset: 0x0850 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI84_87; /* offset: 0x0854 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI88_91; /* offset: 0x0858 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI92_95; /* offset: 0x085C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI96_99; /* offset: 0x0860 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */
+ SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */
+ };
+
+ struct {
+ /* GPDI - GPIO Pad Data Input Register */
+ SIUL_GPDI_8B_tag GPDI0; /* offset: 0x0800 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI1; /* offset: 0x0801 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI2; /* offset: 0x0802 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI3; /* offset: 0x0803 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI4; /* offset: 0x0804 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI5; /* offset: 0x0805 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI6; /* offset: 0x0806 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI7; /* offset: 0x0807 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI8; /* offset: 0x0808 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI9; /* offset: 0x0809 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI10; /* offset: 0x080A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI11; /* offset: 0x080B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI12; /* offset: 0x080C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI13; /* offset: 0x080D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI14; /* offset: 0x080E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI15; /* offset: 0x080F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI16; /* offset: 0x0810 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI17; /* offset: 0x0811 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI18; /* offset: 0x0812 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI19; /* offset: 0x0813 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI20; /* offset: 0x0814 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI21; /* offset: 0x0815 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI22; /* offset: 0x0816 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI23; /* offset: 0x0817 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI24; /* offset: 0x0818 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI25; /* offset: 0x0819 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI26; /* offset: 0x081A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI27; /* offset: 0x081B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI28; /* offset: 0x081C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI29; /* offset: 0x081D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI30; /* offset: 0x081E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI31; /* offset: 0x081F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI32; /* offset: 0x0820 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI33; /* offset: 0x0821 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI34; /* offset: 0x0822 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI35; /* offset: 0x0823 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI36; /* offset: 0x0824 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI37; /* offset: 0x0825 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI38; /* offset: 0x0826 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI39; /* offset: 0x0827 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI40; /* offset: 0x0828 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI41; /* offset: 0x0829 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI42; /* offset: 0x082A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI43; /* offset: 0x082B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI44; /* offset: 0x082C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI45; /* offset: 0x082D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI46; /* offset: 0x082E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI47; /* offset: 0x082F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI48; /* offset: 0x0830 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI49; /* offset: 0x0831 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI50; /* offset: 0x0832 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI51; /* offset: 0x0833 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI52; /* offset: 0x0834 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI53; /* offset: 0x0835 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI54; /* offset: 0x0836 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI55; /* offset: 0x0837 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI56; /* offset: 0x0838 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI57; /* offset: 0x0839 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI58; /* offset: 0x083A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI59; /* offset: 0x083B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI60; /* offset: 0x083C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI61; /* offset: 0x083D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI62; /* offset: 0x083E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI63; /* offset: 0x083F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI64; /* offset: 0x0840 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI65; /* offset: 0x0841 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI66; /* offset: 0x0842 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI67; /* offset: 0x0843 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI68; /* offset: 0x0844 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI69; /* offset: 0x0845 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI70; /* offset: 0x0846 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI71; /* offset: 0x0847 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI72; /* offset: 0x0848 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI73; /* offset: 0x0849 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI74; /* offset: 0x084A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI75; /* offset: 0x084B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI76; /* offset: 0x084C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI77; /* offset: 0x084D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI78; /* offset: 0x084E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI79; /* offset: 0x084F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI80; /* offset: 0x0850 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI81; /* offset: 0x0851 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI82; /* offset: 0x0852 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI83; /* offset: 0x0853 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI84; /* offset: 0x0854 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI85; /* offset: 0x0855 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI86; /* offset: 0x0856 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI87; /* offset: 0x0857 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI88; /* offset: 0x0858 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI89; /* offset: 0x0859 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI90; /* offset: 0x085A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI91; /* offset: 0x085B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI92; /* offset: 0x085C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI93; /* offset: 0x085D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI94; /* offset: 0x085E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI95; /* offset: 0x085F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI96; /* offset: 0x0860 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI97; /* offset: 0x0861 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI98; /* offset: 0x0862 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI99; /* offset: 0x0863 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI100; /* offset: 0x0864 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI101; /* offset: 0x0865 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI102; /* offset: 0x0866 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI103; /* offset: 0x0867 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI104; /* offset: 0x0868 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI105; /* offset: 0x0869 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI106; /* offset: 0x086A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI107; /* offset: 0x086B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI108; /* offset: 0x086C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI109; /* offset: 0x086D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI110; /* offset: 0x086E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI111; /* offset: 0x086F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI112; /* offset: 0x0870 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI113; /* offset: 0x0871 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI114; /* offset: 0x0872 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI115; /* offset: 0x0873 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI116; /* offset: 0x0874 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI117; /* offset: 0x0875 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI118; /* offset: 0x0876 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI119; /* offset: 0x0877 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI120; /* offset: 0x0878 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI121; /* offset: 0x0879 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI122; /* offset: 0x087A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI123; /* offset: 0x087B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI124; /* offset: 0x087C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI125; /* offset: 0x087D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI126; /* offset: 0x087E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI127; /* offset: 0x087F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI128; /* offset: 0x0880 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI129; /* offset: 0x0881 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI130; /* offset: 0x0882 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI131; /* offset: 0x0883 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI132; /* offset: 0x0884 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI133; /* offset: 0x0885 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI134; /* offset: 0x0886 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI135; /* offset: 0x0887 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI136; /* offset: 0x0888 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI137; /* offset: 0x0889 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI138; /* offset: 0x088A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI139; /* offset: 0x088B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI140; /* offset: 0x088C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI141; /* offset: 0x088D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI142; /* offset: 0x088E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI143; /* offset: 0x088F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI144; /* offset: 0x0890 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI145; /* offset: 0x0891 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI146; /* offset: 0x0892 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI147; /* offset: 0x0893 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI148; /* offset: 0x0894 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI149; /* offset: 0x0895 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI150; /* offset: 0x0896 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI151; /* offset: 0x0897 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI152; /* offset: 0x0898 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI153; /* offset: 0x0899 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI154; /* offset: 0x089A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI155; /* offset: 0x089B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI156; /* offset: 0x089C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI157; /* offset: 0x089D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI158; /* offset: 0x089E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI159; /* offset: 0x089F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI160; /* offset: 0x08A0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI161; /* offset: 0x08A1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI162; /* offset: 0x08A2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI163; /* offset: 0x08A3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI164; /* offset: 0x08A4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI165; /* offset: 0x08A5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI166; /* offset: 0x08A6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI167; /* offset: 0x08A7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI168; /* offset: 0x08A8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI169; /* offset: 0x08A9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI170; /* offset: 0x08AA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI171; /* offset: 0x08AB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI172; /* offset: 0x08AC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI173; /* offset: 0x08AD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI174; /* offset: 0x08AE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI175; /* offset: 0x08AF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI176; /* offset: 0x08B0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI177; /* offset: 0x08B1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI178; /* offset: 0x08B2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI179; /* offset: 0x08B3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI180; /* offset: 0x08B4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI181; /* offset: 0x08B5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI182; /* offset: 0x08B6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI183; /* offset: 0x08B7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI184; /* offset: 0x08B8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI185; /* offset: 0x08B9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI186; /* offset: 0x08BA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI187; /* offset: 0x08BB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI188; /* offset: 0x08BC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI189; /* offset: 0x08BD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI190; /* offset: 0x08BE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI191; /* offset: 0x08BF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI192; /* offset: 0x08C0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI193; /* offset: 0x08C1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI194; /* offset: 0x08C2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI195; /* offset: 0x08C3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI196; /* offset: 0x08C4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI197; /* offset: 0x08C5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI198; /* offset: 0x08C6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI199; /* offset: 0x08C7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI200; /* offset: 0x08C8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI201; /* offset: 0x08C9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI202; /* offset: 0x08CA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI203; /* offset: 0x08CB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI204; /* offset: 0x08CC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI205; /* offset: 0x08CD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI206; /* offset: 0x08CE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI207; /* offset: 0x08CF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI208; /* offset: 0x08D0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI209; /* offset: 0x08D1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI210; /* offset: 0x08D2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI211; /* offset: 0x08D3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI212; /* offset: 0x08D4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI213; /* offset: 0x08D5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI214; /* offset: 0x08D6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI215; /* offset: 0x08D7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI216; /* offset: 0x08D8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI217; /* offset: 0x08D9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI218; /* offset: 0x08DA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI219; /* offset: 0x08DB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI220; /* offset: 0x08DC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI221; /* offset: 0x08DD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI222; /* offset: 0x08DE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI223; /* offset: 0x08DF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI224; /* offset: 0x08E0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI225; /* offset: 0x08E1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI226; /* offset: 0x08E2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI227; /* offset: 0x08E3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI228; /* offset: 0x08E4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI229; /* offset: 0x08E5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI230; /* offset: 0x08E6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI231; /* offset: 0x08E7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI232; /* offset: 0x08E8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI233; /* offset: 0x08E9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI234; /* offset: 0x08EA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI235; /* offset: 0x08EB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI236; /* offset: 0x08EC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI237; /* offset: 0x08ED size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI238; /* offset: 0x08EE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI239; /* offset: 0x08EF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI240; /* offset: 0x08F0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI241; /* offset: 0x08F1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI242; /* offset: 0x08F2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI243; /* offset: 0x08F3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI244; /* offset: 0x08F4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI245; /* offset: 0x08F5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI246; /* offset: 0x08F6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI247; /* offset: 0x08F7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI248; /* offset: 0x08F8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI249; /* offset: 0x08F9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI250; /* offset: 0x08FA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI251; /* offset: 0x08FB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI252; /* offset: 0x08FC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI253; /* offset: 0x08FD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI254; /* offset: 0x08FE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI255; /* offset: 0x08FF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI256; /* offset: 0x0900 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI257; /* offset: 0x0901 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI258; /* offset: 0x0902 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI259; /* offset: 0x0903 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI260; /* offset: 0x0904 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI261; /* offset: 0x0905 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI262; /* offset: 0x0906 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI263; /* offset: 0x0907 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI264; /* offset: 0x0908 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI265; /* offset: 0x0909 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI266; /* offset: 0x090A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI267; /* offset: 0x090B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI268; /* offset: 0x090C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI269; /* offset: 0x090D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI270; /* offset: 0x090E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI271; /* offset: 0x090F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI272; /* offset: 0x0910 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI273; /* offset: 0x0911 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI274; /* offset: 0x0912 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI275; /* offset: 0x0913 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI276; /* offset: 0x0914 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI277; /* offset: 0x0915 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI278; /* offset: 0x0916 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI279; /* offset: 0x0917 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI280; /* offset: 0x0918 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI281; /* offset: 0x0919 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI282; /* offset: 0x091A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI283; /* offset: 0x091B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI284; /* offset: 0x091C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI285; /* offset: 0x091D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI286; /* offset: 0x091E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI287; /* offset: 0x091F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI288; /* offset: 0x0920 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI289; /* offset: 0x0921 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI290; /* offset: 0x0922 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI291; /* offset: 0x0923 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI292; /* offset: 0x0924 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI293; /* offset: 0x0925 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI294; /* offset: 0x0926 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI295; /* offset: 0x0927 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI296; /* offset: 0x0928 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI297; /* offset: 0x0929 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI298; /* offset: 0x092A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI299; /* offset: 0x092B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI300; /* offset: 0x092C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI301; /* offset: 0x092D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI302; /* offset: 0x092E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI303; /* offset: 0x092F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI304; /* offset: 0x0930 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI305; /* offset: 0x0931 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI306; /* offset: 0x0932 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI307; /* offset: 0x0933 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI308; /* offset: 0x0934 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI309; /* offset: 0x0935 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI310; /* offset: 0x0936 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI311; /* offset: 0x0937 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI312; /* offset: 0x0938 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI313; /* offset: 0x0939 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI314; /* offset: 0x093A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI315; /* offset: 0x093B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI316; /* offset: 0x093C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI317; /* offset: 0x093D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI318; /* offset: 0x093E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI319; /* offset: 0x093F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI320; /* offset: 0x0940 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI321; /* offset: 0x0941 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI322; /* offset: 0x0942 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI323; /* offset: 0x0943 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI324; /* offset: 0x0944 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI325; /* offset: 0x0945 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI326; /* offset: 0x0946 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI327; /* offset: 0x0947 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI328; /* offset: 0x0948 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI329; /* offset: 0x0949 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI330; /* offset: 0x094A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI331; /* offset: 0x094B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI332; /* offset: 0x094C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI333; /* offset: 0x094D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI334; /* offset: 0x094E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI335; /* offset: 0x094F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI336; /* offset: 0x0950 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI337; /* offset: 0x0951 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI338; /* offset: 0x0952 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI339; /* offset: 0x0953 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI340; /* offset: 0x0954 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI341; /* offset: 0x0955 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI342; /* offset: 0x0956 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI343; /* offset: 0x0957 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI344; /* offset: 0x0958 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI345; /* offset: 0x0959 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI346; /* offset: 0x095A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI347; /* offset: 0x095B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI348; /* offset: 0x095C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI349; /* offset: 0x095D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI350; /* offset: 0x095E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI351; /* offset: 0x095F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI352; /* offset: 0x0960 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI353; /* offset: 0x0961 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI354; /* offset: 0x0962 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI355; /* offset: 0x0963 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI356; /* offset: 0x0964 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI357; /* offset: 0x0965 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI358; /* offset: 0x0966 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI359; /* offset: 0x0967 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI360; /* offset: 0x0968 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI361; /* offset: 0x0969 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI362; /* offset: 0x096A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI363; /* offset: 0x096B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI364; /* offset: 0x096C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI365; /* offset: 0x096D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI366; /* offset: 0x096E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI367; /* offset: 0x096F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI368; /* offset: 0x0970 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI369; /* offset: 0x0971 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI370; /* offset: 0x0972 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI371; /* offset: 0x0973 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI372; /* offset: 0x0974 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI373; /* offset: 0x0975 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI374; /* offset: 0x0976 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI375; /* offset: 0x0977 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI376; /* offset: 0x0978 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI377; /* offset: 0x0979 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI378; /* offset: 0x097A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI379; /* offset: 0x097B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI380; /* offset: 0x097C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI381; /* offset: 0x097D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI382; /* offset: 0x097E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI383; /* offset: 0x097F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI384; /* offset: 0x0980 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI385; /* offset: 0x0981 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI386; /* offset: 0x0982 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI387; /* offset: 0x0983 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI388; /* offset: 0x0984 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI389; /* offset: 0x0985 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI390; /* offset: 0x0986 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI391; /* offset: 0x0987 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI392; /* offset: 0x0988 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI393; /* offset: 0x0989 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI394; /* offset: 0x098A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI395; /* offset: 0x098B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI396; /* offset: 0x098C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI397; /* offset: 0x098D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI398; /* offset: 0x098E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI399; /* offset: 0x098F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI400; /* offset: 0x0990 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI401; /* offset: 0x0991 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI402; /* offset: 0x0992 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI403; /* offset: 0x0993 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI404; /* offset: 0x0994 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI405; /* offset: 0x0995 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI406; /* offset: 0x0996 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI407; /* offset: 0x0997 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI408; /* offset: 0x0998 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI409; /* offset: 0x0999 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI410; /* offset: 0x099A size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI411; /* offset: 0x099B size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI412; /* offset: 0x099C size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI413; /* offset: 0x099D size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI414; /* offset: 0x099E size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI415; /* offset: 0x099F size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI416; /* offset: 0x09A0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI417; /* offset: 0x09A1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI418; /* offset: 0x09A2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI419; /* offset: 0x09A3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI420; /* offset: 0x09A4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI421; /* offset: 0x09A5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI422; /* offset: 0x09A6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI423; /* offset: 0x09A7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI424; /* offset: 0x09A8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI425; /* offset: 0x09A9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI426; /* offset: 0x09AA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI427; /* offset: 0x09AB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI428; /* offset: 0x09AC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI429; /* offset: 0x09AD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI430; /* offset: 0x09AE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI431; /* offset: 0x09AF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI432; /* offset: 0x09B0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI433; /* offset: 0x09B1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI434; /* offset: 0x09B2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI435; /* offset: 0x09B3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI436; /* offset: 0x09B4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI437; /* offset: 0x09B5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI438; /* offset: 0x09B6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI439; /* offset: 0x09B7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI440; /* offset: 0x09B8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI441; /* offset: 0x09B9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI442; /* offset: 0x09BA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI443; /* offset: 0x09BB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI444; /* offset: 0x09BC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI445; /* offset: 0x09BD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI446; /* offset: 0x09BE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI447; /* offset: 0x09BF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI448; /* offset: 0x09C0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI449; /* offset: 0x09C1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI450; /* offset: 0x09C2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI451; /* offset: 0x09C3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI452; /* offset: 0x09C4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI453; /* offset: 0x09C5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI454; /* offset: 0x09C6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI455; /* offset: 0x09C7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI456; /* offset: 0x09C8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI457; /* offset: 0x09C9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI458; /* offset: 0x09CA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI459; /* offset: 0x09CB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI460; /* offset: 0x09CC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI461; /* offset: 0x09CD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI462; /* offset: 0x09CE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI463; /* offset: 0x09CF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI464; /* offset: 0x09D0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI465; /* offset: 0x09D1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI466; /* offset: 0x09D2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI467; /* offset: 0x09D3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI468; /* offset: 0x09D4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI469; /* offset: 0x09D5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI470; /* offset: 0x09D6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI471; /* offset: 0x09D7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI472; /* offset: 0x09D8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI473; /* offset: 0x09D9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI474; /* offset: 0x09DA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI475; /* offset: 0x09DB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI476; /* offset: 0x09DC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI477; /* offset: 0x09DD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI478; /* offset: 0x09DE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI479; /* offset: 0x09DF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI480; /* offset: 0x09E0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI481; /* offset: 0x09E1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI482; /* offset: 0x09E2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI483; /* offset: 0x09E3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI484; /* offset: 0x09E4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI485; /* offset: 0x09E5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI486; /* offset: 0x09E6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI487; /* offset: 0x09E7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI488; /* offset: 0x09E8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI489; /* offset: 0x09E9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI490; /* offset: 0x09EA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI491; /* offset: 0x09EB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI492; /* offset: 0x09EC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI493; /* offset: 0x09ED size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI494; /* offset: 0x09EE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI495; /* offset: 0x09EF size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI496; /* offset: 0x09F0 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI497; /* offset: 0x09F1 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI498; /* offset: 0x09F2 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI499; /* offset: 0x09F3 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI500; /* offset: 0x09F4 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI501; /* offset: 0x09F5 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI502; /* offset: 0x09F6 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI503; /* offset: 0x09F7 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI504; /* offset: 0x09F8 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI505; /* offset: 0x09F9 size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI506; /* offset: 0x09FA size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI507; /* offset: 0x09FB size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI508; /* offset: 0x09FC size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI509; /* offset: 0x09FD size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI510; /* offset: 0x09FE size: 8 bit */
+ SIUL_GPDI_8B_tag GPDI511; /* offset: 0x09FF size: 8 bit */
+ };
+
+ };
+ int8_t SIUL_reserved_0A00_C[512];
+ union {
+ /* PGPDO - Parallel GPIO Pad Data Out Register */
+ SIUL_PGPDO_16B_tag PGPDO[32]; /* offset: 0x0C00 (0x0002 x 32) */
+
+ struct {
+ /* PGPDO - Parallel GPIO Pad Data Out Register */
+ SIUL_PGPDO_16B_tag PGPDO0; /* offset: 0x0C00 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO1; /* offset: 0x0C02 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO2; /* offset: 0x0C04 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO3; /* offset: 0x0C06 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO4; /* offset: 0x0C08 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO5; /* offset: 0x0C0A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO6; /* offset: 0x0C0C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO7; /* offset: 0x0C0E size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO8; /* offset: 0x0C10 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO9; /* offset: 0x0C12 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO10; /* offset: 0x0C14 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO11; /* offset: 0x0C16 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO12; /* offset: 0x0C18 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO13; /* offset: 0x0C1A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO14; /* offset: 0x0C1C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO15; /* offset: 0x0C1E size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO16; /* offset: 0x0C20 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO17; /* offset: 0x0C22 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO18; /* offset: 0x0C24 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO19; /* offset: 0x0C26 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO20; /* offset: 0x0C28 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO21; /* offset: 0x0C2A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO22; /* offset: 0x0C2C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO23; /* offset: 0x0C2E size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO24; /* offset: 0x0C30 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO25; /* offset: 0x0C32 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO26; /* offset: 0x0C34 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO27; /* offset: 0x0C36 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO28; /* offset: 0x0C38 size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO29; /* offset: 0x0C3A size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO30; /* offset: 0x0C3C size: 16 bit */
+ SIUL_PGPDO_16B_tag PGPDO31; /* offset: 0x0C3E size: 16 bit */
+ };
+
+ };
+ union {
+ /* PGPDI - Parallel GPIO Pad Data In Register */
+ SIUL_PGPDI_16B_tag PGPDI[32]; /* offset: 0x0C40 (0x0002 x 32) */
+
+ struct {
+ /* PGPDI - Parallel GPIO Pad Data In Register */
+ SIUL_PGPDI_16B_tag PGPDI0; /* offset: 0x0C40 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI1; /* offset: 0x0C42 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI2; /* offset: 0x0C44 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI3; /* offset: 0x0C46 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI4; /* offset: 0x0C48 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI5; /* offset: 0x0C4A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI6; /* offset: 0x0C4C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI7; /* offset: 0x0C4E size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI8; /* offset: 0x0C50 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI9; /* offset: 0x0C52 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI10; /* offset: 0x0C54 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI11; /* offset: 0x0C56 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI12; /* offset: 0x0C58 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI13; /* offset: 0x0C5A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI14; /* offset: 0x0C5C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI15; /* offset: 0x0C5E size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI16; /* offset: 0x0C60 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI17; /* offset: 0x0C62 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI18; /* offset: 0x0C64 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI19; /* offset: 0x0C66 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI20; /* offset: 0x0C68 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI21; /* offset: 0x0C6A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI22; /* offset: 0x0C6C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI23; /* offset: 0x0C6E size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI24; /* offset: 0x0C70 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI25; /* offset: 0x0C72 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI26; /* offset: 0x0C74 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI27; /* offset: 0x0C76 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI28; /* offset: 0x0C78 size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI29; /* offset: 0x0C7A size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI30; /* offset: 0x0C7C size: 16 bit */
+ SIUL_PGPDI_16B_tag PGPDI31; /* offset: 0x0C7E size: 16 bit */
+ };
+
+ };
+ union {
+ /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
+ SIUL_MPGPDO_32B_tag MPGPDO[32]; /* offset: 0x0C80 (0x0004 x 32) */
+
+ struct {
+ /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
+ SIUL_MPGPDO_32B_tag MPGPDO0; /* offset: 0x0C80 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO1; /* offset: 0x0C84 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO2; /* offset: 0x0C88 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO3; /* offset: 0x0C8C size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO4; /* offset: 0x0C90 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO5; /* offset: 0x0C94 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO6; /* offset: 0x0C98 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO7; /* offset: 0x0C9C size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO8; /* offset: 0x0CA0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO9; /* offset: 0x0CA4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO10; /* offset: 0x0CA8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO11; /* offset: 0x0CAC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO12; /* offset: 0x0CB0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO13; /* offset: 0x0CB4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO14; /* offset: 0x0CB8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO15; /* offset: 0x0CBC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO16; /* offset: 0x0CC0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO17; /* offset: 0x0CC4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO18; /* offset: 0x0CC8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO19; /* offset: 0x0CCC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO20; /* offset: 0x0CD0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO21; /* offset: 0x0CD4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO22; /* offset: 0x0CD8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO23; /* offset: 0x0CDC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO24; /* offset: 0x0CE0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO25; /* offset: 0x0CE4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO26; /* offset: 0x0CE8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO27; /* offset: 0x0CEC size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO28; /* offset: 0x0CF0 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO29; /* offset: 0x0CF4 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO30; /* offset: 0x0CF8 size: 32 bit */
+ SIUL_MPGPDO_32B_tag MPGPDO31; /* offset: 0x0CFC size: 32 bit */
+ };
+
+ };
+ int8_t SIUL_reserved_0D00_C[768];
+ union {
+ /* IFMC - Interrupt Filter Maximum Counter Register */
+ SIUL_IFMC_32B_tag IFMC[32]; /* offset: 0x1000 (0x0004 x 32) */
+
+ struct {
+ /* IFMC - Interrupt Filter Maximum Counter Register */
+ SIUL_IFMC_32B_tag IFMC0; /* offset: 0x1000 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC1; /* offset: 0x1004 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC2; /* offset: 0x1008 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC3; /* offset: 0x100C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC4; /* offset: 0x1010 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC5; /* offset: 0x1014 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC6; /* offset: 0x1018 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC7; /* offset: 0x101C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC8; /* offset: 0x1020 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC9; /* offset: 0x1024 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC10; /* offset: 0x1028 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC11; /* offset: 0x102C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC12; /* offset: 0x1030 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC13; /* offset: 0x1034 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC14; /* offset: 0x1038 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC15; /* offset: 0x103C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC16; /* offset: 0x1040 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC17; /* offset: 0x1044 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC18; /* offset: 0x1048 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC19; /* offset: 0x104C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC20; /* offset: 0x1050 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC21; /* offset: 0x1054 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC22; /* offset: 0x1058 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC23; /* offset: 0x105C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC24; /* offset: 0x1060 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC25; /* offset: 0x1064 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC26; /* offset: 0x1068 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC27; /* offset: 0x106C size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC28; /* offset: 0x1070 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC29; /* offset: 0x1074 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC30; /* offset: 0x1078 size: 32 bit */
+ SIUL_IFMC_32B_tag IFMC31; /* offset: 0x107C size: 32 bit */
+ };
+
+ };
+ /* IFCPR - Inerrupt Filter Clock Prescaler Register */
+ SIUL_IFCPR_32B_tag IFCPR; /* offset: 0x1080 size: 32 bit */
+ } SIUL_tag;
+
+
+#define SIUL (*(volatile SIUL_tag *) 0xC3F90000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: WKPU */
+/* */
+/****************************************************************/
+
+ typedef union { /* WKPU_NSR - NMI Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t NIF0:1; /* NMI Status Flag 0 */
+ vuint32_t NOVF0:1; /* NMI Overrun Status Flag 0 */
+ vuint32_t:6;
+ vuint32_t NIF1:1; /* NMI Status Flag 1 */
+ vuint32_t NOVF1:1; /* NMI Overrun Status Flag 1 */
+ vuint32_t:6;
+ vuint32_t NIF2:1; /* NMI Status Flag 2 */
+ vuint32_t NOVF2:1; /* NMI Overrun Status Flag 2 */
+ vuint32_t:6;
+ vuint32_t NIF3:1; /* NMI Status Flag 3 */
+ vuint32_t NOVF3:1; /* NMI Overrun Status Flag 3 */
+ vuint32_t:6;
+ } B;
+ } WKPU_NSR_32B_tag;
+
+ typedef union { /* WKPU_NCR - NMI Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t NLOCK0:1; /* NMI Configuration Lock Register 0 */
+ vuint32_t NDSS0:2; /* NMI Desination Source Select 0 */
+ vuint32_t NWRE0:1; /* NMI Wakeup Request Enable 0 */
+ vuint32_t:1;
+ vuint32_t NREE0:1; /* NMI Rising Edge Events Enable 0 */
+ vuint32_t NFEE0:1; /* NMI Falling Edge Events Enable 0 */
+ vuint32_t NFE0:1; /* NMI Filter Enable 0 */
+ vuint32_t NLOCK1:1; /* NMI Configuration Lock Register 1 */
+ vuint32_t NDSS1:2; /* NMI Desination Source Select 1 */
+ vuint32_t NWRE1:1; /* NMI Wakeup Request Enable 1 */
+ vuint32_t:1;
+ vuint32_t NREE1:1; /* NMI Rising Edge Events Enable 1 */
+ vuint32_t NFEE1:1; /* NMI Falling Edge Events Enable 1 */
+ vuint32_t NFE1:1; /* NMI Filter Enable 1 */
+ vuint32_t NLOCK2:1; /* NMI Configuration Lock Register 2 */
+ vuint32_t NDSS2:2; /* NMI Desination Source Select 2 */
+ vuint32_t NWRE2:1; /* NMI Wakeup Request Enable 2 */
+ vuint32_t:1;
+ vuint32_t NREE2:1; /* NMI Rising Edge Events Enable 2 */
+ vuint32_t NFEE2:1; /* NMI Falling Edge Events Enable 2 */
+ vuint32_t NFE2:1; /* NMI Filter Enable 2 */
+ vuint32_t NLOCK3:1; /* NMI Configuration Lock Register 3 */
+ vuint32_t NDSS3:2; /* NMI Desination Source Select 3 */
+ vuint32_t NWRE3:1; /* NMI Wakeup Request Enable 3 */
+ vuint32_t:1;
+ vuint32_t NREE3:1; /* NMI Rising Edge Events Enable 3 */
+ vuint32_t NFEE3:1; /* NMI Falling Edge Events Enable 3 */
+ vuint32_t NFE3:1; /* NMI Filter Enable 3 */
+ } B;
+ } WKPU_NCR_32B_tag;
+
+ typedef union { /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIF:32; /* External Wakeup/Interrupt Status Flag */
+ } B;
+ } WKPU_WISR_32B_tag;
+
+ typedef union { /* WKPU_IRER - Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EIRE:32; /* Enable External Interrupt Requests */
+ } B;
+ } WKPU_IRER_32B_tag;
+
+ typedef union { /* WKPU_WRER - Wakeup Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t WRE:32; /* Enable Wakeup requests to the mode entry module */
+ } B;
+ } WKPU_WRER_32B_tag;
+
+ typedef union { /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IREE:32; /* Enable rising-edge events to cause EIF[x] to be set */
+ } B;
+ } WKPU_WIREER_32B_tag;
+
+ typedef union { /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFEE:32; /* Enable Falling-edge events to cause EIF[x] to be set */
+ } B;
+ } WKPU_WIFEER_32B_tag;
+
+ typedef union { /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IFE:32; /* Enable Digital glitch filter on the interrupt pad input */
+ } B;
+ } WKPU_WIFER_32B_tag;
+
+ typedef union { /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t IPUE:32; /* Enable a pullup on the interrupt pad input */
+ } B;
+ } WKPU_WIPUER_32B_tag;
+
+
+
+ typedef struct WKPU_struct_tag { /* start of WKPU_tag */
+ /* WKPU_NSR - NMI Status Flag Register */
+ WKPU_NSR_32B_tag NSR; /* offset: 0x0000 size: 32 bit */
+ int8_t WKPU_reserved_0004[4];
+ /* WKPU_NCR - NMI Configuration Register */
+ WKPU_NCR_32B_tag NCR; /* offset: 0x0008 size: 32 bit */
+ int8_t WKPU_reserved_000C[8];
+ /* WKPU_WISR - Wakeup/Interrupt Status Flag Register */
+ WKPU_WISR_32B_tag WISR; /* offset: 0x0014 size: 32 bit */
+ /* WKPU_IRER - Interrupt Request Enable Register */
+ WKPU_IRER_32B_tag IRER; /* offset: 0x0018 size: 32 bit */
+ /* WKPU_WRER - Wakeup Request Enable Register */
+ WKPU_WRER_32B_tag WRER; /* offset: 0x001C size: 32 bit */
+ int8_t WKPU_reserved_0020[8];
+ /* WKPU_WIREER - Wakeup/Interrupt Rising-Edge Event Enable Register */
+ WKPU_WIREER_32B_tag WIREER; /* offset: 0x0028 size: 32 bit */
+ /* WKPU_WIFEER - Wakeup/Interrupt Falling-Edge Event Enable Register */
+ WKPU_WIFEER_32B_tag WIFEER; /* offset: 0x002C size: 32 bit */
+ /* WKPU_WIFER - Wakeup/Interrupt Filter Enable Register */
+ WKPU_WIFER_32B_tag WIFER; /* offset: 0x0030 size: 32 bit */
+ /* WKPU_WIPUER - Wakeup/Interrupt Pullup Enable Register */
+ WKPU_WIPUER_32B_tag WIPUER; /* offset: 0x0034 size: 32 bit */
+ } WKPU_tag;
+
+
+#define WKPU (*(volatile WKPU_tag *) 0xC3F94000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SSCM */
+/* */
+/****************************************************************/
+
+ typedef union { /* SSCM_STATUS - System Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t LSM:1; /* Lock Step Mode */
+ vuint16_t:2;
+ vuint16_t NXEN1:1; /* Processor 1 Nexus enabled */
+ vuint16_t NXEN:1; /* Processor 0 Nexus enabled */
+ vuint16_t PUB:1; /* Public Serial Access Status */
+ vuint16_t SEC:1; /* Security Status */
+ vuint16_t:1;
+ vuint16_t BMODE:3; /* Device Boot Mode */
+#ifndef USE_FIELD_ALIASES_SSCM
+ vuint16_t VLE:1; /* Variable Length Instruction Mode */
+#else
+ vuint16_t DMID:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t ABD:1; /* Autobaud detection */
+ vuint16_t:3;
+ } B;
+ } SSCM_STATUS_16B_tag;
+
+ typedef union { /* SSCM_MEMCONFIG - System Memory Configuration Register */
+ vuint16_t R;
+ struct {
+ vuint16_t JPIN:10; /* JTAG Part ID Number */
+ vuint16_t IVLD:1; /* Instruction Flash Valid */
+ vuint16_t MREV:4; /* Minor Mask Revision */
+ vuint16_t DVLD:1; /* Data Flash Valid */
+ } B;
+ } SSCM_MEMCONFIG_16B_tag;
+
+ typedef union { /* SSCM_ERROR - Error Configuration */
+ vuint16_t R;
+ struct {
+ vuint16_t:14;
+ vuint16_t PAE:1; /* Peripheral Bus Abort Enable */
+ vuint16_t RAE:1; /* Register Bus Abort Enable */
+ } B;
+ } SSCM_ERROR_16B_tag;
+
+ typedef union { /* SSCM_DEBUGPORT - Debug Status Port Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:13;
+ vuint16_t DEBUG_MODE:3; /* Debug Status Port Mode */
+ } B;
+ } SSCM_DEBUGPORT_16B_tag;
+
+ typedef union { /* SSCM_PWCMPH - Password Comparison Register High */
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_HI:32; /* Password High */
+ } B;
+ } SSCM_PWCMPH_32B_tag;
+
+ typedef union { /* SSCM_PWCMPL - Password Comparison Register Low */
+ vuint32_t R;
+ struct {
+ vuint32_t PWD_LO:32; /* Password Low */
+ } B;
+ } SSCM_PWCMPL_32B_tag;
+
+ typedef union { /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
+ vuint32_t R;
+ struct {
+ vuint32_t P2BOOT:30; /* boot location 2nd processor */
+ vuint32_t DVLE:1; /* VLE mode for 2nd processor */
+ vuint32_t:1;
+ } B;
+ } SSCM_DPMBOOT_32B_tag;
+
+ typedef union { /* SSCM_DPMKEY - Boot Key Register */
+ vuint32_t R;
+ struct {
+ vuint32_t KEY:32; /* Boot Control Key */
+ } B;
+ } SSCM_DPMKEY_32B_tag;
+
+ typedef union { /* SSCM_UOPS - User Option Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t UOPT:32; /* User Option Bits */
+ } B;
+ } SSCM_UOPS_32B_tag;
+
+ typedef union { /* SSCM_SCTR - SSCM Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t TFE:1; /* Test Flash Enable */
+ vuint32_t DSL:1; /* Disable Software-Controlled MBIST */
+ vuint32_t DSM:1; /* Disable Software-Controlled LBIST */
+ } B;
+ } SSCM_SCTR_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t TINFO0:32; /* General purpose TestFlash word 0 */
+ } B;
+ } SSCM_TF_INFO0_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t TINFO1:32; /* General purpose TestFlash word 1 */
+ } B;
+ } SSCM_TF_INFO1_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t TINFO2:32; /* General purpose TestFlash word 2 */
+ } B;
+ } SSCM_TF_INFO2_32B_tag;
+
+ typedef union { /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t TINFO3:32; /* General purpose TestFlash word */
+ } B;
+ } SSCM_TF_INFO3_32B_tag;
+
+
+
+ typedef struct SSCM_struct_tag { /* start of SSCM_tag */
+ /* SSCM_STATUS - System Status Register */
+ SSCM_STATUS_16B_tag STATUS; /* offset: 0x0000 size: 16 bit */
+ /* SSCM_MEMCONFIG - System Memory Configuration Register */
+ SSCM_MEMCONFIG_16B_tag MEMCONFIG; /* offset: 0x0002 size: 16 bit */
+ int8_t SSCM_reserved_0004[2];
+ /* SSCM_ERROR - Error Configuration */
+ SSCM_ERROR_16B_tag ERROR; /* offset: 0x0006 size: 16 bit */
+ /* SSCM_DEBUGPORT - Debug Status Port Register */
+ SSCM_DEBUGPORT_16B_tag DEBUGPORT; /* offset: 0x0008 size: 16 bit */
+ int8_t SSCM_reserved_000A[2];
+ /* SSCM_PWCMPH - Password Comparison Register High */
+ SSCM_PWCMPH_32B_tag PWCMPH; /* offset: 0x000C size: 32 bit */
+ /* SSCM_PWCMPL - Password Comparison Register Low */
+ SSCM_PWCMPL_32B_tag PWCMPL; /* offset: 0x0010 size: 32 bit */
+ int8_t SSCM_reserved_0014[4];
+ /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
+ SSCM_DPMBOOT_32B_tag DPMBOOT; /* offset: 0x0018 size: 32 bit */
+ /* SSCM_DPMKEY - Boot Key Register */
+ SSCM_DPMKEY_32B_tag DPMKEY; /* offset: 0x001C size: 32 bit */
+ /* SSCM_UOPS - User Option Status Register */
+ SSCM_UOPS_32B_tag UOPS; /* offset: 0x0020 size: 32 bit */
+ /* SSCM_SCTR - SSCM Control Register */
+ SSCM_SCTR_32B_tag SCTR; /* offset: 0x0024 size: 32 bit */
+ /* SSCM_TF_INFO0 - TestFlash Information Register 0 */
+ SSCM_TF_INFO0_32B_tag TF_INFO0; /* offset: 0x0028 size: 32 bit */
+ /* SSCM_TF_INFO1 - TestFlash Information Register 1 */
+ SSCM_TF_INFO1_32B_tag TF_INFO1; /* offset: 0x002C size: 32 bit */
+ /* SSCM_TF_INFO2 - TestFlash Information Register 2 */
+ SSCM_TF_INFO2_32B_tag TF_INFO2; /* offset: 0x0030 size: 32 bit */
+ /* SSCM_TF_INFO3 - TestFlash Information Register 3 */
+ SSCM_TF_INFO3_32B_tag TF_INFO3; /* offset: 0x0034 size: 32 bit */
+ } SSCM_tag;
+
+
+#define SSCM (*(volatile SSCM_tag *) 0xC3FD8000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: ME */
+/* */
+/****************************************************************/
+
+ typedef union { /* ME_GS - Global Status Register */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t S_CURRENT_MODE:4; /* Current device mode status */
+#else
+ vuint32_t S_CURRENTMODE:4; /* deprecated name - please avoid */
+#endif
+ vuint32_t S_MTRANS:1; /* Mode transition status */
+ vuint32_t:3;
+ vuint32_t S_PDO:1; /* Output power-down status */
+ vuint32_t:2;
+ vuint32_t S_MVR:1; /* Main voltage regulator status */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t S_FLA:2; /* Flash availability status */
+#else
+ vuint32_t S_CFLA:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+ vuint32_t S_PLL1:1; /* Secondary PLL status */
+ vuint32_t S_PLL0:1; /* System PLL status */
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t S_XOSC:1; /* System crystal oscillator status */
+#else
+ vuint32_t S_OSC:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t S_IRCOSC:1; /* System RC oscillator status */
+#else
+ vuint32_t S_RC:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t S_SYSCLK:4; /* System clock switch status */
+ } B;
+ } ME_GS_32B_tag;
+
+ typedef union { /* ME_MCTL - Mode Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t TARGET_MODE:4; /* Target device mode */
+ vuint32_t:12;
+ vuint32_t KEY:16; /* Control key */
+ } B;
+ } ME_MCTL_32B_tag;
+
+ typedef union { /* ME_MEN - Mode Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:21;
+ vuint32_t STOP0:1; /* STOP0 mode enable */
+ vuint32_t:1;
+ vuint32_t HALT0:1; /* HALT0 mode enable */
+ vuint32_t RUN3:1; /* RUN3 mode enable */
+ vuint32_t RUN2:1; /* RUN2 mode enable */
+ vuint32_t RUN1:1; /* RUN1 mode enable */
+ vuint32_t RUN0:1; /* RUN0 mode enable */
+ vuint32_t DRUN:1; /* DRUN mode enable */
+ vuint32_t SAFE:1; /* SAFE mode enable */
+ vuint32_t:1;
+ vuint32_t RESET:1; /* RESET mode enable */
+ } B;
+ } ME_MEN_32B_tag;
+
+ typedef union { /* ME_IS - Interrupt Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t I_ICONF:1; /* Invalid mode config interrupt */
+#else
+ vuint32_t I_CONF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t I_IMODE:1; /* Invalid mode interrupt */
+#else
+ vuint32_t I_MODE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t I_SAFE:1; /* SAFE mode interrupt */
+#else
+ vuint32_t I_AFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t I_MTC:1; /* Mode transition complete interrupt */
+#else
+ vuint32_t I_TC:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ME_IS_32B_tag;
+
+ typedef union { /* ME_IM - Interrupt Mask Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t M_ICONF:1; /* Invalid mode config interrupt mask */
+#else
+ vuint32_t M_CONF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t M_IMODE:1; /* Invalid mode interrupt mask */
+#else
+ vuint32_t M_MODE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t M_SAFE:1; /* SAFE mode interrupt mask */
+#else
+ vuint32_t M_AFE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t M_MTC:1; /* Mode transition complete interrupt mask */
+#else
+ vuint32_t M_TC:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ME_IM_32B_tag;
+
+ typedef union { /* ME_IMTS - Invalid Mode Transition Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:27;
+ vuint32_t S_MTI:1; /* Mode Transition Illegal status */
+ vuint32_t S_MRI:1; /* Mode Request Illegal status */
+ vuint32_t S_DMA:1; /* Disabled Mode Access status */
+ vuint32_t S_NMA:1; /* Non-existing Mode Access status */
+ vuint32_t S_SEA:1; /* Safe Event Active status */
+ } B;
+ } ME_IMTS_32B_tag;
+
+ typedef union { /* ME_DMTS - Debug Mode Transition Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PREVIOUS_MODE:4; /* Previous Device Mode */
+ vuint32_t:4;
+ vuint32_t MPH_BUSY:1; /* MC_ME/MC_PCU Handshake Busy Indicator */
+ vuint32_t:2;
+ vuint32_t PMC_PROG:1; /* MC_PCU Mode Change in Process Indicator */
+ vuint32_t CORE_DBG:1; /* Processor is in Debug Mode Indicator */
+ vuint32_t:2;
+ vuint32_t SMR:1; /* SAFE Mode Request */
+ vuint32_t:1;
+ vuint32_t VREG_CSRC_SC:1; /* Main VREG Clock Source State Change Indicator */
+ vuint32_t CSRC_CSRC_SC:1; /* Other Clock Source State Change Indicator */
+ vuint32_t IRCOSC_SC:1; /* IRCOSC State Change Indicator */
+ vuint32_t SCSRC_SC:1; /* Secondary System Clock Sources State Change Indicator */
+ vuint32_t SYSCLK_SW:1; /* System Clock Switching pending Status Indicator */
+ vuint32_t:1;
+ vuint32_t FLASH_SC:1; /* FLASH State Change Indicator */
+ vuint32_t CDP_PRPH_0_143:1; /* Clock Disable Process Pending Status for Periph. 0-143 */
+ vuint32_t:4;
+ vuint32_t CDP_PRPH_64_95:1; /* Clock Disable Process Pending Status for Periph. 64-95 */
+ vuint32_t CDP_PRPH_32_63:1; /* Clock Disable Process Pending Status for Periph. 32-63 */
+ vuint32_t CDP_PRPH_0_31:1; /* Clock Disable Process Pending Status for Periph. 0-31 */
+ } B;
+ } ME_DMTS_32B_tag;
+
+ typedef union { /* ME_RESET_MC - RESET Mode Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t FLAON:2; /* Code flash power-down control */
+#else
+ vuint32_t CFLAON:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ vuint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL0ON:1; /* System PLL control */
+#else
+ vuint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ vuint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_RESET_MC_32B_tag;
+
+ typedef union { /* ME_SAFE_MC - Mode Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t FLAON:2; /* Code flash power-down control */
+#else
+ vuint32_t CFLAON:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ vuint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL0ON:1; /* System PLL control */
+#else
+ vuint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ vuint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_SAFE_MC_32B_tag;
+
+ typedef union { /* ME_DRUN_MC - DRUN Mode Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t FLAON:2; /* Code flash power-down control */
+#else
+ vuint32_t CFLAON:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ vuint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL0ON:1; /* System PLL control */
+#else
+ vuint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ vuint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_DRUN_MC_32B_tag;
+
+
+ /* Register layout for all registers RUN_MC... */
+
+ typedef union { /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+ vuint32_t FLAON:2; /* Code flash power-down control */
+ vuint32_t:8;
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+ vuint32_t PLL0ON:1; /* System PLL control */
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_RUN_MC_32B_tag;
+
+ typedef union { /* ME_HALT0_MC - HALT0 Mode Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t FLAON:2; /* Code flash power-down control */
+#else
+ vuint32_t CFLAON:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ vuint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL0ON:1; /* System PLL control */
+#else
+ vuint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ vuint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_HALT0_MC_32B_tag;
+
+ typedef union { /* ME_STOP0_MC - STOP0 Mode Configration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t FLAON:2; /* Code flash power-down control */
+#else
+ vuint32_t CFLAON:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ vuint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL0ON:1; /* System PLL control */
+#else
+ vuint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ vuint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_STOP0_MC_32B_tag;
+
+ typedef union { /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t PDO:1; /* IOs output power-down control */
+ vuint32_t:2;
+ vuint32_t MVRON:1; /* Main voltage regulator control */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t FLAON:2; /* Code flash power-down control */
+#else
+ vuint32_t CFLAON:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL1ON:1; /* Secondary system clock source [8..0] control */
+#else
+ vuint32_t PLL2ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t PLL0ON:1; /* System PLL control */
+#else
+ vuint32_t PLL1ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t XOSCON:1; /* System crystal oscillator control */
+#else
+ vuint32_t XOSC0ON:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ME
+ vuint32_t IRCOSCON:1; /* System RC oscillator control */
+#else
+ vuint32_t IRCON:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SYSCLK:4; /* System clock switch control */
+ } B;
+ } ME_STANDBY0_MC_32B_tag;
+
+ typedef union { /* ME_PS0 - Peripheral Status Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t S_FLEXRAY:1; /* FlexRay status */
+ vuint32_t:6;
+ vuint32_t S_FLEXCAN1:1; /* FlexCAN1 status */
+ vuint32_t S_FLEXCAN0:1; /* FlexCAN0 status */
+ vuint32_t:9;
+ vuint32_t S_DSPI2:1; /* DSPI2 status */
+ vuint32_t S_DSPI1:1; /* DSPI1 status */
+ vuint32_t S_DSPI0:1; /* DSPI0 status */
+ vuint32_t:4;
+ } B;
+ } ME_PS0_32B_tag;
+
+ typedef union { /* ME_PS1 - Peripheral Status Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t S_SWG:1; /* SWG status */
+ vuint32_t:3;
+ vuint32_t S_CRC:1; /* CRC status */
+ vuint32_t:8;
+ vuint32_t S_LIN_FLEX1:1; /* LinFlex1 status */
+ vuint32_t S_LIN_FLEX0:1; /* LinFlex0 status */
+ vuint32_t:5;
+ vuint32_t S_FLEXPWM1:1; /* FlexPWM1 status */
+ vuint32_t S_FLEXPWM0:1; /* FlexPWM0 status */
+ vuint32_t S_ETIMER2:1; /* eTimer2 status */
+ vuint32_t S_ETIMER1:1; /* eTimer1 status */
+ vuint32_t S_ETIMER0:1; /* eTimer0 status */
+ vuint32_t:2;
+ vuint32_t S_CTU:1; /* CTU status */
+ vuint32_t:1;
+ vuint32_t S_ADC1:1; /* ADC1 status */
+ vuint32_t S_ADC0:1; /* ADC0 status */
+ } B;
+ } ME_PS1_32B_tag;
+
+ typedef union { /* ME_PS2 - Peripheral Status Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t S_PIT:1; /* PIT status */
+ vuint32_t:28;
+ } B;
+ } ME_PS2_32B_tag;
+
+
+ /* Register layout for all registers RUN_PC... */
+
+ typedef union { /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t RUN3:1; /* Peripheral control during RUN3 */
+ vuint32_t RUN2:1; /* Peripheral control during RUN2 */
+ vuint32_t RUN1:1; /* Peripheral control during RUN1 */
+ vuint32_t RUN0:1; /* Peripheral control during RUN0 */
+ vuint32_t DRUN:1; /* Peripheral control during DRUN */
+ vuint32_t SAFE:1; /* Peripheral control during SAFE */
+ vuint32_t TEST:1; /* Peripheral control during TEST */
+ vuint32_t RESET:1; /* Peripheral control during RESET */
+ } B;
+ } ME_RUN_PC_32B_tag;
+
+
+ /* Register layout for all registers LP_PC... */
+
+ typedef union { /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t:21;
+ vuint32_t STOP0:1; /* Peripheral control during STOP0 */
+ vuint32_t:1;
+ vuint32_t HALT0:1; /* Peripheral control during HALT0 */
+ vuint32_t:8;
+ } B;
+ } ME_LP_PC_32B_tag;
+
+
+ /* Register layout for all registers PCTL... */
+
+ typedef union { /* ME_PCTL[0...143] - Peripheral Control Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t DBG_F:1; /* Peripheral control in debug mode */
+ vuint8_t LP_CFG:3; /* Peripheral configuration select for non-RUN modes */
+ vuint8_t RUN_CFG:3; /* Peripheral configuration select for RUN modes */
+ } B;
+ } ME_PCTL_8B_tag;
+
+
+
+
+ /* Register layout for generated register(s) PS... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } ME_PS_32B_tag;
+
+
+
+
+
+
+ typedef struct ME_struct_tag { /* start of ME_tag */
+ /* ME_GS - Global Status Register */
+ ME_GS_32B_tag GS; /* offset: 0x0000 size: 32 bit */
+ /* ME_MCTL - Mode Control Register */
+ ME_MCTL_32B_tag MCTL; /* offset: 0x0004 size: 32 bit */
+ union {
+ ME_MEN_32B_tag MER; /* deprecated - please avoid */
+
+ /* ME_MEN - Mode Enable Register */
+ ME_MEN_32B_tag MEN; /* offset: 0x0008 size: 32 bit */
+
+ };
+ /* ME_IS - Interrupt Status Register */
+ ME_IS_32B_tag IS; /* offset: 0x000C size: 32 bit */
+ /* ME_IM - Interrupt Mask Register */
+ ME_IM_32B_tag IM; /* offset: 0x0010 size: 32 bit */
+ /* ME_IMTS - Invalid Mode Transition Status Register */
+ ME_IMTS_32B_tag IMTS; /* offset: 0x0014 size: 32 bit */
+ /* ME_DMTS - Debug Mode Transition Status Register */
+ ME_DMTS_32B_tag DMTS; /* offset: 0x0018 size: 32 bit */
+ int8_t ME_reserved_001C_C[4];
+ union {
+ /* ME_RESET_MC - RESET Mode Configuration Register */
+ ME_RESET_MC_32B_tag RESET_MC; /* offset: 0x0020 size: 32 bit */
+
+ ME_RESET_MC_32B_tag RESET; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_0024_C[4];
+ union {
+ /* ME_SAFE_MC - Mode Configuration Register */
+ ME_SAFE_MC_32B_tag SAFE_MC; /* offset: 0x0028 size: 32 bit */
+
+ ME_SAFE_MC_32B_tag SAFE; /* deprecated - please avoid */
+
+ };
+ union {
+ /* ME_DRUN_MC - DRUN Mode Configuration Register */
+ ME_DRUN_MC_32B_tag DRUN_MC; /* offset: 0x002C size: 32 bit */
+
+ ME_DRUN_MC_32B_tag DRUN; /* deprecated - please avoid */
+
+ };
+ union {
+ /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
+ ME_RUN_MC_32B_tag RUN_MC[4]; /* offset: 0x0030 (0x0004 x 4) */
+
+ ME_RUN_MC_32B_tag RUN[4]; /* offset: 0x0030 (0x0004 x 4) */ /* deprecated - please avoid */
+
+ struct {
+ /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
+ ME_RUN_MC_32B_tag RUN0_MC; /* offset: 0x0030 size: 32 bit */
+ ME_RUN_MC_32B_tag RUN1_MC; /* offset: 0x0034 size: 32 bit */
+ ME_RUN_MC_32B_tag RUN2_MC; /* offset: 0x0038 size: 32 bit */
+ ME_RUN_MC_32B_tag RUN3_MC; /* offset: 0x003C size: 32 bit */
+ };
+
+ };
+ union {
+ /* ME_HALT0_MC - HALT0 Mode Configuration Register */
+ ME_HALT0_MC_32B_tag HALT0_MC; /* offset: 0x0040 size: 32 bit */
+
+ ME_HALT0_MC_32B_tag HALT0; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_0044_C[4];
+ union {
+ /* ME_STOP0_MC - STOP0 Mode Configration Register */
+ ME_STOP0_MC_32B_tag STOP0_MC; /* offset: 0x0048 size: 32 bit */
+
+ ME_STOP0_MC_32B_tag STOP0; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_004C_C[8];
+ union {
+ /* ME_STANDBY0_MC - STANDBY0 Mode Configration Register */
+ ME_STANDBY0_MC_32B_tag STANDBY0_MC; /* offset: 0x0054 size: 32 bit */
+
+ ME_STANDBY0_MC_32B_tag STANDBY0; /* deprecated - please avoid */
+
+ };
+ int8_t ME_reserved_0058_C[8];
+ union {
+ ME_PS_32B_tag PS[3]; /* offset: 0x0060 (0x0004 x 3) */
+
+ struct {
+ /* ME_PS0 - Peripheral Status Register 0 */
+ ME_PS0_32B_tag PS0; /* offset: 0x0060 size: 32 bit */
+ /* ME_PS1 - Peripheral Status Register 1 */
+ ME_PS1_32B_tag PS1; /* offset: 0x0064 size: 32 bit */
+ /* ME_PS2 - Peripheral Status Register 2 */
+ ME_PS2_32B_tag PS2; /* offset: 0x0068 size: 32 bit */
+ };
+
+ };
+ int8_t ME_reserved_006C_C[20];
+ union {
+ ME_RUN_PC_32B_tag RUNPC[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
+ ME_RUN_PC_32B_tag RUN_PC[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ struct {
+ /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
+ ME_RUN_PC_32B_tag RUN_PC0; /* offset: 0x0080 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC1; /* offset: 0x0084 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC2; /* offset: 0x0088 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC3; /* offset: 0x008C size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC4; /* offset: 0x0090 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC5; /* offset: 0x0094 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC6; /* offset: 0x0098 size: 32 bit */
+ ME_RUN_PC_32B_tag RUN_PC7; /* offset: 0x009C size: 32 bit */
+ };
+
+ };
+ union {
+ ME_LP_PC_32B_tag LPPC[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
+ ME_LP_PC_32B_tag LP_PC[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ struct {
+ /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
+ ME_LP_PC_32B_tag LP_PC0; /* offset: 0x00A0 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC1; /* offset: 0x00A4 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC2; /* offset: 0x00A8 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC3; /* offset: 0x00AC size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC4; /* offset: 0x00B0 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC5; /* offset: 0x00B4 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC6; /* offset: 0x00B8 size: 32 bit */
+ ME_LP_PC_32B_tag LP_PC7; /* offset: 0x00BC size: 32 bit */
+ };
+
+ };
+ union {
+ /* ME_PCTL[0...143] - Peripheral Control Registers */
+ ME_PCTL_8B_tag PCTL[144]; /* offset: 0x00C0 (0x0001 x 144) */
+
+ struct {
+ /* ME_PCTL[0...143] - Peripheral Control Registers */
+ ME_PCTL_8B_tag PCTL0; /* offset: 0x00C0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL1; /* offset: 0x00C1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL2; /* offset: 0x00C2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL3; /* offset: 0x00C3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL4; /* offset: 0x00C4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL5; /* offset: 0x00C5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL6; /* offset: 0x00C6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL7; /* offset: 0x00C7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL8; /* offset: 0x00C8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL9; /* offset: 0x00C9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL10; /* offset: 0x00CA size: 8 bit */
+ ME_PCTL_8B_tag PCTL11; /* offset: 0x00CB size: 8 bit */
+ ME_PCTL_8B_tag PCTL12; /* offset: 0x00CC size: 8 bit */
+ ME_PCTL_8B_tag PCTL13; /* offset: 0x00CD size: 8 bit */
+ ME_PCTL_8B_tag PCTL14; /* offset: 0x00CE size: 8 bit */
+ ME_PCTL_8B_tag PCTL15; /* offset: 0x00CF size: 8 bit */
+ ME_PCTL_8B_tag PCTL16; /* offset: 0x00D0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL17; /* offset: 0x00D1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL18; /* offset: 0x00D2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL19; /* offset: 0x00D3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL20; /* offset: 0x00D4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL21; /* offset: 0x00D5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL22; /* offset: 0x00D6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL23; /* offset: 0x00D7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL24; /* offset: 0x00D8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL25; /* offset: 0x00D9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL26; /* offset: 0x00DA size: 8 bit */
+ ME_PCTL_8B_tag PCTL27; /* offset: 0x00DB size: 8 bit */
+ ME_PCTL_8B_tag PCTL28; /* offset: 0x00DC size: 8 bit */
+ ME_PCTL_8B_tag PCTL29; /* offset: 0x00DD size: 8 bit */
+ ME_PCTL_8B_tag PCTL30; /* offset: 0x00DE size: 8 bit */
+ ME_PCTL_8B_tag PCTL31; /* offset: 0x00DF size: 8 bit */
+ ME_PCTL_8B_tag PCTL32; /* offset: 0x00E0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL33; /* offset: 0x00E1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL34; /* offset: 0x00E2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL35; /* offset: 0x00E3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL36; /* offset: 0x00E4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL37; /* offset: 0x00E5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL38; /* offset: 0x00E6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL39; /* offset: 0x00E7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL40; /* offset: 0x00E8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL41; /* offset: 0x00E9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL42; /* offset: 0x00EA size: 8 bit */
+ ME_PCTL_8B_tag PCTL43; /* offset: 0x00EB size: 8 bit */
+ ME_PCTL_8B_tag PCTL44; /* offset: 0x00EC size: 8 bit */
+ ME_PCTL_8B_tag PCTL45; /* offset: 0x00ED size: 8 bit */
+ ME_PCTL_8B_tag PCTL46; /* offset: 0x00EE size: 8 bit */
+ ME_PCTL_8B_tag PCTL47; /* offset: 0x00EF size: 8 bit */
+ ME_PCTL_8B_tag PCTL48; /* offset: 0x00F0 size: 8 bit */
+ ME_PCTL_8B_tag PCTL49; /* offset: 0x00F1 size: 8 bit */
+ ME_PCTL_8B_tag PCTL50; /* offset: 0x00F2 size: 8 bit */
+ ME_PCTL_8B_tag PCTL51; /* offset: 0x00F3 size: 8 bit */
+ ME_PCTL_8B_tag PCTL52; /* offset: 0x00F4 size: 8 bit */
+ ME_PCTL_8B_tag PCTL53; /* offset: 0x00F5 size: 8 bit */
+ ME_PCTL_8B_tag PCTL54; /* offset: 0x00F6 size: 8 bit */
+ ME_PCTL_8B_tag PCTL55; /* offset: 0x00F7 size: 8 bit */
+ ME_PCTL_8B_tag PCTL56; /* offset: 0x00F8 size: 8 bit */
+ ME_PCTL_8B_tag PCTL57; /* offset: 0x00F9 size: 8 bit */
+ ME_PCTL_8B_tag PCTL58; /* offset: 0x00FA size: 8 bit */
+ ME_PCTL_8B_tag PCTL59; /* offset: 0x00FB size: 8 bit */
+ ME_PCTL_8B_tag PCTL60; /* offset: 0x00FC size: 8 bit */
+ ME_PCTL_8B_tag PCTL61; /* offset: 0x00FD size: 8 bit */
+ ME_PCTL_8B_tag PCTL62; /* offset: 0x00FE size: 8 bit */
+ ME_PCTL_8B_tag PCTL63; /* offset: 0x00FF size: 8 bit */
+ ME_PCTL_8B_tag PCTL64; /* offset: 0x0100 size: 8 bit */
+ ME_PCTL_8B_tag PCTL65; /* offset: 0x0101 size: 8 bit */
+ ME_PCTL_8B_tag PCTL66; /* offset: 0x0102 size: 8 bit */
+ ME_PCTL_8B_tag PCTL67; /* offset: 0x0103 size: 8 bit */
+ ME_PCTL_8B_tag PCTL68; /* offset: 0x0104 size: 8 bit */
+ ME_PCTL_8B_tag PCTL69; /* offset: 0x0105 size: 8 bit */
+ ME_PCTL_8B_tag PCTL70; /* offset: 0x0106 size: 8 bit */
+ ME_PCTL_8B_tag PCTL71; /* offset: 0x0107 size: 8 bit */
+ ME_PCTL_8B_tag PCTL72; /* offset: 0x0108 size: 8 bit */
+ ME_PCTL_8B_tag PCTL73; /* offset: 0x0109 size: 8 bit */
+ ME_PCTL_8B_tag PCTL74; /* offset: 0x010A size: 8 bit */
+ ME_PCTL_8B_tag PCTL75; /* offset: 0x010B size: 8 bit */
+ ME_PCTL_8B_tag PCTL76; /* offset: 0x010C size: 8 bit */
+ ME_PCTL_8B_tag PCTL77; /* offset: 0x010D size: 8 bit */
+ ME_PCTL_8B_tag PCTL78; /* offset: 0x010E size: 8 bit */
+ ME_PCTL_8B_tag PCTL79; /* offset: 0x010F size: 8 bit */
+ ME_PCTL_8B_tag PCTL80; /* offset: 0x0110 size: 8 bit */
+ ME_PCTL_8B_tag PCTL81; /* offset: 0x0111 size: 8 bit */
+ ME_PCTL_8B_tag PCTL82; /* offset: 0x0112 size: 8 bit */
+ ME_PCTL_8B_tag PCTL83; /* offset: 0x0113 size: 8 bit */
+ ME_PCTL_8B_tag PCTL84; /* offset: 0x0114 size: 8 bit */
+ ME_PCTL_8B_tag PCTL85; /* offset: 0x0115 size: 8 bit */
+ ME_PCTL_8B_tag PCTL86; /* offset: 0x0116 size: 8 bit */
+ ME_PCTL_8B_tag PCTL87; /* offset: 0x0117 size: 8 bit */
+ ME_PCTL_8B_tag PCTL88; /* offset: 0x0118 size: 8 bit */
+ ME_PCTL_8B_tag PCTL89; /* offset: 0x0119 size: 8 bit */
+ ME_PCTL_8B_tag PCTL90; /* offset: 0x011A size: 8 bit */
+ ME_PCTL_8B_tag PCTL91; /* offset: 0x011B size: 8 bit */
+ ME_PCTL_8B_tag PCTL92; /* offset: 0x011C size: 8 bit */
+ ME_PCTL_8B_tag PCTL93; /* offset: 0x011D size: 8 bit */
+ ME_PCTL_8B_tag PCTL94; /* offset: 0x011E size: 8 bit */
+ ME_PCTL_8B_tag PCTL95; /* offset: 0x011F size: 8 bit */
+ ME_PCTL_8B_tag PCTL96; /* offset: 0x0120 size: 8 bit */
+ ME_PCTL_8B_tag PCTL97; /* offset: 0x0121 size: 8 bit */
+ ME_PCTL_8B_tag PCTL98; /* offset: 0x0122 size: 8 bit */
+ ME_PCTL_8B_tag PCTL99; /* offset: 0x0123 size: 8 bit */
+ ME_PCTL_8B_tag PCTL100; /* offset: 0x0124 size: 8 bit */
+ ME_PCTL_8B_tag PCTL101; /* offset: 0x0125 size: 8 bit */
+ ME_PCTL_8B_tag PCTL102; /* offset: 0x0126 size: 8 bit */
+ ME_PCTL_8B_tag PCTL103; /* offset: 0x0127 size: 8 bit */
+ ME_PCTL_8B_tag PCTL104; /* offset: 0x0128 size: 8 bit */
+ ME_PCTL_8B_tag PCTL105; /* offset: 0x0129 size: 8 bit */
+ ME_PCTL_8B_tag PCTL106; /* offset: 0x012A size: 8 bit */
+ ME_PCTL_8B_tag PCTL107; /* offset: 0x012B size: 8 bit */
+ ME_PCTL_8B_tag PCTL108; /* offset: 0x012C size: 8 bit */
+ ME_PCTL_8B_tag PCTL109; /* offset: 0x012D size: 8 bit */
+ ME_PCTL_8B_tag PCTL110; /* offset: 0x012E size: 8 bit */
+ ME_PCTL_8B_tag PCTL111; /* offset: 0x012F size: 8 bit */
+ ME_PCTL_8B_tag PCTL112; /* offset: 0x0130 size: 8 bit */
+ ME_PCTL_8B_tag PCTL113; /* offset: 0x0131 size: 8 bit */
+ ME_PCTL_8B_tag PCTL114; /* offset: 0x0132 size: 8 bit */
+ ME_PCTL_8B_tag PCTL115; /* offset: 0x0133 size: 8 bit */
+ ME_PCTL_8B_tag PCTL116; /* offset: 0x0134 size: 8 bit */
+ ME_PCTL_8B_tag PCTL117; /* offset: 0x0135 size: 8 bit */
+ ME_PCTL_8B_tag PCTL118; /* offset: 0x0136 size: 8 bit */
+ ME_PCTL_8B_tag PCTL119; /* offset: 0x0137 size: 8 bit */
+ ME_PCTL_8B_tag PCTL120; /* offset: 0x0138 size: 8 bit */
+ ME_PCTL_8B_tag PCTL121; /* offset: 0x0139 size: 8 bit */
+ ME_PCTL_8B_tag PCTL122; /* offset: 0x013A size: 8 bit */
+ ME_PCTL_8B_tag PCTL123; /* offset: 0x013B size: 8 bit */
+ ME_PCTL_8B_tag PCTL124; /* offset: 0x013C size: 8 bit */
+ ME_PCTL_8B_tag PCTL125; /* offset: 0x013D size: 8 bit */
+ ME_PCTL_8B_tag PCTL126; /* offset: 0x013E size: 8 bit */
+ ME_PCTL_8B_tag PCTL127; /* offset: 0x013F size: 8 bit */
+ ME_PCTL_8B_tag PCTL128; /* offset: 0x0140 size: 8 bit */
+ ME_PCTL_8B_tag PCTL129; /* offset: 0x0141 size: 8 bit */
+ ME_PCTL_8B_tag PCTL130; /* offset: 0x0142 size: 8 bit */
+ ME_PCTL_8B_tag PCTL131; /* offset: 0x0143 size: 8 bit */
+ ME_PCTL_8B_tag PCTL132; /* offset: 0x0144 size: 8 bit */
+ ME_PCTL_8B_tag PCTL133; /* offset: 0x0145 size: 8 bit */
+ ME_PCTL_8B_tag PCTL134; /* offset: 0x0146 size: 8 bit */
+ ME_PCTL_8B_tag PCTL135; /* offset: 0x0147 size: 8 bit */
+ ME_PCTL_8B_tag PCTL136; /* offset: 0x0148 size: 8 bit */
+ ME_PCTL_8B_tag PCTL137; /* offset: 0x0149 size: 8 bit */
+ ME_PCTL_8B_tag PCTL138; /* offset: 0x014A size: 8 bit */
+ ME_PCTL_8B_tag PCTL139; /* offset: 0x014B size: 8 bit */
+ ME_PCTL_8B_tag PCTL140; /* offset: 0x014C size: 8 bit */
+ ME_PCTL_8B_tag PCTL141; /* offset: 0x014D size: 8 bit */
+ ME_PCTL_8B_tag PCTL142; /* offset: 0x014E size: 8 bit */
+ ME_PCTL_8B_tag PCTL143; /* offset: 0x014F size: 8 bit */
+ };
+
+ };
+ } ME_tag;
+
+
+#define ME (*(volatile ME_tag *) 0xC3FDC000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: OSC */
+/* */
+/****************************************************************/
+
+ typedef union { /* OSC_CTL - Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t OSCBYP:1; /* High Frequency Oscillator Bypass */
+ vuint32_t:7;
+ vuint32_t EOCV:8; /* End of Count Value */
+ vuint32_t M_OSC:1; /* High Frequency Oscillator Clock Interrupt Mask */
+ vuint32_t:2;
+ vuint32_t OSCDIV:5; /* High Frequency Oscillator Division Factor */
+ vuint32_t I_OSC:1; /* High Frequency Oscillator Clock Interrupt */
+ vuint32_t:5;
+ vuint32_t S_OSC:1;
+ vuint32_t OSCON:1; } B;
+ } OSC_CTL_32B_tag;
+
+
+
+ typedef struct OSC_struct_tag { /* start of OSC_tag */
+ /* OSC_CTL - Control Register */
+ OSC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
+ } OSC_tag;
+
+
+#define OSC (*(volatile OSC_tag *) 0xC3FE0000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: RC */
+/* */
+/****************************************************************/
+
+ typedef union { /* RC_CTL - Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t RCTRIM:6; /* Main RC Trimming Bits */
+ vuint32_t:3;
+ vuint32_t RCDIV:5; /* Main RC Clock Division Factor */
+ vuint32_t:2;
+ vuint32_t S_RC_STDBY:1; /* MRC Oscillator Powerdown Status */
+ vuint32_t:5;
+ } B;
+ } RC_CTL_32B_tag;
+
+
+
+ typedef struct RC_struct_tag { /* start of RC_tag */
+ /* RC_CTL - Control Register */
+ RC_CTL_32B_tag CTL; /* offset: 0x0000 size: 32 bit */
+ } RC_tag;
+
+
+#define RC (*(volatile RC_tag *) 0xC3FE0060UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PLLD */
+/* */
+/****************************************************************/
+
+ typedef union { /* PLLD_CR - Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:2;
+ vuint32_t IDF:4; /* PLL Input Division Factor */
+ vuint32_t ODF:2; /* PLL Output Division Factor */
+ vuint32_t:1;
+ vuint32_t NDIV:7; /* PLL Loop Division Factor */
+ vuint32_t:7;
+ vuint32_t EN_PLL_SW:1; /* Enable Progressive Clock Switching */
+ vuint32_t MODE:1; /* Activate 1:1 Mode */
+ vuint32_t UNLOCK_ONCE:1; /* PLL Loss of Lock */
+ vuint32_t M_LOCK:1; /* Mask for the i_lock Output Interrupt */
+ vuint32_t I_LOCK:1; /* PLL Lock Signal Toggle Indicator */
+ vuint32_t S_LOCK:1; /* PLL has Aquired Lock */
+ vuint32_t PLL_FAIL_MASK:1; /* PLL Fail Mask */
+ vuint32_t PLL_FAIL_FLAG:1; /* PLL Fail Flag */
+ vuint32_t PLL_ON:1; /* PLL ON Bit */
+ } B;
+ } PLLD_CR_32B_tag;
+
+ typedef union { /* PLLD_MR - PLLD Modulation Register */
+ vuint32_t R;
+ struct {
+ vuint32_t STRB_BYPASS:1; /* Strobe Bypass */
+ vuint32_t:1;
+ vuint32_t SPRD_SEL:1; /* Spread Type Selection */
+ vuint32_t MOD_PERIOD:13; /* Modulation Period */
+ vuint32_t SSCG_EN:1; /* Spread Spectrum Clock Generation Enable */
+ vuint32_t INC_STEP:15; /* Increment Step */
+ } B;
+ } PLLD_MR_32B_tag;
+
+
+
+ typedef struct PLLD_struct_tag { /* start of PLLD_tag */
+ /* PLLD_CR - Control Register */
+ PLLD_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
+ /* PLLD_MR - PLLD Modulation Register */
+ PLLD_MR_32B_tag MR; /* offset: 0x0004 size: 32 bit */
+
+ vuint32_t plld_reserved[6];
+ } PLLD_tag;
+
+
+#define PLLD0 (*(volatile PLLD_tag *) 0xC3FE00A0UL)
+#define PLLD1 (*(volatile PLLD_tag *) 0xC3FE00C0UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CMU */
+/* */
+/****************************************************************/
+
+ typedef union { /* CMU_CSR - Control Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SFM:1; /* Start Frequency Measure */
+ vuint32_t:13;
+ vuint32_t CKSEL1:2; /* RC Oscillator(s) Selection Bit */
+ vuint32_t:5;
+ vuint32_t RCDIV:2; /* RCfast Clock Division Factor */
+ vuint32_t CME_A:1; /* PLL_A Clock Monitor Enable */
+ } B;
+ } CMU_CSR_32B_tag;
+
+ typedef union { /* CMU_FDR - Frequency Display Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t FD:20; /* Measured Frequency Bits */
+ } B;
+ } CMU_FDR_32B_tag;
+
+ typedef union { /* CMU_HFREFR_A - High Frequency Reference Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t HFREF_A:12; /* High Frequency Reference Value */
+ } B;
+ } CMU_HFREFR_A_32B_tag;
+
+ typedef union { /* CMU_LFREFR_A - Low Frequency Reference Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t LFREF_A:12; /* Low Frequency Reference Value */
+ } B;
+ } CMU_LFREFR_A_32B_tag;
+
+ typedef union { /* CMU_ISR - Interrupt Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t FLCI_A:1; /* PLL_A Clock Frequency less than Reference Clock Interrupt */
+ vuint32_t FHH_AI:1; /* PLL_A Clock Frequency higher than high Reference Interrupt */
+ vuint32_t FLLI_A:1; /* PLL_A Clock Frequency less than low Reference Interrupt */
+ vuint32_t OLRI:1; /* Oscillator Frequency less than RC Frequency Interrupt */
+ } B;
+ } CMU_ISR_32B_tag;
+
+ typedef union { /* CMU_IMR - Interrupt Mask Register */
+ vuint32_t R;
+ } CMU_IMR_32B_tag;
+
+ typedef union { /* CMU_MDR - Measurement Duration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t MD:20; /* Measurment Duration Bits */
+ } B;
+ } CMU_MDR_32B_tag;
+
+
+
+ typedef struct CMU_struct_tag { /* start of CMU_tag */
+ /* CMU_CSR - Control Status Register */
+ CMU_CSR_32B_tag CSR; /* offset: 0x0000 size: 32 bit */
+ /* CMU_FDR - Frequency Display Register */
+ CMU_FDR_32B_tag FDR; /* offset: 0x0004 size: 32 bit */
+ /* CMU_HFREFR_A - High Frequency Reference Register */
+ CMU_HFREFR_A_32B_tag HFREFR_A; /* offset: 0x0008 size: 32 bit */
+ /* CMU_LFREFR_A - Low Frequency Reference Register */
+ CMU_LFREFR_A_32B_tag LFREFR_A; /* offset: 0x000C size: 32 bit */
+ /* CMU_ISR - Interrupt Status Register */
+ CMU_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
+ /* CMU_IMR - Interrupt Mask Register */
+ CMU_IMR_32B_tag IMR; /* offset: 0x0014 size: 32 bit */
+ /* CMU_MDR - Measurement Duration Register */
+ CMU_MDR_32B_tag MDR; /* offset: 0x0018 size: 32 bit */
+ } CMU_tag;
+
+
+#define CMU0 (*(volatile CMU_tag *) 0xC3FE0100UL)
+#define CMU1 (*(volatile CMU_tag *) 0xC3FE0120UL)
+#define CMU2 (*(volatile CMU_tag *) 0xC3FE0140UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CGM */
+/* */
+/****************************************************************/
+
+ typedef union { /* Output Clock Enable Register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ struct {
+ vuint32_t:31;
+ vuint32_t EN:1; /* Clock Enable Bit */
+ } B;
+ } CGM_OC_EN_32B_tag;
+
+ typedef union { /* Output Clock Division Select Register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ struct {
+ vuint32_t:2;
+ vuint32_t SELDIV:2; /* Output Clock Division Select */
+ vuint32_t SELCTL:4; /* Output Clock Source Selection Control */
+ vuint32_t:24;
+ } B;
+ } CGM_OCDS_SC_32B_tag;
+
+ typedef union { /* System Clock Select Status Register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ struct {
+ vuint32_t:4;
+ vuint32_t SELSTAT:4; /* System Clock Source Selection Status */
+ vuint32_t:24;
+ } B;
+ } CGM_SC_SS_32B_tag;
+
+ typedef union { /* System Clock Divider Configuration Register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ struct {
+ vuint32_t DE0:1; /* Divider 0 Enable */
+ vuint32_t:3;
+ vuint32_t DIV0:4; /* Divider 0 Value */
+ vuint32_t:24;
+ } B;
+ } CGM_SC_DC0_3_32B_tag;
+
+
+ /* Register layout for all registers SC_DC... */
+
+ typedef union { /* System Clock Divider Configuration Register */
+ vuint8_t R;
+ struct {
+ vuint8_t DE:1; /* Divider Enable */
+ vuint8_t:3;
+ vuint8_t DIV:4; /* Divider Division Value */
+ } B;
+ } CGM_SC_DC_8B_tag;
+
+
+ /* Register layout for all registers AC_SC... */
+
+ typedef union { /* Auxiliary Clock Select Control Registers */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ struct {
+ vuint32_t:4;
+ vuint32_t SELCTL:4; /* Auxliary Clock Source Selection Control */
+ vuint32_t:24;
+ } B;
+ } CGM_AC_SC_32B_tag;
+
+
+ /* Register layout for all registers AC_DC0_3... */
+
+ typedef union { /* Auxiliary Clock Divider Configuration Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t DE0:1; /* Divider 0 Enable */
+ vuint32_t:3;
+ vuint32_t DIV0:4; /* Divider 0 Value */
+ vuint32_t DE1:1; /* Divider 1 Enable */
+ vuint32_t:3;
+ vuint32_t DIV1:4; /* Divider 1 Value */
+ vuint32_t:16;
+ } B;
+ } CGM_AC_DC0_3_32B_tag;
+
+
+ typedef struct CGM_AUXCLK_struct_tag {
+
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC_SC; /* relative offset: 0x0000 */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC_DC0_3; /* relative offset: 0x0004 */
+
+ } CGM_AUXCLK_tag;
+
+
+ typedef struct CGM_struct_tag { /* start of CGM_tag */
+ OSC_CTL_32B_tag OSC_CTL; /* offset: 0x0000 size: 32 bit */
+ int8_t CGM_reserved_0004[92];
+ RC_CTL_32B_tag RC_CTL; /* offset: 0x0060 size: 32 bit */
+ int8_t CGM_reserved_0064[60];
+ PLLD_tag FMPLL[2]; /* offset: 0x00A0 (0x0020 x 2) */
+ int8_t CGM_reserved_00E0[32];
+ CMU_CSR_32B_tag CMU_0_CSR; /* offset: 0x0100 size: 32 bit */
+ CMU_FDR_32B_tag CMU_0_FDR; /* offset: 0x0104 size: 32 bit */
+ CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A; /* offset: 0x0108 size: 32 bit */
+ CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A; /* offset: 0x010C size: 32 bit */
+ CMU_ISR_32B_tag CMU_0_ISR; /* offset: 0x0110 size: 32 bit */
+ CMU_IMR_32B_tag CMU_0_IMR; /* offset: 0x0114 size: 32 bit */
+ CMU_MDR_32B_tag CMU_0_MDR; /* offset: 0x0118 size: 32 bit */
+ int8_t CGM_reserved_011C[4];
+ CMU_CSR_32B_tag CMU_1_CSR; /* offset: 0x0120 size: 32 bit */
+ int8_t CGM_reserved_0124[4];
+ CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A; /* offset: 0x0128 size: 32 bit */
+ CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A; /* offset: 0x012C size: 32 bit */
+ CMU_ISR_32B_tag CMU_1_ISR; /* offset: 0x0130 size: 32 bit */
+ int8_t CGM_reserved_0134[572];
+ /* Output Clock Enable Register */
+ CGM_OC_EN_32B_tag OC_EN; /* offset: 0x0370 size: 32 bit */
+ /* Output Clock Division Select Register */
+ CGM_OCDS_SC_32B_tag OCDS_SC; /* offset: 0x0374 size: 32 bit */
+ /* System Clock Select Status Register */
+ CGM_SC_SS_32B_tag SC_SS; /* offset: 0x0378 size: 32 bit */
+ union {
+ struct {
+ /* System Clock Divider Configuration Register */
+ CGM_SC_DC_8B_tag SC_DC[2]; /* offset: 0x037C (0x0001 x 2) */
+ int8_t CGM_reserved_037E_E0[2];
+ };
+
+ struct {
+ /* System Clock Divider Configuration Register */
+ CGM_SC_DC_8B_tag SC_DC0; /* offset: 0x037C size: 8 bit */
+ CGM_SC_DC_8B_tag SC_DC1; /* offset: 0x037D size: 8 bit */
+ int8_t CGM_reserved_037E_E1[2];
+ };
+
+ /* System Clock Divider Configuration Register */
+ CGM_SC_DC0_3_32B_tag SC_DC0_3; /* offset: 0x037C size: 32 bit */
+
+ };
+ union {
+ /* Register set AUXCLK */
+ CGM_AUXCLK_tag AUXCLK[6]; /* offset: 0x0380 (0x0008 x 6) */
+
+ struct {
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC0_SC; /* offset: 0x0380 size: 32 bit */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC0_DC0_3; /* offset: 0x0384 size: 32 bit */
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC1_SC; /* offset: 0x0388 size: 32 bit */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC1_DC0_3; /* offset: 0x038C size: 32 bit */
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC2_SC; /* offset: 0x0390 size: 32 bit */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC2_DC0_3; /* offset: 0x0394 size: 32 bit */
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC3_SC; /* offset: 0x0398 size: 32 bit */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC3_DC0_3; /* offset: 0x039C size: 32 bit */
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC4_SC; /* offset: 0x03A0 size: 32 bit */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC4_DC0_3; /* offset: 0x03A4 size: 32 bit */
+ /* Auxiliary Clock Select Control Registers */
+ CGM_AC_SC_32B_tag AC5_SC; /* offset: 0x03A8 size: 32 bit */
+ /* Auxiliary Clock Divider Configuration Registers */
+ CGM_AC_DC0_3_32B_tag AC5_DC0_3; /* offset: 0x03AC size: 32 bit */
+ };
+
+ };
+ } CGM_tag;
+
+
+#define CGM (*(volatile CGM_tag *) 0xC3FE0000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: RGM */
+/* */
+/****************************************************************/
+
+ typedef union { /* Functional Event Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t F_EXR:1; /* Flag for External Reset */
+ vuint16_t F_FCCU_HARD:1; /* Flag for FCCU hard reaction request */
+ vuint16_t F_FCCU_SOFT:1; /* Flag for FCCU soft reaction request */
+ vuint16_t F_ST_DONE:1; /* Flag for self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t F_CMU12_FHL:1; /* Flag for CMU 1/2 clock freq. too high/low */
+#else
+ vuint16_t F_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t F_FL_ECC_RCC:1; /* Flag for Flash, ECC, or lock-step error */
+ vuint16_t F_PLL1:1; /* Flag for PLL1 fail */
+ vuint16_t F_SWT:1; /* Flag for Software Watchdog Timer */
+ vuint16_t F_FCCU_SAFE:1; /* Flag for FCCU SAFE mode request */
+ vuint16_t F_CMU0_FHL:1; /* Flag for CMU 0 clock freq. too high/low */
+ vuint16_t F_CMU0_OLR:1; /* Flag for oscillator freq. too low */
+ vuint16_t F_PLL0:1; /* Flag for PLL0 fail */
+ vuint16_t F_CWD:1; /* Flag for Core Watchdog Reset */
+ vuint16_t F_SOFT:1; /* Flag for software reset */
+ vuint16_t F_CORE:1; /* Flag for core reset */
+ vuint16_t F_JTAG:1; /* Flag for JTAG initiated reset */
+ } B;
+ } RGM_FES_16B_tag;
+
+ typedef union { /* Destructive Event Status Register */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t F_POR:1; /* Flag for Power on Reset */
+#else
+ vuint16_t POR:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t:7;
+ vuint16_t F_COMP:1; /* Flag for comparator error */
+ vuint16_t F_LVD27_IO:1; /* Flag for 2.7V low-voltage detected (I/O) */
+ vuint16_t F_LVD27_FLASH:1; /* Flag for 2.7V low-voltage detected (Flash) */
+ vuint16_t F_LVD27_VREG:1; /* Flag for 2.7V low-voltage detected (VREG) */
+ vuint16_t:2;
+ vuint16_t F_HVD12:1; /* Flag for 1.2V high-voltage detected */
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t F_LVD12:1; /* Flag for 1.2V low-voltage detected */
+#else
+ vuint16_t F_LVD12_PD0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } RGM_DES_16B_tag;
+
+ typedef union { /* Functional Event Reset Disable Register */
+ vuint16_t R;
+ struct {
+ vuint16_t D_EXR:1; /* Disable External Pad Event Reset */
+ vuint16_t D_FCCU_HARD:1; /* Disable FCCU hard reaction request */
+ vuint16_t D_FCCU_SOFT:1; /* Disable FCCU soft reaction request */
+ vuint16_t D_ST_DONE:1; /* Disable self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t D_CMU12_FHL:1; /* Disable CMU 1/2 clock freq. too high/low */
+#else
+ vuint16_t D_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t D_FL_ECC_RCC:1; /* Disable Flash, ECC, or lock-step error */
+ vuint16_t D_PLL1:1; /* Disable PLL1 fail */
+ vuint16_t D_SWT:1; /* Disable Software Watchdog Timer */
+ vuint16_t D_FCCU_SAFE:1; /* Disable FCCU SAFE mode request */
+ vuint16_t D_CMU0_FHL:1; /* Disable CMU 0 clock freq. too high/low */
+ vuint16_t D_CMU0_OLR:1; /* Disable oscillator freq. too low */
+ vuint16_t D_PLL0:1; /* Disable PLL0 fail */
+ vuint16_t D_CWD:1; /* Disable Core Watchdog Reset */
+ vuint16_t D_SOFT:1; /* Disable software reset */
+ vuint16_t D_CORE:1; /* Disable core reset */
+ vuint16_t D_JTAG:1; /* Disable JTAG initiated reset */
+ } B;
+ } RGM_FERD_16B_tag;
+
+ typedef union { /* Destructive Event Reset Disable Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t D_COMP:1; /* Disable comparator error */
+ vuint16_t D_LVD27_IO:1; /* Disable 2.7V low-voltage detected (I/O) */
+ vuint16_t D_LVD27_FLASH:1; /* Disable 2.7V low-voltage detected (Flash) */
+ vuint16_t D_LVD27_VREG:1; /* Disable 2.7V low-voltage detected (VREG) */
+ vuint16_t:2;
+ vuint16_t D_HVD12:1; /* Disable 1.2V high-voltage detected */
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t D_LVD12:1; /* Disable 1.2V low-voltage detected */
+#else
+ vuint16_t D_LVD12_PD0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } RGM_DERD_16B_tag;
+
+ typedef union { /* Functional Event Alternate Request Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t AR_CMU12_FHL:1; /* Alternate Request for CMU1/2 clock freq. too high/low */
+#else
+ vuint16_t AR_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t:1;
+ vuint16_t AR_PLL1:1; /* Alternate Request for PLL1 fail */
+ vuint16_t:1;
+ vuint16_t AR_FCCU_SAVE:1; /* Alternate Request for FCCU SAFE mode request */
+ vuint16_t AR_CMU0_FHL:1; /* Alternate Request for CMU0 clock freq.
+ too high/low */
+ vuint16_t AR_CMU0_OLR:1; /* Alternate Request for oscillator freq. too low */
+ vuint16_t AR_PLL0:1; /* Alternate Request for PLL0 fail */
+ vuint16_t AR_CWD:1; /* Alternate Request for core watchdog reset */
+ vuint16_t:3;
+ } B;
+ } RGM_FEAR_16B_tag;
+
+ typedef union { /* Functional Event Short Sequence Register */
+ vuint16_t R;
+ struct {
+ vuint16_t SS_EXR:1; /* Short Sequence for External Reset */
+ vuint16_t SS_FCCU_HARD:1; /* Short Sequence for FCCU hard reaction request */
+ vuint16_t SS_FCCU_SOFT:1; /* Short Sequence for FCCU soft reaction request */
+ vuint16_t SS_ST_DONE:1; /* Short Sequence for self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t SS_CMU12_FHL:1; /* Short Sequence for CMU 1/2 clock freq. too high/low */
+#else
+ vuint16_t SS_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t SS_FL_ECC_RCC:1; /* Short Sequence for Flash, ECC, or lock-step error */
+ vuint16_t SS_PLL1:1; /* Short Sequence for PLL1 fail */
+ vuint16_t SS_SWT:1; /* Short Sequence for Software Watchdog Timer */
+ vuint16_t:1;
+ vuint16_t SS_CMU0_FHL:1; /* Short Sequence for CMU 0 clock freq. too high/low */
+ vuint16_t SS_CMU0_OLR:1; /* Short Sequence for oscillator freq. too low */
+ vuint16_t SS_PLL0:1; /* Short Sequence for PLL0 fail */
+ vuint16_t SS_CWD:1; /* Short Sequence for Core Watchdog Reset */
+ vuint16_t SS_SOFT:1; /* Short Sequence for software reset */
+ vuint16_t SS_CORE:1; /* Short Sequence for core reset */
+ vuint16_t SS_JTAG:1; /* Short Sequence for JTAG initiated reset */
+ } B;
+ } RGM_FESS_16B_tag;
+
+ typedef union { /* Functional Bidirectional Reset Enable Register */
+ vuint16_t R;
+ struct {
+ vuint16_t BE_EXR:1; /* Bidirectional Reset Enable for External Reset */
+ vuint16_t BE_FCCU_HARD:1; /* Bidirectional Reset Enable for FCCU hard reaction request */
+ vuint16_t BE_FCCU_SOFT:1; /* Bidirectional Reset Enable for FCCU soft reaction request */
+ vuint16_t BE_ST_DONE:1; /* Bidirectional Reset Enable for self-test completed */
+#ifndef USE_FIELD_ALIASES_RGM
+ vuint16_t BE_CMU12_FHL:1; /* Bidirectional Reset Enable for CMU 1/2 clock freq. too high/low */
+#else
+ vuint16_t BE_CMU1_FHL:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t BE_FL_ECC_RCC:1; /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */
+ vuint16_t BE_PLL1:1; /* Bidirectional Reset Enable for PLL1 fail */
+ vuint16_t BE_SWT:1; /* Bidirectional Reset Enable for Software Watchdog Timer */
+ vuint16_t:1;
+ vuint16_t BE_CMU0_FHL:1; /* Bidirectional Reset Enable for CMU 0 clock freq. too high/low */
+ vuint16_t BE_CMU0_OLR:1; /* Bidirectional Reset Enable for oscillator freq. too low */
+ vuint16_t BE_PLL0:1; /* Bidirectional Reset Enable for PLL0 fail */
+ vuint16_t BE_CWD:1; /* Bidirectional Reset Enable for Core Watchdog Reset */
+ vuint16_t BE_SOFT:1; /* Bidirectional Reset Enable for software reset */
+ vuint16_t BE_CORE:1; /* Bidirectional Reset Enable for core reset */
+ vuint16_t BE_JTAG:1; /* Bidirectional Reset Enable for JTAG initiated reset */
+ } B;
+ } RGM_FBRE_16B_tag;
+
+
+
+ typedef struct RGM_struct_tag { /* start of RGM_tag */
+ /* Functional Event Status Register */
+ RGM_FES_16B_tag FES; /* offset: 0x0000 size: 16 bit */
+ /* Destructive Event Status Register */
+ RGM_DES_16B_tag DES; /* offset: 0x0002 size: 16 bit */
+ /* Functional Event Reset Disable Register */
+ RGM_FERD_16B_tag FERD; /* offset: 0x0004 size: 16 bit */
+ /* Destructive Event Reset Disable Register */
+ RGM_DERD_16B_tag DERD; /* offset: 0x0006 size: 16 bit */
+ int8_t RGM_reserved_0008[8];
+ /* Functional Event Alternate Request Register */
+ RGM_FEAR_16B_tag FEAR; /* offset: 0x0010 size: 16 bit */
+ int8_t RGM_reserved_0012[6];
+ /* Functional Event Short Sequence Register */
+ RGM_FESS_16B_tag FESS; /* offset: 0x0018 size: 16 bit */
+ int8_t RGM_reserved_001A[2];
+ /* Functional Bidirectional Reset Enable Register */
+ RGM_FBRE_16B_tag FBRE; /* offset: 0x001C size: 16 bit */
+ } RGM_tag;
+
+
+#define RGM (*(volatile RGM_tag *) 0xC3FE4000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PCU */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers PCONF... */
+
+ typedef union { /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t STBY0:1; /* Power domain control during STBY0 */
+ vuint32_t:2;
+ vuint32_t STOP0:1; /* Power domain control during STOP0 */
+ vuint32_t:1;
+ vuint32_t HALT0:1; /* Power domain control during HALT0 */
+ vuint32_t RUN3:1; /* Power domain control during RUN3 */
+ vuint32_t RUN2:1; /* Power domain control during RUN2 */
+ vuint32_t RUN1:1; /* Power domain control during RUN1 */
+ vuint32_t RUN0:1; /* Power domain control during RUN0 */
+ vuint32_t DRUN:1; /* Power domain control during DRUN */
+ vuint32_t SAFE:1; /* Power domain control during SAFE */
+ vuint32_t TEST:1; /* Power domain control during TEST */
+ vuint32_t RST:1; /* Power domain control during RST */
+ } B;
+ } PCU_PCONF_32B_tag;
+
+ typedef union { /* PCU_PSTAT - Power Domain Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t PD15:1; /* Power Status for Power Domain 15 */
+ vuint32_t PD14:1; /* Power Status for Power Domain 14 */
+ vuint32_t PD13:1; /* Power Status for Power Domain 13 */
+ vuint32_t PD12:1; /* Power Status for Power Domain 12 */
+ vuint32_t PD11:1; /* Power Status for Power Domain 11 */
+ vuint32_t PD10:1; /* Power Status for Power Domain 10 */
+ vuint32_t PD9:1; /* Power Status for Power Domain 9 */
+ vuint32_t PD8:1; /* Power Status for Power Domain 8 */
+ vuint32_t PD7:1; /* Power Status for Power Domain 7 */
+ vuint32_t PD6:1; /* Power Status for Power Domain 6 */
+ vuint32_t PD5:1; /* Power Status for Power Domain 5 */
+ vuint32_t PD4:1; /* Power Status for Power Domain 4 */
+ vuint32_t PD3:1; /* Power Status for Power Domain 3 */
+ vuint32_t PD2:1; /* Power Status for Power Domain 2 */
+ vuint32_t PD1:1; /* Power Status for Power Domain 1 */
+ vuint32_t PD0:1; /* Power Status for Power Domain 0 */
+ } B;
+ } PCU_PSTAT_32B_tag;
+
+
+
+ typedef struct PCU_struct_tag { /* start of PCU_tag */
+ union {
+ /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
+ PCU_PCONF_32B_tag PCONF[16]; /* offset: 0x0000 (0x0004 x 16) */
+
+ struct {
+ /* PCU_PCONF[0..15] - Power Domain #0..#15 Configuration Register */
+ PCU_PCONF_32B_tag PCONF0; /* offset: 0x0000 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF1; /* offset: 0x0004 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF2; /* offset: 0x0008 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF3; /* offset: 0x000C size: 32 bit */
+ PCU_PCONF_32B_tag PCONF4; /* offset: 0x0010 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF5; /* offset: 0x0014 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF6; /* offset: 0x0018 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF7; /* offset: 0x001C size: 32 bit */
+ PCU_PCONF_32B_tag PCONF8; /* offset: 0x0020 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF9; /* offset: 0x0024 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF10; /* offset: 0x0028 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF11; /* offset: 0x002C size: 32 bit */
+ PCU_PCONF_32B_tag PCONF12; /* offset: 0x0030 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF13; /* offset: 0x0034 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF14; /* offset: 0x0038 size: 32 bit */
+ PCU_PCONF_32B_tag PCONF15; /* offset: 0x003C size: 32 bit */
+ };
+
+ };
+ /* PCU_PSTAT - Power Domain Status Register */
+ PCU_PSTAT_32B_tag PSTAT; /* offset: 0x0040 size: 32 bit */
+ } PCU_tag;
+
+
+#define PCU (*(volatile PCU_tag *) 0xC3FE8000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PMUCTRL */
+/* */
+/****************************************************************/
+
+ typedef union { /* PMUCTRL_STATHVD - PMU Status Register HVD */
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t HVDT_LPB:5; /* High Voltage Detector trimming bits LPB bus */
+ vuint32_t:6;
+ vuint32_t HVD_M:1; /* High Voltage Detector Main */
+ vuint32_t HVD_B:1; /* High Voltage Detector Backup */
+ vuint32_t:4;
+ vuint32_t HVD_LP:4; /* High Voltage Detector trimming bits LP bus */
+ } B;
+ } PMUCTRL_STATHVD_32B_tag;
+
+ typedef union { /* PMUCTRL_STATLVD - PMU Status Register LVD */
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t LVDT_LPB:5; /* Ligh Voltage Detector trimming bits LPB bus */
+ vuint32_t:6;
+ vuint32_t LVD_M:1; /* Ligh Voltage Detector Main */
+ vuint32_t LVD_B:1; /* Ligh Voltage Detector Backup */
+ vuint32_t:4;
+ vuint32_t LVD_LP:4; /* Ligh Voltage Detector trimming bits LP bus */
+ } B;
+ } PMUCTRL_STATLVD_32B_tag;
+
+ typedef union { /* PMUCTRL_STATIREG - PMU Status Register IREG */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IIREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
+ } B;
+ } PMUCTRL_STATIREG_32B_tag;
+
+ typedef union { /* PMUCTRL_STATEREG - PMU Status Register EREG */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t EEREG_HP:4; /* Internal ballast REGulator hpreg1 trimming bits */
+ } B;
+ } PMUCTRL_STATEREG_32B_tag;
+
+ typedef union { /* PMUCTRL_STATUS - PMU Status Register STATUS */
+ vuint32_t R;
+ struct {
+ vuint32_t EBMM:1; /* External Ballast Management Mode */
+ vuint32_t AEBD:1; /* Automatic External Ballast Detection */
+ vuint32_t ENPN:1; /* External NPN status flag */
+ vuint32_t:13;
+ vuint32_t CTB:2; /* Configuration Trace Bits */
+ vuint32_t:6;
+ vuint32_t CBS:4; /* Current BIST Status */
+ vuint32_t CPCS:4; /* Current Pmu Configuration Status */
+ } B;
+ } PMUCTRL_STATUS_32B_tag;
+
+ typedef union { /* PMUCTRL_CTRL - PMU Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t SILHT:2; /* Start Idle or LVD or HVD BIST Test */
+ } B;
+ } PMUCTRL_CTRL_32B_tag;
+
+ typedef union { /* PMUCTRL_MASKF - PMU Mask Fault Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MF_BB:4; /* Mask Fault Bypass Balast */
+ vuint32_t:28;
+ } B;
+ } PMUCTRL_MASKF_32B_tag;
+
+ typedef union { /* PMUCTRL_FAULT - PMU Fault Monitor Register */
+ vuint32_t R;
+ struct {
+ vuint32_t BB_LV:4; /* Bypass Ballast Low Voltage */
+ vuint32_t:9;
+ vuint32_t FLNCF:1; /* FLash voltage monitor Non Critical Fault */
+ vuint32_t IONCF:1; /* IO voltage monitor Non Critical Fault */
+ vuint32_t RENCF:1; /* REgulator voltage monitor Non Critical Fault */
+ vuint32_t:13;
+ vuint32_t LHCF:1; /* Low High voltage detector Critical Fault */
+ vuint32_t LNCF:1; /* Low voltage detector Non Critical Fault */
+ vuint32_t HNCF:1; /* High voltage detector Non Critical Fault */
+ } B;
+ } PMUCTRL_FAULT_32B_tag;
+
+ typedef union { /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t MFVMP:1; /* Main Flash Voltage Monitor interrupt Pending */
+ vuint32_t BFVMP:1; /* Backup Flash Voltage Monitor interrupt Pending */
+ vuint32_t MIVMP:1; /* MAin IO Voltage Monitor interrupt Pending */
+ vuint32_t BIVMP:1; /* Backup IO Voltage Monitor interrupt Pending */
+ vuint32_t MRVMP:1; /* Main Regulator Voltage Monitor interrupt Pending */
+ vuint32_t BRVMP:1; /* Backup Regulator Voltage Monitor interrupt Pending */
+ vuint32_t:12;
+ vuint32_t MLVDP:1; /* Main Low Voltage Detector error interrupt Pending */
+ vuint32_t BLVDP:1; /* Backup Low Voltage Detector error interrupt Pending */
+ vuint32_t MHVDP:1; /* Main High Voltage Detector error interrupt Pending */
+ vuint32_t BHVDP:1; /* Backup High Voltage Detector error interrupt Pending */
+ } B;
+ } PMUCTRL_IRQS_32B_tag;
+
+ typedef union { /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t MFVME:1; /* Main Flash Voltage Monitor interrupt Enable */
+ vuint32_t BFVME:1; /* Backup Flash Voltage Monitor interrupt Enable */
+ vuint32_t MIVME:1; /* MAin IO Voltage Monitor interrupt Enable */
+ vuint32_t BIVME:1; /* Backup IO Voltage Monitor interrupt Enable */
+ vuint32_t MRVME:1; /* Main Regulator Voltage Monitor interrupt Enable */
+ vuint32_t BRVME:1; /* Backup Regulator Voltage Monitor interrupt Enable */
+ vuint32_t:12;
+ vuint32_t MLVDE:1; /* Main Low Voltage Detector error interrupt Enable */
+ vuint32_t BLVDE:1; /* Backup Low Voltage Detector error interrupt Enable */
+ vuint32_t MHVDE:1; /* Main High Voltage Detector error interrupt Enable */
+ vuint32_t BHVDE:1; /* Backup High Voltage Detector error interrupt Enable */
+ } B;
+ } PMUCTRL_IRQE_32B_tag;
+
+
+
+ typedef struct PMUCTRL_struct_tag { /* start of PMUCTRL_tag */
+ int8_t PMUCTRL_reserved_0000[4];
+ /* PMUCTRL_STATHVD - PMU Status Register HVD */
+ PMUCTRL_STATHVD_32B_tag STATHVD; /* offset: 0x0004 size: 32 bit */
+ /* PMUCTRL_STATLVD - PMU Status Register LVD */
+ PMUCTRL_STATLVD_32B_tag STATLVD; /* offset: 0x0008 size: 32 bit */
+ int8_t PMUCTRL_reserved_000C[20];
+ /* PMUCTRL_STATIREG - PMU Status Register IREG */
+ PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */
+ /* PMUCTRL_STATEREG - PMU Status Register EREG */
+ PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */
+ int8_t PMUCTRL_reserved_0028[24];
+ /* PMUCTRL_STATUS - PMU Status Register STATUS */
+ PMUCTRL_STATUS_32B_tag STATUS; /* offset: 0x0040 size: 32 bit */
+ /* PMUCTRL_CTRL - PMU Control Register */
+ PMUCTRL_CTRL_32B_tag CTRL; /* offset: 0x0044 size: 32 bit */
+ int8_t PMUCTRL_reserved_0048[40];
+ /* PMUCTRL_MASKF - PMU Mask Fault Register */
+ PMUCTRL_MASKF_32B_tag MASKF; /* offset: 0x0070 size: 32 bit */
+ /* PMUCTRL_FAULT - PMU Fault Monitor Register */
+ PMUCTRL_FAULT_32B_tag FAULT; /* offset: 0x0074 size: 32 bit */
+ /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
+ PMUCTRL_IRQS_32B_tag IRQS; /* offset: 0x0078 size: 32 bit */
+ /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
+ PMUCTRL_IRQE_32B_tag IRQE; /* offset: 0x007C size: 32 bit */
+ } PMUCTRL_tag;
+
+
+#define PMUCTRL (*(volatile PMUCTRL_tag *) 0xC3FE8080UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: PIT_RTI */
+/* */
+/****************************************************************/
+
+ typedef union { /* PIT_RTI_PITMCR - PIT Module Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t MDIS:1; /* Module Disable. Disable the module clock */
+ vuint32_t FRZ:1; /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */
+ } B;
+ } PIT_RTI_PITMCR_32B_tag;
+
+
+ /* Register layout for all registers LDVAL... */
+
+ typedef union { /* PIT_RTI_LDVAL - Timer Load Value Register */
+ vuint32_t R;
+ struct {
+ vuint32_t TSV:32; /* Time Start Value Bits */
+ } B;
+ } PIT_RTI_LDVAL_32B_tag;
+
+
+ /* Register layout for all registers CVAL... */
+
+ typedef union { /* PIT_RTI_CVAL - Current Timer Value Register */
+ vuint32_t R;
+ struct {
+ vuint32_t TVL:32; /* Current Timer Value Bits */
+ } B;
+ } PIT_RTI_CVAL_32B_tag;
+
+
+ /* Register layout for all registers TCTRL... */
+
+ typedef union { /* PIT_RTI_TCTRL - Timer Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t TIE:1; /* Timer Interrupt Enable Bit */
+ vuint32_t TEN:1; /* Timer Enable Bit */
+ } B;
+ } PIT_RTI_TCTRL_32B_tag;
+
+
+ /* Register layout for all registers TFLG... */
+
+ typedef union { /* PIT_RTI_TFLG - Timer Flag Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1; /* Timer Interrupt Flag Bit */
+ } B;
+ } PIT_RTI_TFLG_32B_tag;
+
+
+ typedef struct PIT_RTI_CHANNEL_struct_tag {
+
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL; /* relative offset: 0x0000 */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL; /* relative offset: 0x0004 */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL; /* relative offset: 0x0008 */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG; /* relative offset: 0x000C */
+
+ } PIT_RTI_CHANNEL_tag;
+
+
+ typedef struct PIT_RTI_struct_tag { /* start of PIT_RTI_tag */
+ /* PIT_RTI_PITMCR - PIT Module Control Register */
+ PIT_RTI_PITMCR_32B_tag PITMCR; /* offset: 0x0000 size: 32 bit */
+ int8_t PIT_RTI_reserved_0004_C[252];
+ union {
+ /* Register set CHANNEL */
+ PIT_RTI_CHANNEL_tag CHANNEL[4]; /* offset: 0x0100 (0x0010 x 4) */
+
+ struct {
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL0; /* offset: 0x0100 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL0; /* offset: 0x0104 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL0; /* offset: 0x0108 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG0; /* offset: 0x010C size: 32 bit */
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL1; /* offset: 0x0110 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL1; /* offset: 0x0114 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL1; /* offset: 0x0118 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG1; /* offset: 0x011C size: 32 bit */
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL2; /* offset: 0x0120 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL2; /* offset: 0x0124 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL2; /* offset: 0x0128 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG2; /* offset: 0x012C size: 32 bit */
+ /* PIT_RTI_LDVAL - Timer Load Value Register */
+ PIT_RTI_LDVAL_32B_tag LDVAL3; /* offset: 0x0130 size: 32 bit */
+ /* PIT_RTI_CVAL - Current Timer Value Register */
+ PIT_RTI_CVAL_32B_tag CVAL3; /* offset: 0x0134 size: 32 bit */
+ /* PIT_RTI_TCTRL - Timer Control Register */
+ PIT_RTI_TCTRL_32B_tag TCTRL3; /* offset: 0x0138 size: 32 bit */
+ /* PIT_RTI_TFLG - Timer Flag Register */
+ PIT_RTI_TFLG_32B_tag TFLG3; /* offset: 0x013C size: 32 bit */
+ };
+
+ };
+ } PIT_RTI_tag;
+
+
+#define PIT_RTI (*(volatile PIT_RTI_tag *) 0xC3FF0000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: ADC */
+/* */
+/****************************************************************/
+
+ typedef union { /* module configuration register */
+ vuint32_t R;
+ struct {
+ vuint32_t OWREN:1; /* Overwrite enable */
+ vuint32_t WLSIDE:1; /* Write Left/right Alligned */
+ vuint32_t MODE:1; /* One Shot/Scan Mode Selectiom */
+ vuint32_t EDGLEV:1; /* edge or level selection for external start trigger */
+ vuint32_t TRGEN:1; /* external trigger enable */
+ vuint32_t EDGE:1; /* start trigger egde /level detection */
+ vuint32_t XSTRTEN:1; /* EXTERNAL START ENABLE */
+ vuint32_t NSTART:1; /* start normal conversion */
+ vuint32_t:1;
+ vuint32_t JTRGEN:1; /* Injectin External Trigger Enable */
+ vuint32_t JEDGE:1; /* start trigger egde /level detection for injected */
+ vuint32_t JSTART:1; /* injected conversion start */
+ vuint32_t:2;
+ vuint32_t CTUEN:1; /* CTU enabaled */
+ vuint32_t:8;
+ vuint32_t ADCLKSEL:1; /* Select which clock for device */
+ vuint32_t ABORTCHAIN:1; /* abort chain conversion */
+ vuint32_t ABORT:1; /* abort current conversion */
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t ACKO:1; /* Auto Clock Off Enable */
+#else
+ vuint32_t ACK0:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t OFFREFRESH:1; /* offset phase selection */
+ vuint32_t OFFCANC:1; /* offset phase cancellation selection */
+ vuint32_t:2;
+ vuint32_t PWDN:1; /* Power Down Enable */
+ } B;
+ } ADC_MCR_32B_tag;
+
+ typedef union { /* module status register */
+ vuint32_t R;
+ struct {
+ vuint32_t:7;
+ vuint32_t NSTART:1; /* normal conversion status */
+ vuint32_t JABORT:1; /* Injection chain abort status */
+ vuint32_t:2;
+ vuint32_t JSTART:1; /* Injection Start status */
+ vuint32_t:3;
+ vuint32_t CTUSTART:1; /* ctu start status */
+ vuint32_t CHADDR:7; /* which address conv is goin on */
+ vuint32_t:3;
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t ACKO:1; /* Auto Clock Off Enable status */
+#else
+ vuint32_t ACK0:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t OFFREFRESH:1; /* offset refresh status */
+ vuint32_t OFFCANC:1; /* offset phase cancellation status */
+ vuint32_t ADCSTATUS:3; /* status of ADC FSM */
+ } B;
+ } ADC_MSR_32B_tag;
+
+ typedef union { /* Interrupt status register */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t OFFCANCOVR:1; /* Offset cancellation phase over */
+ vuint32_t EOFFSET:1; /* error in offset refresh */
+ vuint32_t EOCTU:1; /* end of CTU channel conversion */
+ vuint32_t JEOC:1; /* end of injected channel conversion */
+ vuint32_t JECH:1; /* end ofinjected chain conversion */
+ vuint32_t EOC:1; /* end of channel conversion */
+ vuint32_t ECH:1; /* end of chain conversion */
+ } B;
+ } ADC_ISR_32B_tag;
+
+ typedef union { /* CHANNEL PENDING REGISTER 0 */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH31:1; /* Channel 31 conversion over */
+#else
+ vuint32_t EOC31:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH30:1; /* Channel 30 conversion over */
+#else
+ vuint32_t EOC30:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH29:1; /* Channel 29 conversion over */
+#else
+ vuint32_t EOC29:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH28:1; /* Channel 28 conversion over */
+#else
+ vuint32_t EOC28:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH27:1; /* Channel 27 conversion over */
+#else
+ vuint32_t EOC27:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH26:1; /* Channel 26 conversion over */
+#else
+ vuint32_t EOC26:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH25:1; /* Channel 25 conversion over */
+#else
+ vuint32_t EOC25:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH24:1; /* Channel 24 conversion over */
+#else
+ vuint32_t EOC24:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH23:1; /* Channel 23 conversion over */
+#else
+ vuint32_t EOC23:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH22:1; /* Channel 22 conversion over */
+#else
+ vuint32_t EOC22:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH21:1; /* Channel 21 conversion over */
+#else
+ vuint32_t EOC21:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH20:1; /* Channel 20 conversion over */
+#else
+ vuint32_t EOC20:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH19:1; /* Channel 19 conversion over */
+#else
+ vuint32_t EOC19:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH18:1; /* Channel 18 conversion over */
+#else
+ vuint32_t EOC18:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH17:1; /* Channel 17 conversion over */
+#else
+ vuint32_t EOC17:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH16:1; /* Channel 16 conversion over */
+#else
+ vuint32_t EOC16:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH15:1; /* Channel 15 conversion over */
+#else
+ vuint32_t EOC15:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH14:1; /* Channel 14 conversion over */
+#else
+ vuint32_t EOC14:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH13:1; /* Channel 13 conversion over */
+#else
+ vuint32_t EOC13:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH12:1; /* Channel 12 conversion over */
+#else
+ vuint32_t EOC12:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH11:1; /* Channel 11 conversion over */
+#else
+ vuint32_t EOC11:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH10:1; /* Channel 10 conversion over */
+#else
+ vuint32_t EOC10:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH9:1; /* Channel 9 conversion over */
+#else
+ vuint32_t EOC9:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH8:1; /* Channel 8 conversion over */
+#else
+ vuint32_t EOC8:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH7:1; /* Channel 7 conversion over */
+#else
+ vuint32_t EOC7:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH6:1; /* Channel 6 conversion over */
+#else
+ vuint32_t EOC6:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH5:1; /* Channel 5 conversion over */
+#else
+ vuint32_t EOC5:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH4:1; /* Channel 4 conversion over */
+#else
+ vuint32_t EOC4:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH3:1; /* Channel 3 conversion over */
+#else
+ vuint32_t EOC3:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH2:1; /* Channel 2 conversion over */
+#else
+ vuint32_t EOC2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH1:1; /* Channel 1 conversion over */
+#else
+ vuint32_t EOC1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t EOC_CH0:1; /* Channel 0 conversion over */
+#else
+ vuint32_t EOC0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ADC_CEOCFR0_32B_tag;
+
+ typedef union { /* CHANNEL PENDING REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH63:1; /* Channel 63 conversion over */
+ vuint32_t EOC_CH62:1; /* Channel 62 conversion over */
+ vuint32_t EOC_CH61:1; /* Channel 61 conversion over */
+ vuint32_t EOC_CH60:1; /* Channel 60 conversion over */
+ vuint32_t EOC_CH59:1; /* Channel 59 conversion over */
+ vuint32_t EOC_CH58:1; /* Channel 58 conversion over */
+ vuint32_t EOC_CH57:1; /* Channel 57 conversion over */
+ vuint32_t EOC_CH56:1; /* Channel 56 conversion over */
+ vuint32_t EOC_CH55:1; /* Channel 55 conversion over */
+ vuint32_t EOC_CH54:1; /* Channel 54 conversion over */
+ vuint32_t EOC_CH53:1; /* Channel 53 conversion over */
+ vuint32_t EOC_CH52:1; /* Channel 52 conversion over */
+ vuint32_t EOC_CH51:1; /* Channel 51 conversion over */
+ vuint32_t EOC_CH50:1; /* Channel 50 conversion over */
+ vuint32_t EOC_CH49:1; /* Channel 49 conversion over */
+ vuint32_t EOC_CH48:1; /* Channel 48 conversion over */
+ vuint32_t EOC_CH47:1; /* Channel 47 conversion over */
+ vuint32_t EOC_CH46:1; /* Channel 46 conversion over */
+ vuint32_t EOC_CH45:1; /* Channel 45 conversion over */
+ vuint32_t EOC_CH44:1; /* Channel 44 conversion over */
+ vuint32_t EOC_CH43:1; /* Channel 43 conversion over */
+ vuint32_t EOC_CH42:1; /* Channel 42 conversion over */
+ vuint32_t EOC_CH41:1; /* Channel 41 conversion over */
+ vuint32_t EOC_CH40:1; /* Channel 40 conversion over */
+ vuint32_t EOC_CH39:1; /* Channel 39 conversion over */
+ vuint32_t EOC_CH38:1; /* Channel 38 conversion over */
+ vuint32_t EOC_CH37:1; /* Channel 37 conversion over */
+ vuint32_t EOC_CH36:1; /* Channel 36 conversion over */
+ vuint32_t EOC_CH35:1; /* Channel 35 conversion over */
+ vuint32_t EOC_CH34:1; /* Channel 34 conversion over */
+ vuint32_t EOC_CH33:1; /* Channel 33 conversion over */
+ vuint32_t EOC_CH32:1; /* Channel 32 conversion over */
+ } B;
+ } ADC_CEOCFR1_32B_tag;
+
+ typedef union { /* CHANNEL PENDING REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t EOC_CH95:1; /* Channel 95 conversion over */
+ vuint32_t EOC_CH94:1; /* Channel 94 conversion over */
+ vuint32_t EOC_CH93:1; /* Channel 93 conversion over */
+ vuint32_t EOC_CH92:1; /* Channel 92 conversion over */
+ vuint32_t EOC_CH91:1; /* Channel 91 conversion over */
+ vuint32_t EOC_CH90:1; /* Channel 90 conversion over */
+ vuint32_t EOC_CH89:1; /* Channel 89 conversion over */
+ vuint32_t EOC_CH88:1; /* Channel 88 conversion over */
+ vuint32_t EOC_CH87:1; /* Channel 87 conversion over */
+ vuint32_t EOC_CH86:1; /* Channel 86 conversion over */
+ vuint32_t EOC_CH85:1; /* Channel 85 conversion over */
+ vuint32_t EOC_CH84:1; /* Channel 84 conversion over */
+ vuint32_t EOC_CH83:1; /* Channel 83 conversion over */
+ vuint32_t EOC_CH82:1; /* Channel 82 conversion over */
+ vuint32_t EOC_CH81:1; /* Channel 81 conversion over */
+ vuint32_t EOC_CH80:1; /* Channel 80 conversion over */
+ vuint32_t EOC_CH79:1; /* Channel 79 conversion over */
+ vuint32_t EOC_CH78:1; /* Channel 78 conversion over */
+ vuint32_t EOC_CH77:1; /* Channel 77 conversion over */
+ vuint32_t EOC_CH76:1; /* Channel 76 conversion over */
+ vuint32_t EOC_CH75:1; /* Channel 75 conversion over */
+ vuint32_t EOC_CH74:1; /* Channel 74 conversion over */
+ vuint32_t EOC_CH73:1; /* Channel 73 conversion over */
+ vuint32_t EOC_CH72:1; /* Channel 72 conversion over */
+ vuint32_t EOC_CH71:1; /* Channel 71 conversion over */
+ vuint32_t EOC_CH70:1; /* Channel 70 conversion over */
+ vuint32_t EOC_CH69:1; /* Channel 69 conversion over */
+ vuint32_t EOC_CH68:1; /* Channel 68 conversion over */
+ vuint32_t EOC_CH67:1; /* Channel 67 conversion over */
+ vuint32_t EOC_CH66:1; /* Channel 66 conversion over */
+ vuint32_t EOC_CH65:1; /* Channel 65 conversion over */
+ vuint32_t EOC_CH64:1; /* Channel 64 conversion over */
+ } B;
+ } ADC_CEOCFR2_32B_tag;
+
+ typedef union { /* interrupt mask register */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t MSKOFFCANCOVR:1; /* mask bit for Calibration over */
+ vuint32_t MSKEOFFSET:1; /* mask bit for Error in offset refresh */
+ vuint32_t MSKEOCTU:1; /* mask bit for EOCTU */
+ vuint32_t MSKJEOC:1; /* mask bit for JEOC */
+ vuint32_t MSKJECH:1; /* mask bit for JECH */
+ vuint32_t MSKEOC:1; /* mask bit for EOC */
+ vuint32_t MSKECH:1; /* mask bit for ECH */
+ } B;
+ } ADC_IMR_32B_tag;
+
+ typedef union { /* CHANNEL INTERRUPT MASK REGISTER 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIM31:1; /* Channel 31 mask register */
+ vuint32_t CIM30:1; /* Channel 30 mask register */
+ vuint32_t CIM29:1; /* Channel 29 mask register */
+ vuint32_t CIM28:1; /* Channel 28 mask register */
+ vuint32_t CIM27:1; /* Channel 27 mask register */
+ vuint32_t CIM26:1; /* Channel 26 mask register */
+ vuint32_t CIM25:1; /* Channel 25 mask register */
+ vuint32_t CIM24:1; /* Channel 24 mask register */
+ vuint32_t CIM23:1; /* Channel 23 mask register */
+ vuint32_t CIM22:1; /* Channel 22 mask register */
+ vuint32_t CIM21:1; /* Channel 21 mask register */
+ vuint32_t CIM20:1; /* Channel 20 mask register */
+ vuint32_t CIM19:1; /* Channel 19 mask register */
+ vuint32_t CIM18:1; /* Channel 18 mask register */
+ vuint32_t CIM17:1; /* Channel 17 mask register */
+ vuint32_t CIM16:1; /* Channel 16 mask register */
+ vuint32_t CIM15:1; /* Channel 15 mask register */
+ vuint32_t CIM14:1; /* Channel 14 mask register */
+ vuint32_t CIM13:1; /* Channel 13 mask register */
+ vuint32_t CIM12:1; /* Channel 12 mask register */
+ vuint32_t CIM11:1; /* Channel 11 mask register */
+ vuint32_t CIM10:1; /* Channel 10 mask register */
+ vuint32_t CIM9:1; /* Channel 9 mask register */
+ vuint32_t CIM8:1; /* Channel 8 mask register */
+ vuint32_t CIM7:1; /* Channel 7 mask register */
+ vuint32_t CIM6:1; /* Channel 6 mask register */
+ vuint32_t CIM5:1; /* Channel 5 mask register */
+ vuint32_t CIM4:1; /* Channel 4 mask register */
+ vuint32_t CIM3:1; /* Channel 3 mask register */
+ vuint32_t CIM2:1; /* Channel 2 mask register */
+ vuint32_t CIM1:1; /* Channel 1 mask register */
+ vuint32_t CIM0:1; /* Channel 0 mask register */
+ } B;
+ } ADC_CIMR0_32B_tag;
+
+ typedef union { /* CHANNEL INTERRUPT MASK REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIM63:1; /* Channel 63 mask register */
+ vuint32_t CIM62:1; /* Channel 62 mask register */
+ vuint32_t CIM61:1; /* Channel 61 mask register */
+ vuint32_t CIM60:1; /* Channel 60 mask register */
+ vuint32_t CIM59:1; /* Channel 59 mask register */
+ vuint32_t CIM58:1; /* Channel 58 mask register */
+ vuint32_t CIM57:1; /* Channel 57 mask register */
+ vuint32_t CIM56:1; /* Channel 56 mask register */
+ vuint32_t CIM55:1; /* Channel 55 mask register */
+ vuint32_t CIM54:1; /* Channel 54 mask register */
+ vuint32_t CIM53:1; /* Channel 53 mask register */
+ vuint32_t CIM52:1; /* Channel 52 mask register */
+ vuint32_t CIM51:1; /* Channel 51 mask register */
+ vuint32_t CIM50:1; /* Channel 50 mask register */
+ vuint32_t CIM49:1; /* Channel 49 mask register */
+ vuint32_t CIM48:1; /* Channel 48 mask register */
+ vuint32_t CIM47:1; /* Channel 47 mask register */
+ vuint32_t CIM46:1; /* Channel 46 mask register */
+ vuint32_t CIM45:1; /* Channel 45 mask register */
+ vuint32_t CIM44:1; /* Channel 44 mask register */
+ vuint32_t CIM43:1; /* Channel 43 mask register */
+ vuint32_t CIM42:1; /* Channel 42 mask register */
+ vuint32_t CIM41:1; /* Channel 41 mask register */
+ vuint32_t CIM40:1; /* Channel 40 mask register */
+ vuint32_t CIM39:1; /* Channel 39 mask register */
+ vuint32_t CIM38:1; /* Channel 38 mask register */
+ vuint32_t CIM37:1; /* Channel 37 mask register */
+ vuint32_t CIM36:1; /* Channel 36 mask register */
+ vuint32_t CIM35:1; /* Channel 35 mask register */
+ vuint32_t CIM34:1; /* Channel 34 mask register */
+ vuint32_t CIM33:1; /* Channel 33 mask register */
+ vuint32_t CIM32:1; /* Channel 32 mask register */
+ } B;
+ } ADC_CIMR1_32B_tag;
+
+ typedef union { /* CHANNEL INTERRUPT MASK REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t CIM95:1; /* Channel 95 mask register */
+ vuint32_t CIM94:1; /* Channel 94 mask register */
+ vuint32_t CIM93:1; /* Channel 93 mask register */
+ vuint32_t CIM92:1; /* Channel 92 mask register */
+ vuint32_t CIM91:1; /* Channel 91 mask register */
+ vuint32_t CIM90:1; /* Channel 90 mask register */
+ vuint32_t CIM89:1; /* Channel 89 mask register */
+ vuint32_t CIM88:1; /* Channel 88 mask register */
+ vuint32_t CIM87:1; /* Channel 87 mask register */
+ vuint32_t CIM86:1; /* Channel 86 mask register */
+ vuint32_t CIM85:1; /* Channel 85 mask register */
+ vuint32_t CIM84:1; /* Channel 84 mask register */
+ vuint32_t CIM83:1; /* Channel 83 mask register */
+ vuint32_t CIM82:1; /* Channel 82 mask register */
+ vuint32_t CIM81:1; /* Channel 81 mask register */
+ vuint32_t CIM80:1; /* Channel 80 mask register */
+ vuint32_t CIM79:1; /* Channel 79 mask register */
+ vuint32_t CIM78:1; /* Channel 78 mask register */
+ vuint32_t CIM77:1; /* Channel 77 mask register */
+ vuint32_t CIM76:1; /* Channel 76 mask register */
+ vuint32_t CIM75:1; /* Channel 75 mask register */
+ vuint32_t CIM74:1; /* Channel 74 mask register */
+ vuint32_t CIM73:1; /* Channel 73 mask register */
+ vuint32_t CIM72:1; /* Channel 72 mask register */
+ vuint32_t CIM71:1; /* Channel 71 mask register */
+ vuint32_t CIM70:1; /* Channel 70 mask register */
+ vuint32_t CIM69:1; /* Channel 69 mask register */
+ vuint32_t CIM68:1; /* Channel 68 mask register */
+ vuint32_t CIM67:1; /* Channel 67 mask register */
+ vuint32_t CIM66:1; /* Channel 66 mask register */
+ vuint32_t CIM65:1; /* Channel 65 mask register */
+ vuint32_t CIM64:1; /* Channel 64 mask register */
+ } B;
+ } ADC_CIMR2_32B_tag;
+
+ typedef union { /* Watchdog Threshold interrupt status register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t WDG3H:1; /* Interrupt generated on the value being higher than the HTHV 3 */
+ vuint32_t WDG2H:1; /* Interrupt generated on the value being higher than the HTHV 2 */
+ vuint32_t WDG1H:1; /* Interrupt generated on the value being higher than the HTHV 1 */
+ vuint32_t WDG0H:1; /* Interrupt generated on the value being higher than the HTHV 0 */
+ vuint32_t WDG3L:1; /* Interrupt generated on the value being lower than the LTHV 3 */
+ vuint32_t WDG2L:1; /* Interrupt generated on the value being lower than the LTHV 2 */
+ vuint32_t WDG1L:1; /* Interrupt generated on the value being lower than the LTHV 1 */
+ vuint32_t WDG0L:1; /* Interrupt generated on the value being lower than the LTHV 0 */
+ } B;
+ } ADC_WTISR_32B_tag;
+
+ typedef union { /* Watchdog interrupt MASK register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t MSKWDG3H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */
+ vuint32_t MSKWDG2H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 2 */
+ vuint32_t MSKWDG1H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */
+ vuint32_t MSKWDG0H:1; /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */
+ vuint32_t MSKWDG3L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */
+ vuint32_t MSKWDG2L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */
+ vuint32_t MSKWDG1L:1; /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */
+ vuint32_t MSKWDG0L:1; /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */
+ } B;
+ } ADC_WTIMR_32B_tag;
+
+ typedef union { /* DMAE register */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t DCLR:1; /* DMA clear sequence enable */
+ vuint32_t DMAEN:1; /* DMA global enable */
+ } B;
+ } ADC_DMAE_32B_tag;
+
+ typedef union { /* DMA REGISTER 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t DMA31:1; /* Channel 31 DMA Enable */
+ vuint32_t DMA30:1; /* Channel 30 DMA Enable */
+ vuint32_t DMA29:1; /* Channel 29 DMA Enable */
+ vuint32_t DMA28:1; /* Channel 28 DMA Enable */
+ vuint32_t DMA27:1; /* Channel 27 DMA Enable */
+ vuint32_t DMA26:1; /* Channel 26 DMA Enable */
+ vuint32_t DMA25:1; /* Channel 25 DMA Enable */
+ vuint32_t DMA24:1; /* Channel 24 DMA Enable */
+ vuint32_t DMA23:1; /* Channel 23 DMA Enable */
+ vuint32_t DMA22:1; /* Channel 22 DMA Enable */
+ vuint32_t DMA21:1; /* Channel 21 DMA Enable */
+ vuint32_t DMA20:1; /* Channel 20 DMA Enable */
+ vuint32_t DMA19:1; /* Channel 19 DMA Enable */
+ vuint32_t DMA18:1; /* Channel 18 DMA Enable */
+ vuint32_t DMA17:1; /* Channel 17 DMA Enable */
+ vuint32_t DMA16:1; /* Channel 16 DMA Enable */
+ vuint32_t DMA15:1; /* Channel 15 DMA Enable */
+ vuint32_t DMA14:1; /* Channel 14 DMA Enable */
+ vuint32_t DMA13:1; /* Channel 13 DMA Enable */
+ vuint32_t DMA12:1; /* Channel 12 DMA Enable */
+ vuint32_t DMA11:1; /* Channel 11 DMA Enable */
+ vuint32_t DMA10:1; /* Channel 10 DMA Enable */
+ vuint32_t DMA9:1; /* Channel 9 DMA Enable */
+ vuint32_t DMA8:1; /* Channel 8 DMA Enable */
+ vuint32_t DMA7:1; /* Channel 7 DMA Enable */
+ vuint32_t DMA6:1; /* Channel 6 DMA Enable */
+ vuint32_t DMA5:1; /* Channel 5 DMA Enable */
+ vuint32_t DMA4:1; /* Channel 4 DMA Enable */
+ vuint32_t DMA3:1; /* Channel 3 DMA Enable */
+ vuint32_t DMA2:1; /* Channel 2 DMA Enable */
+ vuint32_t DMA1:1; /* Channel 1 DMA Enable */
+ vuint32_t DMA0:1; /* Channel 0 DMA Enable */
+ } B;
+ } ADC_DMAR0_32B_tag;
+
+ typedef union { /* DMA REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t DMA63:1; /* Channel 63 DMA Enable */
+ vuint32_t DMA62:1; /* Channel 62 DMA Enable */
+ vuint32_t DMA61:1; /* Channel 61 DMA Enable */
+ vuint32_t DMA60:1; /* Channel 60 DMA Enable */
+ vuint32_t DMA59:1; /* Channel 59 DMA Enable */
+ vuint32_t DMA58:1; /* Channel 58 DMA Enable */
+ vuint32_t DMA57:1; /* Channel 57 DMA Enable */
+ vuint32_t DMA56:1; /* Channel 56 DMA Enable */
+ vuint32_t DMA55:1; /* Channel 55 DMA Enable */
+ vuint32_t DMA54:1; /* Channel 54 DMA Enable */
+ vuint32_t DMA53:1; /* Channel 53 DMA Enable */
+ vuint32_t DMA52:1; /* Channel 52 DMA Enable */
+ vuint32_t DMA51:1; /* Channel 51 DMA Enable */
+ vuint32_t DMA50:1; /* Channel 50 DMA Enable */
+ vuint32_t DMA49:1; /* Channel 49 DMA Enable */
+ vuint32_t DMA48:1; /* Channel 48 DMA Enable */
+ vuint32_t DMA47:1; /* Channel 47 DMA Enable */
+ vuint32_t DMA46:1; /* Channel 46 DMA Enable */
+ vuint32_t DMA45:1; /* Channel 45 DMA Enable */
+ vuint32_t DMA44:1; /* Channel 44 DMA Enable */
+ vuint32_t DMA43:1; /* Channel 43 DMA Enable */
+ vuint32_t DMA42:1; /* Channel 42 DMA Enable */
+ vuint32_t DMA41:1; /* Channel 41 DMA Enable */
+ vuint32_t DMA40:1; /* Channel 40 DMA Enable */
+ vuint32_t DMA39:1; /* Channel 39 DMA Enable */
+ vuint32_t DMA38:1; /* Channel 38 DMA Enable */
+ vuint32_t DMA37:1; /* Channel 37 DMA Enable */
+ vuint32_t DMA36:1; /* Channel 36 DMA Enable */
+ vuint32_t DMA35:1; /* Channel 35 DMA Enable */
+ vuint32_t DMA34:1; /* Channel 34 DMA Enable */
+ vuint32_t DMA33:1; /* Channel 33 DMA Enable */
+ vuint32_t DMA32:1; /* Channel 32 DMA Enable */
+ } B;
+ } ADC_DMAR1_32B_tag;
+
+ typedef union { /* DMA REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t DMA95:1; /* Channel 95 DMA Enable */
+ vuint32_t DMA94:1; /* Channel 94 DMA Enable */
+ vuint32_t DMA93:1; /* Channel 93 DMA Enable */
+ vuint32_t DMA92:1; /* Channel 92 DMA Enable */
+ vuint32_t DMA91:1; /* Channel 91 DMA Enable */
+ vuint32_t DMA90:1; /* Channel 90 DMA Enable */
+ vuint32_t DMA89:1; /* Channel 89 DMA Enable */
+ vuint32_t DMA88:1; /* Channel 88 DMA Enable */
+ vuint32_t DMA87:1; /* Channel 87 DMA Enable */
+ vuint32_t DMA86:1; /* Channel 86 DMA Enable */
+ vuint32_t DMA85:1; /* Channel 85 DMA Enable */
+ vuint32_t DMA84:1; /* Channel 84 DMA Enable */
+ vuint32_t DMA83:1; /* Channel 83 DMA Enable */
+ vuint32_t DMA82:1; /* Channel 82 DMA Enable */
+ vuint32_t DMA81:1; /* Channel 81 DMA Enable */
+ vuint32_t DMA80:1; /* Channel 80 DMA Enable */
+ vuint32_t DMA79:1; /* Channel 79 DMA Enable */
+ vuint32_t DMA78:1; /* Channel 78 DMA Enable */
+ vuint32_t DMA77:1; /* Channel 77 DMA Enable */
+ vuint32_t DMA76:1; /* Channel 76 DMA Enable */
+ vuint32_t DMA75:1; /* Channel 75 DMA Enable */
+ vuint32_t DMA74:1; /* Channel 74 DMA Enable */
+ vuint32_t DMA73:1; /* Channel 73 DMA Enable */
+ vuint32_t DMA72:1; /* Channel 72 DMA Enable */
+ vuint32_t DMA71:1; /* Channel 71 DMA Enable */
+ vuint32_t DMA70:1; /* Channel 70 DMA Enable */
+ vuint32_t DMA69:1; /* Channel 69 DMA Enable */
+ vuint32_t DMA68:1; /* Channel 68 DMA Enable */
+ vuint32_t DMA67:1; /* Channel 67 DMA Enable */
+ vuint32_t DMA66:1; /* Channel 66 DMA Enable */
+ vuint32_t DMA65:1; /* Channel 65 DMA Enable */
+ vuint32_t DMA64:1; /* Channel 64 DMA Enable */
+ } B;
+ } ADC_DMAR2_32B_tag;
+
+
+ /* Register layout for all registers TRC... */
+
+ typedef union { /* Threshold Control register C */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t THREN:1; /* Threshold enable */
+ vuint32_t THRINV:1; /* invert the output pin */
+ vuint32_t THROP:1; /* output pin register */
+ vuint32_t:6;
+ vuint32_t THRCH:7; /* Choose channel for threshold register */
+ } B;
+ } ADC_TRC_32B_tag;
+
+
+ /* Register layout for all registers THRHLR... */
+
+ typedef union { /* Upper Threshold register */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR_32B_tag;
+
+
+ /* Register layout for all registers THRALT... */
+
+ typedef union { /* alternate Upper Threshold register */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t THRH:10; /* high threshold value s */
+ vuint32_t:6;
+ vuint32_t THRL:10; /* low threshold value s */
+ } B;
+ } ADC_THRALT_32B_tag;
+
+ typedef union { /* PRESAMPLING CONTROL REGISTER */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t PREVAL2:2; /* INternal Voltage selection for Presampling */
+ vuint32_t PREVAL1:2; /* INternal Voltage selection for Presampling */
+ vuint32_t PREVAL0:2; /* INternal Voltage selection for Presampling */
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t PRECONV:1; /* Presampled value */
+#else
+ vuint32_t PREONCE:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } ADC_PSCR_32B_tag;
+
+ typedef union { /* Presampling Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t PRES31:1; /* Channel 31 Presampling Enable */
+ vuint32_t PRES30:1; /* Channel 30 Presampling Enable */
+ vuint32_t PRES29:1; /* Channel 29 Presampling Enable */
+ vuint32_t PRES28:1; /* Channel 28 Presampling Enable */
+ vuint32_t PRES27:1; /* Channel 27 Presampling Enable */
+ vuint32_t PRES26:1; /* Channel 26 Presampling Enable */
+ vuint32_t PRES25:1; /* Channel 25 Presampling Enable */
+ vuint32_t PRES24:1; /* Channel 24 Presampling Enable */
+ vuint32_t PRES23:1; /* Channel 23 Presampling Enable */
+ vuint32_t PRES22:1; /* Channel 22 Presampling Enable */
+ vuint32_t PRES21:1; /* Channel 21 Presampling Enable */
+ vuint32_t PRES20:1; /* Channel 20 Presampling Enable */
+ vuint32_t PRES19:1; /* Channel 19 Presampling Enable */
+ vuint32_t PRES18:1; /* Channel 18 Presampling Enable */
+ vuint32_t PRES17:1; /* Channel 17 Presampling Enable */
+ vuint32_t PRES16:1; /* Channel 16 Presampling Enable */
+ vuint32_t PRES15:1; /* Channel 15 Presampling Enable */
+ vuint32_t PRES14:1; /* Channel 14 Presampling Enable */
+ vuint32_t PRES13:1; /* Channel 13 Presampling Enable */
+ vuint32_t PRES12:1; /* Channel 12 Presampling Enable */
+ vuint32_t PRES11:1; /* Channel 11 Presampling Enable */
+ vuint32_t PRES10:1; /* Channel 10 Presampling Enable */
+ vuint32_t PRES9:1; /* Channel 9 Presampling Enable */
+ vuint32_t PRES8:1; /* Channel 8 Presampling Enable */
+ vuint32_t PRES7:1; /* Channel 7 Presampling Enable */
+ vuint32_t PRES6:1; /* Channel 6 Presampling Enable */
+ vuint32_t PRES5:1; /* Channel 5 Presampling Enable */
+ vuint32_t PRES4:1; /* Channel 4 Presampling Enable */
+ vuint32_t PRES3:1; /* Channel 3 Presampling Enable */
+ vuint32_t PRES2:1; /* Channel 2 Presampling Enable */
+ vuint32_t PRES1:1; /* Channel 1presampling Enable */
+ vuint32_t PRES0:1; /* Channel 0 Presampling Enable */
+ } B;
+ } ADC_PSR0_32B_tag;
+
+ typedef union { /* Presampling REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t PRES63:1; /* Channel 63 Presampling Enable */
+ vuint32_t PRES62:1; /* Channel 62 Presampling Enable */
+ vuint32_t PRES61:1; /* Channel 61 Presampling Enable */
+ vuint32_t PRES60:1; /* Channel 60 Presampling Enable */
+ vuint32_t PRES59:1; /* Channel 59 Presampling Enable */
+ vuint32_t PRES58:1; /* Channel 58 Presampling Enable */
+ vuint32_t PRES57:1; /* Channel 57 Presampling Enable */
+ vuint32_t PRES56:1; /* Channel 56 Presampling Enable */
+ vuint32_t PRES55:1; /* Channel 55 Presampling Enable */
+ vuint32_t PRES54:1; /* Channel 54 Presampling Enable */
+ vuint32_t PRES53:1; /* Channel 53 Presampling Enable */
+ vuint32_t PRES52:1; /* Channel 52 Presampling Enable */
+ vuint32_t PRES51:1; /* Channel 51 Presampling Enable */
+ vuint32_t PRES50:1; /* Channel 50 Presampling Enable */
+ vuint32_t PRES49:1; /* Channel 49 Presampling Enable */
+ vuint32_t PRES48:1; /* Channel 48 Presampling Enable */
+ vuint32_t PRES47:1; /* Channel 47 Presampling Enable */
+ vuint32_t PRES46:1; /* Channel 46 Presampling Enable */
+ vuint32_t PRES45:1; /* Channel 45 Presampling Enable */
+ vuint32_t PRES44:1; /* Channel 44 Presampling Enable */
+ vuint32_t PRES43:1; /* Channel 43 Presampling Enable */
+ vuint32_t PRES42:1; /* Channel 42 Presampling Enable */
+ vuint32_t PRES41:1; /* Channel 41 Presampling Enable */
+ vuint32_t PRES40:1; /* Channel 40 Presampling Enable */
+ vuint32_t PRES39:1; /* Channel 39 Presampling Enable */
+ vuint32_t PRES38:1; /* Channel 38 Presampling Enable */
+ vuint32_t PRES37:1; /* Channel 37 Presampling Enable */
+ vuint32_t PRES36:1; /* Channel 36 Presampling Enable */
+ vuint32_t PRES35:1; /* Channel 35 Presampling Enable */
+ vuint32_t PRES34:1; /* Channel 34 Presampling Enable */
+ vuint32_t PRES33:1; /* Channel 33 Presampling Enable */
+ vuint32_t PRES32:1; /* Channel 32 Presampling Enable */
+ } B;
+ } ADC_PSR1_32B_tag;
+
+ typedef union { /* Presampling REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t PRES95:1; /* Channel 95 Presampling Enable */
+ vuint32_t PRES94:1; /* Channel 94 Presampling Enable */
+ vuint32_t PRES93:1; /* Channel 93 Presampling Enable */
+ vuint32_t PRES92:1; /* Channel 92 Presampling Enable */
+ vuint32_t PRES91:1; /* Channel 91 Presampling Enable */
+ vuint32_t PRES90:1; /* Channel 90 Presampling Enable */
+ vuint32_t PRES89:1; /* Channel 89 Presampling Enable */
+ vuint32_t PRES88:1; /* Channel 88 Presampling Enable */
+ vuint32_t PRES87:1; /* Channel 87 Presampling Enable */
+ vuint32_t PRES86:1; /* Channel 86 Presampling Enable */
+ vuint32_t PRES85:1; /* Channel 85 Presampling Enable */
+ vuint32_t PRES84:1; /* Channel 84 Presampling Enable */
+ vuint32_t PRES83:1; /* Channel 83 Presampling Enable */
+ vuint32_t PRES82:1; /* Channel 82 Presampling Enable */
+ vuint32_t PRES81:1; /* Channel 81 Presampling Enable */
+ vuint32_t PRES80:1; /* Channel 80 Presampling Enable */
+ vuint32_t PRES79:1; /* Channel 79 Presampling Enable */
+ vuint32_t PRES78:1; /* Channel 78 Presampling Enable */
+ vuint32_t PRES77:1; /* Channel 77 Presampling Enable */
+ vuint32_t PRES76:1; /* Channel 76 Presampling Enable */
+ vuint32_t PRES75:1; /* Channel 75 Presampling Enable */
+ vuint32_t PRES74:1; /* Channel 74 Presampling Enable */
+ vuint32_t PRES73:1; /* Channel 73 Presampling Enable */
+ vuint32_t PRES72:1; /* Channel 72 Presampling Enable */
+ vuint32_t PRES71:1; /* Channel 71 Presampling Enable */
+ vuint32_t PRES70:1; /* Channel 70 Presampling Enable */
+ vuint32_t PRES69:1; /* Channel 69 Presampling Enable */
+ vuint32_t PRES68:1; /* Channel 68 Presampling Enable */
+ vuint32_t PRES67:1; /* Channel 67 Presampling Enable */
+ vuint32_t PRES66:1; /* Channel 66 Presampling Enable */
+ vuint32_t PRES65:1; /* Channel 65 Presampling Enable */
+ vuint32_t PRES64:1; /* Channel 64 Presampling Enable */
+ } B;
+ } ADC_PSR2_32B_tag;
+
+
+ /* Register layout for all registers CTR... */
+
+ typedef union { /* conversion timing register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t INPLATCH:1; /* configuration bits for the LATCHING PHASE duration */
+ vuint32_t:1;
+ vuint32_t OFFSHIFT:2; /* configuration for offset shift characteristics */
+ vuint32_t:1;
+ vuint32_t INPCMP:2; /* configuration bits for the COMPARISON duration */
+ vuint32_t:1;
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t INSAMP:8; /* configuration bits for the SAMPLING PHASE duration */
+#else
+ vuint32_t INPSAMP:8;
+#endif
+ } B;
+ } ADC_CTR_32B_tag;
+
+ typedef union { /* NORMAL CONVERSION MASK REGISTER 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1; /* Channel 31 Normal Sampling Enable */
+ vuint32_t CH30:1; /* Channel 30 Normal Sampling Enable */
+ vuint32_t CH29:1; /* Channel 29 Normal Sampling Enable */
+ vuint32_t CH28:1; /* Channel 28 Normal Sampling Enable */
+ vuint32_t CH27:1; /* Channel 27 Normal Sampling Enable */
+ vuint32_t CH26:1; /* Channel 26 Normal Sampling Enable */
+ vuint32_t CH25:1; /* Channel 25 Normal Sampling Enable */
+ vuint32_t CH24:1; /* Channel 24 Normal Sampling Enable */
+ vuint32_t CH23:1; /* Channel 23 Normal Sampling Enable */
+ vuint32_t CH22:1; /* Channel 22 Normal Sampling Enable */
+ vuint32_t CH21:1; /* Channel 21 Normal Sampling Enable */
+ vuint32_t CH20:1; /* Channel 20 Normal Sampling Enable */
+ vuint32_t CH19:1; /* Channel 19 Normal Sampling Enable */
+ vuint32_t CH18:1; /* Channel 18 Normal Sampling Enable */
+ vuint32_t CH17:1; /* Channel 17 Normal Sampling Enable */
+ vuint32_t CH16:1; /* Channel 16 Normal Sampling Enable */
+ vuint32_t CH15:1; /* Channel 15 Normal Sampling Enable */
+ vuint32_t CH14:1; /* Channel 14 Normal Sampling Enable */
+ vuint32_t CH13:1; /* Channel 13 Normal Sampling Enable */
+ vuint32_t CH12:1; /* Channel 12 Normal Sampling Enable */
+ vuint32_t CH11:1; /* Channel 11 Normal Sampling Enable */
+ vuint32_t CH10:1; /* Channel 10 Normal Sampling Enable */
+ vuint32_t CH9:1; /* Channel 9 Normal Sampling Enable */
+ vuint32_t CH8:1; /* Channel 8 Normal Sampling Enable */
+ vuint32_t CH7:1; /* Channel 7 Normal Sampling Enable */
+ vuint32_t CH6:1; /* Channel 6 Normal Sampling Enable */
+ vuint32_t CH5:1; /* Channel 5 Normal Sampling Enable */
+ vuint32_t CH4:1; /* Channel 4 Normal Sampling Enable */
+ vuint32_t CH3:1; /* Channel 3 Normal Sampling Enable */
+ vuint32_t CH2:1; /* Channel 2 Normal Sampling Enable */
+ vuint32_t CH1:1; /* Channel 1 Normal Sampling Enable */
+ vuint32_t CH0:1; /* Channel 0 Normal Sampling Enable */
+ } B;
+ } ADC_NCMR0_32B_tag;
+
+ typedef union { /* NORMAL CONVERSION MASK REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t CH63:1; /* Channel 63 Normal Sampling Enable */
+ vuint32_t CH62:1; /* Channel 62 Normal Sampling Enable */
+ vuint32_t CH61:1; /* Channel 61 Normal Sampling Enable */
+ vuint32_t CH60:1; /* Channel 60 Normal Sampling Enable */
+ vuint32_t CH59:1; /* Channel 59 Normal Sampling Enable */
+ vuint32_t CH58:1; /* Channel 58 Normal Sampling Enable */
+ vuint32_t CH57:1; /* Channel 57 Normal Sampling Enable */
+ vuint32_t CH56:1; /* Channel 56 Normal Sampling Enable */
+ vuint32_t CH55:1; /* Channel 55 Normal Sampling Enable */
+ vuint32_t CH54:1; /* Channel 54 Normal Sampling Enable */
+ vuint32_t CH53:1; /* Channel 53 Normal Sampling Enable */
+ vuint32_t CH52:1; /* Channel 52 Normal Sampling Enable */
+ vuint32_t CH51:1; /* Channel 51 Normal Sampling Enable */
+ vuint32_t CH50:1; /* Channel 50 Normal Sampling Enable */
+ vuint32_t CH49:1; /* Channel 49 Normal Sampling Enable */
+ vuint32_t CH48:1; /* Channel 48 Normal Sampling Enable */
+ vuint32_t CH47:1; /* Channel 47 Normal Sampling Enable */
+ vuint32_t CH46:1; /* Channel 46 Normal Sampling Enable */
+ vuint32_t CH45:1; /* Channel 45 Normal Sampling Enable */
+ vuint32_t CH44:1; /* Channel 44 Normal Sampling Enable */
+ vuint32_t CH43:1; /* Channel 43 Normal Sampling Enable */
+ vuint32_t CH42:1; /* Channel 42 Normal Sampling Enable */
+ vuint32_t CH41:1; /* Channel 41 Normal Sampling Enable */
+ vuint32_t CH40:1; /* Channel 40 Normal Sampling Enable */
+ vuint32_t CH39:1; /* Channel 39 Normal Sampling Enable */
+ vuint32_t CH38:1; /* Channel 38 Normal Sampling Enable */
+ vuint32_t CH37:1; /* Channel 37 Normal Sampling Enable */
+ vuint32_t CH36:1; /* Channel 36 Normal Sampling Enable */
+ vuint32_t CH35:1; /* Channel 35 Normal Sampling Enable */
+ vuint32_t CH34:1; /* Channel 34 Normal Sampling Enable */
+ vuint32_t CH33:1; /* Channel 33 Normal Sampling Enable */
+ vuint32_t CH32:1; /* Channel 32 Normal Sampling Enable */
+ } B;
+ } ADC_NCMR1_32B_tag;
+
+ typedef union { /* NORMAL CONVERSION MASK REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t CH95:1; /* Channel 95 Normal Sampling Enable */
+ vuint32_t CH94:1; /* Channel 94 Normal Sampling Enable */
+ vuint32_t CH93:1; /* Channel 93 Normal Sampling Enable */
+ vuint32_t CH92:1; /* Channel 92 Normal Sampling Enable */
+ vuint32_t CH91:1; /* Channel 91 Normal Sampling Enable */
+ vuint32_t CH90:1; /* Channel 90 Normal Sampling Enable */
+ vuint32_t CH89:1; /* Channel 89 Normal Sampling Enable */
+ vuint32_t CH88:1; /* Channel 88 Normal Sampling Enable */
+ vuint32_t CH87:1; /* Channel 87 Normal Sampling Enable */
+ vuint32_t CH86:1; /* Channel 86 Normal Sampling Enable */
+ vuint32_t CH85:1; /* Channel 85 Normal Sampling Enable */
+ vuint32_t CH84:1; /* Channel 84 Normal Sampling Enable */
+ vuint32_t CH83:1; /* Channel 83 Normal Sampling Enable */
+ vuint32_t CH82:1; /* Channel 82 Normal Sampling Enable */
+ vuint32_t CH81:1; /* Channel 81 Normal Sampling Enable */
+ vuint32_t CH80:1; /* Channel 80 Normal Sampling Enable */
+ vuint32_t CH79:1; /* Channel 79 Normal Sampling Enable */
+ vuint32_t CH78:1; /* Channel 78 Normal Sampling Enable */
+ vuint32_t CH77:1; /* Channel 77 Normal Sampling Enable */
+ vuint32_t CH76:1; /* Channel 76 Normal Sampling Enable */
+ vuint32_t CH75:1; /* Channel 75 Normal Sampling Enable */
+ vuint32_t CH74:1; /* Channel 74 Normal Sampling Enable */
+ vuint32_t CH73:1; /* Channel 73 Normal Sampling Enable */
+ vuint32_t CH72:1; /* Channel 72 Normal Sampling Enable */
+ vuint32_t CH71:1; /* Channel 71 Normal Sampling Enable */
+ vuint32_t CH70:1; /* Channel 70 Normal Sampling Enable */
+ vuint32_t CH69:1; /* Channel 69 Normal Sampling Enable */
+ vuint32_t CH68:1; /* Channel 68 Normal Sampling Enable */
+ vuint32_t CH67:1; /* Channel 67 Normal Sampling Enable */
+ vuint32_t CH66:1; /* Channel 66 Normal Sampling Enable */
+ vuint32_t CH65:1; /* Channel 65 Normal Sampling Enable */
+ vuint32_t CH64:1; /* Channel 64 Normal Sampling Enable */
+ } B;
+ } ADC_NCMR2_32B_tag;
+
+ typedef union { /* Injected Conversion Mask Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t CH31:1; /* Channel 31 Injected Sampling Enable */
+ vuint32_t CH30:1; /* Channel 30 Injected Sampling Enable */
+ vuint32_t CH29:1; /* Channel 29 Injected Sampling Enable */
+ vuint32_t CH28:1; /* Channel 28 Injected Sampling Enable */
+ vuint32_t CH27:1; /* Channel 27 Injected Sampling Enable */
+ vuint32_t CH26:1; /* Channel 26 Injected Sampling Enable */
+ vuint32_t CH25:1; /* Channel 25 Injected Sampling Enable */
+ vuint32_t CH24:1; /* Channel 24 Injected Sampling Enable */
+ vuint32_t CH23:1; /* Channel 23 Injected Sampling Enable */
+ vuint32_t CH22:1; /* Channel 22 Injected Sampling Enable */
+ vuint32_t CH21:1; /* Channel 21 Injected Sampling Enable */
+ vuint32_t CH20:1; /* Channel 20 Injected Sampling Enable */
+ vuint32_t CH19:1; /* Channel 19 Injected Sampling Enable */
+ vuint32_t CH18:1; /* Channel 18 Injected Sampling Enable */
+ vuint32_t CH17:1; /* Channel 17 Injected Sampling Enable */
+ vuint32_t CH16:1; /* Channel 16 Injected Sampling Enable */
+ vuint32_t CH15:1; /* Channel 15 Injected Sampling Enable */
+ vuint32_t CH14:1; /* Channel 14 Injected Sampling Enable */
+ vuint32_t CH13:1; /* Channel 13 Injected Sampling Enable */
+ vuint32_t CH12:1; /* Channel 12 Injected Sampling Enable */
+ vuint32_t CH11:1; /* Channel 11 Injected Sampling Enable */
+ vuint32_t CH10:1; /* Channel 10 Injected Sampling Enable */
+ vuint32_t CH9:1; /* Channel 9 Injected Sampling Enable */
+ vuint32_t CH8:1; /* Channel 8 Injected Sampling Enable */
+ vuint32_t CH7:1; /* Channel 7 Injected Sampling Enable */
+ vuint32_t CH6:1; /* Channel 6 Injected Sampling Enable */
+ vuint32_t CH5:1; /* Channel 5 Injected Sampling Enable */
+ vuint32_t CH4:1; /* Channel 4 Injected Sampling Enable */
+ vuint32_t CH3:1; /* Channel 3 Injected Sampling Enable */
+ vuint32_t CH2:1; /* Channel 2 Injected Sampling Enable */
+ vuint32_t CH1:1; /* Channel 1 injected Sampling Enable */
+ vuint32_t CH0:1; /* Channel 0 injected Sampling Enable */
+ } B;
+ } ADC_JCMR0_32B_tag;
+
+ typedef union { /* INJECTED CONVERSION MASK REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t CH63:1; /* Channel 63 Injected Sampling Enable */
+ vuint32_t CH62:1; /* Channel 62 Injected Sampling Enable */
+ vuint32_t CH61:1; /* Channel 61 Injected Sampling Enable */
+ vuint32_t CH60:1; /* Channel 60 Injected Sampling Enable */
+ vuint32_t CH59:1; /* Channel 59 Injected Sampling Enable */
+ vuint32_t CH58:1; /* Channel 58 Injected Sampling Enable */
+ vuint32_t CH57:1; /* Channel 57 Injected Sampling Enable */
+ vuint32_t CH56:1; /* Channel 56 Injected Sampling Enable */
+ vuint32_t CH55:1; /* Channel 55 Injected Sampling Enable */
+ vuint32_t CH54:1; /* Channel 54 Injected Sampling Enable */
+ vuint32_t CH53:1; /* Channel 53 Injected Sampling Enable */
+ vuint32_t CH52:1; /* Channel 52 Injected Sampling Enable */
+ vuint32_t CH51:1; /* Channel 51 Injected Sampling Enable */
+ vuint32_t CH50:1; /* Channel 50 Injected Sampling Enable */
+ vuint32_t CH49:1; /* Channel 49 Injected Sampling Enable */
+ vuint32_t CH48:1; /* Channel 48 Injected Sampling Enable */
+ vuint32_t CH47:1; /* Channel 47 Injected Sampling Enable */
+ vuint32_t CH46:1; /* Channel 46 Injected Sampling Enable */
+ vuint32_t CH45:1; /* Channel 45 Injected Sampling Enable */
+ vuint32_t CH44:1; /* Channel 44 Injected Sampling Enable */
+ vuint32_t CH43:1; /* Channel 43 Injected Sampling Enable */
+ vuint32_t CH42:1; /* Channel 42 Injected Sampling Enable */
+ vuint32_t CH41:1; /* Channel 41 Injected Sampling Enable */
+ vuint32_t CH40:1; /* Channel 40 Injected Sampling Enable */
+ vuint32_t CH39:1; /* Channel 39 Injected Sampling Enable */
+ vuint32_t CH38:1; /* Channel 38 Injected Sampling Enable */
+ vuint32_t CH37:1; /* Channel 37 Injected Sampling Enable */
+ vuint32_t CH36:1; /* Channel 36 Injected Sampling Enable */
+ vuint32_t CH35:1; /* Channel 35 Injected Sampling Enable */
+ vuint32_t CH34:1; /* Channel 34 Injected Sampling Enable */
+ vuint32_t CH33:1; /* Channel 33 Injected Sampling Enable */
+ vuint32_t CH32:1; /* Channel 32 Injected Sampling Enable */
+ } B;
+ } ADC_JCMR1_32B_tag;
+
+ typedef union { /* INJECTED CONVERSION MASK REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t CH95:1; /* Channel 95 Injected Sampling Enable */
+ vuint32_t CH94:1; /* Channel 94 Injected Sampling Enable */
+ vuint32_t CH93:1; /* Channel 93 Injected Sampling Enable */
+ vuint32_t CH92:1; /* Channel 92 Injected Sampling Enable */
+ vuint32_t CH91:1; /* Channel 91 Injected Sampling Enable */
+ vuint32_t CH90:1; /* Channel 90 Injected Sampling Enable */
+ vuint32_t CH89:1; /* Channel 89 Injected Sampling Enable */
+ vuint32_t CH88:1; /* Channel 88 Injected Sampling Enable */
+ vuint32_t CH87:1; /* Channel 87 Injected Sampling Enable */
+ vuint32_t CH86:1; /* Channel 86 Injected Sampling Enable */
+ vuint32_t CH85:1; /* Channel 85 Injected Sampling Enable */
+ vuint32_t CH84:1; /* Channel 84 Injected Sampling Enable */
+ vuint32_t CH83:1; /* Channel 83 Injected Sampling Enable */
+ vuint32_t CH82:1; /* Channel 82 Injected Sampling Enable */
+ vuint32_t CH81:1; /* Channel 81 Injected Sampling Enable */
+ vuint32_t CH80:1; /* Channel 80 Injected Sampling Enable */
+ vuint32_t CH79:1; /* Channel 79 Injected Sampling Enable */
+ vuint32_t CH78:1; /* Channel 78 Injected Sampling Enable */
+ vuint32_t CH77:1; /* Channel 77 Injected Sampling Enable */
+ vuint32_t CH76:1; /* Channel 76 Injected Sampling Enable */
+ vuint32_t CH75:1; /* Channel 75 Injected Sampling Enable */
+ vuint32_t CH74:1; /* Channel 74 Injected Sampling Enable */
+ vuint32_t CH73:1; /* Channel 73 Injected Sampling Enable */
+ vuint32_t CH72:1; /* Channel 72 Injected Sampling Enable */
+ vuint32_t CH71:1; /* Channel 71 Injected Sampling Enable */
+ vuint32_t CH70:1; /* Channel 70 Injected Sampling Enable */
+ vuint32_t CH69:1; /* Channel 69 Injected Sampling Enable */
+ vuint32_t CH68:1; /* Channel 68 Injected Sampling Enable */
+ vuint32_t CH67:1; /* Channel 67 Injected Sampling Enable */
+ vuint32_t CH66:1; /* Channel 66 Injected Sampling Enable */
+ vuint32_t CH65:1; /* Channel 65 Injected Sampling Enable */
+ vuint32_t CH64:1; /* Channel 64 Injected Sampling Enable */
+ } B;
+ } ADC_JCMR2_32B_tag;
+
+ typedef union { /* Offset Word Regsiter */
+ vuint32_t R;
+ struct {
+ vuint32_t:15;
+ vuint32_t OFFSETLOAD:1; /* load_offset */
+ vuint32_t:8;
+#ifndef USE_FIELD_ALIASES_ADC
+ vuint32_t OFFSET_WORD:8; /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */
+#else
+ vuint32_t OFFSETWORD:8;
+#endif
+ } B;
+ } ADC_OFFWR_32B_tag;
+
+ typedef union { /* Decode Signal Delay Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t DSD:8; /* take into account the settling time of the external mux */
+ } B;
+ } ADC_DSDR_32B_tag;
+
+ typedef union { /* Power Down Dealy Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t PDED:8; /* The delay between the power down bit reset and the starting of conversion */
+ } B;
+ } ADC_PDEDR_32B_tag;
+
+
+ /* Register layout for all registers CDR... */
+
+ typedef union { /* CHANNEL DATA REGS */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1; /* validity of data */
+ vuint32_t OVERW:1; /* overwrite data */
+ vuint32_t RESULT:2; /* reflects mode conversion */
+ vuint32_t:6;
+ vuint32_t CDATA:10; /* Channel 0 converted data */
+ } B;
+ } ADC_CDR_32B_tag;
+
+ typedef union { /* Upper Threshold register 4 is not contiguous to 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR4_32B_tag;
+
+ typedef union { /* Upper Threshold register 5 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR5_32B_tag;
+
+ typedef union { /* Upper Threshold register 6 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR6_32B_tag;
+
+ typedef union { /* Upper Threshold register 7 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR7_32B_tag;
+
+ typedef union { /* Upper Threshold register 8 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR8_32B_tag;
+
+ typedef union { /* Upper Threshold register 9 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR9_32B_tag;
+
+ typedef union { /* Upper Threshold register 10 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR10_32B_tag;
+
+ typedef union { /* Upper Threshold register 11 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR11_32B_tag;
+
+ typedef union { /* Upper Threshold register 12 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR12_32B_tag;
+
+ typedef union { /* Upper Threshold register 13 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR13_32B_tag;
+
+ typedef union { /* Upper Threshold register 14 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR14_32B_tag;
+
+ typedef union { /* Upper Threshold register 15 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* high threshold value s */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* low threshold value s */
+ } B;
+ } ADC_THRHLR15_32B_tag;
+
+
+ /* Register layout for all registers CWSELR... */
+
+ typedef union { /* Channel Watchdog Select register */
+ vuint32_t R;
+ struct {
+ vuint32_t WSEL_CH7:4; /* Channel Watchdog select for channel 7+R*8 */
+ vuint32_t WSEL_CH6:4; /* Channel Watchdog select for channel 6+R*8 */
+ vuint32_t WSEL_CH5:4; /* Channel Watchdog select for channel 5+R*8 */
+ vuint32_t WSEL_CH4:4; /* Channel Watchdog select for channel 4+R*8 */
+ vuint32_t WSEL_CH3:4; /* Channel Watchdog select for channel 3+R*8 */
+ vuint32_t WSEL_CH2:4; /* Channel Watchdog select for channel 2+R*8 */
+ vuint32_t WSEL_CH1:4; /* Channel Watchdog select for channel 1+R*8 */
+ vuint32_t WSEL_CH0:4; /* Channel Watchdog select for channel 0+R*8 */
+ } B;
+ } ADC_CWSELR_32B_tag;
+
+
+ /* Register layout for all registers CWENR... */
+
+ typedef union { /* Channel Watchdog Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CWEN15PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN14PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN13PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN12PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN11PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN10PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN09PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN08PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN07PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN06PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN05PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN04PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN03PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN02PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN01PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ vuint32_t CWEN00PRT32:1; /* Channel Watchdog Enable 0+R*32 */
+ } B;
+ } ADC_CWENR_32B_tag;
+
+
+ /* Register layout for all registers AWORR... */
+
+ typedef union { /* Analog Watchdog Out of Range Register */
+ vuint32_t R;
+ struct {
+ vuint32_t AWOR_CH31:1; /* Channel 31+R*32 converted data out of range */
+ vuint32_t AWOR_CH30:1; /* Channel 30+R*32 converted data out of range */
+ vuint32_t AWOR_CH29:1; /* Channel 29+R*32 converted data out of range */
+ vuint32_t AWOR_CH28:1; /* Channel 28+R*32 converted data out of range */
+ vuint32_t AWOR_CH27:1; /* Channel 27+R*32 converted data out of range */
+ vuint32_t AWOR_CH26:1; /* Channel 26+R*32 converted data out of range */
+ vuint32_t AWOR_CH25:1; /* Channel 25+R*32 converted data out of range */
+ vuint32_t AWOR_CH24:1; /* Channel 24+R*32 converted data out of range */
+ vuint32_t AWOR_CH23:1; /* Channel 23+R*32 converted data out of range */
+ vuint32_t AWOR_CH22:1; /* Channel 22+R*32 converted data out of range */
+ vuint32_t AWOR_CH21:1; /* Channel 21+R*32 converted data out of range */
+ vuint32_t AWOR_CH20:1; /* Channel 20+R*32 converted data out of range */
+ vuint32_t AWOR_CH19:1; /* Channel 19+R*32 converted data out of range */
+ vuint32_t AWOR_CH18:1; /* Channel 18+R*32 converted data out of range */
+ vuint32_t AWOR_CH17:1; /* Channel 17+R*32 converted data out of range */
+ vuint32_t AWOR_CH16:1; /* Channel 16+R*32 converted data out of range */
+ vuint32_t AWOR_CH15:1; /* Channel 15+R*32 converted data out of range */
+ vuint32_t AWOR_CH14:1; /* Channel 14+R*32 converted data out of range */
+ vuint32_t AWOR_CH13:1; /* Channel 13+R*32 converted data out of range */
+ vuint32_t AWOR_CH12:1; /* Channel 12+R*32 converted data out of range */
+ vuint32_t AWOR_CH11:1; /* Channel 11+R*32 converted data out of range */
+ vuint32_t AWOR_CH10:1; /* Channel 10+R*32 converted data out of range */
+ vuint32_t AWOR_CH9:1; /* Channel 9+R*32 converted data out of range */
+ vuint32_t AWOR_CH8:1; /* Channel 8+R*32 converted data out of range */
+ vuint32_t AWOR_CH7:1; /* Channel 7+R*32 converted data out of range */
+ vuint32_t AWOR_CH6:1; /* Channel 6+R*32 converted data out of range */
+ vuint32_t AWOR_CH5:1; /* Channel 5+R*32 converted data out of range */
+ vuint32_t AWOR_CH4:1; /* Channel 4+R*32 converted data out of range */
+ vuint32_t AWOR_CH3:1; /* Channel 3+R*32 converted data out of range */
+ vuint32_t AWOR_CH2:1; /* Channel 2+R*32 converted data out of range */
+ vuint32_t AWOR_CH1:1; /* Channel 1+R*32 converted data out of range */
+ vuint32_t AWOR_CH0:1; /* Channel 0+R*32 converted data out of range */
+ } B;
+ } ADC_AWORR_32B_tag;
+
+ typedef union { /* SELF TEST CONFIGURATION REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t INPSAMP_C:8; /* Sampling phase duration for the test conversions - algorithm C */
+ vuint32_t INPSAMP_RC:8; /* Sampling phase duration for the test conversions - algorithm RC */
+ vuint32_t INPSAMP_S:8; /* Sampling phase duration for the test conversions - algorithm S */
+ vuint32_t:5;
+ vuint32_t ST_INPCMP:2; /* Configuration bit for comparison phase duration for self test channel */
+ vuint32_t ST_INPLATCH:1; /* Configuration bit for Latching phase duration for self test channel */
+ } B;
+ } ADC_STCR1_32B_tag;
+
+ typedef union { /* SELF TEST CONFIGURATION REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t:5;
+ vuint32_t SERR:1; /* Error fault injection bit (write only) */
+ vuint32_t MSKSTWDTERR:1; /* Interrupt enable (STSR2.WDTERR status bit) */
+ vuint32_t:1;
+ vuint32_t MSKST_EOC:1; /* Interrupt enable bit for STSR2.ST_EOC */
+ vuint32_t:4;
+ vuint32_t MSKWDG_EOA_C:1; /* Interrupt enable (WDG_EOA_C status bit) */
+ vuint32_t MSKWDG_EOA_RC:1; /* Interrupt enable (WDG_EOA_RC status bit) */
+ vuint32_t MSKWDG_EOA_S:1; /* Interrupt enable (WDG_EOA_S status bit) */
+ vuint32_t MSKERR_C:1; /* Interrupt enable (ERR_C status bit) */
+ vuint32_t MSKERR_RC:1; /* Interrupt enable (ERR_RC status bit) */
+ vuint32_t MSKERR_S2:1; /* Interrupt enable (ERR_S2 status bit) */
+ vuint32_t MSKERR_S1:1; /* Interrupt enable (ERR_S1 status bit) */
+ vuint32_t MSKERR_S0:1; /* Interrupt enable (ERR_S0 status bit) */
+ vuint32_t:3;
+ vuint32_t EN:1; /* Self testing channel enable */
+ vuint32_t:4;
+ vuint32_t FMA_C:1; /* Fault mapping for the algorithm C */
+ vuint32_t FMAR_C:1; /* Fault mapping for the algorithm RC */
+ vuint32_t FMA_S:1; /* Fault mapping for the algorithm BGAP */
+ } B;
+ } ADC_STCR2_32B_tag;
+
+ typedef union { /* SELF TEST CONFIGURATION REGISTER 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t ALG:2; /* Algorithm scheduling */
+ vuint32_t:8;
+ } B;
+ } ADC_STCR3_32B_tag;
+
+ typedef union { /* SELF TEST BAUD RATE REGISTER */
+ vuint32_t R;
+ struct {
+ vuint32_t:13;
+ vuint32_t WDT:3; /* Watchdog timer value */
+ vuint32_t:8;
+ vuint32_t BR:8; /* Baud rate for the selected algorithm in SCAN mode */
+ } B;
+ } ADC_STBRR_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t WDTERR:1; /* Watchdog timer error */
+ vuint32_t OVERWR:1; /* Overwrite error */
+ vuint32_t ST_EOC:1; /* Self test EOC bit */
+ vuint32_t:4;
+ vuint32_t WDG_EOA_C:1; /* Algorithm C completed without error */
+ vuint32_t WDG_EOA_RC:1; /* Algorithm RC completed without error */
+ vuint32_t WDG_EOA_S:1; /* Algorithm S completed without error */
+ vuint32_t ERR_C:1; /* Error on the self testing channel (algorithm C) */
+ vuint32_t ERR_RC:1; /* Error on the self testing channel (algorithm RC) */
+ vuint32_t ERR_S2:1; /* Error on the self testing channel (algorithm SUPPLY, step 2) */
+ vuint32_t ERR_S1:1; /* Error on the self testing channel (algorithm SUPPLY, step 1) */
+ vuint32_t ERR_S0:1; /* Error on the self testing channel (algorithm SUPPLY, step 0) */
+ vuint32_t:1;
+ vuint32_t STEP_C:5; /* Step of algorithm C when ERR_C has occurred */
+ vuint32_t STEP_RC:5; /* Step of algorithm RC when ERR_RC has occurred */
+ } B;
+ } ADC_STSR1_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t OVFL:1; /* Overflow bit */
+ vuint32_t:3;
+ vuint32_t DATA1:12; /* Test channel converted data when ERR_S1 has occurred */
+ vuint32_t:4;
+ vuint32_t DATA0:12; /* Test channel converted data when ERR_S1 has occurred */
+ } B;
+ } ADC_STSR2_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t DATA1:12; /* Test channel converted data when ERR_S0 has occurred */
+ vuint32_t:4;
+ vuint32_t DATA0:12; /* Test channel converted data when ERR_S0 has occurred */
+ } B;
+ } ADC_STSR3_32B_tag;
+
+ typedef union { /* SELF TEST STATUS REGISTER 4 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t DATA1:12; /* Test channel converted data when ERR_C has occurred */
+ vuint32_t:4;
+ vuint32_t DATA0:12; /* Test channel converted data when ERR_C has occurred */
+ } B;
+ } ADC_STSR4_32B_tag;
+
+ typedef union { /* SELF TEST DATA REGISTER 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t:12;
+ vuint32_t VALID:1; /* Valid data */
+ vuint32_t OVERWR:1; /* Overwrite data */
+ vuint32_t:6;
+ vuint32_t TCDATA:12; /* Test channel converted data */
+ } B;
+ } ADC_STDR1_32B_tag;
+
+ typedef union { /* SELF TEST DATA REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t FDATA:12; /* Fractional part of the ratio TEST for algorithm S */
+ vuint32_t VALID:1; /* Valid data */
+ vuint32_t OVERWR:1; /* Overwrite data */
+ vuint32_t:6;
+ vuint32_t IDATA:12; /* Integer part of the ratio TEST for algorithm S */
+ } B;
+ } ADC_STDR2_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
+ vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm S */
+ vuint32_t:2;
+ vuint32_t THRH:12; /* High threshold value for channel 0 */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* Low threshold value for channel 0 */
+ } B;
+ } ADC_STAW0R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
+ vuint32_t R;
+ struct {
+ vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
+ vuint32_t:3;
+ vuint32_t THRH:12; /* High threshold value for test channel - algorithm S */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
+ } B;
+ } ADC_STAW1AR_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* High threshold value for test channel - algorithm S */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* Low threshold value for test channel - algorithm S */
+ } B;
+ } ADC_STAW1BR_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm S */
+ vuint32_t:19;
+ vuint32_t THRL:12; /* Low threshold value for channel */
+ } B;
+ } ADC_STAW2R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm RC */
+ vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm RC */
+ vuint32_t:2;
+ vuint32_t THRH:12; /* High threshold value for channel 3 */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* Low threshold value for channel 3 */
+ } B;
+ } ADC_STAW3R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
+ vuint32_t R;
+ struct {
+ vuint32_t AWDE:1; /* Analog WatchDog Enable - algorithm C */
+ vuint32_t WDTE:1; /* WatchDog Timer Enable - algorithm C */
+ vuint32_t:2;
+ vuint32_t THRH:12; /* High threshold value for channel 4 */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* Low threshold value for channel 4 */
+ } B;
+ } ADC_STAW4R_32B_tag;
+
+ typedef union { /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t THRH:12; /* High threshold value for algorithm C */
+ vuint32_t:4;
+ vuint32_t THRL:12; /* Low threshold value for algorithm C */
+ } B;
+ } ADC_STAW5R_32B_tag;
+
+
+
+ typedef struct ADC_struct_tag { /* start of ADC_tag */
+ /* module configuration register */
+ ADC_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
+ /* module status register */
+ ADC_MSR_32B_tag MSR; /* offset: 0x0004 size: 32 bit */
+ int8_t ADC_reserved_0008[8];
+ /* Interrupt status register */
+ ADC_ISR_32B_tag ISR; /* offset: 0x0010 size: 32 bit */
+ union {
+ ADC_CEOCFR0_32B_tag CEOCFR[3]; /* offset: 0x0014 (0x0004 x 3) */
+
+ struct {
+ /* CHANNEL PENDING REGISTER 0 */
+ ADC_CEOCFR0_32B_tag CEOCFR0; /* offset: 0x0014 size: 32 bit */
+ /* CHANNEL PENDING REGISTER 1 */
+ ADC_CEOCFR1_32B_tag CEOCFR1; /* offset: 0x0018 size: 32 bit */
+ /* CHANNEL PENDING REGISTER 2 */
+ ADC_CEOCFR2_32B_tag CEOCFR2; /* offset: 0x001C size: 32 bit */
+ };
+
+ };
+ /* interrupt mask register */
+ ADC_IMR_32B_tag IMR; /* offset: 0x0020 size: 32 bit */
+ union {
+ ADC_CIMR0_32B_tag CIMR[3]; /* offset: 0x0024 (0x0004 x 3) */
+
+ struct {
+ /* CHANNEL INTERRUPT MASK REGISTER 0 */
+ ADC_CIMR0_32B_tag CIMR0; /* offset: 0x0024 size: 32 bit */
+ /* CHANNEL INTERRUPT MASK REGISTER 1 */
+ ADC_CIMR1_32B_tag CIMR1; /* offset: 0x0028 size: 32 bit */
+ /* CHANNEL INTERRUPT MASK REGISTER 2 */
+ ADC_CIMR2_32B_tag CIMR2; /* offset: 0x002C size: 32 bit */
+ };
+
+ };
+ /* Watchdog Threshold interrupt status register */
+ ADC_WTISR_32B_tag WTISR; /* offset: 0x0030 size: 32 bit */
+ /* Watchdog interrupt MASK register */
+ ADC_WTIMR_32B_tag WTIMR; /* offset: 0x0034 size: 32 bit */
+ int8_t ADC_reserved_0038[8];
+ /* DMAE register */
+ ADC_DMAE_32B_tag DMAE; /* offset: 0x0040 size: 32 bit */
+ union {
+ ADC_DMAR0_32B_tag DMAR[3]; /* offset: 0x0044 (0x0004 x 3) */
+
+ struct {
+ /* DMA REGISTER 0 */
+ ADC_DMAR0_32B_tag DMAR0; /* offset: 0x0044 size: 32 bit */
+ /* DMA REGISTER 1 */
+ ADC_DMAR1_32B_tag DMAR1; /* offset: 0x0048 size: 32 bit */
+ /* DMA REGISTER 2 */
+ ADC_DMAR2_32B_tag DMAR2; /* offset: 0x004C size: 32 bit */
+ };
+
+ };
+ union {
+ /* Threshold Control register C */
+ ADC_TRC_32B_tag TRC[4]; /* offset: 0x0050 (0x0004 x 4) */
+
+ struct {
+ /* Threshold Control register C */
+ ADC_TRC_32B_tag TRC0; /* offset: 0x0050 size: 32 bit */
+ ADC_TRC_32B_tag TRC1; /* offset: 0x0054 size: 32 bit */
+ ADC_TRC_32B_tag TRC2; /* offset: 0x0058 size: 32 bit */
+ ADC_TRC_32B_tag TRC3; /* offset: 0x005C size: 32 bit */
+ };
+
+ };
+ union {
+ /* Upper Threshold register */
+ ADC_THRHLR_32B_tag THRHLR[4]; /* offset: 0x0060 (0x0004 x 4) */
+
+ struct {
+ /* Upper Threshold register */
+ ADC_THRHLR_32B_tag THRHLR0; /* offset: 0x0060 size: 32 bit */
+ ADC_THRHLR_32B_tag THRHLR1; /* offset: 0x0064 size: 32 bit */
+ ADC_THRHLR_32B_tag THRHLR2; /* offset: 0x0068 size: 32 bit */
+ ADC_THRHLR_32B_tag THRHLR3; /* offset: 0x006C size: 32 bit */
+ };
+
+ };
+ union {
+ /* alternate Upper Threshold register */
+ ADC_THRALT_32B_tag THRALT[4]; /* offset: 0x0070 (0x0004 x 4) */
+
+ struct {
+ /* alternate Upper Threshold register */
+ ADC_THRALT_32B_tag THRALT0; /* offset: 0x0070 size: 32 bit */
+ ADC_THRALT_32B_tag THRALT1; /* offset: 0x0074 size: 32 bit */
+ ADC_THRALT_32B_tag THRALT2; /* offset: 0x0078 size: 32 bit */
+ ADC_THRALT_32B_tag THRALT3; /* offset: 0x007C size: 32 bit */
+ };
+
+ };
+ /* PRESAMPLING CONTROL REGISTER */
+ ADC_PSCR_32B_tag PSCR; /* offset: 0x0080 size: 32 bit */
+ union {
+ ADC_PSR0_32B_tag PSR[3]; /* offset: 0x0084 (0x0004 x 3) */
+
+ struct {
+ /* Presampling Register 0 */
+ ADC_PSR0_32B_tag PSR0; /* offset: 0x0084 size: 32 bit */
+ /* Presampling REGISTER 1 */
+ ADC_PSR1_32B_tag PSR1; /* offset: 0x0088 size: 32 bit */
+ /* Presampling REGISTER 2 */
+ ADC_PSR2_32B_tag PSR2; /* offset: 0x008C size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_0090_C[4];
+ union {
+ /* conversion timing register */
+ ADC_CTR_32B_tag CTR[3]; /* offset: 0x0094 (0x0004 x 3) */
+
+ struct {
+ /* conversion timing register */
+ ADC_CTR_32B_tag CTR0; /* offset: 0x0094 size: 32 bit */
+ ADC_CTR_32B_tag CTR1; /* offset: 0x0098 size: 32 bit */
+ ADC_CTR_32B_tag CTR2; /* offset: 0x009C size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_00A0_C[4];
+ union {
+ ADC_NCMR0_32B_tag NCMR[3]; /* offset: 0x00A4 (0x0004 x 3) */
+
+ struct {
+ /* NORMAL CONVERSION MASK REGISTER 0 */
+ ADC_NCMR0_32B_tag NCMR0; /* offset: 0x00A4 size: 32 bit */
+ /* NORMAL CONVERSION MASK REGISTER 1 */
+ ADC_NCMR1_32B_tag NCMR1; /* offset: 0x00A8 size: 32 bit */
+ /* NORMAL CONVERSION MASK REGISTER 2 */
+ ADC_NCMR2_32B_tag NCMR2; /* offset: 0x00AC size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_00B0_C[4];
+ union {
+ ADC_JCMR0_32B_tag JCMR[3]; /* offset: 0x00B4 (0x0004 x 3) */
+
+ struct {
+ /* Injected Conversion Mask Register 0 */
+ ADC_JCMR0_32B_tag JCMR0; /* offset: 0x00B4 size: 32 bit */
+ /* INJECTED CONVERSION MASK REGISTER 1 */
+ ADC_JCMR1_32B_tag JCMR1; /* offset: 0x00B8 size: 32 bit */
+ /* INJECTED CONVERSION MASK REGISTER 2 */
+ ADC_JCMR2_32B_tag JCMR2; /* offset: 0x00BC size: 32 bit */
+ };
+
+ };
+ /* Offset Word Regsiter */
+ ADC_OFFWR_32B_tag OFFWR; /* offset: 0x00C0 size: 32 bit */
+ /* Decode Signal Delay Register */
+ ADC_DSDR_32B_tag DSDR; /* offset: 0x00C4 size: 32 bit */
+ /* Power Down Dealy Register */
+ ADC_PDEDR_32B_tag PDEDR; /* offset: 0x00C8 size: 32 bit */
+ int8_t ADC_reserved_00CC_C[52];
+ union {
+ /* CHANNEL DATA REGS */
+ ADC_CDR_32B_tag CDR[96]; /* offset: 0x0100 (0x0004 x 96) */
+
+ struct {
+ /* CHANNEL DATA REGS */
+ ADC_CDR_32B_tag CDR0; /* offset: 0x0100 size: 32 bit */
+ ADC_CDR_32B_tag CDR1; /* offset: 0x0104 size: 32 bit */
+ ADC_CDR_32B_tag CDR2; /* offset: 0x0108 size: 32 bit */
+ ADC_CDR_32B_tag CDR3; /* offset: 0x010C size: 32 bit */
+ ADC_CDR_32B_tag CDR4; /* offset: 0x0110 size: 32 bit */
+ ADC_CDR_32B_tag CDR5; /* offset: 0x0114 size: 32 bit */
+ ADC_CDR_32B_tag CDR6; /* offset: 0x0118 size: 32 bit */
+ ADC_CDR_32B_tag CDR7; /* offset: 0x011C size: 32 bit */
+ ADC_CDR_32B_tag CDR8; /* offset: 0x0120 size: 32 bit */
+ ADC_CDR_32B_tag CDR9; /* offset: 0x0124 size: 32 bit */
+ ADC_CDR_32B_tag CDR10; /* offset: 0x0128 size: 32 bit */
+ ADC_CDR_32B_tag CDR11; /* offset: 0x012C size: 32 bit */
+ ADC_CDR_32B_tag CDR12; /* offset: 0x0130 size: 32 bit */
+ ADC_CDR_32B_tag CDR13; /* offset: 0x0134 size: 32 bit */
+ ADC_CDR_32B_tag CDR14; /* offset: 0x0138 size: 32 bit */
+ ADC_CDR_32B_tag CDR15; /* offset: 0x013C size: 32 bit */
+ ADC_CDR_32B_tag CDR16; /* offset: 0x0140 size: 32 bit */
+ ADC_CDR_32B_tag CDR17; /* offset: 0x0144 size: 32 bit */
+ ADC_CDR_32B_tag CDR18; /* offset: 0x0148 size: 32 bit */
+ ADC_CDR_32B_tag CDR19; /* offset: 0x014C size: 32 bit */
+ ADC_CDR_32B_tag CDR20; /* offset: 0x0150 size: 32 bit */
+ ADC_CDR_32B_tag CDR21; /* offset: 0x0154 size: 32 bit */
+ ADC_CDR_32B_tag CDR22; /* offset: 0x0158 size: 32 bit */
+ ADC_CDR_32B_tag CDR23; /* offset: 0x015C size: 32 bit */
+ ADC_CDR_32B_tag CDR24; /* offset: 0x0160 size: 32 bit */
+ ADC_CDR_32B_tag CDR25; /* offset: 0x0164 size: 32 bit */
+ ADC_CDR_32B_tag CDR26; /* offset: 0x0168 size: 32 bit */
+ ADC_CDR_32B_tag CDR27; /* offset: 0x016C size: 32 bit */
+ ADC_CDR_32B_tag CDR28; /* offset: 0x0170 size: 32 bit */
+ ADC_CDR_32B_tag CDR29; /* offset: 0x0174 size: 32 bit */
+ ADC_CDR_32B_tag CDR30; /* offset: 0x0178 size: 32 bit */
+ ADC_CDR_32B_tag CDR31; /* offset: 0x017C size: 32 bit */
+ ADC_CDR_32B_tag CDR32; /* offset: 0x0180 size: 32 bit */
+ ADC_CDR_32B_tag CDR33; /* offset: 0x0184 size: 32 bit */
+ ADC_CDR_32B_tag CDR34; /* offset: 0x0188 size: 32 bit */
+ ADC_CDR_32B_tag CDR35; /* offset: 0x018C size: 32 bit */
+ ADC_CDR_32B_tag CDR36; /* offset: 0x0190 size: 32 bit */
+ ADC_CDR_32B_tag CDR37; /* offset: 0x0194 size: 32 bit */
+ ADC_CDR_32B_tag CDR38; /* offset: 0x0198 size: 32 bit */
+ ADC_CDR_32B_tag CDR39; /* offset: 0x019C size: 32 bit */
+ ADC_CDR_32B_tag CDR40; /* offset: 0x01A0 size: 32 bit */
+ ADC_CDR_32B_tag CDR41; /* offset: 0x01A4 size: 32 bit */
+ ADC_CDR_32B_tag CDR42; /* offset: 0x01A8 size: 32 bit */
+ ADC_CDR_32B_tag CDR43; /* offset: 0x01AC size: 32 bit */
+ ADC_CDR_32B_tag CDR44; /* offset: 0x01B0 size: 32 bit */
+ ADC_CDR_32B_tag CDR45; /* offset: 0x01B4 size: 32 bit */
+ ADC_CDR_32B_tag CDR46; /* offset: 0x01B8 size: 32 bit */
+ ADC_CDR_32B_tag CDR47; /* offset: 0x01BC size: 32 bit */
+ ADC_CDR_32B_tag CDR48; /* offset: 0x01C0 size: 32 bit */
+ ADC_CDR_32B_tag CDR49; /* offset: 0x01C4 size: 32 bit */
+ ADC_CDR_32B_tag CDR50; /* offset: 0x01C8 size: 32 bit */
+ ADC_CDR_32B_tag CDR51; /* offset: 0x01CC size: 32 bit */
+ ADC_CDR_32B_tag CDR52; /* offset: 0x01D0 size: 32 bit */
+ ADC_CDR_32B_tag CDR53; /* offset: 0x01D4 size: 32 bit */
+ ADC_CDR_32B_tag CDR54; /* offset: 0x01D8 size: 32 bit */
+ ADC_CDR_32B_tag CDR55; /* offset: 0x01DC size: 32 bit */
+ ADC_CDR_32B_tag CDR56; /* offset: 0x01E0 size: 32 bit */
+ ADC_CDR_32B_tag CDR57; /* offset: 0x01E4 size: 32 bit */
+ ADC_CDR_32B_tag CDR58; /* offset: 0x01E8 size: 32 bit */
+ ADC_CDR_32B_tag CDR59; /* offset: 0x01EC size: 32 bit */
+ ADC_CDR_32B_tag CDR60; /* offset: 0x01F0 size: 32 bit */
+ ADC_CDR_32B_tag CDR61; /* offset: 0x01F4 size: 32 bit */
+ ADC_CDR_32B_tag CDR62; /* offset: 0x01F8 size: 32 bit */
+ ADC_CDR_32B_tag CDR63; /* offset: 0x01FC size: 32 bit */
+ ADC_CDR_32B_tag CDR64; /* offset: 0x0200 size: 32 bit */
+ ADC_CDR_32B_tag CDR65; /* offset: 0x0204 size: 32 bit */
+ ADC_CDR_32B_tag CDR66; /* offset: 0x0208 size: 32 bit */
+ ADC_CDR_32B_tag CDR67; /* offset: 0x020C size: 32 bit */
+ ADC_CDR_32B_tag CDR68; /* offset: 0x0210 size: 32 bit */
+ ADC_CDR_32B_tag CDR69; /* offset: 0x0214 size: 32 bit */
+ ADC_CDR_32B_tag CDR70; /* offset: 0x0218 size: 32 bit */
+ ADC_CDR_32B_tag CDR71; /* offset: 0x021C size: 32 bit */
+ ADC_CDR_32B_tag CDR72; /* offset: 0x0220 size: 32 bit */
+ ADC_CDR_32B_tag CDR73; /* offset: 0x0224 size: 32 bit */
+ ADC_CDR_32B_tag CDR74; /* offset: 0x0228 size: 32 bit */
+ ADC_CDR_32B_tag CDR75; /* offset: 0x022C size: 32 bit */
+ ADC_CDR_32B_tag CDR76; /* offset: 0x0230 size: 32 bit */
+ ADC_CDR_32B_tag CDR77; /* offset: 0x0234 size: 32 bit */
+ ADC_CDR_32B_tag CDR78; /* offset: 0x0238 size: 32 bit */
+ ADC_CDR_32B_tag CDR79; /* offset: 0x023C size: 32 bit */
+ ADC_CDR_32B_tag CDR80; /* offset: 0x0240 size: 32 bit */
+ ADC_CDR_32B_tag CDR81; /* offset: 0x0244 size: 32 bit */
+ ADC_CDR_32B_tag CDR82; /* offset: 0x0248 size: 32 bit */
+ ADC_CDR_32B_tag CDR83; /* offset: 0x024C size: 32 bit */
+ ADC_CDR_32B_tag CDR84; /* offset: 0x0250 size: 32 bit */
+ ADC_CDR_32B_tag CDR85; /* offset: 0x0254 size: 32 bit */
+ ADC_CDR_32B_tag CDR86; /* offset: 0x0258 size: 32 bit */
+ ADC_CDR_32B_tag CDR87; /* offset: 0x025C size: 32 bit */
+ ADC_CDR_32B_tag CDR88; /* offset: 0x0260 size: 32 bit */
+ ADC_CDR_32B_tag CDR89; /* offset: 0x0264 size: 32 bit */
+ ADC_CDR_32B_tag CDR90; /* offset: 0x0268 size: 32 bit */
+ ADC_CDR_32B_tag CDR91; /* offset: 0x026C size: 32 bit */
+ ADC_CDR_32B_tag CDR92; /* offset: 0x0270 size: 32 bit */
+ ADC_CDR_32B_tag CDR93; /* offset: 0x0274 size: 32 bit */
+ ADC_CDR_32B_tag CDR94; /* offset: 0x0278 size: 32 bit */
+ ADC_CDR_32B_tag CDR95; /* offset: 0x027C size: 32 bit */
+ };
+
+ };
+ /* Upper Threshold register 4 is not contiguous to 3 */
+ ADC_THRHLR4_32B_tag THRHLR4; /* offset: 0x0280 size: 32 bit */
+ /* Upper Threshold register 5 */
+ ADC_THRHLR5_32B_tag THRHLR5; /* offset: 0x0284 size: 32 bit */
+ /* Upper Threshold register 6 */
+ ADC_THRHLR6_32B_tag THRHLR6; /* offset: 0x0288 size: 32 bit */
+ /* Upper Threshold register 7 */
+ ADC_THRHLR7_32B_tag THRHLR7; /* offset: 0x028C size: 32 bit */
+ /* Upper Threshold register 8 */
+ ADC_THRHLR8_32B_tag THRHLR8; /* offset: 0x0290 size: 32 bit */
+ /* Upper Threshold register 9 */
+ ADC_THRHLR9_32B_tag THRHLR9; /* offset: 0x0294 size: 32 bit */
+ /* Upper Threshold register 10 */
+ ADC_THRHLR10_32B_tag THRHLR10; /* offset: 0x0298 size: 32 bit */
+ /* Upper Threshold register 11 */
+ ADC_THRHLR11_32B_tag THRHLR11; /* offset: 0x029C size: 32 bit */
+ /* Upper Threshold register 12 */
+ ADC_THRHLR12_32B_tag THRHLR12; /* offset: 0x02A0 size: 32 bit */
+ /* Upper Threshold register 13 */
+ ADC_THRHLR13_32B_tag THRHLR13; /* offset: 0x02A4 size: 32 bit */
+ /* Upper Threshold register 14 */
+ ADC_THRHLR14_32B_tag THRHLR14; /* offset: 0x02A8 size: 32 bit */
+ /* Upper Threshold register 15 */
+ ADC_THRHLR15_32B_tag THRHLR15; /* offset: 0x02AC size: 32 bit */
+ union {
+ /* Channel Watchdog Select register */
+ ADC_CWSELR_32B_tag CWSELR[12]; /* offset: 0x02B0 (0x0004 x 12) */
+
+ struct {
+ /* Channel Watchdog Select register */
+ ADC_CWSELR_32B_tag CWSELR0; /* offset: 0x02B0 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR1; /* offset: 0x02B4 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR2; /* offset: 0x02B8 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR3; /* offset: 0x02BC size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR4; /* offset: 0x02C0 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR5; /* offset: 0x02C4 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR6; /* offset: 0x02C8 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR7; /* offset: 0x02CC size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR8; /* offset: 0x02D0 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR9; /* offset: 0x02D4 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR10; /* offset: 0x02D8 size: 32 bit */
+ ADC_CWSELR_32B_tag CWSELR11; /* offset: 0x02DC size: 32 bit */
+ };
+
+ };
+ union {
+ /* Channel Watchdog Enable Register */
+ ADC_CWENR_32B_tag CWENR[3]; /* offset: 0x02E0 (0x0004 x 3) */
+
+ struct {
+ /* Channel Watchdog Enable Register */
+ ADC_CWENR_32B_tag CWENR0; /* offset: 0x02E0 size: 32 bit */
+ ADC_CWENR_32B_tag CWENR1; /* offset: 0x02E4 size: 32 bit */
+ ADC_CWENR_32B_tag CWENR2; /* offset: 0x02E8 size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_02EC_C[4];
+ union {
+ /* Analog Watchdog Out of Range Register */
+ ADC_AWORR_32B_tag AWORR[3]; /* offset: 0x02F0 (0x0004 x 3) */
+
+ struct {
+ /* Analog Watchdog Out of Range Register */
+ ADC_AWORR_32B_tag AWORR0; /* offset: 0x02F0 size: 32 bit */
+ ADC_AWORR_32B_tag AWORR1; /* offset: 0x02F4 size: 32 bit */
+ ADC_AWORR_32B_tag AWORR2; /* offset: 0x02F8 size: 32 bit */
+ };
+
+ };
+ int8_t ADC_reserved_02FC[68];
+ /* SELF TEST CONFIGURATION REGISTER 1 */
+ ADC_STCR1_32B_tag STCR1; /* offset: 0x0340 size: 32 bit */
+ /* SELF TEST CONFIGURATION REGISTER 2 */
+ ADC_STCR2_32B_tag STCR2; /* offset: 0x0344 size: 32 bit */
+ /* SELF TEST CONFIGURATION REGISTER 3 */
+ ADC_STCR3_32B_tag STCR3; /* offset: 0x0348 size: 32 bit */
+ /* SELF TEST BAUD RATE REGISTER */
+ ADC_STBRR_32B_tag STBRR; /* offset: 0x034C size: 32 bit */
+ /* SELF TEST STATUS REGISTER 1 */
+ ADC_STSR1_32B_tag STSR1; /* offset: 0x0350 size: 32 bit */
+ /* SELF TEST STATUS REGISTER 2 */
+ ADC_STSR2_32B_tag STSR2; /* offset: 0x0354 size: 32 bit */
+ /* SELF TEST STATUS REGISTER 3 */
+ ADC_STSR3_32B_tag STSR3; /* offset: 0x0358 size: 32 bit */
+ /* SELF TEST STATUS REGISTER 4 */
+ ADC_STSR4_32B_tag STSR4; /* offset: 0x035C size: 32 bit */
+ int8_t ADC_reserved_0360[16];
+ /* SELF TEST DATA REGISTER 1 */
+ ADC_STDR1_32B_tag STDR1; /* offset: 0x0370 size: 32 bit */
+ /* SELF TEST DATA REGISTER 2 */
+ ADC_STDR2_32B_tag STDR2; /* offset: 0x0374 size: 32 bit */
+ int8_t ADC_reserved_0378[8];
+ /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
+ ADC_STAW0R_32B_tag STAW0R; /* offset: 0x0380 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
+ ADC_STAW1AR_32B_tag STAW1AR; /* offset: 0x0384 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
+ ADC_STAW1BR_32B_tag STAW1BR; /* offset: 0x0388 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
+ ADC_STAW2R_32B_tag STAW2R; /* offset: 0x038C size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
+ ADC_STAW3R_32B_tag STAW3R; /* offset: 0x0390 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
+ ADC_STAW4R_32B_tag STAW4R; /* offset: 0x0394 size: 32 bit */
+ /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
+ ADC_STAW5R_32B_tag STAW5R; /* offset: 0x0398 size: 32 bit */
+ } ADC_tag;
+
+
+#define ADC0 (*(volatile ADC_tag *) 0xFFE00000UL)
+#define ADC1 (*(volatile ADC_tag *) 0xFFE04000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CTU */
+/* */
+/****************************************************************/
+
+ typedef union { /* Trigger Generator Subunit Input Selection register */
+ vuint32_t R;
+ struct {
+ vuint32_t I15_FE:1; /* ext_signal Falling Edge */
+ vuint32_t I15_RE:1; /* ext_signal Rising Edge */
+ vuint32_t I14_FE:1; /* eTimer2 Falling Edge Enable */
+ vuint32_t I14_RE:1; /* eTimer2 Rising Edge Enable */
+ vuint32_t I13_FE:1; /* eTimer1 Falling Edge Enable */
+ vuint32_t I13_RE:1; /* eTimer1 Rising Edge Enable */
+ vuint32_t I12_FE:1; /* RPWM ch3 Falling Edge Enable */
+ vuint32_t I12_RE:1; /* RPWM ch3 Rising Edge Enable */
+ vuint32_t I11_FE:1; /* RPWM ch2 Falling Edge Enable */
+ vuint32_t I11_RE:1; /* RPWM ch2 Rising Edge Enable */
+ vuint32_t I10_FE:1; /* RPWM ch1 Falling Edge Enable */
+ vuint32_t I10_RE:1; /* RPWM ch1 Rising Edge Enable */
+ vuint32_t I9_FE:1; /* RPWM ch0 Falling Edge Enable */
+ vuint32_t I9_RE:1; /* RPWM ch0 Rising Edge Enable */
+ vuint32_t I8_FE:1; /* PWM ch3 even trig Falling edge Enable */
+ vuint32_t I8_RE:1; /* PWM ch3 even trig Rising edge Enable */
+ vuint32_t I7_FE:1; /* PWM ch2 even trig Falling edge Enable */
+ vuint32_t I7_RE:1; /* PWM ch2 even trig Rising edge Enable */
+ vuint32_t I6_FE:1; /* PWM ch1 even trig Falling edge Enable */
+ vuint32_t I6_RE:1; /* PWM ch1 even trig Rising edge Enable */
+ vuint32_t I5_FE:1; /* PWM ch0 even trig Falling edge Enable */
+ vuint32_t I5_RE:1; /* PWM ch0 even trig Rising edge Enable */
+ vuint32_t I4_FE:1; /* PWM ch3 odd trig Falling edge Enable */
+ vuint32_t I4_RE:1; /* PWM ch3 odd trig Rising edge Enable */
+ vuint32_t I3_FE:1; /* PWM ch2 odd trig Falling edge Enable */
+ vuint32_t I3_RE:1; /* PWM ch2 odd trig Rising edge Enable */
+ vuint32_t I2_FE:1; /* PWM ch1 odd trig Falling edge Enable */
+ vuint32_t I2_RE:1; /* PWM ch1 odd trig Rising edge Enable */
+ vuint32_t I1_FE:1; /* PWM ch0 odd trig Falling edge Enable */
+ vuint32_t I1_RE:1; /* PWM ch0 odd trig Rising edge Enable */
+ vuint32_t I0_FE:1; /* PWM Reload Falling Edge Enable */
+ vuint32_t I0_RE:1; /* PWM Reload Rising Edge Enable */
+ } B;
+ } CTU_TGSISR_32B_tag;
+
+ typedef union { /* Trigger Generator Subunit Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:7;
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t ET_TM:1; /* Toggle Mode Enable */
+#else
+ vuint16_t ETTM:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t PRES:2; /* TGS Prescaler Selection */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_SM:5; /* MRS Selection in Sequential Mode */
+#else
+ vuint16_t MRSSM:5; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t TGS_M:1; /* Trigger Generator Subunit Mode */
+#else
+ vuint16_t TGSM:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } CTU_TGSCR_16B_tag;
+
+ typedef union { /* */
+ vuint16_t R;
+ } CTU_TCR_16B_tag;
+
+ typedef union { /* TGS Counter Compare Register */
+ vuint16_t R;
+#ifndef USE_FIELD_ALIASES_CTU
+ struct {
+ vuint16_t TGSCCV:16; /* deprecated field -- do not use */
+ } B;
+#endif
+ } CTU_TGSCCR_16B_tag;
+
+ typedef union { /* TGS Counter Reload Register */
+ vuint16_t R;
+#ifndef USE_FIELD_ALIASES_CTU
+ struct {
+ vuint16_t TGSCRV:16; /* deprecated field -- do not use */
+ } B;
+#endif
+ } CTU_TGSCRR_16B_tag;
+
+ typedef union { /* Commands List Control Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t T3INDEX:5; /* Trigger 3 First Command address */
+ vuint32_t:3;
+ vuint32_t T2INDEX:5; /* Trigger 2 First Command address */
+ vuint32_t:3;
+ vuint32_t T1INDEX:5; /* Trigger 1 First Command address */
+ vuint32_t:3;
+ vuint32_t T0INDEX:5; /* Trigger 0 First Command address */
+ } B;
+ } CTU_CLCR1_32B_tag;
+
+ typedef union { /* Commands List Control Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t T7INDEX:5; /* Trigger 7 First Command address */
+ vuint32_t:3;
+ vuint32_t T6INDEX:5; /* Trigger 6 First Command address */
+ vuint32_t:3;
+ vuint32_t T5INDEX:5; /* Trigger 5 First Command address */
+ vuint32_t:3;
+ vuint32_t T4INDEX:5; /* Trigger 4 First Command address */
+ } B;
+ } CTU_CLCR2_32B_tag;
+
+ typedef union { /* Trigger Handler Control Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t T3_E:1; /* Trigger 3 enable */
+ vuint32_t T3_ETE:1; /* Trigger 3 Ext Trigger output enable */
+ vuint32_t T3_T4E:1; /* Trigger 3 Timer4 output enable */
+ vuint32_t T3_T3E:1; /* Trigger 3 Timer3 output enable */
+ vuint32_t T3_T2E:1; /* Trigger 3 Timer2 output enable */
+ vuint32_t T3_T1E:1; /* Trigger 3 Timer1 output enable */
+ vuint32_t T3_ADCE:1; /* Trigger 3 ADC Command output enable */
+ vuint32_t:1;
+ vuint32_t T2_E:1; /* Trigger 2 enable */
+ vuint32_t T2_ETE:1; /* Trigger 2 Ext Trigger output enable */
+ vuint32_t T2_T4E:1; /* Trigger 2 Timer4 output enable */
+ vuint32_t T2_T3E:1; /* Trigger 2 Timer3 output enable */
+ vuint32_t T2_T2E:1; /* Trigger 2 Timer2 output enable */
+ vuint32_t T2_T1E:1; /* Trigger 2 Timer1 output enable */
+ vuint32_t T2_ADCE:1; /* Trigger 2 ADC Command output enable */
+ vuint32_t:1;
+ vuint32_t T1_E:1; /* Trigger 1 enable */
+ vuint32_t T1_ETE:1; /* Trigger 1 Ext Trigger output enable */
+ vuint32_t T1_T4E:1; /* Trigger 1 Timer4 output enable */
+ vuint32_t T1_T3E:1; /* Trigger 1 Timer3 output enable */
+ vuint32_t T1_T2E:1; /* Trigger 1 Timer2 output enable */
+ vuint32_t T1_T1E:1; /* Trigger 1 Timer1 output enable */
+ vuint32_t T1_ADCE:1; /* Trigger 1 ADC Command output enable */
+ vuint32_t:1;
+ vuint32_t T0_E:1; /* Trigger 0 enable */
+ vuint32_t T0_ETE:1; /* Trigger 0 Ext Trigger output enable */
+ vuint32_t T0_T4E:1; /* Trigger 0 Timer4 output enable */
+ vuint32_t T0_T3E:1; /* Trigger 0 Timer3 output enable */
+ vuint32_t T0_T2E:1; /* Trigger 0 Timer2 output enable */
+ vuint32_t T0_T1E:1; /* Trigger 0 Timer1 output enable */
+ vuint32_t T0_ADCE:1; /* Trigger 0 ADC Command output enable */
+ } B;
+ } CTU_THCR1_32B_tag;
+
+ typedef union { /* Trigger Handler Control Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t T7_E:1; /* Trigger 7 enable */
+ vuint32_t T7_ETE:1; /* Trigger 7 Ext Trigger output enable */
+ vuint32_t T7_T4E:1; /* Trigger 7 Timer4 output enable */
+ vuint32_t T7_T3E:1; /* Trigger 7 Timer3 output enable */
+ vuint32_t T7_T2E:1; /* Trigger 7 Timer2 output enable */
+ vuint32_t T7_T1E:1; /* Trigger 7 Timer1 output enable */
+ vuint32_t T7_ADCE:1; /* Trigger 7 ADC Command output enable */
+ vuint32_t:1;
+ vuint32_t T6_E:1; /* Trigger 6 enable */
+ vuint32_t T6_ETE:1; /* Trigger 6 Ext Trigger output enable */
+ vuint32_t T6_T4E:1; /* Trigger 6 Timer4 output enable */
+ vuint32_t T6_T3E:1; /* Trigger 6 Timer3 output enable */
+ vuint32_t T6_T2E:1; /* Trigger 6 Timer2 output enable */
+ vuint32_t T6_T1E:1; /* Trigger 6 Timer1 output enable */
+ vuint32_t T6_ADCE:1; /* Trigger 6 ADC Command output enable */
+ vuint32_t:1;
+ vuint32_t T5_E:1; /* Trigger 5 enable */
+ vuint32_t T5_ETE:1; /* Trigger 5 Ext Trigger output enable */
+ vuint32_t T5_T4E:1; /* Trigger 5 Timer4 output enable */
+ vuint32_t T5_T3E:1; /* Trigger 5 Timer3 output enable */
+ vuint32_t T5_T2E:1; /* Trigger 5 Timer2 output enable */
+ vuint32_t T5_T1E:1; /* Trigger 5 Timer1 output enable */
+ vuint32_t T5_ADCE:1; /* Trigger 5 ADC Command output enable */
+ vuint32_t:1;
+ vuint32_t T4_E:1; /* Trigger 4 enable */
+ vuint32_t T4_ETE:1; /* Trigger 4 Ext Trigger output enable */
+ vuint32_t T4_T4E:1; /* Trigger 4 Timer4 output enable */
+ vuint32_t T4_T3E:1; /* Trigger 4 Timer3 output enable */
+ vuint32_t T4_T2E:1; /* Trigger 4 Timer2 output enable */
+ vuint32_t T4_T1E:1; /* Trigger 4 Timer1 output enable */
+ vuint32_t T4_ADCE:1; /* Trigger 4 ADC Command output enable */
+ } B;
+ } CTU_THCR2_32B_tag;
+
+
+ /* Register layout for all registers CLR_DCM... */
+
+ typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
+ vuint16_t R;
+ struct {
+ vuint16_t CIR:1; /* Command Interrupt Request */
+ vuint16_t LC:1; /* Last Command */
+ vuint16_t CMS:1; /* Conversion Mode Selection */
+ vuint16_t FIFO:3; /* FIFO for ADC A/B */
+ vuint16_t:1;
+ vuint16_t CHB:4; /* ADC unit B channel number */
+ vuint16_t:1;
+ vuint16_t CHA:4; /* ADC unit A channel number */
+ } B;
+ } CTU_CLR_DCM_16B_tag;
+
+
+ /* Register layout for all registers CLR_SCM... */
+
+ typedef union { /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
+ vuint16_t R;
+ struct {
+ vuint16_t CIR:1; /* Command Interrupt Request */
+ vuint16_t LC:1; /* Last Command */
+ vuint16_t CMS:1; /* Conversion Mode Selection */
+ vuint16_t FIFO:3; /* FIFO for ADC A/B */
+ vuint16_t:4;
+ vuint16_t SU:1; /* Selection ADC Unit */
+ vuint16_t:1;
+ vuint16_t CH:4; /* ADC unit channel number */
+ } B;
+ } CTU_CLR_SCM_16B_tag;
+
+
+ /* Register layout for all registers CLR... */
+
+
+ typedef union { /* Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t EMPTY_CLR7:1; /* Empty Clear 7 */
+ vuint16_t EMPTY_CLR6:1; /* Empty Clear 6 */
+ vuint16_t EMPTY_CLR5:1; /* Empty Clear 5 */
+ vuint16_t EMPTY_CLR4:1; /* Empty Clear 4 */
+ vuint16_t EMPTY_CLR3:1; /* Empty Clear 3 */
+ vuint16_t EMPTY_CLR2:1; /* Empty Clear 2 */
+ vuint16_t EMPTY_CLR1:1; /* Empty Clear 1 */
+ vuint16_t EMPTY_CLR0:1; /* Empty Clear 0 */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN7:1; /* Enable DMA interface for FIFO 7 */
+#else
+ vuint16_t DMAEN7:1; /* Enable DMA interface for FIFO 7 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN6:1; /* Enable DMA interface for FIFO 6 */
+#else
+ vuint16_t DMAEN6:1; /* Enable DMA interface for FIFO 6 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN5:1; /* Enable DMA interface for FIFO 5 */
+#else
+ vuint16_t DMAEN5:1; /* Enable DMA interface for FIFO 5 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN4:1; /* Enable DMA interface for FIFO 4 */
+#else
+ vuint16_t DMAEN4:1; /* Enable DMA interface for FIFO 4 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN3:1; /* Enable DMA interface for FIFO 3 */
+#else
+ vuint16_t DMAEN3:1; /* Enable DMA interface for FIFO 3 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN2:1; /* Enable DMA interface for FIFO 2 */
+#else
+ vuint16_t DMAEN2:1; /* Enable DMA interface for FIFO 2 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN1:1; /* Enable DMA interface for FIFO 1 */
+#else
+ vuint16_t DMAEN1:1; /* Enable DMA interface for FIFO 1 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t DMA_EN0:1; /* Enable DMA interface for FIFO 0 */
+#else
+ vuint16_t DMAEN0:1; /* Enable DMA interface for FIFO 0 */
+#endif
+ } B;
+ } CTU_CR_16B_tag;
+
+ typedef union { /* Control Register FIFO */
+ vuint32_t R;
+ struct {
+ vuint32_t FIFO_OVERRUN_EN7:1; /* FIFO 7 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN7:1; /* FIFO 7 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN7:1; /* FIFO 7 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN7:1; /* FIFO 7 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN6:1; /* FIFO 6 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN6:1; /* FIFO 6 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN6:1; /* FIFO 6 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN6:1; /* FIFO 6 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN5:1; /* FIFO 5 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN5:1; /* FIFO 5 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN5:1; /* FIFO 5 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN5:1; /* FIFO 5 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN4:1; /* FIFO 4 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN4:1; /* FIFO 4 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN4:1; /* FIFO 4 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN4:1; /* FIFO 4 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN3:1; /* FIFO 3 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN3:1; /* FIFO 3 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN3:1; /* FIFO 3 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN3:1; /* FIFO 3 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN2:1; /* FIFO 2 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN2:1; /* FIFO 2 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN2:1; /* FIFO 2 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN2:1; /* FIFO 2 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN1:1; /* FIFO 1 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN1:1; /* FIFO 1 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN1:1; /* FIFO 1 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN1:1; /* FIFO 1 FULL Enable Interrupt */
+ vuint32_t FIFO_OVERRUN_EN0:1; /* FIFO 0 OVERRUN Enable Interrupt */
+ vuint32_t FIFO_OVERFLOW_EN0:1; /* FIFO 0 OVERFLOW Enable Interrupt */
+ vuint32_t FIFO_EMPTY_EN0:1; /* FIFO 0 EMPTY Enable Interrupt */
+ vuint32_t FIFO_FULL_EN0:1; /* FIFO 0 FULL Enable Interrupt */
+ } B;
+ } CTU_FCR_32B_tag;
+
+ typedef union { /* Threshold 1 Register */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD3:8; /* Threshlod FIFO 3 */
+#else
+ vuint32_t THRESHOLD3:8; /* Threshlod FIFO 3 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD2:8; /* Threshlod FIFO 2 */
+#else
+ vuint32_t THRESHOLD2:8; /* Threshlod FIFO 2 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD1:8; /* Threshlod FIFO 1 */
+#else
+ vuint32_t THRESHOLD1:8; /* Threshlod FIFO 1 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD0:8; /* Threshlod FIFO 0 */
+#else
+ vuint32_t THRESHOLD0:8; /* Threshlod FIFO 0 */
+#endif
+ } B;
+ } CTU_TH1_32B_tag;
+
+ typedef union { /* Threshold 2 Register */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD7:8; /* Threshlod FIFO 7 */
+#else
+ vuint32_t THRESHOLD7:8; /* Threshlod FIFO 7 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD6:8; /* Threshlod FIFO 6 */
+#else
+ vuint32_t THRESHOLD6:8; /* Threshlod FIFO 6 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD5:8; /* Threshlod FIFO 5 */
+#else
+ vuint32_t THRESHOLD5:8; /* Threshlod FIFO 5 */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint32_t TRESHOLD4:8; /* Threshlod FIFO 4 */
+#else
+ vuint32_t THRESHOLD4:8; /* Threshlod FIFO 4 */
+#endif
+ } B;
+ } CTU_TH2_32B_tag;
+
+ typedef union { /* Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t FIFO_OVERRUN7:1; /* FIFO 7 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW7:1; /* FIFO 7 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY7:1; /* FIFO 7 EMPTY Flag */
+ vuint32_t FIFO_FULL7:1; /* FIFO 7 FULL Flag */
+ vuint32_t FIFO_OVERRUN6:1; /* FIFO 6 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW6:1; /* FIFO 6 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY6:1; /* FIFO 6 EMPTY Flag */
+ vuint32_t FIFO_FULL6:1; /* FIFO 6 FULL Flag */
+ vuint32_t FIFO_OVERRUN5:1; /* FIFO 5 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW5:1; /* FIFO 5 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY5:1; /* FIFO 5 EMPTY Flag */
+ vuint32_t FIFO_FULL5:1; /* FIFO 5 FULL Flag */
+ vuint32_t FIFO_OVERRUN4:1; /* FIFO 4 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW4:1; /* FIFO 4 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY4:1; /* FIFO 4 EMPTY Flag */
+ vuint32_t FIFO_FULL4:1; /* FIFO 4 FULL Flag */
+ vuint32_t FIFO_OVERRUN3:1; /* FIFO 3 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW3:1; /* FIFO 3 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY3:1; /* FIFO 3 EMPTY Flag */
+ vuint32_t FIFO_FULL3:1; /* FIFO 3 FULL Flag */
+ vuint32_t FIFO_OVERRUN2:1; /* FIFO 2 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW2:1; /* FIFO 2 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY2:1; /* FIFO 2 EMPTY Flag */
+ vuint32_t FIFO_FULL2:1; /* FIFO 2 FULL Flag */
+ vuint32_t FIFO_OVERRUN1:1; /* FIFO 1 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW1:1; /* FIFO 1 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY1:1; /* FIFO 1 EMPTY Flag */
+ vuint32_t FIFO_FULL1:1; /* FIFO 1 FULL Flag */
+ vuint32_t FIFO_OVERRUN0:1; /* FIFO 0 OVERRUN Flag */
+ vuint32_t FIFO_OVERFLOW0:1; /* FIFO 0 OVERFLOW Flag */
+ vuint32_t FIFO_EMPTY0:1; /* FIFO 0 EMPTY Flag */
+ vuint32_t FIFO_FULL0:1; /* FIFO 0 FULL Flag */
+ } B;
+ } CTU_STS_32B_tag;
+
+
+ /* Register layout for all registers FR... */
+
+ typedef union { /* FIFO Right Aligned register */
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t ADC:1; /* ADC Unit */
+ vuint32_t N_CH:4; /* Number Channel */
+ vuint32_t:4;
+ vuint32_t DATA:12; /* Data Fifo */
+ } B;
+ } CTU_FR_32B_tag;
+
+
+ /* Register layout for all registers FL... */
+
+ typedef union { /* FIFO Left Aligned register */
+ vuint32_t R;
+ struct {
+ vuint32_t:11;
+ vuint32_t ADC:1; /* ADC Unit */
+ vuint32_t N_CH:4; /* Number Channel */
+ vuint32_t:1;
+ vuint32_t DATA:12; /* Data Fifo */
+ vuint32_t:3;
+ } B;
+ } CTU_FL_32B_tag;
+
+ typedef union { /* CTU Error Flag Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t CS:1; /* Counter Status */
+ vuint16_t ET_OE:1; /* ExtTrigger Generation Overrun */
+ vuint16_t ERR_CMP:1; /* Set if counter reaches TGSCCR register */
+ vuint16_t T4_OE:1; /* Timer4 Generation Overrun */
+ vuint16_t T3_OE:1; /* Timer3 Generation Overrun */
+ vuint16_t T2_OE:1; /* Timer2 Generation Overrun */
+ vuint16_t T1_OE:1; /* Timer1 Generation Overrun */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t ADC_OE:1; /* ADC Command Generation Overrun */
+#else
+ vuint16_t ADCOE:1; /* ADC Command Generation Overrun */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t TGS_OSM:1; /* TGS Overrun */
+#else
+ vuint16_t TGSOSM:1; /* TGS Overrun */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_O:1; /* MRS Overrun */
+#else
+ vuint16_t MRSO:1; /* TGS Overrun */
+#endif
+ vuint16_t ICE:1; /* Invalid Command Error */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t SM_TO:1; /* Trigger Overrun */
+#else
+ vuint16_t SMTO:1; /* Trigger Overrun */
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_RE:1; /* MRS Reload Error */
+#else
+ vuint16_t MRSRE:1; /* MRS Reload Error */
+#endif
+ } B;
+ } CTU_CTUEFR_16B_tag;
+
+ typedef union { /* CTU Interrupt Flag Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t S_E_B:1; /* Slice time OK */
+ vuint16_t S_E_A:1; /* Slice time OK */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t ADC_I:1; /* ADC Command Interrupt Flag */
+#else
+ vuint16_t ADC:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T7_I:1; /* Trigger 7 Interrupt Flag */
+#else
+ vuint16_t T7:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T6_I:1; /* Trigger 6 Interrupt Flag */
+#else
+ vuint16_t T6:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T5_I:1; /* Trigger 5 Interrupt Flag */
+#else
+ vuint16_t T5:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T4_I:1; /* Trigger 4 Interrupt Flag */
+#else
+ vuint16_t T4:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T3_I:1; /* Trigger 3 Interrupt Flag */
+#else
+ vuint16_t T3:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T2_I:1; /* Trigger 2 Interrupt Flag */
+#else
+ vuint16_t T2:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T1_I:1; /* Trigger 1 Interrupt Flag */
+#else
+ vuint16_t T1:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T0_I:1; /* Trigger 0 Interrupt Flag */
+#else
+ vuint16_t T0:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_I:1; /* MRS Interrupt Flag */
+#else
+ vuint16_t MRS:1;
+#endif
+ } B;
+ } CTU_CTUIFR_16B_tag;
+
+ typedef union { /* CTU Interrupt/DMA Register */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T7_I:1; /* Trigger 7 Interrupt Enable */
+#else
+ vuint16_t T7IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T6_I:1; /* Trigger 6 Interrupt Enable */
+#else
+ vuint16_t T6IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T5_I:1; /* Trigger 5 Interrupt Enable */
+#else
+ vuint16_t T5IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T4_I:1; /* Trigger 4 Interrupt Enable */
+#else
+ vuint16_t T4IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T3_I:1; /* Trigger 3 Interrupt Enable */
+#else
+ vuint16_t T3IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T2_I:1; /* Trigger 2 Interrupt Enable */
+#else
+ vuint16_t T2IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T1_I:1; /* Trigger 1 Interrupt Enable */
+#else
+ vuint16_t T1IE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T0_I:1; /* Trigger 0 Interrupt Enable */
+#else
+ vuint16_t T0IE:1;
+#endif
+ vuint16_t:2;
+ vuint16_t SAF_CNT_B_EN:1; /* Conversion time counter enabled */
+ vuint16_t SAF_CNT_A_EN:1; /* Conversion time counter enabled */
+ vuint16_t DMA_DE:1; /* DMA and gre bit */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_DMAE:1; /* DMA Transfer Enable */
+#else
+ vuint16_t MRSDMAE:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_IE:1; /* MRS Interrupt Enable */
+#else
+ vuint16_t MRSIE:1;
+#endif
+ vuint16_t IEE:1; /* Interrupt Error Enable */
+ } B;
+ } CTU_CTUIR_16B_tag;
+
+ typedef union { /* Control On-Time Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t COTR_COTR:8; /* Control On-Time Register and Guard Time */
+#else
+ vuint16_t COTR:8;
+#endif
+ } B;
+ } CTU_COTR_16B_tag;
+
+ typedef union { /* CTU Control Register */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T7_SG:1; /* Trigger 7 Software Generated */
+#else
+ vuint16_t T7SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T6_SG:1; /* Trigger 6 Software Generated */
+#else
+ vuint16_t T6SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T5_SG:1; /* Trigger 5 Software Generated */
+#else
+ vuint16_t T5SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T4_SG:1; /* Trigger 4 Software Generated */
+#else
+ vuint16_t T4SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T3_SG:1; /* Trigger 3 Software Generated */
+#else
+ vuint16_t T3SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T2_SG:1; /* Trigger 2 Software Generated */
+#else
+ vuint16_t T2SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T1_SG:1; /* Trigger 1 Software Generated */
+#else
+ vuint16_t T1SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t T0_SG:1; /* Trigger 0 Software Generated */
+#else
+ vuint16_t T0SG:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t CTU_ADC_RESET:1; /* CTU ADC State Machine Reset */
+#else
+ vuint16_t CTUADCRESET:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t CTU_ODIS:1; /* CTU Output Disable */
+#else
+ vuint16_t CTUODIS:1;
+#endif
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t FILTER_EN:1; /* Synchronize Filter Register value */
+#else
+ vuint16_t FILTERENABLE:1;
+#endif
+ vuint16_t CGRE:1; /* Clear GRE */
+ vuint16_t FGRE:1; /* GRE Flag */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t MRS_SG:1; /* MRS Software Generated */
+#else
+ vuint16_t MRSSG:1;
+#endif
+ vuint16_t GRE:1; /* General Reload Enable */
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t TGSISR_RE:1; /* TGSISR Reload Enable */
+#else
+ vuint16_t TGSISRRE:1;
+#endif
+ } B;
+ } CTU_CTUCR_16B_tag;
+
+ typedef union { /* CTU Digital Filter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+#ifndef USE_FIELD_ALIASES_CTU
+ vuint16_t FILTER_VALUE:8; /* Filter Value */
+#else
+ vuint16_t FILTERVALUE:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } CTU_FILTER_16B_tag;
+
+ typedef union { /* CTU Expected A Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t EXPECTED_A_VALUE:16; /* Expected A Value */
+ } B;
+ } CTU_EXPECTED_A_16B_tag;
+
+ typedef union { /* CTU Expected B Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t EXPECTED_B_VALUE:16; /* Expected B Value */
+ } B;
+ } CTU_EXPECTED_B_16B_tag;
+
+ typedef union { /* CTU Counter Range Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t CNT_RANGE_VALUE:8; /* Counter Range Value */
+ } B;
+ } CTU_CNT_RANGE_16B_tag;
+
+
+ /* Register layout for generated register(s) FRA... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } CTU_FRA_32B_tag;
+
+
+ /* Register layout for generated register(s) FLA... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } CTU_FLA_32B_tag;
+
+
+
+ typedef struct CTU_struct_tag { /* start of CTU_tag */
+ /* Trigger Generator Subunit Input Selection register */
+ CTU_TGSISR_32B_tag TGSISR; /* offset: 0x0000 size: 32 bit */
+ /* Trigger Generator Subunit Control Register */
+ CTU_TGSCR_16B_tag TGSCR; /* offset: 0x0004 size: 16 bit */
+ union {
+ CTU_TCR_16B_tag TCR[8]; /* offset: 0x0006 (0x0002 x 8) */
+
+ struct {
+ CTU_TCR_16B_tag T0CR; /* offset: 0x0006 size: 16 bit */
+ CTU_TCR_16B_tag T1CR; /* offset: 0x0008 size: 16 bit */
+ CTU_TCR_16B_tag T2CR; /* offset: 0x000A size: 16 bit */
+ CTU_TCR_16B_tag T3CR; /* offset: 0x000C size: 16 bit */
+ CTU_TCR_16B_tag T4CR; /* offset: 0x000E size: 16 bit */
+ CTU_TCR_16B_tag T5CR; /* offset: 0x0010 size: 16 bit */
+ CTU_TCR_16B_tag T6CR; /* offset: 0x0012 size: 16 bit */
+ CTU_TCR_16B_tag T7CR; /* offset: 0x0014 size: 16 bit */
+ };
+
+ };
+ /* TGS Counter Compare Register */
+ CTU_TGSCCR_16B_tag TGSCCR; /* offset: 0x0016 size: 16 bit */
+ /* TGS Counter Reload Register */
+ CTU_TGSCRR_16B_tag TGSCRR; /* offset: 0x0018 size: 16 bit */
+ int8_t CTU_reserved_001A[2];
+ /* Commands List Control Register 1 */
+ CTU_CLCR1_32B_tag CLCR1; /* offset: 0x001C size: 32 bit */
+ /* Commands List Control Register 2 */
+ CTU_CLCR2_32B_tag CLCR2; /* offset: 0x0020 size: 32 bit */
+ /* Trigger Handler Control Register 1 */
+ CTU_THCR1_32B_tag THCR1; /* offset: 0x0024 size: 32 bit */
+ /* Trigger Handler Control Register 2 */
+ CTU_THCR2_32B_tag THCR2; /* offset: 0x0028 size: 32 bit */
+ union {
+ /* Command List Register. View: BIT13, BIT9 */
+ CTU_CLR_SCM_16B_tag CLR[24]; /* offset: 0x002C (0x0002 x 24) */ /* deprecated name - please avoid */
+
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
+ CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C (0x0002 x 24) */
+
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
+ CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C (0x0002 x 24) */
+
+ struct {
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
+ CTU_CLR_SCM_16B_tag CLR_SCM1; /* offset: 0x002C size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM2; /* offset: 0x002E size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM3; /* offset: 0x0030 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM4; /* offset: 0x0032 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM5; /* offset: 0x0034 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM6; /* offset: 0x0036 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM7; /* offset: 0x0038 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM8; /* offset: 0x003A size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM9; /* offset: 0x003C size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */
+ CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */
+ };
+
+ struct {
+ /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
+ CTU_CLR_DCM_16B_tag CLR_DCM1; /* offset: 0x002C size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM2; /* offset: 0x002E size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM3; /* offset: 0x0030 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM4; /* offset: 0x0032 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM5; /* offset: 0x0034 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM6; /* offset: 0x0036 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM7; /* offset: 0x0038 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM8; /* offset: 0x003A size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM9; /* offset: 0x003C size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */
+ CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */
+ };
+
+ };
+ int8_t CTU_reserved_005C[16];
+ /* Control Register */
+ CTU_CR_16B_tag CR; /* offset: 0x006C size: 16 bit */
+ int8_t CTU_reserved_006E[2];
+ /* Control Register FIFO */
+ CTU_FCR_32B_tag FCR; /* offset: 0x0070 size: 32 bit */
+ /* Threshold 1 Register */
+ CTU_TH1_32B_tag TH1; /* offset: 0x0074 size: 32 bit */
+ /* Threshold 2 Register */
+ CTU_TH2_32B_tag TH2; /* offset: 0x0078 size: 32 bit */
+ union {
+ /* Status Register */
+ CTU_STS_32B_tag STS; /* offset: 0x007C size: 32 bit */
+
+ CTU_STS_32B_tag STATUS; /* deprecated - please avoid */
+
+ };
+ union {
+ CTU_FRA_32B_tag FRA[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ /* FIFO Right Aligned register */
+ CTU_FR_32B_tag FR[8]; /* offset: 0x0080 (0x0004 x 8) */
+
+ struct {
+ /* FIFO Right Aligned register */
+ CTU_FR_32B_tag FR0; /* offset: 0x0080 size: 32 bit */
+ CTU_FR_32B_tag FR1; /* offset: 0x0084 size: 32 bit */
+ CTU_FR_32B_tag FR2; /* offset: 0x0088 size: 32 bit */
+ CTU_FR_32B_tag FR3; /* offset: 0x008C size: 32 bit */
+ CTU_FR_32B_tag FR4; /* offset: 0x0090 size: 32 bit */
+ CTU_FR_32B_tag FR5; /* offset: 0x0094 size: 32 bit */
+ CTU_FR_32B_tag FR6; /* offset: 0x0098 size: 32 bit */
+ CTU_FR_32B_tag FR7; /* offset: 0x009C size: 32 bit */
+ };
+
+ };
+ union {
+ CTU_FLA_32B_tag FLA[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ /* FIFO Left Aligned register */
+ CTU_FL_32B_tag FL[8]; /* offset: 0x00A0 (0x0004 x 8) */
+
+ struct {
+ /* FIFO Left Aligned register */
+ CTU_FL_32B_tag FL0; /* offset: 0x00A0 size: 32 bit */
+ CTU_FL_32B_tag FL1; /* offset: 0x00A4 size: 32 bit */
+ CTU_FL_32B_tag FL2; /* offset: 0x00A8 size: 32 bit */
+ CTU_FL_32B_tag FL3; /* offset: 0x00AC size: 32 bit */
+ CTU_FL_32B_tag FL4; /* offset: 0x00B0 size: 32 bit */
+ CTU_FL_32B_tag FL5; /* offset: 0x00B4 size: 32 bit */
+ CTU_FL_32B_tag FL6; /* offset: 0x00B8 size: 32 bit */
+ CTU_FL_32B_tag FL7; /* offset: 0x00BC size: 32 bit */
+ };
+
+ };
+ /* CTU Error Flag Register */
+ CTU_CTUEFR_16B_tag CTUEFR; /* offset: 0x00C0 size: 16 bit */
+ /* CTU Interrupt Flag Register */
+ CTU_CTUIFR_16B_tag CTUIFR; /* offset: 0x00C2 size: 16 bit */
+ /* CTU Interrupt/DMA Register */
+ CTU_CTUIR_16B_tag CTUIR; /* offset: 0x00C4 size: 16 bit */
+ /* Control On-Time Register */
+ CTU_COTR_16B_tag COTR; /* offset: 0x00C6 size: 16 bit */
+ /* CTU Control Register */
+ CTU_CTUCR_16B_tag CTUCR; /* offset: 0x00C8 size: 16 bit */
+ union {
+ /* CTU Digital Filter Register */
+ CTU_FILTER_16B_tag FILTER; /* offset: 0x00CA size: 16 bit */
+
+ CTU_FILTER_16B_tag CTUFILTER; /* deprecated - please avoid */
+
+ };
+ /* CTU Expected A Value Register */
+ CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */
+
+ /* CTU Expected B Value Register */
+ CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */
+ /* CTU Counter Range Register */
+ CTU_CNT_RANGE_16B_tag CNT_RANGE; /* offset: 0x00D0 size: 16 bit */
+ } CTU_tag;
+
+
+#define CTU (*(volatile CTU_tag *) 0xFFE0C000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: mcTIMER */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers COMP1... */
+
+ typedef union { /* Compare Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t COMP1:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_COMP1_16B_tag;
+
+
+ /* Register layout for all registers COMP2... */
+
+ typedef union { /* Compare Register 2 */
+ vuint16_t R;
+ struct {
+ vuint16_t COMP2:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_COMP2_16B_tag;
+
+
+ /* Register layout for all registers CAPT1... */
+
+ typedef union { /* Capture Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT1:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CAPT1_16B_tag;
+
+
+ /* Register layout for all registers CAPT2... */
+
+ typedef union { /* Capture Register 2 */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPT2:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CAPT2_16B_tag;
+
+
+ /* Register layout for all registers LOAD... */
+
+ typedef union { /* Load Register */
+ vuint16_t R;
+ struct {
+ vuint16_t LOAD:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_LOAD_16B_tag;
+
+
+ /* Register layout for all registers HOLD... */
+
+ typedef union { /* Hold Register */
+ vuint16_t R;
+ struct {
+ vuint16_t HOLD:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_HOLD_16B_tag;
+
+
+ /* Register layout for all registers CNTR... */
+
+ typedef union { /* Counter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CNTR:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CNTR_16B_tag;
+
+
+ /* Register layout for all registers CTRL1... */
+
+ typedef union { /* Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CNTMODE:3; /* Count Mode */
+ vuint16_t PRISRC:5; /* Primary Count Source */
+ vuint16_t ONCE:1; /* Count Once */
+ vuint16_t LENGTH:1; /* Count Length */
+ vuint16_t DIR:1; /* Count Direction */
+ vuint16_t SECSRC:5; /* Secondary Count Source */
+ } B;
+ } mcTIMER_CTRL1_16B_tag;
+
+
+ /* Register layout for all registers CTRL2... */
+
+ typedef union { /* Control Register 2 */
+ vuint16_t R;
+ struct {
+ vuint16_t OEN:1; /* Output Enable */
+ vuint16_t RDNT:1; /* Redundant Channel Enable */
+ vuint16_t INPUT:1; /* External Input Signal */
+ vuint16_t VAL:1; /* Forced OFLAG Value */
+ vuint16_t FORCE:1; /* Force the OFLAG output */
+ vuint16_t COFRC:1; /* Co-channel OFLAG Force */
+ vuint16_t COINIT:2; /* Co-channel Initialization */
+ vuint16_t SIPS:1; /* Secondary Source Input Polarity Select */
+ vuint16_t PIPS:1; /* Primary Source Input Polarity Select */
+ vuint16_t OPS:1; /* Output Polarity Select */
+ vuint16_t MSTR:1; /* Master Mode */
+ vuint16_t OUTMODE:4; /* Output Mode */
+ } B;
+ } mcTIMER_CTRL2_16B_tag;
+
+
+ /* Register layout for all registers CTRL3... */
+
+ typedef union { /* Control Register 3 */
+ vuint16_t R;
+ struct {
+ vuint16_t STPEN:1; /* Stop Action Enable */
+ vuint16_t ROC:2; /* Reload On Capture */
+ vuint16_t FMODE:1; /* Fault Safing Mode */
+ vuint16_t FDIS:4; /* Fault Disable Mask */
+ vuint16_t C2FCNT:3; /* CAPT2 FIFO Word Count */
+ vuint16_t C1FCNT:3; /* CAPT1 FIFO Word Count */
+ vuint16_t DBGEN:2; /* Debug Actions Enable */
+ } B;
+ } mcTIMER_CTRL3_16B_tag;
+
+
+ /* Register layout for all registers STS... */
+
+ typedef union { /* Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t WDF:1; /* Watchdog Time-out Flag */
+ vuint16_t RCF:1; /* Redundant Channel Flag */
+ vuint16_t ICF2:1; /* Input Capture 2 Flag */
+ vuint16_t ICF1:1; /* Input Capture 1 Flag */
+ vuint16_t IEHF:1; /* Input Edge High Flag */
+ vuint16_t IELF:1; /* Input Edge Low Flag */
+ vuint16_t TOF:1; /* Timer Overflow Flag */
+ vuint16_t TCF2:1; /* Timer Compare 2 Flag */
+ vuint16_t TCF1:1; /* Timer Compare 1 Flag */
+ vuint16_t TCF:1; /* Timer Compare Flag */
+ } B;
+ } mcTIMER_STS_16B_tag;
+
+
+ /* Register layout for all registers INTDMA... */
+
+ typedef union { /* Interrupt and DMA Enable Register */
+ vuint16_t R;
+ struct {
+ vuint16_t ICF2DE:1; /* Input Capture 2 Flag DMA Enable */
+ vuint16_t ICF1DE:1; /* Input Capture 1 Flag DMA Enable */
+ vuint16_t CMPLD2DE:1; /* Comparator Load Register 2 Flag DMA Enable */
+ vuint16_t CMPLD1DE:1; /* Comparator Load Register 1 Flag DMA Enable */
+ vuint16_t:2;
+ vuint16_t WDFIE:1; /* Watchdog Flag Interrupt Enable */
+ vuint16_t RCFIE:1; /* Redundant Channel Flag Interrupt Enable */
+ vuint16_t ICF2IE:1; /* Input Capture 2 Flag Interrupt Enable */
+ vuint16_t ICF1IE:1; /* Input Capture 1 Flag Interrupt Enable */
+ vuint16_t IEHFIE:1; /* Input Edge High Flag Interrupt Enable */
+ vuint16_t IELFIE:1; /* Input Edge Low Flag Interrupt Enable */
+ vuint16_t TOFIE:1; /* Timer Overflow Flag Interrupt Enable */
+ vuint16_t TCF2IE:1; /* Timer Compare 2 Flag Interrupt Enable */
+ vuint16_t TCF1IE:1; /* Timer Compare 1 Flag Interrupt Enable */
+ vuint16_t TCFIE:1; /* Timer Compare Flag Interrupt Enable */
+ } B;
+ } mcTIMER_INTDMA_16B_tag;
+
+
+ /* Register layout for all registers CMPLD1... */
+
+ typedef union { /* Comparator Load Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD1:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CMPLD1_16B_tag;
+
+
+ /* Register layout for all registers CMPLD2... */
+
+ typedef union { /* Comparator Load Register 2 */
+ vuint16_t R;
+ struct {
+ vuint16_t CMPLD2:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_CMPLD2_16B_tag;
+
+
+ /* Register layout for all registers CCCTRL... */
+
+ typedef union { /* Compare and Capture Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CLC2:3; /* Compare Load Control 2 */
+ vuint16_t CLC1:3; /* Compare Load Control 1 */
+ vuint16_t CMPMODE:2; /* Compare Mode */
+ vuint16_t CPT2MODE:2; /* Capture 2 Mode Control */
+ vuint16_t CPT1MODE:2; /* Capture 1 Mode Control */
+ vuint16_t CFWM:2; /* Capture FIFO Water Mark */
+ vuint16_t ONESHOT:1; /* One Shot Capture Mode */
+ vuint16_t ARM:1; /* Arm Capture */
+ } B;
+ } mcTIMER_CCCTRL_16B_tag;
+
+
+ /* Register layout for all registers FILT... */
+
+ typedef union { /* Input Filter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ vuint16_t FILT_CNT:3; /* Input Filter Sample Count */
+#else
+ vuint16_t FILTCNT:3; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ vuint16_t FILT_PER:8; /* Input Filter Sample Period */
+#else
+ vuint16_t FILTPER:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcTIMER_FILT_16B_tag;
+
+ typedef union { /* Watchdog Time-out Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOL:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_WDTOL_16B_tag;
+
+ typedef union { /* Watchdog Time-out Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WDTOH:16; /* deprecated definition -- do not use */
+ } B;
+ } mcTIMER_WDTOH_16B_tag;
+
+ typedef union { /* Fault Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t FTEST:1; /* Fault Test */
+ vuint16_t FIE:4; /* Fault Interrupt Enable */
+ vuint16_t:4;
+ vuint16_t FLVL:4; /* Fault Active Logic Level */
+ } B;
+ } mcTIMER_FCTRL_16B_tag;
+
+ typedef union { /* Fault Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t FFPIN:4; /* Filtered Fault Pin */
+ vuint16_t:4;
+ vuint16_t FFLAG:4; /* Fault Flag */
+ } B;
+ } mcTIMER_FSTS_16B_tag;
+
+ typedef union { /* Fault Filter Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ vuint16_t FFPIN:3; /* Fault Filter Sample Count */
+#else
+ vuint16_t FFILTCNT:3; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcTIMER
+ vuint16_t FFILT_PER:8; /* Fault Filter Sample Period */
+#else
+ vuint16_t FFILTPER:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcTIMER_FFILT_16B_tag;
+
+ typedef union { /* Channel Enable Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t ENBL:8; /* Timer Channel Enable */
+ } B;
+ } mcTIMER_ENBL_16B_tag;
+
+ typedef union { /* DMA Request 0 Select Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t DREQ0V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ0_16B_tag;
+
+ typedef union { /* DMA Request 1 Select Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t DREQ1V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ1_16B_tag;
+
+ typedef union { /* DMA Request 2 Select Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t DREQ2V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ2_16B_tag;
+
+ typedef union { /* DMA Request 3 Select Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t DREQ3V:5; /* DMA Request Select */
+ } B;
+ } mcTIMER_DREQ3_16B_tag;
+
+
+ /* Register layout for generated register(s) DREQ... */
+
+ typedef union { /* */
+ vuint16_t R;
+ } mcTIMER_DREQ_16B_tag;
+
+
+ typedef struct mcTIMER_CHANNEL_struct_tag {
+
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP1; /* relative offset: 0x0000 */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP2; /* relative offset: 0x0002 */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT1; /* relative offset: 0x0004 */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT2; /* relative offset: 0x0006 */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD; /* relative offset: 0x0008 */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD; /* relative offset: 0x000A */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR; /* relative offset: 0x000C */
+ union {
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL1; /* relative offset: 0x000E */
+ mcTIMER_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
+ };
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL2; /* relative offset: 0x0010 */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL3; /* relative offset: 0x0012 */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS; /* relative offset: 0x0014 */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA; /* relative offset: 0x0016 */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD1; /* relative offset: 0x0018 */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD2; /* relative offset: 0x001A */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL; /* relative offset: 0x001C */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT; /* relative offset: 0x001E */
+
+ } mcTIMER_CHANNEL_tag;
+
+
+ typedef struct mcTIMER_struct_tag { /* start of mcTIMER_tag */
+ union {
+ /* Register set CHANNEL */
+ mcTIMER_CHANNEL_tag CHANNEL[6]; /* offset: 0x0000 (0x0020 x 6) */
+
+ struct {
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP10; /* offset: 0x0000 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP20; /* offset: 0x0002 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT10; /* offset: 0x0004 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT20; /* offset: 0x0006 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD0; /* offset: 0x0008 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD0; /* offset: 0x000A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR0; /* offset: 0x000C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL10; /* offset: 0x000E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL20; /* offset: 0x0010 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL30; /* offset: 0x0012 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS0; /* offset: 0x0014 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA0; /* offset: 0x0016 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD10; /* offset: 0x0018 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD20; /* offset: 0x001A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL0; /* offset: 0x001C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT0; /* offset: 0x001E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP11; /* offset: 0x0020 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP21; /* offset: 0x0022 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT11; /* offset: 0x0024 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT21; /* offset: 0x0026 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD1; /* offset: 0x0028 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD1; /* offset: 0x002A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR1; /* offset: 0x002C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL11; /* offset: 0x002E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL21; /* offset: 0x0030 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL31; /* offset: 0x0032 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS1; /* offset: 0x0034 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA1; /* offset: 0x0036 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD11; /* offset: 0x0038 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD21; /* offset: 0x003A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL1; /* offset: 0x003C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT1; /* offset: 0x003E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP12; /* offset: 0x0040 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP22; /* offset: 0x0042 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT12; /* offset: 0x0044 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT22; /* offset: 0x0046 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD2; /* offset: 0x0048 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD2; /* offset: 0x004A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR2; /* offset: 0x004C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL12; /* offset: 0x004E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL22; /* offset: 0x0050 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL32; /* offset: 0x0052 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS2; /* offset: 0x0054 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA2; /* offset: 0x0056 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD12; /* offset: 0x0058 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD22; /* offset: 0x005A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL2; /* offset: 0x005C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT2; /* offset: 0x005E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP13; /* offset: 0x0060 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP23; /* offset: 0x0062 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT13; /* offset: 0x0064 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT23; /* offset: 0x0066 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD3; /* offset: 0x0068 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD3; /* offset: 0x006A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR3; /* offset: 0x006C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL13; /* offset: 0x006E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL23; /* offset: 0x0070 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL33; /* offset: 0x0072 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS3; /* offset: 0x0074 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA3; /* offset: 0x0076 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD13; /* offset: 0x0078 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD23; /* offset: 0x007A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL3; /* offset: 0x007C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT3; /* offset: 0x007E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP14; /* offset: 0x0080 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP24; /* offset: 0x0082 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT14; /* offset: 0x0084 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT24; /* offset: 0x0086 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD4; /* offset: 0x0088 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD4; /* offset: 0x008A size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR4; /* offset: 0x008C size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL14; /* offset: 0x008E size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL24; /* offset: 0x0090 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL34; /* offset: 0x0092 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS4; /* offset: 0x0094 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA4; /* offset: 0x0096 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD14; /* offset: 0x0098 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD24; /* offset: 0x009A size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL4; /* offset: 0x009C size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT4; /* offset: 0x009E size: 16 bit */
+ /* Compare Register 1 */
+ mcTIMER_COMP1_16B_tag COMP15; /* offset: 0x00A0 size: 16 bit */
+ /* Compare Register 2 */
+ mcTIMER_COMP2_16B_tag COMP25; /* offset: 0x00A2 size: 16 bit */
+ /* Capture Register 1 */
+ mcTIMER_CAPT1_16B_tag CAPT15; /* offset: 0x00A4 size: 16 bit */
+ /* Capture Register 2 */
+ mcTIMER_CAPT2_16B_tag CAPT25; /* offset: 0x00A6 size: 16 bit */
+ /* Load Register */
+ mcTIMER_LOAD_16B_tag LOAD5; /* offset: 0x00A8 size: 16 bit */
+ /* Hold Register */
+ mcTIMER_HOLD_16B_tag HOLD5; /* offset: 0x00AA size: 16 bit */
+ /* Counter Register */
+ mcTIMER_CNTR_16B_tag CNTR5; /* offset: 0x00AC size: 16 bit */
+ /* Control Register */
+ mcTIMER_CTRL1_16B_tag CTRL15; /* offset: 0x00AE size: 16 bit */
+ /* Control Register 2 */
+ mcTIMER_CTRL2_16B_tag CTRL25; /* offset: 0x00B0 size: 16 bit */
+ /* Control Register 3 */
+ mcTIMER_CTRL3_16B_tag CTRL35; /* offset: 0x00B2 size: 16 bit */
+ /* Status Register */
+ mcTIMER_STS_16B_tag STS5; /* offset: 0x00B4 size: 16 bit */
+ /* Interrupt and DMA Enable Register */
+ mcTIMER_INTDMA_16B_tag INTDMA5; /* offset: 0x00B6 size: 16 bit */
+ /* Comparator Load Register 1 */
+ mcTIMER_CMPLD1_16B_tag CMPLD15; /* offset: 0x00B8 size: 16 bit */
+ /* Comparator Load Register 2 */
+ mcTIMER_CMPLD2_16B_tag CMPLD25; /* offset: 0x00BA size: 16 bit */
+ /* Compare and Capture Control Register */
+ mcTIMER_CCCTRL_16B_tag CCCTRL5; /* offset: 0x00BC size: 16 bit */
+ /* Input Filter Register */
+ mcTIMER_FILT_16B_tag FILT5; /* offset: 0x00BE size: 16 bit */
+ };
+
+ };
+ int8_t mcTIMER_reserved_00C0[64];
+ /* Watchdog Time-out Register */
+ mcTIMER_WDTOL_16B_tag WDTOL; /* offset: 0x0100 size: 16 bit */
+ /* Watchdog Time-out Register */
+ mcTIMER_WDTOH_16B_tag WDTOH; /* offset: 0x0102 size: 16 bit */
+ /* Fault Control Register */
+ mcTIMER_FCTRL_16B_tag FCTRL; /* offset: 0x0104 size: 16 bit */
+ /* Fault Status Register */
+ mcTIMER_FSTS_16B_tag FSTS; /* offset: 0x0106 size: 16 bit */
+ /* Fault Filter Registers */
+ mcTIMER_FFILT_16B_tag FFILT; /* offset: 0x0108 size: 16 bit */
+ int8_t mcTIMER_reserved_010A[2];
+ /* Channel Enable Registers */
+ mcTIMER_ENBL_16B_tag ENBL; /* offset: 0x010C size: 16 bit */
+ int8_t mcTIMER_reserved_010E_C[2];
+ union {
+ mcTIMER_DREQ_16B_tag DREQ[4]; /* offset: 0x0110 (0x0002 x 4) */
+
+ struct {
+ /* DMA Request 0 Select Registers */
+ mcTIMER_DREQ0_16B_tag DREQ0; /* offset: 0x0110 size: 16 bit */
+ /* DMA Request 1 Select Registers */
+ mcTIMER_DREQ1_16B_tag DREQ1; /* offset: 0x0112 size: 16 bit */
+ /* DMA Request 2 Select Registers */
+ mcTIMER_DREQ2_16B_tag DREQ2; /* offset: 0x0114 size: 16 bit */
+ /* DMA Request 3 Select Registers */
+ mcTIMER_DREQ3_16B_tag DREQ3; /* offset: 0x0116 size: 16 bit */
+ };
+
+ };
+ } mcTIMER_tag;
+
+
+#define mcTIMER0 (*(volatile mcTIMER_tag *) 0xFFE18000UL)
+#define mcTIMER1 (*(volatile mcTIMER_tag *) 0xFFE1C000UL)
+#define mcTIMER2 (*(volatile mcTIMER_tag *) 0xFFE20000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: mcPWM */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers CNT... */
+
+ typedef union { /* Counter Register */
+ vuint16_t R;
+ } mcPWM_CNT_16B_tag;
+
+
+ /* Register layout for all registers INIT... */
+
+ typedef union { /* Initial Counter Register */
+ vuint16_t R;
+ } mcPWM_INIT_16B_tag;
+
+
+ /* Register layout for all registers CTRL2... */
+
+ typedef union { /* Control 2 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t DBGEN:1; /* Debug Enable */
+ vuint16_t WAITEN:1; /* Wait Enable */
+ vuint16_t INDEP:1; /* Independent or Complementary Pair Operation */
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t PWM23_INIT:1; /* PWM23 Initial Value */
+#else
+ vuint16_t PWMA_INIT:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t PWM45_INIT:1; /* PWM23 Initial Value */
+#else
+ vuint16_t PWMB_INIT:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t PWMX_INIT:1; /* PWMX Initial Value */
+ vuint16_t INIT_SEL:2; /* Initialization Control Select */
+ vuint16_t FRCEN:1; /* Force Initialization enable */
+ vuint16_t FORCE:1; /* Force Initialization */
+ vuint16_t FORCE_SEL:3; /* Force Source Select */
+ vuint16_t RELOAD_SEL:1; /* Reload Source Select */
+ vuint16_t CLK_SEL:2; /* Clock Source Select */
+ } B;
+ } mcPWM_CTRL2_16B_tag;
+
+
+ /* Register layout for all registers CTRL1... */
+
+ typedef union { /* Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t LDFQ:4; /* Load Frequency */
+ vuint16_t HALF:1; /* Half Cycle Reload */
+ vuint16_t FULL:1; /* Full Cycle Reload */
+ vuint16_t DT:2; /* Deadtime */
+ vuint16_t:1;
+ vuint16_t PRSC:3; /* Prescaler */
+ vuint16_t:1;
+ vuint16_t LDMOD:1; /* Load Mode Select */
+ vuint16_t:1;
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t DBL_EN:1; /* Double Switching Enable */
+#else
+ vuint16_t DBLEN:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcPWM_CTRL1_16B_tag;
+
+
+ /* Register layout for all registers VAL_0... */
+
+ typedef union { /* Value Register 0 */
+ vuint16_t R;
+ } mcPWM_VAL_0_16B_tag;
+
+
+ /* Register layout for all registers VAL_1... */
+
+ typedef union { /* Value Register 1 */
+ vuint16_t R;
+ } mcPWM_VAL_1_16B_tag;
+
+
+ /* Register layout for all registers VAL_2... */
+
+ typedef union { /* Value Register 2 */
+ vuint16_t R;
+ } mcPWM_VAL_2_16B_tag;
+
+
+ /* Register layout for all registers VAL_3... */
+
+ typedef union { /* Value Register 3 */
+ vuint16_t R;
+ } mcPWM_VAL_3_16B_tag;
+
+
+ /* Register layout for all registers VAL_4... */
+
+ typedef union { /* Value Register 4 */
+ vuint16_t R;
+ } mcPWM_VAL_4_16B_tag;
+
+
+ /* Register layout for all registers VAL_5... */
+
+ typedef union { /* Value Register 5 */
+ vuint16_t R;
+ } mcPWM_VAL_5_16B_tag;
+
+
+ /* Register layout for all registers FRACA... */
+
+ typedef union { /* Fractional Delay Register A */
+ vuint16_t R;
+ struct {
+ vuint16_t FRACA_EN:1; /* Fractional Delay Enable */
+ vuint16_t:10;
+ vuint16_t FRACA_DLY:5; /* Fractional Delay Value */
+ } B;
+ } mcPWM_FRACA_16B_tag;
+
+
+ /* Register layout for all registers FRACB... */
+
+ typedef union { /* Fractional Delay Register B */
+ vuint16_t R;
+ struct {
+ vuint16_t FRACA_EN:1; /* Fractional Delay Enable */
+ vuint16_t:10;
+ vuint16_t FRACA_DLY:5; /* Fractional Delay Value */
+ } B;
+ } mcPWM_FRACB_16B_tag;
+
+
+ /* Register layout for all registers OCTRL... */
+
+ typedef union { /* Output Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t PWMA_IN:1; /* PWMA Input */
+ vuint16_t PWMB_IN:1; /* PWMB Input */
+ vuint16_t PWMX_IN:1; /* PWMX Input */
+ vuint16_t:2;
+ vuint16_t POLA:1; /* PWMA Output Polarity */
+ vuint16_t POLB:1; /* PWMB Output Polarity */
+ vuint16_t POLX:1; /* PWMX Output Polarity */
+ vuint16_t:2;
+ vuint16_t PWMAFS:2; /* PWMA Fault State */
+ vuint16_t PWMBFS:2; /* PWMB Fault State */
+ vuint16_t PWMXFS:2; /* PWMX Fault State */
+ } B;
+ } mcPWM_OCTRL_16B_tag;
+
+
+ /* Register layout for all registers STS... */
+
+ typedef union { /* Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t RUF:1; /* Registers Updated Flag */
+ vuint16_t REF:1; /* Reload Error Flag */
+ vuint16_t RF:1; /* Reload Flag */
+ vuint16_t CFA1:1; /* Capture Flag A1 */
+ vuint16_t CFA0:1; /* Capture Flag A0 */
+ vuint16_t CFB1:1; /* Capture Flag B1 */
+ vuint16_t CFB0:1; /* Capture Flag B0 */
+ vuint16_t CFX1:1; /* Capture Flag X1 */
+ vuint16_t CFX0:1; /* Capture Flag X0 */
+ vuint16_t CMPF:6; /* Compare Flags */
+ } B;
+ } mcPWM_STS_16B_tag;
+
+
+ /* Register layout for all registers INTEN... */
+
+ typedef union { /* Interrupt Enable Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t REIE:1; /* Reload Error Interrupt Enable */
+ vuint16_t RIE:1; /* Reload Interrupt Enable */
+ vuint16_t CA1IE:1; /* Capture A1 Interrupt Enable */
+ vuint16_t CA0IE:1; /* Capture A0 Interrupt Enable */
+ vuint16_t CB1IE:1; /* Capture B1 Interrupt Enable */
+ vuint16_t CB0IE:1; /* Capture B0 Interrupt Enable */
+ vuint16_t CX1IE:1; /* Capture X1 Interrupt Enable */
+ vuint16_t CX0IE:1; /* Capture X0 Interrupt Enable */
+ vuint16_t CMPIE:6; /* Compare Interrupt Enables */
+ } B;
+ } mcPWM_INTEN_16B_tag;
+
+
+ /* Register layout for all registers DMAEN... */
+
+ typedef union { /* DMA Enable Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t VALDE:1; /* Value Register DMA Enable */
+ vuint16_t FAND:1; /* FIFO Watermark AND Control */
+ vuint16_t CAPTDE:2; /* Capture DMA Enable Source Select */
+ vuint16_t CA1DE:1; /* Capture A1 FIFO DMA Enable */
+ vuint16_t CA0DE:1; /* Capture A0 FIFO DMA Enable */
+ vuint16_t CB1DE:1; /* Capture B1 FIFO DMA Enable */
+ vuint16_t CB0DE:1; /* Capture B0 FIFO DMA Enable */
+ vuint16_t CX1DE:1; /* Capture X1 FIFO DMA Enable */
+ vuint16_t CX0DE:1; /* Capture X0 FIFO DMA Enable */
+ } B;
+ } mcPWM_DMAEN_16B_tag;
+
+
+ /* Register layout for all registers TCTRL... */
+
+ typedef union { /* Output Trigger Control Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:10;
+ vuint16_t OUT_TRIG_EN:6; /* Output Trigger Enables */
+ } B;
+ } mcPWM_TCTRL_16B_tag;
+
+
+ /* Register layout for all registers DISMAP... */
+
+ typedef union { /* Fault Disable Mapping Registers */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t DISX:4; /* PWMX Fault Disable Mask */
+ vuint16_t DISB:4; /* PWMB Fault Disable Mask */
+ vuint16_t DISA:4; /* PWMA Fault Disable Mask */
+ } B;
+ } mcPWM_DISMAP_16B_tag;
+
+
+ /* Register layout for all registers DTCNT0... */
+
+ typedef union { /* Deadtime Count Register 0 */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t DTCNT0:11; /* Deadtime Count Register 0 */
+ } B;
+ } mcPWM_DTCNT0_16B_tag;
+
+
+ /* Register layout for all registers DTCNT1... */
+
+ typedef union { /* Deadtime Count Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t DTCNT1:11; /* Deadtime Count Register 1 */
+ } B;
+ } mcPWM_DTCNT1_16B_tag;
+
+
+ /* Register layout for all registers CAPTCTRLA... */
+
+ typedef union { /* Capture Control A Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CA1CNT:3; /* Capture A1 FIFO Word Count */
+ vuint16_t CA0CNT:3; /* Capture A0 FIFO Word Count */
+ vuint16_t CFAWM:2; /* Capture A FIFOs Water Mark */
+ vuint16_t EDGCNTAEN:1; /* Edge Counter A Enable */
+ vuint16_t INPSELA:1; /* Input Select A */
+ vuint16_t EDGA1:2; /* Edge A 1 */
+ vuint16_t EDGA0:2; /* Edge A 0 */
+ vuint16_t ONESHOTA:1; /* One Shot Mode A */
+ vuint16_t ARMA:1; /* Arm A */
+ } B;
+ } mcPWM_CAPTCTRLA_16B_tag;
+
+
+ /* Register layout for all registers CAPTCMPA... */
+
+ typedef union { /* Capture Compare A Register */
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTA:8; /* Edge Counter A */
+ vuint16_t EDGCMPA:8; /* Edge Compare A */
+ } B;
+ } mcPWM_CAPTCMPA_16B_tag;
+
+
+ /* Register layout for all registers CAPTCTRLB... */
+
+ typedef union { /* Capture Control B Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CB1CNT:3; /* Capture B1 FIFO Word Count */
+ vuint16_t CB0CNT:3; /* Capture B0 FIFO Word Count */
+ vuint16_t CFBWM:2; /* Capture B FIFOs Water Mark */
+ vuint16_t EDGCNTBEN:1; /* Edge Counter B Enable */
+ vuint16_t INPSELB:1; /* Input Select B */
+ vuint16_t EDGB1:2; /* Edge B 1 */
+ vuint16_t EDGB0:2; /* Edge B 0 */
+ vuint16_t ONESHOTB:1; /* One Shot Mode B */
+ vuint16_t ARMB:1; /* Arm B */
+ } B;
+ } mcPWM_CAPTCTRLB_16B_tag;
+
+
+ /* Register layout for all registers CAPTCMPB... */
+
+ typedef union { /* Capture Compare B Register */
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTB:8; /* Edge Counter B */
+ vuint16_t EDGCMPB:8; /* Edge Compare B */
+ } B;
+ } mcPWM_CAPTCMPB_16B_tag;
+
+
+ /* Register layout for all registers CAPTCTRLX... */
+
+ typedef union { /* Capture Control X Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CX1CNT:3; /* Capture X1 FIFO Word Count */
+ vuint16_t CX0CNT:3; /* Capture X0 FIFO Word Count */
+ vuint16_t CFXWM:2; /* Capture X FIFOs Water Mark */
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t EDGCNTXEN:1; /* Edge Counter X Enable */
+#else
+ vuint16_t EDGCNTX_EN:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t INPSELX:1; /* Input Select X */
+#else
+ vuint16_t INP_SELX:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t EDGX1:2; /* Edge X 1 */
+ vuint16_t EDGX0:2; /* Edge X 0 */
+ vuint16_t ONESHOTX:1; /* One Shot Mode X */
+ vuint16_t ARMX:1; /* Arm X */
+ } B;
+ } mcPWM_CAPTCTRLX_16B_tag;
+
+
+ /* Register layout for all registers CAPTCMPX... */
+
+ typedef union { /* Capture Compare X Register */
+ vuint16_t R;
+ struct {
+ vuint16_t EDGCNTX:8; /* Edge Counter X */
+ vuint16_t EDGCMPX:8; /* Edge Compare X */
+ } B;
+ } mcPWM_CAPTCMPX_16B_tag;
+
+
+ /* Register layout for all registers CVAL0... */
+
+ typedef union { /* Capture Value 0 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL0:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL0_16B_tag;
+
+
+ /* Register layout for all registers CVAL0CYC... */
+
+ typedef union { /* Capture Value 0 Cycle Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL0CYC:4; /* Capture Value 0 Cycle */
+ } B;
+ } mcPWM_CVAL0CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL1... */
+
+ typedef union { /* Capture Value 1 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL1:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL1_16B_tag;
+
+
+ /* Register layout for all registers CVAL1CYC... */
+
+ typedef union { /* Capture Value 1 Cycle Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL1CYC:4; /* Capture Value 1 Cycle */
+ } B;
+ } mcPWM_CVAL1CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL2... */
+
+ typedef union { /* Capture Value 2 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL2:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL2_16B_tag;
+
+
+ /* Register layout for all registers CVAL2CYC... */
+
+ typedef union { /* Capture Value 2 Cycle Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL2CYC:4; /* Capture Value 2 Cycle */
+ } B;
+ } mcPWM_CVAL2CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL3... */
+
+ typedef union { /* Capture Value 3 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL3:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL3_16B_tag;
+
+
+ /* Register layout for all registers CVAL3CYC... */
+
+ typedef union { /* Capture Value 3 Cycle Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL3CYC:4; /* Capture Value 3 Cycle */
+ } B;
+ } mcPWM_CVAL3CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL4... */
+
+ typedef union { /* Capture Value 4 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL4:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL4_16B_tag;
+
+
+ /* Register layout for all registers CVAL4CYC... */
+
+ typedef union { /* Capture Value 4 Cycle Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL4CYC:4; /* Capture Value 4 Cycle */
+ } B;
+ } mcPWM_CVAL4CYC_16B_tag;
+
+
+ /* Register layout for all registers CVAL5... */
+
+ typedef union { /* Capture Value 5 Register */
+ vuint16_t R;
+ struct {
+ vuint16_t CAPTVAL5:16; /* Captured value from submodule counter */
+ } B;
+ } mcPWM_CVAL5_16B_tag;
+
+
+ /* Register layout for all registers CVAL5CYC... */
+
+ typedef union { /* Capture Value 5 Cycle Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t CVAL5CYC:4; /* Capture Value 5 Cycle */
+ } B;
+ } mcPWM_CVAL5CYC_16B_tag;
+
+ typedef union { /* Output Enable Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t PWMA_EN:4; /* PWMA Output Enables */
+ vuint16_t PWMB_EN:4; /* PWMB Output Enables */
+ vuint16_t PWMX_EN:4; /* PWMX Output Enables */
+ } B;
+ } mcPWM_OUTEN_16B_tag;
+
+ typedef union { /* Mask Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t MASKA:4; /* PWMA Masks */
+ vuint16_t MASKB:4; /* PWMB Masks */
+ vuint16_t MASKX:4; /* PWMX Masks */
+ } B;
+ } mcPWM_MASK_16B_tag;
+
+ typedef union { /* Software Controlled Output Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT23_3:1; /* Software Controlled Output 23_3 */
+#else
+ vuint16_t OUTA_3:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT45_3:1; /* Software Controlled Output 45_3 */
+#else
+ vuint16_t OUTB_3:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT23_2:1; /* Software Controlled Output 23_2 */
+#else
+ vuint16_t OUTA_2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT45_2:1; /* Software Controlled Output 45_2 */
+#else
+ vuint16_t OUTB_2:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT23_1:1; /* Software Controlled Output 23_1 */
+#else
+ vuint16_t OUTA_1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT45_1:1; /* Software Controlled Output 45_1 */
+#else
+ vuint16_t OUTB_1:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT23_0:1; /* Software Controlled Output 23_0 */
+#else
+ vuint16_t OUTA_0:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t OUT45_0:1; /* Software Controlled Output 45_0 */
+#else
+ vuint16_t OUTB_0:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcPWM_SWCOUT_16B_tag;
+
+ typedef union { /* Deadtime Source Select Register */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL23_3:2; /* PWM23_3 Control Select */
+#else
+ vuint16_t SELA_3:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL45_3:2; /* PWM45_3 Control Select */
+#else
+ vuint16_t SELB_3:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL23_2:2; /* PWM23_2 Control Select */
+#else
+ vuint16_t SELA_2:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL45_2:2; /* PWM45_2 Control Select */
+#else
+ vuint16_t SELB_2:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL23_1:2; /* PWM23_1 Control Select */
+#else
+ vuint16_t SELA_1:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL45_1:2; /* PWM45_1 Control Select */
+#else
+ vuint16_t SELB_1:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL23_0:2; /* PWM23_0 Control Select */
+#else
+ vuint16_t SELA_0:2; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t SEL45_0:2; /* PWM45_0 Control Select */
+#else
+ vuint16_t SELB_0:2; /* deprecated name - please avoid */
+#endif
+ } B;
+ } mcPWM_DTSRCSEL_16B_tag;
+
+ typedef union { /* Master Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t IPOL:4; /* Current Polarity */
+ vuint16_t RUN:4; /* Run */
+#ifndef USE_FIELD_ALIASES_mcPWM
+ vuint16_t CLOK:4; /* Clear Load Okay */
+#else
+ vuint16_t CLDOK:4; /* deprecated name - please avoid */
+#endif
+ vuint16_t LDOK:4; /* Load Okay */
+ } B;
+ } mcPWM_MCTRL_16B_tag;
+
+ typedef union { /* Fault Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t FLVL:4; /* Fault Level */
+ vuint16_t FAUTO:4; /* Automatic Fault Clearing */
+ vuint16_t FSAFE:4; /* Fault Safety Mode */
+ vuint16_t FIE:4; /* Fault Interrupt Enables */
+ } B;
+ } mcPWM_FCTRL_16B_tag;
+
+ typedef union { /* Fault Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:3;
+ vuint16_t FTEST:1; /* Fault Test */
+ vuint16_t FFPIN:4; /* Filtered Fault Pins */
+ vuint16_t:4;
+ vuint16_t FFLAG:4; /* Fault Flags */
+ } B;
+ } mcPWM_FSTS_16B_tag;
+
+ typedef union { /* Fault Filter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FILT_CNT:3; /* Fault Filter Count */
+ vuint16_t FILT_PER:8; /* Fault Filter Period */
+ } B;
+ } mcPWM_FFILT_16B_tag;
+
+
+ /* Register layout for generated register(s) VAL... */
+
+ typedef union { /* */
+ vuint16_t R;
+ } mcPWM_VAL_16B_tag;
+
+
+ typedef struct mcPWM_SUBMOD_struct_tag {
+
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT; /* relative offset: 0x0000 */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT; /* relative offset: 0x0002 */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL2; /* relative offset: 0x0004 */
+ union {
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL1; /* relative offset: 0x0006 */
+ mcPWM_CTRL1_16B_tag CTRL; /* deprecated - please avoid */
+ };
+ /* Value Register 0 */
+
+ union {
+
+ struct {
+
+ mcPWM_VAL_0_16B_tag VAL_0; /* relative offset: 0x0008 */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_1; /* relative offset: 0x000A */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_2; /* relative offset: 0x000C */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_3; /* relative offset: 0x000E */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_4; /* relative offset: 0x0010 */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_5; /* relative offset: 0x0012 */
+
+ };
+
+ mcPWM_VAL_0_16B_tag VAL[6]; /* offset: 0x0008 size: 16 bit */
+
+ };
+ /* Fractional Delay Register A */
+ mcPWM_FRACA_16B_tag FRACA; /* relative offset: 0x0014 */
+ /* Fractional Delay Register B */
+ mcPWM_FRACB_16B_tag FRACB; /* relative offset: 0x0016 */
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL; /* relative offset: 0x0018 */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS; /* relative offset: 0x001A */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN; /* relative offset: 0x001C */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN; /* relative offset: 0x001E */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL; /* relative offset: 0x0020 */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP; /* relative offset: 0x0022 */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT0; /* relative offset: 0x0024 */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT1; /* relative offset: 0x0026 */
+ /* Capture Control A Register */
+ mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA; /* relative offset: 0x0028 */
+ union {
+ /* Capture Compare A Register */
+ mcPWM_CAPTCMPA_16B_tag CAPTCMPA; /* relative offset: 0x002A */
+ mcPWM_CAPTCMPA_16B_tag CAPTCOMPA; /* deprecated - please avoid */
+ };
+ /* Capture Control B Register */
+ mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB; /* relative offset: 0x002C */
+ union {
+ /* Capture Compare B Register */
+ mcPWM_CAPTCMPB_16B_tag CAPTCMPB; /* relative offset: 0x002E */
+ mcPWM_CAPTCMPB_16B_tag CAPTCOMPB; /* deprecated - please avoid */
+ };
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */
+ union {
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */
+ mcPWM_CAPTCMPX_16B_tag CAPTCOMPX; /* deprecated - please avoid */
+ };
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL0; /* relative offset: 0x0034 */
+ union {
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */
+ mcPWM_CVAL0CYC_16B_tag CVAL0C; /* deprecated - please avoid */
+ };
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL1; /* relative offset: 0x0038 */
+ union {
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */
+ mcPWM_CVAL1CYC_16B_tag CVAL1C; /* deprecated - please avoid */
+ };
+ /* Capture Value 2 Register */
+ mcPWM_CVAL2_16B_tag CVAL2; /* relative offset: 0x003C */
+ union {
+ /* Capture Value 2 Cycle Register */
+ mcPWM_CVAL2CYC_16B_tag CVAL2CYC; /* relative offset: 0x003E */
+ mcPWM_CVAL2CYC_16B_tag CVAL2C; /* deprecated - please avoid */
+ };
+ /* Capture Value 3 Register */
+ mcPWM_CVAL3_16B_tag CVAL3; /* relative offset: 0x0040 */
+ union {
+ /* Capture Value 3 Cycle Register */
+ mcPWM_CVAL3CYC_16B_tag CVAL3CYC; /* relative offset: 0x0042 */
+ mcPWM_CVAL3CYC_16B_tag CVAL3C; /* deprecated - please avoid */
+ };
+ /* Capture Value 4 Register */
+ mcPWM_CVAL4_16B_tag CVAL4; /* relative offset: 0x0044 */
+ union {
+ /* Capture Value 4 Cycle Register */
+ mcPWM_CVAL4CYC_16B_tag CVAL4CYC; /* relative offset: 0x0046 */
+ mcPWM_CVAL4CYC_16B_tag CVAL4C; /* deprecated - please avoid */
+ };
+ /* Capture Value 5 Register */
+ mcPWM_CVAL5_16B_tag CVAL5; /* relative offset: 0x0048 */
+ union {
+ /* Capture Value 5 Cycle Register */
+ mcPWM_CVAL5CYC_16B_tag CVAL5CYC; /* relative offset: 0x004A */
+ mcPWM_CVAL5CYC_16B_tag CVAL5C; /* deprecated - please avoid */
+ };
+ int8_t mcPWM_SUBMOD_reserved_004C[4];
+
+ } mcPWM_SUBMOD_tag;
+
+
+ typedef struct mcPWM_struct_tag { /* start of mcPWM_tag */
+ union {
+ /* Register set SUBMOD */
+ mcPWM_SUBMOD_tag SUBMOD[4]; /* offset: 0x0000 (0x0050 x 4) */
+
+ struct {
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT0; /* offset: 0x0000 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT0; /* offset: 0x0002 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL20; /* offset: 0x0004 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL10; /* offset: 0x0006 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_00; /* offset: 0x0008 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_10; /* offset: 0x000A size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_20; /* offset: 0x000C size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_30; /* offset: 0x000E size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_40; /* offset: 0x0010 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_50; /* offset: 0x0012 size: 16 bit */
+ /* Fractional Delay Register A */
+ mcPWM_FRACA_16B_tag FRACA0; /* offset: 0x0014 size: 16 bit */
+ /* Fractional Delay Register B */
+ mcPWM_FRACB_16B_tag FRACB0; /* offset: 0x0016 size: 16 bit */
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL0; /* offset: 0x0018 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS0; /* offset: 0x001A size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN0; /* offset: 0x001C size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN0; /* offset: 0x001E size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL0; /* offset: 0x0020 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP0; /* offset: 0x0022 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT00; /* offset: 0x0024 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT10; /* offset: 0x0026 size: 16 bit */
+ /* Capture Control A Register */
+ mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA0; /* offset: 0x0028 size: 16 bit */
+ /* Capture Compare A Register */
+ mcPWM_CAPTCMPA_16B_tag CAPTCMPA0; /* offset: 0x002A size: 16 bit */
+ /* Capture Control B Register */
+ mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB0; /* offset: 0x002C size: 16 bit */
+ /* Capture Compare B Register */
+ mcPWM_CAPTCMPB_16B_tag CAPTCMPB0; /* offset: 0x002E size: 16 bit */
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0; /* offset: 0x0030 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX0; /* offset: 0x0032 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL00; /* offset: 0x0034 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC0; /* offset: 0x0036 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL10; /* offset: 0x0038 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC0; /* offset: 0x003A size: 16 bit */
+ /* Capture Value 2 Register */
+ mcPWM_CVAL2_16B_tag CVAL20; /* offset: 0x003C size: 16 bit */
+ /* Capture Value 2 Cycle Register */
+ mcPWM_CVAL2CYC_16B_tag CVAL2CYC0; /* offset: 0x003E size: 16 bit */
+ /* Capture Value 3 Register */
+ mcPWM_CVAL3_16B_tag CVAL30; /* offset: 0x0040 size: 16 bit */
+ /* Capture Value 3 Cycle Register */
+ mcPWM_CVAL3CYC_16B_tag CVAL3CYC0; /* offset: 0x0042 size: 16 bit */
+ /* Capture Value 4 Register */
+ mcPWM_CVAL4_16B_tag CVAL40; /* offset: 0x0044 size: 16 bit */
+ /* Capture Value 4 Cycle Register */
+ mcPWM_CVAL4CYC_16B_tag CVAL4CYC0; /* offset: 0x0046 size: 16 bit */
+ /* Capture Value 5 Register */
+ mcPWM_CVAL5_16B_tag CVAL50; /* offset: 0x0048 size: 16 bit */
+ /* Capture Value 5 Cycle Register */
+ mcPWM_CVAL5CYC_16B_tag CVAL5CYC0; /* offset: 0x004A size: 16 bit */
+ int8_t mcPWM_reserved_004C_I2[4];
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT1; /* offset: 0x0050 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT1; /* offset: 0x0052 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL21; /* offset: 0x0054 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL11; /* offset: 0x0056 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_01; /* offset: 0x0058 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_11; /* offset: 0x005A size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_21; /* offset: 0x005C size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_31; /* offset: 0x005E size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_41; /* offset: 0x0060 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_51; /* offset: 0x0062 size: 16 bit */
+ /* Fractional Delay Register A */
+ mcPWM_FRACA_16B_tag FRACA1; /* offset: 0x0064 size: 16 bit */
+ /* Fractional Delay Register B */
+ mcPWM_FRACB_16B_tag FRACB1; /* offset: 0x0066 size: 16 bit */
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL1; /* offset: 0x0068 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS1; /* offset: 0x006A size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN1; /* offset: 0x006C size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN1; /* offset: 0x006E size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL1; /* offset: 0x0070 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP1; /* offset: 0x0072 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT01; /* offset: 0x0074 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT11; /* offset: 0x0076 size: 16 bit */
+ /* Capture Control A Register */
+ mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA1; /* offset: 0x0078 size: 16 bit */
+ /* Capture Compare A Register */
+ mcPWM_CAPTCMPA_16B_tag CAPTCMPA1; /* offset: 0x007A size: 16 bit */
+ /* Capture Control B Register */
+ mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB1; /* offset: 0x007C size: 16 bit */
+ /* Capture Compare B Register */
+ mcPWM_CAPTCMPB_16B_tag CAPTCMPB1; /* offset: 0x007E size: 16 bit */
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1; /* offset: 0x0080 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX1; /* offset: 0x0082 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL01; /* offset: 0x0084 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC1; /* offset: 0x0086 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL11; /* offset: 0x0088 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC1; /* offset: 0x008A size: 16 bit */
+ /* Capture Value 2 Register */
+ mcPWM_CVAL2_16B_tag CVAL21; /* offset: 0x008C size: 16 bit */
+ /* Capture Value 2 Cycle Register */
+ mcPWM_CVAL2CYC_16B_tag CVAL2CYC1; /* offset: 0x008E size: 16 bit */
+ /* Capture Value 3 Register */
+ mcPWM_CVAL3_16B_tag CVAL31; /* offset: 0x0090 size: 16 bit */
+ /* Capture Value 3 Cycle Register */
+ mcPWM_CVAL3CYC_16B_tag CVAL3CYC1; /* offset: 0x0092 size: 16 bit */
+ /* Capture Value 4 Register */
+ mcPWM_CVAL4_16B_tag CVAL41; /* offset: 0x0094 size: 16 bit */
+ /* Capture Value 4 Cycle Register */
+ mcPWM_CVAL4CYC_16B_tag CVAL4CYC1; /* offset: 0x0096 size: 16 bit */
+ /* Capture Value 5 Register */
+ mcPWM_CVAL5_16B_tag CVAL51; /* offset: 0x0098 size: 16 bit */
+ /* Capture Value 5 Cycle Register */
+ mcPWM_CVAL5CYC_16B_tag CVAL5CYC1; /* offset: 0x009A size: 16 bit */
+ int8_t mcPWM_reserved_009C_I2[4];
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT2; /* offset: 0x00A0 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT2; /* offset: 0x00A2 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL22; /* offset: 0x00A4 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL12; /* offset: 0x00A6 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_02; /* offset: 0x00A8 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_12; /* offset: 0x00AA size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_22; /* offset: 0x00AC size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_32; /* offset: 0x00AE size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_42; /* offset: 0x00B0 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_52; /* offset: 0x00B2 size: 16 bit */
+ /* Fractional Delay Register A */
+ mcPWM_FRACA_16B_tag FRACA2; /* offset: 0x00B4 size: 16 bit */
+ /* Fractional Delay Register B */
+ mcPWM_FRACB_16B_tag FRACB2; /* offset: 0x00B6 size: 16 bit */
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL2; /* offset: 0x00B8 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS2; /* offset: 0x00BA size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN2; /* offset: 0x00BC size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN2; /* offset: 0x00BE size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL2; /* offset: 0x00C0 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP2; /* offset: 0x00C2 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT02; /* offset: 0x00C4 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT12; /* offset: 0x00C6 size: 16 bit */
+ /* Capture Control A Register */
+ mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA2; /* offset: 0x00C8 size: 16 bit */
+ /* Capture Compare A Register */
+ mcPWM_CAPTCMPA_16B_tag CAPTCMPA2; /* offset: 0x00CA size: 16 bit */
+ /* Capture Control B Register */
+ mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB2; /* offset: 0x00CC size: 16 bit */
+ /* Capture Compare B Register */
+ mcPWM_CAPTCMPB_16B_tag CAPTCMPB2; /* offset: 0x00CE size: 16 bit */
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2; /* offset: 0x00D0 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX2; /* offset: 0x00D2 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL02; /* offset: 0x00D4 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC2; /* offset: 0x00D6 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL12; /* offset: 0x00D8 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC2; /* offset: 0x00DA size: 16 bit */
+ /* Capture Value 2 Register */
+ mcPWM_CVAL2_16B_tag CVAL22; /* offset: 0x00DC size: 16 bit */
+ /* Capture Value 2 Cycle Register */
+ mcPWM_CVAL2CYC_16B_tag CVAL2CYC2; /* offset: 0x00DE size: 16 bit */
+ /* Capture Value 3 Register */
+ mcPWM_CVAL3_16B_tag CVAL32; /* offset: 0x00E0 size: 16 bit */
+ /* Capture Value 3 Cycle Register */
+ mcPWM_CVAL3CYC_16B_tag CVAL3CYC2; /* offset: 0x00E2 size: 16 bit */
+ /* Capture Value 4 Register */
+ mcPWM_CVAL4_16B_tag CVAL42; /* offset: 0x00E4 size: 16 bit */
+ /* Capture Value 4 Cycle Register */
+ mcPWM_CVAL4CYC_16B_tag CVAL4CYC2; /* offset: 0x00E6 size: 16 bit */
+ /* Capture Value 5 Register */
+ mcPWM_CVAL5_16B_tag CVAL52; /* offset: 0x00E8 size: 16 bit */
+ /* Capture Value 5 Cycle Register */
+ mcPWM_CVAL5CYC_16B_tag CVAL5CYC2; /* offset: 0x00EA size: 16 bit */
+ int8_t mcPWM_reserved_00EC_I2[4];
+ /* Counter Register */
+ mcPWM_CNT_16B_tag CNT3; /* offset: 0x00F0 size: 16 bit */
+ /* Initial Counter Register */
+ mcPWM_INIT_16B_tag INIT3; /* offset: 0x00F2 size: 16 bit */
+ /* Control 2 Register */
+ mcPWM_CTRL2_16B_tag CTRL23; /* offset: 0x00F4 size: 16 bit */
+ /* Control Register */
+ mcPWM_CTRL1_16B_tag CTRL13; /* offset: 0x00F6 size: 16 bit */
+ /* Value Register 0 */
+ mcPWM_VAL_0_16B_tag VAL_03; /* offset: 0x00F8 size: 16 bit */
+ /* Value Register 1 */
+ mcPWM_VAL_1_16B_tag VAL_13; /* offset: 0x00FA size: 16 bit */
+ /* Value Register 2 */
+ mcPWM_VAL_2_16B_tag VAL_23; /* offset: 0x00FC size: 16 bit */
+ /* Value Register 3 */
+ mcPWM_VAL_3_16B_tag VAL_33; /* offset: 0x00FE size: 16 bit */
+ /* Value Register 4 */
+ mcPWM_VAL_4_16B_tag VAL_43; /* offset: 0x0100 size: 16 bit */
+ /* Value Register 5 */
+ mcPWM_VAL_5_16B_tag VAL_53; /* offset: 0x0102 size: 16 bit */
+ /* Fractional Delay Register A */
+ mcPWM_FRACA_16B_tag FRACA3; /* offset: 0x0104 size: 16 bit */
+ /* Fractional Delay Register B */
+ mcPWM_FRACB_16B_tag FRACB3; /* offset: 0x0106 size: 16 bit */
+ /* Output Control Register */
+ mcPWM_OCTRL_16B_tag OCTRL3; /* offset: 0x0108 size: 16 bit */
+ /* Status Register */
+ mcPWM_STS_16B_tag STS3; /* offset: 0x010A size: 16 bit */
+ /* Interrupt Enable Registers */
+ mcPWM_INTEN_16B_tag INTEN3; /* offset: 0x010C size: 16 bit */
+ /* DMA Enable Registers */
+ mcPWM_DMAEN_16B_tag DMAEN3; /* offset: 0x010E size: 16 bit */
+ /* Output Trigger Control Registers */
+ mcPWM_TCTRL_16B_tag TCTRL3; /* offset: 0x0110 size: 16 bit */
+ /* Fault Disable Mapping Registers */
+ mcPWM_DISMAP_16B_tag DISMAP3; /* offset: 0x0112 size: 16 bit */
+ /* Deadtime Count Register 0 */
+ mcPWM_DTCNT0_16B_tag DTCNT03; /* offset: 0x0114 size: 16 bit */
+ /* Deadtime Count Register 1 */
+ mcPWM_DTCNT1_16B_tag DTCNT13; /* offset: 0x0116 size: 16 bit */
+ /* Capture Control A Register */
+ mcPWM_CAPTCTRLA_16B_tag CAPTCTRLA3; /* offset: 0x0118 size: 16 bit */
+ /* Capture Compare A Register */
+ mcPWM_CAPTCMPA_16B_tag CAPTCMPA3; /* offset: 0x011A size: 16 bit */
+ /* Capture Control B Register */
+ mcPWM_CAPTCTRLB_16B_tag CAPTCTRLB3; /* offset: 0x011C size: 16 bit */
+ /* Capture Compare B Register */
+ mcPWM_CAPTCMPB_16B_tag CAPTCMPB3; /* offset: 0x011E size: 16 bit */
+ /* Capture Control X Register */
+ mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3; /* offset: 0x0120 size: 16 bit */
+ /* Capture Compare X Register */
+ mcPWM_CAPTCMPX_16B_tag CAPTCMPX3; /* offset: 0x0122 size: 16 bit */
+ /* Capture Value 0 Register */
+ mcPWM_CVAL0_16B_tag CVAL03; /* offset: 0x0124 size: 16 bit */
+ /* Capture Value 0 Cycle Register */
+ mcPWM_CVAL0CYC_16B_tag CVAL0CYC3; /* offset: 0x0126 size: 16 bit */
+ /* Capture Value 1 Register */
+ mcPWM_CVAL1_16B_tag CVAL13; /* offset: 0x0128 size: 16 bit */
+ /* Capture Value 1 Cycle Register */
+ mcPWM_CVAL1CYC_16B_tag CVAL1CYC3; /* offset: 0x012A size: 16 bit */
+ /* Capture Value 2 Register */
+ mcPWM_CVAL2_16B_tag CVAL23; /* offset: 0x012C size: 16 bit */
+ /* Capture Value 2 Cycle Register */
+ mcPWM_CVAL2CYC_16B_tag CVAL2CYC3; /* offset: 0x012E size: 16 bit */
+ /* Capture Value 3 Register */
+ mcPWM_CVAL3_16B_tag CVAL33; /* offset: 0x0130 size: 16 bit */
+ /* Capture Value 3 Cycle Register */
+ mcPWM_CVAL3CYC_16B_tag CVAL3CYC3; /* offset: 0x0132 size: 16 bit */
+ /* Capture Value 4 Register */
+ mcPWM_CVAL4_16B_tag CVAL43; /* offset: 0x0134 size: 16 bit */
+ /* Capture Value 4 Cycle Register */
+ mcPWM_CVAL4CYC_16B_tag CVAL4CYC3; /* offset: 0x0136 size: 16 bit */
+ /* Capture Value 5 Register */
+ mcPWM_CVAL5_16B_tag CVAL53; /* offset: 0x0138 size: 16 bit */
+ /* Capture Value 5 Cycle Register */
+ mcPWM_CVAL5CYC_16B_tag CVAL5CYC3; /* offset: 0x013A size: 16 bit */
+ int8_t mcPWM_reserved_013C_E2[4];
+ };
+
+ };
+ /* Output Enable Register */
+ mcPWM_OUTEN_16B_tag OUTEN; /* offset: 0x0140 size: 16 bit */
+ /* Mask Register */
+ mcPWM_MASK_16B_tag MASK; /* offset: 0x0142 size: 16 bit */
+ /* Software Controlled Output Register */
+ mcPWM_SWCOUT_16B_tag SWCOUT; /* offset: 0x0144 size: 16 bit */
+ /* Deadtime Source Select Register */
+ mcPWM_DTSRCSEL_16B_tag DTSRCSEL; /* offset: 0x0146 size: 16 bit */
+ /* Master Control Register */
+ mcPWM_MCTRL_16B_tag MCTRL; /* offset: 0x0148 size: 16 bit */
+ int8_t mcPWM_reserved_014A[2];
+ /* Fault Control Register */
+ mcPWM_FCTRL_16B_tag FCTRL; /* offset: 0x014C size: 16 bit */
+ /* Fault Status Register */
+ mcPWM_FSTS_16B_tag FSTS; /* offset: 0x014E size: 16 bit */
+ /* Fault Filter Register */
+ mcPWM_FFILT_16B_tag FFILT; /* offset: 0x0150 size: 16 bit */
+ } mcPWM_tag;
+
+
+#define mcPWM_A (*(volatile mcPWM_tag *) 0xFFE24000UL)
+#define mcPWM_B (*(volatile mcPWM_tag *) 0xFFE28000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: LINFLEX */
+/* */
+/****************************************************************/
+
+ typedef union { /* LIN Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CCD:1; /* Checksum Calculation Disable */
+ vuint32_t CFD:1; /* Checksum Field Disable */
+ vuint32_t LASE:1; /* LIN Auto Synchronization Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t AUTOWU:1; /* Auto Wake Up */
+#else
+ vuint32_t AWUM:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t MBL:4; /* Master Break Length */
+ vuint32_t BF:1; /* By-Pass Filter */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t SLFM:1; /* Selftest Mode */
+#else
+ vuint32_t SFTM:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t LBKM:1; /* Loopback Mode */
+ vuint32_t MME:1; /* Master Mode Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t SSBL:1; /* Slave Mode Synch Break Length */
+#else
+ vuint32_t SSDT:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t RBLM:1; /* Receiver Buffer Locked Mode */
+ vuint32_t SLEEP:1; /* Sleep Mode Request */
+ vuint32_t INIT:1; /* Initialization Mode Request */
+ } B;
+ } LINFLEX_LINCR1_32B_tag;
+
+ typedef union { /* LIN Interrupt Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SZIE:1; /* Stuck at Zero Interrupt Enable */
+ vuint32_t OCIE:1; /* Output Compare Interrupt Enable */
+ vuint32_t BEIE:1; /* Bit Error Interrupt Enable */
+ vuint32_t CEIE:1; /* Checksum Error Interrupt Enable */
+ vuint32_t HEIE:1; /* Header Error Interrupt Enable */
+ vuint32_t:2;
+ vuint32_t FEIE:1; /* Frame Error Interrupt Enable */
+ vuint32_t BOIE:1; /* Buffer Overrun Error Interrupt Enable */
+ vuint32_t LSIE:1; /* LIN State Interrupt Enable */
+ vuint32_t WUIE:1; /* Wakeup Interrupt Enable */
+ vuint32_t DBFIE:1; /* Data Buffer Full Interrupt Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t DBEIE_TOIE:1; /* Data Buffer Empty Interrupt Enable */
+#else
+ vuint32_t DBEIE:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t DRIE:1; /* Data Reception complete Interrupt Enable */
+ vuint32_t DTIE:1; /* Data Transmitted Interrupt Enable */
+ vuint32_t HRIE:1; /* Header Received Interrupt Enable */
+ } B;
+ } LINFLEX_LINIER_32B_tag;
+
+ typedef union { /* LIN Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t LINS:4; /* LIN State */
+ vuint32_t:2;
+ vuint32_t RMB:1; /* Release Message Buffer */
+ vuint32_t:1;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t RXBUSY:1; /* Receiver Busy Flag */
+#else
+ vuint32_t RBSY:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t RDI:1; /* LIN Receive Signal */
+#else
+ vuint32_t RPS:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t WUF:1; /* Wake Up Flag */
+ vuint32_t DBFF:1; /* Data Buffer Full Flag */
+ vuint32_t DBEF:1; /* Data Buffer Empty Flag */
+ vuint32_t DRF:1; /* Data Reception Completed Flag */
+ vuint32_t DTF:1; /* Data Transmission Completed Flag */
+ vuint32_t HRF:1; /* Header Received Flag */
+ } B;
+ } LINFLEX_LINSR_32B_tag;
+
+ typedef union { /* LIN Error Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SZF:1; /* Stuck at Zero Flag */
+ vuint32_t OCF:1; /* Output Compare Flag */
+ vuint32_t BEF:1; /* Bit Error Flag */
+ vuint32_t CEF:1; /* Checksum Error Flag */
+ vuint32_t SFEF:1; /* Sync Field Error Flag */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t SDEF:1; /* Sync Delimiter Error Flag */
+#else
+ vuint32_t BDEF:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t IDPEF:1; /* ID Parity Error Flag */
+ vuint32_t FEF:1; /* Framing Error Flag */
+ vuint32_t BOF:1; /* Buffer Overrun Flag */
+ vuint32_t:6;
+ vuint32_t NF:1; /* Noise Flag */
+ } B;
+ } LINFLEX_LINESR_32B_tag;
+
+ typedef union { /* UART Mode Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t TDFL_TFC:3; /* Transmitter Data Field Length/TX FIFO Counter */
+ vuint32_t RDFL_RFC0:3; /* Reception Data Field Length/RX FIFO Counter */
+ vuint32_t RFBM:1; /* RX FIFO/ Buffer Mode */
+ vuint32_t TFBM:1; /* TX FIFO/ Buffer Mode */
+ vuint32_t WL1:1; /* Word Length in UART mode - bit 1 */
+ vuint32_t PC1:1; /* Parity Check - bit 1 */
+ vuint32_t RXEN:1; /* Receiver Enable */
+ vuint32_t TXEN:1; /* Transmitter Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t PC0:1; /* Parity Check - bit 0 */
+#else
+ vuint32_t OP:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t PCE:1; /* Parity Control Enable */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t WL0:1; /* Word Length in UART Mode - bit 0 */
+#else
+ vuint32_t WL:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t UART:1; /* UART Mode */
+ } B;
+ } LINFLEX_UARTCR_32B_tag;
+
+ typedef union { /* UART Mode Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SZF:1; /* Stuck at Zero Flag */
+ vuint32_t OCF:1; /* Output Compare Flag */
+ vuint32_t PE:4; /* Parity Error Flag */
+ vuint32_t RMB:1; /* Release Message Buffer */
+ vuint32_t FEF:1; /* Framing Error Flag */
+ vuint32_t BOF:1; /* Buffer Overrun Flag */
+ vuint32_t RDI:1; /* Receiver Data Input Signal */
+ vuint32_t WUF:1; /* Wakeup Flag */
+ vuint32_t:1;
+ vuint32_t TO:1; /* Time Out */
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t DRF_RFE:1; /* Data Reception Completed Flag/RX FIFO Empty Flag */
+#else
+ vuint32_t DRF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t DTF_TFF:1; /* Data Transmission Completed Flag/TX FIFO Full Flag */
+#else
+ vuint32_t DTF:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t NF:1; /* Noise Flag */
+ } B;
+ } LINFLEX_UARTSR_32B_tag;
+
+ typedef union { /* LIN Time-Out Control Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:21;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t MODE:1; /* Time-out Counter Mode */
+#else
+ vuint32_t LTOM:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t IOT:1; /* Idle on Timeout */
+ vuint32_t TOCE:1; /* Time-Out Counter Enable */
+ vuint32_t CNT:8; /* Counter Value */
+ } B;
+ } LINFLEX_LINTCSR_32B_tag;
+
+ typedef union { /* LIN Output Compare Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t OC2:8; /* Output Compare Value 2 */
+ vuint32_t OC1:8; /* Output Compare Value 1 */
+ } B;
+ } LINFLEX_LINOCR_32B_tag;
+
+ typedef union { /* LIN Time-Out Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t RTO:4; /* Response Time-Out Value */
+ vuint32_t:1;
+ vuint32_t HTO:7; /* Header Time-Out Value */
+ } B;
+ } LINFLEX_LINTOCR_32B_tag;
+
+ typedef union { /* LIN Fractional Baud Rate Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t FBR:4; /* Fractional Baud Rates */
+#else
+ vuint32_t DIV_F:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } LINFLEX_LINFBRR_32B_tag;
+
+ typedef union { /* LIN Integer Baud Rate Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:13;
+#ifndef USE_FIELD_ALIASES_LINFLEX
+ vuint32_t IBR:19; /* Integer Baud Rates */
+#else
+ vuint32_t DIV_M:19; /* deprecated name - please avoid */
+#endif
+ } B;
+ } LINFLEX_LINIBRR_32B_tag;
+
+ typedef union { /* LIN Checksum Field Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t CF:8; /* Checksum Bits */
+ } B;
+ } LINFLEX_LINCFR_32B_tag;
+
+ typedef union { /* LIN Control Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t IOBE:1; /* Idle on Bit Error */
+ vuint32_t IOPE:1; /* Idle on Identifier Parity Error */
+ vuint32_t WURQ:1; /* Wakeup Generate Request */
+ vuint32_t DDRQ:1; /* Data Discard Request */
+ vuint32_t DTRQ:1; /* Data Transmission Request */
+ vuint32_t ABRQ:1; /* Abort Request */
+ vuint32_t HTRQ:1; /* Header Transmission Request */
+ vuint32_t:8;
+ } B;
+ } LINFLEX_LINCR2_32B_tag;
+
+ typedef union { /* Buffer Identifier Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6; /* Data Field Length */
+ vuint32_t DIR:1; /* Direction */
+ vuint32_t CCS:1; /* Classic Checksum */
+ vuint32_t:2;
+ vuint32_t ID:6; /* Identifier */
+ } B;
+ } LINFLEX_BIDR_32B_tag;
+
+ typedef union { /* Buffer Data Register Least Significant */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA3:8; /* Data3 */
+ vuint32_t DATA2:8; /* Data2 */
+ vuint32_t DATA1:8; /* Data1 */
+ vuint32_t DATA0:8; /* Data0 */
+ } B;
+ } LINFLEX_BDRL_32B_tag;
+
+ typedef union { /* Buffer Data Register Most Significant */
+ vuint32_t R;
+ struct {
+ vuint32_t DATA7:8; /* Data7 */
+ vuint32_t DATA6:8; /* Data6 */
+ vuint32_t DATA5:8; /* Data5 */
+ vuint32_t DATA4:8; /* Data4 */
+ } B;
+ } LINFLEX_BDRM_32B_tag;
+
+ typedef union { /* Identifier Filter Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FACT:8; /* Filter Active */
+ } B;
+ } LINFLEX_IFER_32B_tag;
+
+ typedef union { /* Identifier Filter Match Index */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFMI_IFMI:4; /* Filter Match Index */
+ } B;
+ } LINFLEX_IFMI_32B_tag;
+
+ typedef union { /* Identifier Filter Mode Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t IFM:4; /* Filter Mode */
+ } B;
+ } LINFLEX_IFMR_32B_tag;
+
+
+ /* Register layout for all registers IFCR... */
+
+ typedef union { /* Identifier Filter Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DFL:6; /* Data Field Length */
+ vuint32_t DIR:1; /* Direction */
+ vuint32_t CCS:1; /* Classic Checksum */
+ vuint32_t:2;
+ vuint32_t ID:6; /* Identifier */
+ } B;
+ } LINFLEX_IFCR_32B_tag;
+
+ typedef union { /* Global Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t TDFBM:1; /* Transmit Data First Bit MSB */
+ vuint32_t RDFBM:1; /* Received Data First Bit MSB */
+ vuint32_t TDLIS:1; /* Transmit Data Level Inversion Selection */
+ vuint32_t RDLIS:1; /* Received Data Level Inversion Selection */
+ vuint32_t STOP:1; /* 1/2 stop bit configuration */
+ vuint32_t SR:1; /* Soft Reset */
+ } B;
+ } LINFLEX_GCR_32B_tag;
+
+ typedef union { /* UART Preset Time Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t PTO:12; /* Preset Time Out */
+ } B;
+ } LINFLEX_UARTPTO_32B_tag;
+
+ typedef union { /* UART Current Time Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:20;
+ vuint32_t CTO:12; /* Current Time Out */
+ } B;
+ } LINFLEX_UARTCTO_32B_tag;
+
+ typedef union { /* DMA TX Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t DTE:15; /* DMA Tx channel Enable */
+ } B;
+ } LINFLEX_DMATXE_32B_tag;
+
+ typedef union { /* DMA RX Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:17;
+ vuint32_t DRE:15; /* DMA Rx channel Enable */
+ } B;
+ } LINFLEX_DMARXE_32B_tag;
+
+
+
+ typedef struct LINFLEX_tag{ /* start of LINFLEX_tag */
+ /* LIN Control Register */
+ LINFLEX_LINCR1_32B_tag LINCR1; /* offset: 0x0000 size: 32 bit */
+ /* LIN Interrupt Enable Register */
+ LINFLEX_LINIER_32B_tag LINIER; /* offset: 0x0004 size: 32 bit */
+ /* LIN Status Register */
+ LINFLEX_LINSR_32B_tag LINSR; /* offset: 0x0008 size: 32 bit */
+ /* LIN Error Status Register */
+ LINFLEX_LINESR_32B_tag LINESR; /* offset: 0x000C size: 32 bit */
+ /* UART Mode Control Register */
+ LINFLEX_UARTCR_32B_tag UARTCR; /* offset: 0x0010 size: 32 bit */
+ /* UART Mode Status Register */
+ LINFLEX_UARTSR_32B_tag UARTSR; /* offset: 0x0014 size: 32 bit */
+ /* LIN Time-Out Control Status Register */
+ LINFLEX_LINTCSR_32B_tag LINTCSR; /* offset: 0x0018 size: 32 bit */
+ /* LIN Output Compare Register */
+ LINFLEX_LINOCR_32B_tag LINOCR; /* offset: 0x001C size: 32 bit */
+ /* LIN Time-Out Control Register */
+ LINFLEX_LINTOCR_32B_tag LINTOCR; /* offset: 0x0020 size: 32 bit */
+ /* LIN Fractional Baud Rate Register */
+ LINFLEX_LINFBRR_32B_tag LINFBRR; /* offset: 0x0024 size: 32 bit */
+ /* LIN Integer Baud Rate Register */
+ LINFLEX_LINIBRR_32B_tag LINIBRR; /* offset: 0x0028 size: 32 bit */
+ /* LIN Checksum Field Register */
+ LINFLEX_LINCFR_32B_tag LINCFR; /* offset: 0x002C size: 32 bit */
+ /* LIN Control Register 2 */
+ LINFLEX_LINCR2_32B_tag LINCR2; /* offset: 0x0030 size: 32 bit */
+ /* Buffer Identifier Register */
+ LINFLEX_BIDR_32B_tag BIDR; /* offset: 0x0034 size: 32 bit */
+ /* Buffer Data Register Least Significant */
+ LINFLEX_BDRL_32B_tag BDRL; /* offset: 0x0038 size: 32 bit */
+ /* Buffer Data Register Most Significant */
+ LINFLEX_BDRM_32B_tag BDRM; /* offset: 0x003C size: 32 bit */
+ /* Identifier Filter Enable Register */
+ LINFLEX_IFER_32B_tag IFER; /* offset: 0x0040 size: 32 bit */
+ /* Identifier Filter Match Index */
+ LINFLEX_IFMI_32B_tag IFMI; /* offset: 0x0044 size: 32 bit */
+ /* Identifier Filter Mode Register */
+ LINFLEX_IFMR_32B_tag IFMR; /* offset: 0x0048 size: 32 bit */
+ union {
+ /* Identifier Filter Control Register */
+ LINFLEX_IFCR_32B_tag IFCR[8]; /* offset: 0x004C (0x0004 x 8) */
+
+ struct {
+ /* Identifier Filter Control Register */
+ LINFLEX_IFCR_32B_tag IFCR0; /* offset: 0x004C size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR1; /* offset: 0x0050 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR2; /* offset: 0x0054 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR3; /* offset: 0x0058 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR4; /* offset: 0x005C size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR5; /* offset: 0x0060 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR6; /* offset: 0x0064 size: 32 bit */
+ LINFLEX_IFCR_32B_tag IFCR7; /* offset: 0x0068 size: 32 bit */
+ };
+
+ };
+ int8_t LINFLEX_reserved_006C[32];
+ /* Global Control Register */
+ LINFLEX_GCR_32B_tag GCR; /* offset: 0x008C size: 32 bit */
+ /* UART Preset Time Out Register */
+ LINFLEX_UARTPTO_32B_tag UARTPTO; /* offset: 0x0090 size: 32 bit */
+ /* UART Current Time Out Register */
+ LINFLEX_UARTCTO_32B_tag UARTCTO; /* offset: 0x0094 size: 32 bit */
+ /* DMA TX Enable Register */
+ LINFLEX_DMATXE_32B_tag DMATXE; /* offset: 0x0098 size: 32 bit */
+ /* DMA RX Enable Register */
+ LINFLEX_DMARXE_32B_tag DMARXE; /* offset: 0x009C size: 32 bit */
+ } LINFLEX_tag;
+
+
+#define LINFLEX0 (*(volatile LINFLEX_tag *) 0xFFE40000UL)
+#define LINFLEX1 (*(volatile LINFLEX_tag *) 0xFFE44000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: CRC */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers CFG... */
+
+ typedef union { /* CRC_CFG - CRC Configuration register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ struct {
+ vuint32_t:29;
+ vuint32_t POLYG:1; /* Polynomal selection 0- CRC-CCITT, 1- CRC-CRC-32 INV selection */
+ vuint32_t SWAP:1; /* SWAP selection */
+ vuint32_t INV:1; /* INV selection */
+ } B;
+ } CRC_CFG_32B_tag;
+
+
+ /* Register layout for all registers INP... */
+
+ typedef union { /* CRC_INP - CRC Input register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ } CRC_INP_32B_tag;
+
+
+ /* Register layout for all registers CSTAT... */
+
+ typedef union { /* CRC_STATUS - CRC Status register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ } CRC_CSTAT_32B_tag;
+
+
+ /* Register layout for all registers OUTP... */
+
+ typedef union { /* CRC_STATUS - CRC OUTPUT register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint16_t HALF[2]; /* individual halfwords can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ } CRC_OUTP_32B_tag;
+
+
+ typedef struct CRC_CNTX_struct_tag {
+
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG; /* relative offset: 0x0000 */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP; /* relative offset: 0x0004 */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT; /* relative offset: 0x0008 */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP; /* relative offset: 0x000C */
+
+ } CRC_CNTX_tag;
+
+
+ typedef struct CRC_struct_tag { /* start of CRC_tag */
+ union {
+ /* Register set CNTX */
+ CRC_CNTX_tag CNTX[3]; /* offset: 0x0000 (0x0010 x 3) */
+
+ struct {
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG0; /* offset: 0x0000 size: 32 bit */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP0; /* offset: 0x0004 size: 32 bit */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT0; /* offset: 0x0008 size: 32 bit */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP0; /* offset: 0x000C size: 32 bit */
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG1; /* offset: 0x0010 size: 32 bit */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP1; /* offset: 0x0014 size: 32 bit */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT1; /* offset: 0x0018 size: 32 bit */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP1; /* offset: 0x001C size: 32 bit */
+ /* CRC_CFG - CRC Configuration register */
+ CRC_CFG_32B_tag CFG2; /* offset: 0x0020 size: 32 bit */
+ /* CRC_INP - CRC Input register */
+ CRC_INP_32B_tag INP2; /* offset: 0x0024 size: 32 bit */
+ /* CRC_STATUS - CRC Status register */
+ CRC_CSTAT_32B_tag CSTAT2; /* offset: 0x0028 size: 32 bit */
+ /* CRC_STATUS - CRC OUTPUT register */
+ CRC_OUTP_32B_tag OUTP2; /* offset: 0x002C size: 32 bit */
+ };
+
+ };
+ } CRC_tag;
+
+
+#define CRC (*(volatile CRC_tag *) 0xFFE68000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: FCCU */
+/* */
+/****************************************************************/
+
+ typedef union { /* FCCU Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:23;
+ vuint32_t NVML:1; /* NVM configuration loaded */
+ vuint32_t OPS:2; /* Operation status */
+ vuint32_t:1;
+ vuint32_t OPR:5; /* Operation run */
+ } B;
+ } FCCU_CTRL_32B_tag;
+
+ typedef union { /* FCCU CTRL Key Register */
+ vuint32_t R;
+ } FCCU_CTRLK_32B_tag;
+
+ typedef union { /* FCCU Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:10;
+ vuint32_t RCCE1:1; /* RCC1 enable */
+ vuint32_t RCCE0:1; /* RCC0 enable */
+ vuint32_t SMRT:4; /* Safe Mode Request Timer */
+ vuint32_t:4;
+ vuint32_t CM:1; /* Config mode */
+ vuint32_t SM:1; /* Switching mode */
+ vuint32_t PS:1; /* Polarity Selection */
+ vuint32_t FOM:3; /* Fault Output Mode Selection */
+ vuint32_t FOP:6; /* Fault Output Prescaler */
+ } B;
+ } FCCU_CFG_32B_tag;
+
+ typedef union { /* FCCU CF Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFC31:1; /* CF 31 configuration */
+ vuint32_t CFC30:1; /* CF 30 configuration */
+ vuint32_t CFC29:1; /* CF 29 configuration */
+ vuint32_t CFC28:1; /* CF 28 configuration */
+ vuint32_t CFC27:1; /* CF 27 configuration */
+ vuint32_t CFC26:1; /* CF 26 configuration */
+ vuint32_t CFC25:1; /* CF 25 configuration */
+ vuint32_t CFC24:1; /* CF 24 configuration */
+ vuint32_t CFC23:1; /* CF 23 configuration */
+ vuint32_t CFC22:1; /* CF 22 configuration */
+ vuint32_t CFC21:1; /* CF 21 configuration */
+ vuint32_t CFC20:1; /* CF 20 configuration */
+ vuint32_t CFC19:1; /* CF 19 configuration */
+ vuint32_t CFC18:1; /* CF 18 configuration */
+ vuint32_t CFC17:1; /* CF 17 configuration */
+ vuint32_t CFC16:1; /* CF 16 configuration */
+ vuint32_t CFC15:1; /* CF 15 configuration */
+ vuint32_t CFC14:1; /* CF 14 configuration */
+ vuint32_t CFC13:1; /* CF 13 configuration */
+ vuint32_t CFC12:1; /* CF 12 configuration */
+ vuint32_t CFC11:1; /* CF 11 configuration */
+ vuint32_t CFC10:1; /* CF 10 configuration */
+ vuint32_t CFC9:1; /* CF 9 configuration */
+ vuint32_t CFC8:1; /* CF 8 configuration */
+ vuint32_t CFC7:1; /* CF 7 configuration */
+ vuint32_t CFC6:1; /* CF 6 configuration */
+ vuint32_t CFC5:1; /* CF 5 configuration */
+ vuint32_t CFC4:1; /* CF 4 configuration */
+ vuint32_t CFC3:1; /* CF 3 configuration */
+ vuint32_t CFC2:1; /* CF 2 configuration */
+ vuint32_t CFC1:1; /* CF 1 configuration */
+ vuint32_t CFC0:1; /* CF 0 configuration */
+ } B;
+ } FCCU_CF_CFG0_32B_tag;
+
+ typedef union { /* FCCU CF Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFC63:1; /* CF 63 configuration */
+ vuint32_t CFC62:1; /* CF 62 configuration */
+ vuint32_t CFC61:1; /* CF 61 configuration */
+ vuint32_t CFC60:1; /* CF 60 configuration */
+ vuint32_t CFC59:1; /* CF 59 configuration */
+ vuint32_t CFC58:1; /* CF 58 configuration */
+ vuint32_t CFC57:1; /* CF 57 configuration */
+ vuint32_t CFC56:1; /* CF 56 configuration */
+ vuint32_t CFC55:1; /* CF 55 configuration */
+ vuint32_t CFC54:1; /* CF 54 configuration */
+ vuint32_t CFC53:1; /* CF 53 configuration */
+ vuint32_t CFC52:1; /* CF 52 configuration */
+ vuint32_t CFC51:1; /* CF 51 configuration */
+ vuint32_t CFC50:1; /* CF 50 configuration */
+ vuint32_t CFC49:1; /* CF 49 configuration */
+ vuint32_t CFC48:1; /* CF 48 configuration */
+ vuint32_t CFC47:1; /* CF 47 configuration */
+ vuint32_t CFC46:1; /* CF 46 configuration */
+ vuint32_t CFC45:1; /* CF 45 configuration */
+ vuint32_t CFC44:1; /* CF 44 configuration */
+ vuint32_t CFC43:1; /* CF 43 configuration */
+ vuint32_t CFC42:1; /* CF 42 configuration */
+ vuint32_t CFC41:1; /* CF 41 configuration */
+ vuint32_t CFC40:1; /* CF 40 configuration */
+ vuint32_t CFC39:1; /* CF 39 configuration */
+ vuint32_t CFC38:1; /* CF 38 configuration */
+ vuint32_t CFC37:1; /* CF 37 configuration */
+ vuint32_t CFC36:1; /* CF 36 configuration */
+ vuint32_t CFC35:1; /* CF 35 configuration */
+ vuint32_t CFC34:1; /* CF 34 configuration */
+ vuint32_t CFC33:1; /* CF 33 configuration */
+ vuint32_t CFC32:1; /* CF 32 configuration */
+ } B;
+ } FCCU_CF_CFG1_32B_tag;
+
+ typedef union { /* FCCU CF Configuration Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFC95:1; /* CF 95 configuration */
+ vuint32_t CFC94:1; /* CF 94 configuration */
+ vuint32_t CFC93:1; /* CF 93 configuration */
+ vuint32_t CFC92:1; /* CF 92 configuration */
+ vuint32_t CFC91:1; /* CF 91 configuration */
+ vuint32_t CFC90:1; /* CF 90 configuration */
+ vuint32_t CFC89:1; /* CF 89 configuration */
+ vuint32_t CFC88:1; /* CF 88 configuration */
+ vuint32_t CFC87:1; /* CF 87 configuration */
+ vuint32_t CFC86:1; /* CF 86 configuration */
+ vuint32_t CFC85:1; /* CF 85 configuration */
+ vuint32_t CFC84:1; /* CF 84 configuration */
+ vuint32_t CFC83:1; /* CF 83 configuration */
+ vuint32_t CFC82:1; /* CF 82 configuration */
+ vuint32_t CFC81:1; /* CF 81 configuration */
+ vuint32_t CFC80:1; /* CF 80 configuration */
+ vuint32_t CFC79:1; /* CF 79 configuration */
+ vuint32_t CFC78:1; /* CF 78 configuration */
+ vuint32_t CFC77:1; /* CF 77 configuration */
+ vuint32_t CFC76:1; /* CF 76 configuration */
+ vuint32_t CFC75:1; /* CF 75 configuration */
+ vuint32_t CFC74:1; /* CF 74 configuration */
+ vuint32_t CFC73:1; /* CF 73 configuration */
+ vuint32_t CFC72:1; /* CF 72 configuration */
+ vuint32_t CFC71:1; /* CF 71 configuration */
+ vuint32_t CFC70:1; /* CF 70 configuration */
+ vuint32_t CFC69:1; /* CF 69 configuration */
+ vuint32_t CFC68:1; /* CF 68 configuration */
+ vuint32_t CFC67:1; /* CF 67 configuration */
+ vuint32_t CFC66:1; /* CF 66 configuration */
+ vuint32_t CFC65:1; /* CF 65 configuration */
+ vuint32_t CFC64:1; /* CF 64 configuration */
+ } B;
+ } FCCU_CF_CFG2_32B_tag;
+
+ typedef union { /* FCCU CF Configuration Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFC127:1; /* CF 127 configuration */
+ vuint32_t CFC126:1; /* CF 126 configuration */
+ vuint32_t CFC125:1; /* CF 125 configuration */
+ vuint32_t CFC124:1; /* CF 124 configuration */
+ vuint32_t CFC123:1; /* CF 123 configuration */
+ vuint32_t CFC122:1; /* CF 122 configuration */
+ vuint32_t CFC121:1; /* CF 121 configuration */
+ vuint32_t CFC120:1; /* CF 120 configuration */
+ vuint32_t CFC119:1; /* CF 119 configuration */
+ vuint32_t CFC118:1; /* CF 118 configuration */
+ vuint32_t CFC117:1; /* CF 117 configuration */
+ vuint32_t CFC116:1; /* CF 116 configuration */
+ vuint32_t CFC115:1; /* CF 115 configuration */
+ vuint32_t CFC114:1; /* CF 114 configuration */
+ vuint32_t CFC113:1; /* CF 113 configuration */
+ vuint32_t CFC112:1; /* CF 112 configuration */
+ vuint32_t CFC111:1; /* CF 111 configuration */
+ vuint32_t CFC110:1; /* CF 110 configuration */
+ vuint32_t CFC109:1; /* CF 109 configuration */
+ vuint32_t CFC108:1; /* CF 108 configuration */
+ vuint32_t CFC107:1; /* CF 107 configuration */
+ vuint32_t CFC106:1; /* CF 106 configuration */
+ vuint32_t CFC105:1; /* CF 105 configuration */
+ vuint32_t CFC104:1; /* CF 104 configuration */
+ vuint32_t CFC103:1; /* CF 103 configuration */
+ vuint32_t CFC102:1; /* CF 102 configuration */
+ vuint32_t CFC101:1; /* CF 101 configuration */
+ vuint32_t CFC100:1; /* CF 100 configuration */
+ vuint32_t CFC99:1; /* CF 99 configuration */
+ vuint32_t CFC98:1; /* CF 98 configuration */
+ vuint32_t CFC97:1; /* CF 97 configuration */
+ vuint32_t CFC96:1; /* CF 96 configuration */
+ } B;
+ } FCCU_CF_CFG3_32B_tag;
+
+ typedef union { /* FCCU NCF Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFC31:1; /* NCF 31 configuration */
+ vuint32_t NCFC30:1; /* NCF 30 configuration */
+ vuint32_t NCFC29:1; /* NCF 29 configuration */
+ vuint32_t NCFC28:1; /* NCF 28 configuration */
+ vuint32_t NCFC27:1; /* NCF 27 configuration */
+ vuint32_t NCFC26:1; /* NCF 26 configuration */
+ vuint32_t NCFC25:1; /* NCF 25 configuration */
+ vuint32_t NCFC24:1; /* NCF 24 configuration */
+ vuint32_t NCFC23:1; /* NCF 23 configuration */
+ vuint32_t NCFC22:1; /* NCF 22 configuration */
+ vuint32_t NCFC21:1; /* NCF 21 configuration */
+ vuint32_t NCFC20:1; /* NCF 20 configuration */
+ vuint32_t NCFC19:1; /* NCF 19 configuration */
+ vuint32_t NCFC18:1; /* NCF 18 configuration */
+ vuint32_t NCFC17:1; /* NCF 17 configuration */
+ vuint32_t NCFC16:1; /* NCF 16 configuration */
+ vuint32_t NCFC15:1; /* NCF 15 configuration */
+ vuint32_t NCFC14:1; /* NCF 14 configuration */
+ vuint32_t NCFC13:1; /* NCF 13 configuration */
+ vuint32_t NCFC12:1; /* NCF 12 configuration */
+ vuint32_t NCFC11:1; /* NCF 11 configuration */
+ vuint32_t NCFC10:1; /* NCF 10 configuration */
+ vuint32_t NCFC9:1; /* NCF 9 configuration */
+ vuint32_t NCFC8:1; /* NCF 8 configuration */
+ vuint32_t NCFC7:1; /* NCF 7 configuration */
+ vuint32_t NCFC6:1; /* NCF 6 configuration */
+ vuint32_t NCFC5:1; /* NCF 5 configuration */
+ vuint32_t NCFC4:1; /* NCF 4 configuration */
+ vuint32_t NCFC3:1; /* NCF 3 configuration */
+ vuint32_t NCFC2:1; /* NCF 2 configuration */
+ vuint32_t NCFC1:1; /* NCF 1 configuration */
+ vuint32_t NCFC0:1; /* NCF 0 configuration */
+ } B;
+ } FCCU_NCF_CFG0_32B_tag;
+
+ typedef union { /* FCCU NCF Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFC63:1; /* NCF 63 configuration */
+ vuint32_t NCFC62:1; /* NCF 62 configuration */
+ vuint32_t NCFC61:1; /* NCF 61 configuration */
+ vuint32_t NCFC60:1; /* NCF 60 configuration */
+ vuint32_t NCFC59:1; /* NCF 59 configuration */
+ vuint32_t NCFC58:1; /* NCF 58 configuration */
+ vuint32_t NCFC57:1; /* NCF 57 configuration */
+ vuint32_t NCFC56:1; /* NCF 56 configuration */
+ vuint32_t NCFC55:1; /* NCF 55 configuration */
+ vuint32_t NCFC54:1; /* NCF 54 configuration */
+ vuint32_t NCFC53:1; /* NCF 53 configuration */
+ vuint32_t NCFC52:1; /* NCF 52 configuration */
+ vuint32_t NCFC51:1; /* NCF 51 configuration */
+ vuint32_t NCFC50:1; /* NCF 50 configuration */
+ vuint32_t NCFC49:1; /* NCF 49 configuration */
+ vuint32_t NCFC48:1; /* NCF 48 configuration */
+ vuint32_t NCFC47:1; /* NCF 47 configuration */
+ vuint32_t NCFC46:1; /* NCF 46 configuration */
+ vuint32_t NCFC45:1; /* NCF 45 configuration */
+ vuint32_t NCFC44:1; /* NCF 44 configuration */
+ vuint32_t NCFC43:1; /* NCF 43 configuration */
+ vuint32_t NCFC42:1; /* NCF 42 configuration */
+ vuint32_t NCFC41:1; /* NCF 41 configuration */
+ vuint32_t NCFC40:1; /* NCF 40 configuration */
+ vuint32_t NCFC39:1; /* NCF 39 configuration */
+ vuint32_t NCFC38:1; /* NCF 38 configuration */
+ vuint32_t NCFC37:1; /* NCF 37 configuration */
+ vuint32_t NCFC36:1; /* NCF 36 configuration */
+ vuint32_t NCFC35:1; /* NCF 35 configuration */
+ vuint32_t NCFC34:1; /* NCF 34 configuration */
+ vuint32_t NCFC33:1; /* NCF 33 configuration */
+ vuint32_t NCFC32:1; /* NCF 32 configuration */
+ } B;
+ } FCCU_NCF_CFG1_32B_tag;
+
+ typedef union { /* FCCU NCF Configuration Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFC95:1; /* NCF 95 configuration */
+ vuint32_t NCFC94:1; /* NCF 94 configuration */
+ vuint32_t NCFC93:1; /* NCF 93 configuration */
+ vuint32_t NCFC92:1; /* NCF 92 configuration */
+ vuint32_t NCFC91:1; /* NCF 91 configuration */
+ vuint32_t NCFC90:1; /* NCF 90 configuration */
+ vuint32_t NCFC89:1; /* NCF 89 configuration */
+ vuint32_t NCFC88:1; /* NCF 88 configuration */
+ vuint32_t NCFC87:1; /* NCF 87 configuration */
+ vuint32_t NCFC86:1; /* NCF 86 configuration */
+ vuint32_t NCFC85:1; /* NCF 85 configuration */
+ vuint32_t NCFC84:1; /* NCF 84 configuration */
+ vuint32_t NCFC83:1; /* NCF 83 configuration */
+ vuint32_t NCFC82:1; /* NCF 82 configuration */
+ vuint32_t NCFC81:1; /* NCF 81 configuration */
+ vuint32_t NCFC80:1; /* NCF 80 configuration */
+ vuint32_t NCFC79:1; /* NCF 79 configuration */
+ vuint32_t NCFC78:1; /* NCF 78 configuration */
+ vuint32_t NCFC77:1; /* NCF 77 configuration */
+ vuint32_t NCFC76:1; /* NCF 76 configuration */
+ vuint32_t NCFC75:1; /* NCF 75 configuration */
+ vuint32_t NCFC74:1; /* NCF 74 configuration */
+ vuint32_t NCFC73:1; /* NCF 73 configuration */
+ vuint32_t NCFC72:1; /* NCF 72 configuration */
+ vuint32_t NCFC71:1; /* NCF 71 configuration */
+ vuint32_t NCFC70:1; /* NCF 70 configuration */
+ vuint32_t NCFC69:1; /* NCF 69 configuration */
+ vuint32_t NCFC68:1; /* NCF 68 configuration */
+ vuint32_t NCFC67:1; /* NCF 67 configuration */
+ vuint32_t NCFC66:1; /* NCF 66 configuration */
+ vuint32_t NCFC65:1; /* NCF 65 configuration */
+ vuint32_t NCFC64:1; /* NCF 64 configuration */
+ } B;
+ } FCCU_NCF_CFG2_32B_tag;
+
+ typedef union { /* FCCU NCF Configuration Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFC127:1; /* NCF 127 configuration */
+ vuint32_t NCFC126:1; /* NCF 126 configuration */
+ vuint32_t NCFC125:1; /* NCF 125 configuration */
+ vuint32_t NCFC124:1; /* NCF 124 configuration */
+ vuint32_t NCFC123:1; /* NCF 123 configuration */
+ vuint32_t NCFC122:1; /* NCF 122 configuration */
+ vuint32_t NCFC121:1; /* NCF 121 configuration */
+ vuint32_t NCFC120:1; /* NCF 120 configuration */
+ vuint32_t NCFC119:1; /* NCF 119 configuration */
+ vuint32_t NCFC118:1; /* NCF 118 configuration */
+ vuint32_t NCFC117:1; /* NCF 117 configuration */
+ vuint32_t NCFC116:1; /* NCF 116 configuration */
+ vuint32_t NCFC115:1; /* NCF 115 configuration */
+ vuint32_t NCFC114:1; /* NCF 114 configuration */
+ vuint32_t NCFC113:1; /* NCF 113 configuration */
+ vuint32_t NCFC112:1; /* NCF 112 configuration */
+ vuint32_t NCFC111:1; /* NCF 111 configuration */
+ vuint32_t NCFC110:1; /* NCF 110 configuration */
+ vuint32_t NCFC109:1; /* NCF 109 configuration */
+ vuint32_t NCFC108:1; /* NCF 108 configuration */
+ vuint32_t NCFC107:1; /* NCF 107 configuration */
+ vuint32_t NCFC106:1; /* NCF 106 configuration */
+ vuint32_t NCFC105:1; /* NCF 105 configuration */
+ vuint32_t NCFC104:1; /* NCF 104 configuration */
+ vuint32_t NCFC103:1; /* NCF 103 configuration */
+ vuint32_t NCFC102:1; /* NCF 102 configuration */
+ vuint32_t NCFC101:1; /* NCF 101 configuration */
+ vuint32_t NCFC100:1; /* NCF 100 configuration */
+ vuint32_t NCFC99:1; /* NCF 99 configuration */
+ vuint32_t NCFC98:1; /* NCF 98 configuration */
+ vuint32_t NCFC97:1; /* NCF 97 configuration */
+ vuint32_t NCFC96:1; /* NCF 96 configuration */
+ } B;
+ } FCCU_NCF_CFG3_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC15:2; /* CF 15 state configuration */
+ vuint32_t CFSC14:2; /* CF 14 state configuration */
+ vuint32_t CFSC13:2; /* CF 13 state configuration */
+ vuint32_t CFSC12:2; /* CF 12 state configuration */
+ vuint32_t CFSC11:2; /* CF 11 state configuration */
+ vuint32_t CFSC10:2; /* CF 10 state configuration */
+ vuint32_t CFSC9:2; /* CF 9 state configuration */
+ vuint32_t CFSC8:2; /* CF 8 state configuration */
+ vuint32_t CFSC7:2; /* CF 7 state configuration */
+ vuint32_t CFSC6:2; /* CF 6 state configuration */
+ vuint32_t CFSC5:2; /* CF 5 state configuration */
+ vuint32_t CFSC4:2; /* CF 4 state configuration */
+ vuint32_t CFSC3:2; /* CF 3 state configuration */
+ vuint32_t CFSC2:2; /* CF 2 state configuration */
+ vuint32_t CFSC1:2; /* CF 1 state configuration */
+ vuint32_t CFSC0:2; /* CF 0 state configuration */
+ } B;
+ } FCCU_CFS_CFG0_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC31:2; /* CF 31 state configuration */
+ vuint32_t CFSC30:2; /* CF 30 state configuration */
+ vuint32_t CFSC29:2; /* CF 29 state configuration */
+ vuint32_t CFSC28:2; /* CF 28 state configuration */
+ vuint32_t CFSC27:2; /* CF 27 state configuration */
+ vuint32_t CFSC26:2; /* CF 26 state configuration */
+ vuint32_t CFSC25:2; /* CF 25 state configuration */
+ vuint32_t CFSC24:2; /* CF 24 state configuration */
+ vuint32_t CFSC23:2; /* CF 23 state configuration */
+ vuint32_t CFSC22:2; /* CF 22 state configuration */
+ vuint32_t CFSC21:2; /* CF 21 state configuration */
+ vuint32_t CFSC20:2; /* CF 20 state configuration */
+ vuint32_t CFSC19:2; /* CF 19 state configuration */
+ vuint32_t CFSC18:2; /* CF 18 state configuration */
+ vuint32_t CFSC17:2; /* CF 17 state configuration */
+ vuint32_t CFSC16:2; /* CF 16 state configuration */
+ } B;
+ } FCCU_CFS_CFG1_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC47:2; /* CF 47 state configuration */
+ vuint32_t CFSC46:2; /* CF 46 state configuration */
+ vuint32_t CFSC45:2; /* CF 45 state configuration */
+ vuint32_t CFSC44:2; /* CF 44 state configuration */
+ vuint32_t CFSC43:2; /* CF 43 state configuration */
+ vuint32_t CFSC42:2; /* CF 42 state configuration */
+ vuint32_t CFSC41:2; /* CF 41 state configuration */
+ vuint32_t CFSC40:2; /* CF 40 state configuration */
+ vuint32_t CFSC39:2; /* CF 39 state configuration */
+ vuint32_t CFSC38:2; /* CF 38 state configuration */
+ vuint32_t CFSC37:2; /* CF 37 state configuration */
+ vuint32_t CFSC36:2; /* CF 36 state configuration */
+ vuint32_t CFSC35:2; /* CF 35 state configuration */
+ vuint32_t CFSC34:2; /* CF 34 state configuration */
+ vuint32_t CFSC33:2; /* CF 33 state configuration */
+ vuint32_t CFSC32:2; /* CF 32 state configuration */
+ } B;
+ } FCCU_CFS_CFG2_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC63:2; /* CF 63 state configuration */
+ vuint32_t CFSC62:2; /* CF 62 state configuration */
+ vuint32_t CFSC61:2; /* CF 61 state configuration */
+ vuint32_t CFSC60:2; /* CF 60 state configuration */
+ vuint32_t CFSC59:2; /* CF 59 state configuration */
+ vuint32_t CFSC58:2; /* CF 58 state configuration */
+ vuint32_t CFSC57:2; /* CF 57 state configuration */
+ vuint32_t CFSC56:2; /* CF 56 state configuration */
+ vuint32_t CFSC55:2; /* CF 55 state configuration */
+ vuint32_t CFSC54:2; /* CF 54 state configuration */
+ vuint32_t CFSC53:2; /* CF 53 state configuration */
+ vuint32_t CFSC52:2; /* CF 52 state configuration */
+ vuint32_t CFSC51:2; /* CF 51 state configuration */
+ vuint32_t CFSC50:2; /* CF 50 state configuration */
+ vuint32_t CFSC49:2; /* CF 49 state configuration */
+ vuint32_t CFSC48:2; /* CF 48 state configuration */
+ } B;
+ } FCCU_CFS_CFG3_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 4 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC79:2; /* CF 79 state configuration */
+ vuint32_t CFSC78:2; /* CF 78 state configuration */
+ vuint32_t CFSC77:2; /* CF 77 state configuration */
+ vuint32_t CFSC76:2; /* CF 76 state configuration */
+ vuint32_t CFSC75:2; /* CF 75 state configuration */
+ vuint32_t CFSC74:2; /* CF 74 state configuration */
+ vuint32_t CFSC73:2; /* CF 73 state configuration */
+ vuint32_t CFSC72:2; /* CF 72 state configuration */
+ vuint32_t CFSC71:2; /* CF 71 state configuration */
+ vuint32_t CFSC70:2; /* CF 70 state configuration */
+ vuint32_t CFSC69:2; /* CF 69 state configuration */
+ vuint32_t CFSC68:2; /* CF 68 state configuration */
+ vuint32_t CFSC67:2; /* CF 67 state configuration */
+ vuint32_t CFSC66:2; /* CF 66 state configuration */
+ vuint32_t CFSC65:2; /* CF 65 state configuration */
+ vuint32_t CFSC64:2; /* CF 64 state configuration */
+ } B;
+ } FCCU_CFS_CFG4_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 5 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC95:2; /* CF 95 state configuration */
+ vuint32_t CFSC94:2; /* CF 94 state configuration */
+ vuint32_t CFSC93:2; /* CF 93 state configuration */
+ vuint32_t CFSC92:2; /* CF 92 state configuration */
+ vuint32_t CFSC91:2; /* CF 91 state configuration */
+ vuint32_t CFSC90:2; /* CF 90 state configuration */
+ vuint32_t CFSC89:2; /* CF 89 state configuration */
+ vuint32_t CFSC88:2; /* CF 88 state configuration */
+ vuint32_t CFSC87:2; /* CF 87 state configuration */
+ vuint32_t CFSC86:2; /* CF 86 state configuration */
+ vuint32_t CFSC85:2; /* CF 85 state configuration */
+ vuint32_t CFSC84:2; /* CF 84 state configuration */
+ vuint32_t CFSC83:2; /* CF 83 state configuration */
+ vuint32_t CFSC82:2; /* CF 82 state configuration */
+ vuint32_t CFSC81:2; /* CF 81 state configuration */
+ vuint32_t CFSC80:2; /* CF 80 state configuration */
+ } B;
+ } FCCU_CFS_CFG5_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 6 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC111:2; /* CF 111 state configuration */
+ vuint32_t CFSC110:2; /* CF 110 state configuration */
+ vuint32_t CFSC109:2; /* CF 109 state configuration */
+ vuint32_t CFSC108:2; /* CF 108 state configuration */
+ vuint32_t CFSC107:2; /* CF 107 state configuration */
+ vuint32_t CFSC106:2; /* CF 106 state configuration */
+ vuint32_t CFSC105:2; /* CF 105 state configuration */
+ vuint32_t CFSC104:2; /* CF 104 state configuration */
+ vuint32_t CFSC103:2; /* CF 103 state configuration */
+ vuint32_t CFSC102:2; /* CF 102 state configuration */
+ vuint32_t CFSC101:2; /* CF 101 state configuration */
+ vuint32_t CFSC100:2; /* CF 100 state configuration */
+ vuint32_t CFSC99:2; /* CF 99 state configuration */
+ vuint32_t CFSC98:2; /* CF 98 state configuration */
+ vuint32_t CFSC97:2; /* CF 97 state configuration */
+ vuint32_t CFSC96:2; /* CF 96 state configuration */
+ } B;
+ } FCCU_CFS_CFG6_32B_tag;
+
+ typedef union { /* FCCU CFS Configuration Register 7 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFSC127:2; /* CF 127 state configuration */
+ vuint32_t CFSC126:2; /* CF 126 state configuration */
+ vuint32_t CFSC125:2; /* CF 125 state configuration */
+ vuint32_t CFSC124:2; /* CF 124 state configuration */
+ vuint32_t CFSC123:2; /* CF 123 state configuration */
+ vuint32_t CFSC122:2; /* CF 122 state configuration */
+ vuint32_t CFSC121:2; /* CF 121 state configuration */
+ vuint32_t CFSC120:2; /* CF 120 state configuration */
+ vuint32_t CFSC119:2; /* CF 119 state configuration */
+ vuint32_t CFSC118:2; /* CF 118 state configuration */
+ vuint32_t CFSC117:2; /* CF 117 state configuration */
+ vuint32_t CFSC116:2; /* CF 116 state configuration */
+ vuint32_t CFSC115:2; /* CF 115 state configuration */
+ vuint32_t CFSC114:2; /* CF 114 state configuration */
+ vuint32_t CFSC113:2; /* CF 113 state configuration */
+ vuint32_t CFSC112:2; /* CF 112 state configuration */
+ } B;
+ } FCCU_CFS_CFG7_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC15:2; /* NCF 15 state configuration */
+ vuint32_t NCFSC14:2; /* NCF 14 state configuration */
+ vuint32_t NCFSC13:2; /* NCF 13 state configuration */
+ vuint32_t NCFSC12:2; /* NCF 12 state configuration */
+ vuint32_t NCFSC11:2; /* NCF 11 state configuration */
+ vuint32_t NCFSC10:2; /* NCF 10 state configuration */
+ vuint32_t NCFSC9:2; /* NCF 9 state configuration */
+ vuint32_t NCFSC8:2; /* NCF 8 state configuration */
+ vuint32_t NCFSC7:2; /* NCF 7 state configuration */
+ vuint32_t NCFSC6:2; /* NCF 6 state configuration */
+ vuint32_t NCFSC5:2; /* NCF 5 state configuration */
+ vuint32_t NCFSC4:2; /* NCF 4 state configuration */
+ vuint32_t NCFSC3:2; /* NCF 3 state configuration */
+ vuint32_t NCFSC2:2; /* NCF 2 state configuration */
+ vuint32_t NCFSC1:2; /* NCF 1 state configuration */
+ vuint32_t NCFSC0:2; /* NCF 0 state configuration */
+ } B;
+ } FCCU_NCFS_CFG0_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC31:2; /* NCF 31 state configuration */
+ vuint32_t NCFSC30:2; /* NCF 30 state configuration */
+ vuint32_t NCFSC29:2; /* NCF 29 state configuration */
+ vuint32_t NCFSC28:2; /* NCF 28 state configuration */
+ vuint32_t NCFSC27:2; /* NCF 27 state configuration */
+ vuint32_t NCFSC26:2; /* NCF 26 state configuration */
+ vuint32_t NCFSC25:2; /* NCF 25 state configuration */
+ vuint32_t NCFSC24:2; /* NCF 24 state configuration */
+ vuint32_t NCFSC23:2; /* NCF 23 state configuration */
+ vuint32_t NCFSC22:2; /* NCF 22 state configuration */
+ vuint32_t NCFSC21:2; /* NCF 21 state configuration */
+ vuint32_t NCFSC20:2; /* NCF 20 state configuration */
+ vuint32_t NCFSC19:2; /* NCF 19 state configuration */
+ vuint32_t NCFSC18:2; /* NCF 18 state configuration */
+ vuint32_t NCFSC17:2; /* NCF 17 state configuration */
+ vuint32_t NCFSC16:2; /* NCF 16 state configuration */
+ } B;
+ } FCCU_NCFS_CFG1_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC47:2; /* NCF 47 state configuration */
+ vuint32_t NCFSC46:2; /* NCF 46 state configuration */
+ vuint32_t NCFSC45:2; /* NCF 45 state configuration */
+ vuint32_t NCFSC44:2; /* NCF 44 state configuration */
+ vuint32_t NCFSC43:2; /* NCF 43 state configuration */
+ vuint32_t NCFSC42:2; /* NCF 42 state configuration */
+ vuint32_t NCFSC41:2; /* NCF 41 state configuration */
+ vuint32_t NCFSC40:2; /* NCF 40 state configuration */
+ vuint32_t NCFSC39:2; /* NCF 39 state configuration */
+ vuint32_t NCFSC38:2; /* NCF 38 state configuration */
+ vuint32_t NCFSC37:2; /* NCF 37 state configuration */
+ vuint32_t NCFSC36:2; /* NCF 36 state configuration */
+ vuint32_t NCFSC35:2; /* NCF 35 state configuration */
+ vuint32_t NCFSC34:2; /* NCF 34 state configuration */
+ vuint32_t NCFSC33:2; /* NCF 33 state configuration */
+ vuint32_t NCFSC32:2; /* NCF 32 state configuration */
+ } B;
+ } FCCU_NCFS_CFG2_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC63:2; /* NCF 63 state configuration */
+ vuint32_t NCFSC62:2; /* NCF 62 state configuration */
+ vuint32_t NCFSC61:2; /* NCF 61 state configuration */
+ vuint32_t NCFSC60:2; /* NCF 60 state configuration */
+ vuint32_t NCFSC59:2; /* NCF 59 state configuration */
+ vuint32_t NCFSC58:2; /* NCF 58 state configuration */
+ vuint32_t NCFSC57:2; /* NCF 57 state configuration */
+ vuint32_t NCFSC56:2; /* NCF 56 state configuration */
+ vuint32_t NCFSC55:2; /* NCF 55 state configuration */
+ vuint32_t NCFSC54:2; /* NCF 54 state configuration */
+ vuint32_t NCFSC53:2; /* NCF 53 state configuration */
+ vuint32_t NCFSC52:2; /* NCF 52 state configuration */
+ vuint32_t NCFSC51:2; /* NCF 51 state configuration */
+ vuint32_t NCFSC50:2; /* NCF 50 state configuration */
+ vuint32_t NCFSC49:2; /* NCF 49 state configuration */
+ vuint32_t NCFSC48:2; /* NCF 48 state configuration */
+ } B;
+ } FCCU_NCFS_CFG3_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 4 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC79:2; /* NCF 79 state configuration */
+ vuint32_t NCFSC78:2; /* NCF 78 state configuration */
+ vuint32_t NCFSC77:2; /* NCF 77 state configuration */
+ vuint32_t NCFSC76:2; /* NCF 76 state configuration */
+ vuint32_t NCFSC75:2; /* NCF 75 state configuration */
+ vuint32_t NCFSC74:2; /* NCF 74 state configuration */
+ vuint32_t NCFSC73:2; /* NCF 73 state configuration */
+ vuint32_t NCFSC72:2; /* NCF 72 state configuration */
+ vuint32_t NCFSC71:2; /* NCF 71 state configuration */
+ vuint32_t NCFSC70:2; /* NCF 70 state configuration */
+ vuint32_t NCFSC69:2; /* NCF 69 state configuration */
+ vuint32_t NCFSC68:2; /* NCF 68 state configuration */
+ vuint32_t NCFSC67:2; /* NCF 67 state configuration */
+ vuint32_t NCFSC66:2; /* NCF 66 state configuration */
+ vuint32_t NCFSC65:2; /* NCF 65 state configuration */
+ vuint32_t NCFSC64:2; /* NCF 64 state configuration */
+ } B;
+ } FCCU_NCFS_CFG4_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 5 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC95:2; /* NCF 95 state configuration */
+ vuint32_t NCFSC94:2; /* NCF 94 state configuration */
+ vuint32_t NCFSC93:2; /* NCF 93 state configuration */
+ vuint32_t NCFSC92:2; /* NCF 92 state configuration */
+ vuint32_t NCFSC91:2; /* NCF 91 state configuration */
+ vuint32_t NCFSC90:2; /* NCF 90 state configuration */
+ vuint32_t NCFSC89:2; /* NCF 89 state configuration */
+ vuint32_t NCFSC88:2; /* NCF 88 state configuration */
+ vuint32_t NCFSC87:2; /* NCF 87 state configuration */
+ vuint32_t NCFSC86:2; /* NCF 86 state configuration */
+ vuint32_t NCFSC85:2; /* NCF 85 state configuration */
+ vuint32_t NCFSC84:2; /* NCF 84 state configuration */
+ vuint32_t NCFSC83:2; /* NCF 83 state configuration */
+ vuint32_t NCFSC82:2; /* NCF 82 state configuration */
+ vuint32_t NCFSC81:2; /* NCF 81 state configuration */
+ vuint32_t NCFSC80:2; /* NCF 80 state configuration */
+ } B;
+ } FCCU_NCFS_CFG5_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 6 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC111:2; /* NCF 111 state configuration */
+ vuint32_t NCFSC110:2; /* NCF 110 state configuration */
+ vuint32_t NCFSC109:2; /* NCF 109 state configuration */
+ vuint32_t NCFSC108:2; /* NCF 108 state configuration */
+ vuint32_t NCFSC107:2; /* NCF 107 state configuration */
+ vuint32_t NCFSC106:2; /* NCF 106 state configuration */
+ vuint32_t NCFSC105:2; /* NCF 105 state configuration */
+ vuint32_t NCFSC104:2; /* NCF 104 state configuration */
+ vuint32_t NCFSC103:2; /* NCF 103 state configuration */
+ vuint32_t NCFSC102:2; /* NCF 102 state configuration */
+ vuint32_t NCFSC101:2; /* NCF 101 state configuration */
+ vuint32_t NCFSC100:2; /* NCF 100 state configuration */
+ vuint32_t NCFSC99:2; /* NCF 99 state configuration */
+ vuint32_t NCFSC98:2; /* NCF 98 state configuration */
+ vuint32_t NCFSC97:2; /* NCF 97 state configuration */
+ vuint32_t NCFSC96:2; /* NCF 96 state configuration */
+ } B;
+ } FCCU_NCFS_CFG6_32B_tag;
+
+ typedef union { /* FCCU NCFS Configuration Register 7 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFSC127:2; /* NCF 127 state configuration */
+ vuint32_t NCFSC126:2; /* NCF 126 state configuration */
+ vuint32_t NCFSC125:2; /* NCF 125 state configuration */
+ vuint32_t NCFSC124:2; /* NCF 124 state configuration */
+ vuint32_t NCFSC123:2; /* NCF 123 state configuration */
+ vuint32_t NCFSC122:2; /* NCF 122 state configuration */
+ vuint32_t NCFSC121:2; /* NCF 121 state configuration */
+ vuint32_t NCFSC120:2; /* NCF 120 state configuration */
+ vuint32_t NCFSC119:2; /* NCF 119 state configuration */
+ vuint32_t NCFSC118:2; /* NCF 118 state configuration */
+ vuint32_t NCFSC117:2; /* NCF 117 state configuration */
+ vuint32_t NCFSC116:2; /* NCF 116 state configuration */
+ vuint32_t NCFSC115:2; /* NCF 115 state configuration */
+ vuint32_t NCFSC114:2; /* NCF 114 state configuration */
+ vuint32_t NCFSC113:2; /* NCF 113 state configuration */
+ vuint32_t NCFSC112:2; /* NCF 112 state configuration */
+ } B;
+ } FCCU_NCFS_CFG7_32B_tag;
+
+ typedef union { /* FCCU CF Status Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFS31:1; /* CF 31 status */
+ vuint32_t CFS30:1; /* CF 30 status */
+ vuint32_t CFS29:1; /* CF 29 status */
+ vuint32_t CFS28:1; /* CF 28 status */
+ vuint32_t CFS27:1; /* CF 27 status */
+ vuint32_t CFS26:1; /* CF 26 status */
+ vuint32_t CFS25:1; /* CF 25 status */
+ vuint32_t CFS24:1; /* CF 24 status */
+ vuint32_t CFS23:1; /* CF 23 status */
+ vuint32_t CFS22:1; /* CF 22 status */
+ vuint32_t CFS21:1; /* CF 21 status */
+ vuint32_t CFS20:1; /* CF 20 status */
+ vuint32_t CFS19:1; /* CF 19 status */
+ vuint32_t CFS18:1; /* CF 18 status */
+ vuint32_t CFS17:1; /* CF 17 status */
+ vuint32_t CFS16:1; /* CF 16 status */
+ vuint32_t CFS15:1; /* CF 15 status */
+ vuint32_t CFS14:1; /* CF 14 status */
+ vuint32_t CFS13:1; /* CF 13 status */
+ vuint32_t CFS12:1; /* CF 12 status */
+ vuint32_t CFS11:1; /* CF 11 status */
+ vuint32_t CFS10:1; /* CF 10 status */
+ vuint32_t CFS9:1; /* CF 9 status */
+ vuint32_t CFS8:1; /* CF 8 status */
+ vuint32_t CFS7:1; /* CF 7 status */
+ vuint32_t CFS6:1; /* CF 6 status */
+ vuint32_t CFS5:1; /* CF 5 status */
+ vuint32_t CFS4:1; /* CF 4 status */
+ vuint32_t CFS3:1; /* CF 3 status */
+ vuint32_t CFS2:1; /* CF 2 status */
+ vuint32_t CFS1:1; /* CF 1 status */
+ vuint32_t CFS0:1; /* CF 0 status */
+ } B;
+ } FCCU_CFS0_32B_tag;
+
+ typedef union { /* FCCU CF Status Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFS63:1; /* CF 63 status */
+ vuint32_t CFS62:1; /* CF 62 status */
+ vuint32_t CFS61:1; /* CF 61 status */
+ vuint32_t CFS60:1; /* CF 60 status */
+ vuint32_t CFS59:1; /* CF 59 status */
+ vuint32_t CFS58:1; /* CF 58 status */
+ vuint32_t CFS57:1; /* CF 57 status */
+ vuint32_t CFS56:1; /* CF 56 status */
+ vuint32_t CFS55:1; /* CF 55 status */
+ vuint32_t CFS54:1; /* CF 54 status */
+ vuint32_t CFS53:1; /* CF 53 status */
+ vuint32_t CFS52:1; /* CF 52 status */
+ vuint32_t CFS51:1; /* CF 51 status */
+ vuint32_t CFS50:1; /* CF 50 status */
+ vuint32_t CFS49:1; /* CF 49 status */
+ vuint32_t CFS48:1; /* CF 48 status */
+ vuint32_t CFS47:1; /* CF 47 status */
+ vuint32_t CFS46:1; /* CF 46 status */
+ vuint32_t CFS45:1; /* CF 45 status */
+ vuint32_t CFS44:1; /* CF 44 status */
+ vuint32_t CFS43:1; /* CF 43 status */
+ vuint32_t CFS42:1; /* CF 42 status */
+ vuint32_t CFS41:1; /* CF 41 status */
+ vuint32_t CFS40:1; /* CF 40 status */
+ vuint32_t CFS39:1; /* CF 39 status */
+ vuint32_t CFS38:1; /* CF 38 status */
+ vuint32_t CFS37:1; /* CF 37 status */
+ vuint32_t CFS36:1; /* CF 36 status */
+ vuint32_t CFS35:1; /* CF 35 status */
+ vuint32_t CFS34:1; /* CF 34 status */
+ vuint32_t CFS33:1; /* CF 33 status */
+ vuint32_t CFS32:1; /* CF 32 status */
+ } B;
+ } FCCU_CFS1_32B_tag;
+
+ typedef union { /* FCCU CF Status Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFS95:1; /* CF 95 status */
+ vuint32_t CFS94:1; /* CF 94 status */
+ vuint32_t CFS93:1; /* CF 93 status */
+ vuint32_t CFS92:1; /* CF 92 status */
+ vuint32_t CFS91:1; /* CF 91 status */
+ vuint32_t CFS90:1; /* CF 90 status */
+ vuint32_t CFS89:1; /* CF 89 status */
+ vuint32_t CFS88:1; /* CF 88 status */
+ vuint32_t CFS87:1; /* CF 87 status */
+ vuint32_t CFS86:1; /* CF 86 status */
+ vuint32_t CFS85:1; /* CF 85 status */
+ vuint32_t CFS84:1; /* CF 84 status */
+ vuint32_t CFS83:1; /* CF 83 status */
+ vuint32_t CFS82:1; /* CF 82 status */
+ vuint32_t CFS81:1; /* CF 81 status */
+ vuint32_t CFS80:1; /* CF 80 status */
+ vuint32_t CFS79:1; /* CF 79 status */
+ vuint32_t CFS78:1; /* CF 78 status */
+ vuint32_t CFS77:1; /* CF 77 status */
+ vuint32_t CFS76:1; /* CF 76 status */
+ vuint32_t CFS75:1; /* CF 75 status */
+ vuint32_t CFS74:1; /* CF 74 status */
+ vuint32_t CFS73:1; /* CF 73 status */
+ vuint32_t CFS72:1; /* CF 72 status */
+ vuint32_t CFS71:1; /* CF 71 status */
+ vuint32_t CFS70:1; /* CF 70 status */
+ vuint32_t CFS69:1; /* CF 69 status */
+ vuint32_t CFS68:1; /* CF 68 status */
+ vuint32_t CFS67:1; /* CF 67 status */
+ vuint32_t CFS66:1; /* CF 66 status */
+ vuint32_t CFS65:1; /* CF 65 status */
+ vuint32_t CFS64:1; /* CF 64 status */
+ } B;
+ } FCCU_CFS2_32B_tag;
+
+ typedef union { /* FCCU CF Status Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t CFS127:1; /* CF 127 status */
+ vuint32_t CFS126:1; /* CF 126 status */
+ vuint32_t CFS125:1; /* CF 125 status */
+ vuint32_t CFS124:1; /* CF 124 status */
+ vuint32_t CFS123:1; /* CF 123 status */
+ vuint32_t CFS122:1; /* CF 122 status */
+ vuint32_t CFS121:1; /* CF 121 status */
+ vuint32_t CFS120:1; /* CF 120 status */
+ vuint32_t CFS119:1; /* CF 119 status */
+ vuint32_t CFS118:1; /* CF 118 status */
+ vuint32_t CFS117:1; /* CF 117 status */
+ vuint32_t CFS116:1; /* CF 116 status */
+ vuint32_t CFS115:1; /* CF 115 status */
+ vuint32_t CFS114:1; /* CF 114 status */
+ vuint32_t CFS113:1; /* CF 113 status */
+ vuint32_t CFS112:1; /* CF 112 status */
+ vuint32_t CFS111:1; /* CF 111 status */
+ vuint32_t CFS110:1; /* CF 110 status */
+ vuint32_t CFS109:1; /* CF 109 status */
+ vuint32_t CFS108:1; /* CF 108 status */
+ vuint32_t CFS107:1; /* CF 107 status */
+ vuint32_t CFS106:1; /* CF 106 status */
+ vuint32_t CFS105:1; /* CF 105 status */
+ vuint32_t CFS104:1; /* CF 104 status */
+ vuint32_t CFS103:1; /* CF 103 status */
+ vuint32_t CFS102:1; /* CF 102 status */
+ vuint32_t CFS101:1; /* CF 101 status */
+ vuint32_t CFS100:1; /* CF 100 status */
+ vuint32_t CFS99:1; /* CF 99 status */
+ vuint32_t CFS98:1; /* CF 98 status */
+ vuint32_t CFS97:1; /* CF 97 status */
+ vuint32_t CFS96:1; /* CF 96 status */
+ } B;
+ } FCCU_CFS3_32B_tag;
+
+ typedef union { /* FCCU_CFK - FCCU CF Key Register */
+ vuint32_t R;
+ } FCCU_CFK_32B_tag;
+
+ typedef union { /* FCCU NCF Status Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFS31:1; /* NCF 31 status */
+ vuint32_t NCFS30:1; /* NCF 30 status */
+ vuint32_t NCFS29:1; /* NCF 29 status */
+ vuint32_t NCFS28:1; /* NCF 28 status */
+ vuint32_t NCFS27:1; /* NCF 27 status */
+ vuint32_t NCFS26:1; /* NCF 26 status */
+ vuint32_t NCFS25:1; /* NCF 25 status */
+ vuint32_t NCFS24:1; /* NCF 24 status */
+ vuint32_t NCFS23:1; /* NCF 23 status */
+ vuint32_t NCFS22:1; /* NCF 22 status */
+ vuint32_t NCFS21:1; /* NCF 21 status */
+ vuint32_t NCFS20:1; /* NCF 20 status */
+ vuint32_t NCFS19:1; /* NCF 19 status */
+ vuint32_t NCFS18:1; /* NCF 18 status */
+ vuint32_t NCFS17:1; /* NCF 17 status */
+ vuint32_t NCFS16:1; /* NCF 16 status */
+ vuint32_t NCFS15:1; /* NCF 15 status */
+ vuint32_t NCFS14:1; /* NCF 14 status */
+ vuint32_t NCFS13:1; /* NCF 13 status */
+ vuint32_t NCFS12:1; /* NCF 12 status */
+ vuint32_t NCFS11:1; /* NCF 11 status */
+ vuint32_t NCFS10:1; /* NCF 10 status */
+ vuint32_t NCFS9:1; /* NCF 9 status */
+ vuint32_t NCFS8:1; /* NCF 8 status */
+ vuint32_t NCFS7:1; /* NCF 7 status */
+ vuint32_t NCFS6:1; /* NCF 6 status */
+ vuint32_t NCFS5:1; /* NCF 5 status */
+ vuint32_t NCFS4:1; /* NCF 4 status */
+ vuint32_t NCFS3:1; /* NCF 3 status */
+ vuint32_t NCFS2:1; /* NCF 2 status */
+ vuint32_t NCFS1:1; /* NCF 1 status */
+ vuint32_t NCFS0:1; /* NCF 0 status */
+ } B;
+ } FCCU_NCFS0_32B_tag;
+
+ typedef union { /* FCCU NCF Status Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFS63:1; /* NCF 63 status */
+ vuint32_t NCFS62:1; /* NCF 62 status */
+ vuint32_t NCFS61:1; /* NCF 61 status */
+ vuint32_t NCFS60:1; /* NCF 60 status */
+ vuint32_t NCFS59:1; /* NCF 59 status */
+ vuint32_t NCFS58:1; /* NCF 58 status */
+ vuint32_t NCFS57:1; /* NCF 57 status */
+ vuint32_t NCFS56:1; /* NCF 56 status */
+ vuint32_t NCFS55:1; /* NCF 55 status */
+ vuint32_t NCFS54:1; /* NCF 54 status */
+ vuint32_t NCFS53:1; /* NCF 53 status */
+ vuint32_t NCFS52:1; /* NCF 52 status */
+ vuint32_t NCFS51:1; /* NCF 51 status */
+ vuint32_t NCFS50:1; /* NCF 50 status */
+ vuint32_t NCFS49:1; /* NCF 49 status */
+ vuint32_t NCFS48:1; /* NCF 48 status */
+ vuint32_t NCFS47:1; /* NCF 47 status */
+ vuint32_t NCFS46:1; /* NCF 46 status */
+ vuint32_t NCFS45:1; /* NCF 45 status */
+ vuint32_t NCFS44:1; /* NCF 44 status */
+ vuint32_t NCFS43:1; /* NCF 43 status */
+ vuint32_t NCFS42:1; /* NCF 42 status */
+ vuint32_t NCFS41:1; /* NCF 41 status */
+ vuint32_t NCFS40:1; /* NCF 40 status */
+ vuint32_t NCFS39:1; /* NCF 39 status */
+ vuint32_t NCFS38:1; /* NCF 38 status */
+ vuint32_t NCFS37:1; /* NCF 37 status */
+ vuint32_t NCFS36:1; /* NCF 36 status */
+ vuint32_t NCFS35:1; /* NCF 35 status */
+ vuint32_t NCFS34:1; /* NCF 34 status */
+ vuint32_t NCFS33:1; /* NCF 33 status */
+ vuint32_t NCFS32:1; /* NCF 32 status */
+ } B;
+ } FCCU_NCFS1_32B_tag;
+
+ typedef union { /* FCCU NCF Status Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFS95:1; /* NCF 95 status */
+ vuint32_t NCFS94:1; /* NCF 94 status */
+ vuint32_t NCFS93:1; /* NCF 93 status */
+ vuint32_t NCFS92:1; /* NCF 92 status */
+ vuint32_t NCFS91:1; /* NCF 91 status */
+ vuint32_t NCFS90:1; /* NCF 90 status */
+ vuint32_t NCFS89:1; /* NCF 89 status */
+ vuint32_t NCFS88:1; /* NCF 88 status */
+ vuint32_t NCFS87:1; /* NCF 87 status */
+ vuint32_t NCFS86:1; /* NCF 86 status */
+ vuint32_t NCFS85:1; /* NCF 85 status */
+ vuint32_t NCFS84:1; /* NCF 84 status */
+ vuint32_t NCFS83:1; /* NCF 83 status */
+ vuint32_t NCFS82:1; /* NCF 82 status */
+ vuint32_t NCFS81:1; /* NCF 81 status */
+ vuint32_t NCFS80:1; /* NCF 80 status */
+ vuint32_t NCFS79:1; /* NCF 79 status */
+ vuint32_t NCFS78:1; /* NCF 78 status */
+ vuint32_t NCFS77:1; /* NCF 77 status */
+ vuint32_t NCFS76:1; /* NCF 76 status */
+ vuint32_t NCFS75:1; /* NCF 75 status */
+ vuint32_t NCFS74:1; /* NCF 74 status */
+ vuint32_t NCFS73:1; /* NCF 73 status */
+ vuint32_t NCFS72:1; /* NCF 72 status */
+ vuint32_t NCFS71:1; /* NCF 71 status */
+ vuint32_t NCFS70:1; /* NCF 70 status */
+ vuint32_t NCFS69:1; /* NCF 69 status */
+ vuint32_t NCFS68:1; /* NCF 68 status */
+ vuint32_t NCFS67:1; /* NCF 67 status */
+ vuint32_t NCFS66:1; /* NCF 66 status */
+ vuint32_t NCFS65:1; /* NCF 65 status */
+ vuint32_t NCFS64:1; /* NCF 64 status */
+ } B;
+ } FCCU_NCFS2_32B_tag;
+
+ typedef union { /* FCCU NCF Status Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFS127:1; /* NCF 127 status */
+ vuint32_t NCFS126:1; /* NCF 126 status */
+ vuint32_t NCFS125:1; /* NCF 125 status */
+ vuint32_t NCFS124:1; /* NCF 124 status */
+ vuint32_t NCFS123:1; /* NCF 123 status */
+ vuint32_t NCFS122:1; /* NCF 122 status */
+ vuint32_t NCFS121:1; /* NCF 121 status */
+ vuint32_t NCFS120:1; /* NCF 120 status */
+ vuint32_t NCFS119:1; /* NCF 119 status */
+ vuint32_t NCFS118:1; /* NCF 118 status */
+ vuint32_t NCFS117:1; /* NCF 117 status */
+ vuint32_t NCFS116:1; /* NCF 116 status */
+ vuint32_t NCFS115:1; /* NCF 115 status */
+ vuint32_t NCFS114:1; /* NCF 114 status */
+ vuint32_t NCFS113:1; /* NCF 113 status */
+ vuint32_t NCFS112:1; /* NCF 112 status */
+ vuint32_t NCFS111:1; /* NCF 111 status */
+ vuint32_t NCFS110:1; /* NCF 110 status */
+ vuint32_t NCFS109:1; /* NCF 109 status */
+ vuint32_t NCFS108:1; /* NCF 108 status */
+ vuint32_t NCFS107:1; /* NCF 107 status */
+ vuint32_t NCFS106:1; /* NCF 106 status */
+ vuint32_t NCFS105:1; /* NCF 105 status */
+ vuint32_t NCFS104:1; /* NCF 104 status */
+ vuint32_t NCFS103:1; /* NCF 103 status */
+ vuint32_t NCFS102:1; /* NCF 102 status */
+ vuint32_t NCFS101:1; /* NCF 101 status */
+ vuint32_t NCFS100:1; /* NCF 100 status */
+ vuint32_t NCFS99:1; /* NCF 99 status */
+ vuint32_t NCFS98:1; /* NCF 98 status */
+ vuint32_t NCFS97:1; /* NCF 97 status */
+ vuint32_t NCFS96:1; /* NCF 96 status */
+ } B;
+ } FCCU_NCFS3_32B_tag;
+
+ typedef union { /* FCCU_NCFK - FCCU NCF Key Register */
+ vuint32_t R;
+ } FCCU_NCFK_32B_tag;
+
+ typedef union { /* FCCU NCF Enable Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFE31:1; /* NCF 31 enable */
+ vuint32_t NCFE30:1; /* NCF 30 enable */
+ vuint32_t NCFE29:1; /* NCF 29 enable */
+ vuint32_t NCFE28:1; /* NCF 28 enable */
+ vuint32_t NCFE27:1; /* NCF 27 enable */
+ vuint32_t NCFE26:1; /* NCF 26 enable */
+ vuint32_t NCFE25:1; /* NCF 25 enable */
+ vuint32_t NCFE24:1; /* NCF 24 enable */
+ vuint32_t NCFE23:1; /* NCF 23 enable */
+ vuint32_t NCFE22:1; /* NCF 22 enable */
+ vuint32_t NCFE21:1; /* NCF 21 enable */
+ vuint32_t NCFE20:1; /* NCF 20 enable */
+ vuint32_t NCFE19:1; /* NCF 19 enable */
+ vuint32_t NCFE18:1; /* NCF 18 enable */
+ vuint32_t NCFE17:1; /* NCF 17 enable */
+ vuint32_t NCFE16:1; /* NCF 16 enable */
+ vuint32_t NCFE15:1; /* NCF 15 enable */
+ vuint32_t NCFE14:1; /* NCF 14 enable */
+ vuint32_t NCFE13:1; /* NCF 13 enable */
+ vuint32_t NCFE12:1; /* NCF 12 enable */
+ vuint32_t NCFE11:1; /* NCF 11 enable */
+ vuint32_t NCFE10:1; /* NCF 10 enable */
+ vuint32_t NCFE9:1; /* NCF 9 enable */
+ vuint32_t NCFE8:1; /* NCF 8 enable */
+ vuint32_t NCFE7:1; /* NCF 7 enable */
+ vuint32_t NCFE6:1; /* NCF 6 enable */
+ vuint32_t NCFE5:1; /* NCF 5 enable */
+ vuint32_t NCFE4:1; /* NCF 4 enable */
+ vuint32_t NCFE3:1; /* NCF 3 enable */
+ vuint32_t NCFE2:1; /* NCF 2 enable */
+ vuint32_t NCFE1:1; /* NCF 1 enable */
+ vuint32_t NCFE0:1; /* NCF 0 enable */
+ } B;
+ } FCCU_NCFE0_32B_tag;
+
+ typedef union { /* FCCU NCF Enable Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFE63:1; /* NCF 63 enable */
+ vuint32_t NCFE62:1; /* NCF 62 enable */
+ vuint32_t NCFE61:1; /* NCF 61 enable */
+ vuint32_t NCFE60:1; /* NCF 60 enable */
+ vuint32_t NCFE59:1; /* NCF 59 enable */
+ vuint32_t NCFE58:1; /* NCF 58 enable */
+ vuint32_t NCFE57:1; /* NCF 57 enable */
+ vuint32_t NCFE56:1; /* NCF 56 enable */
+ vuint32_t NCFE55:1; /* NCF 55 enable */
+ vuint32_t NCFE54:1; /* NCF 54 enable */
+ vuint32_t NCFE53:1; /* NCF 53 enable */
+ vuint32_t NCFE52:1; /* NCF 52 enable */
+ vuint32_t NCFE51:1; /* NCF 51 enable */
+ vuint32_t NCFE50:1; /* NCF 50 enable */
+ vuint32_t NCFE49:1; /* NCF 49 enable */
+ vuint32_t NCFE48:1; /* NCF 48 enable */
+ vuint32_t NCFE47:1; /* NCF 47 enable */
+ vuint32_t NCFE46:1; /* NCF 46 enable */
+ vuint32_t NCFE45:1; /* NCF 45 enable */
+ vuint32_t NCFE44:1; /* NCF 44 enable */
+ vuint32_t NCFE43:1; /* NCF 43 enable */
+ vuint32_t NCFE42:1; /* NCF 42 enable */
+ vuint32_t NCFE41:1; /* NCF 41 enable */
+ vuint32_t NCFE40:1; /* NCF 40 enable */
+ vuint32_t NCFE39:1; /* NCF 39 enable */
+ vuint32_t NCFE38:1; /* NCF 38 enable */
+ vuint32_t NCFE37:1; /* NCF 37 enable */
+ vuint32_t NCFE36:1; /* NCF 36 enable */
+ vuint32_t NCFE35:1; /* NCF 35 enable */
+ vuint32_t NCFE34:1; /* NCF 34 enable */
+ vuint32_t NCFE33:1; /* NCF 33 enable */
+ vuint32_t NCFE32:1; /* NCF 32 enable */
+ } B;
+ } FCCU_NCFE1_32B_tag;
+
+ typedef union { /* FCCU NCF Enable Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFE95:1; /* NCF 95 enable */
+ vuint32_t NCFE94:1; /* NCF 94 enable */
+ vuint32_t NCFE93:1; /* NCF 93 enable */
+ vuint32_t NCFE92:1; /* NCF 92 enable */
+ vuint32_t NCFE91:1; /* NCF 91 enable */
+ vuint32_t NCFE90:1; /* NCF 90 enable */
+ vuint32_t NCFE89:1; /* NCF 89 enable */
+ vuint32_t NCFE88:1; /* NCF 88 enable */
+ vuint32_t NCFE87:1; /* NCF 87 enable */
+ vuint32_t NCFE86:1; /* NCF 86 enable */
+ vuint32_t NCFE85:1; /* NCF 85 enable */
+ vuint32_t NCFE84:1; /* NCF 84 enable */
+ vuint32_t NCFE83:1; /* NCF 83 enable */
+ vuint32_t NCFE82:1; /* NCF 82 enable */
+ vuint32_t NCFE81:1; /* NCF 81 enable */
+ vuint32_t NCFE80:1; /* NCF 80 enable */
+ vuint32_t NCFE79:1; /* NCF 79 enable */
+ vuint32_t NCFE78:1; /* NCF 78 enable */
+ vuint32_t NCFE77:1; /* NCF 77 enable */
+ vuint32_t NCFE76:1; /* NCF 76 enable */
+ vuint32_t NCFE75:1; /* NCF 75 enable */
+ vuint32_t NCFE74:1; /* NCF 74 enable */
+ vuint32_t NCFE73:1; /* NCF 73 enable */
+ vuint32_t NCFE72:1; /* NCF 72 enable */
+ vuint32_t NCFE71:1; /* NCF 71 enable */
+ vuint32_t NCFE70:1; /* NCF 70 enable */
+ vuint32_t NCFE69:1; /* NCF 69 enable */
+ vuint32_t NCFE68:1; /* NCF 68 enable */
+ vuint32_t NCFE67:1; /* NCF 67 enable */
+ vuint32_t NCFE66:1; /* NCF 66 enable */
+ vuint32_t NCFE65:1; /* NCF 65 enable */
+ vuint32_t NCFE64:1; /* NCF 64 enable */
+ } B;
+ } FCCU_NCFE2_32B_tag;
+
+ typedef union { /* FCCU NCF Enable Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFE127:1; /* NCF 127 enable */
+ vuint32_t NCFE126:1; /* NCF 126 enable */
+ vuint32_t NCFE125:1; /* NCF 125 enable */
+ vuint32_t NCFE124:1; /* NCF 124 enable */
+ vuint32_t NCFE123:1; /* NCF 123 enable */
+ vuint32_t NCFE122:1; /* NCF 122 enable */
+ vuint32_t NCFE121:1; /* NCF 121 enable */
+ vuint32_t NCFE120:1; /* NCF 120 enable */
+ vuint32_t NCFE119:1; /* NCF 119 enable */
+ vuint32_t NCFE118:1; /* NCF 118 enable */
+ vuint32_t NCFE117:1; /* NCF 117 enable */
+ vuint32_t NCFE116:1; /* NCF 116 enable */
+ vuint32_t NCFE115:1; /* NCF 115 enable */
+ vuint32_t NCFE114:1; /* NCF 114 enable */
+ vuint32_t NCFE113:1; /* NCF 113 enable */
+ vuint32_t NCFE112:1; /* NCF 112 enable */
+ vuint32_t NCFE111:1; /* NCF 111 enable */
+ vuint32_t NCFE110:1; /* NCF 110 enable */
+ vuint32_t NCFE109:1; /* NCF 109 enable */
+ vuint32_t NCFE108:1; /* NCF 108 enable */
+ vuint32_t NCFE107:1; /* NCF 107 enable */
+ vuint32_t NCFE106:1; /* NCF 106 enable */
+ vuint32_t NCFE105:1; /* NCF 105 enable */
+ vuint32_t NCFE104:1; /* NCF 104 enable */
+ vuint32_t NCFE103:1; /* NCF 103 enable */
+ vuint32_t NCFE102:1; /* NCF 102 enable */
+ vuint32_t NCFE101:1; /* NCF 101 enable */
+ vuint32_t NCFE100:1; /* NCF 100 enable */
+ vuint32_t NCFE99:1; /* NCF 99 enable */
+ vuint32_t NCFE98:1; /* NCF 98 enable */
+ vuint32_t NCFE97:1; /* NCF 97 enable */
+ vuint32_t NCFE96:1; /* NCF 96 enable */
+ } B;
+ } FCCU_NCFE3_32B_tag;
+
+ typedef union { /* FCCU NCF Time-out Enable Register 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFTOE31:1; /* NCF 31 time-out enable */
+ vuint32_t NCFTOE30:1; /* NCF 30 time-out enable */
+ vuint32_t NCFTOE29:1; /* NCF 29 time-out enable */
+ vuint32_t NCFTOE28:1; /* NCF 28 time-out enable */
+ vuint32_t NCFTOE27:1; /* NCF 27 time-out enable */
+ vuint32_t NCFTOE26:1; /* NCF 26 time-out enable */
+ vuint32_t NCFTOE25:1; /* NCF 25 time-out enable */
+ vuint32_t NCFTOE24:1; /* NCF 24 time-out enable */
+ vuint32_t NCFTOE23:1; /* NCF 23 time-out enable */
+ vuint32_t NCFTOE22:1; /* NCF 22 time-out enable */
+ vuint32_t NCFTOE21:1; /* NCF 21 time-out enable */
+ vuint32_t NCFTOE20:1; /* NCF 20 time-out enable */
+ vuint32_t NCFTOE19:1; /* NCF 19 time-out enable */
+ vuint32_t NCFTOE18:1; /* NCF 18 time-out enable */
+ vuint32_t NCFTOE17:1; /* NCF 17 time-out enable */
+ vuint32_t NCFTOE16:1; /* NCF 16 time-out enable */
+ vuint32_t NCFTOE15:1; /* NCF 15 time-out enable */
+ vuint32_t NCFTOE14:1; /* NCF 14 time-out enable */
+ vuint32_t NCFTOE13:1; /* NCF 13 time-out enable */
+ vuint32_t NCFTOE12:1; /* NCF 12 time-out enable */
+ vuint32_t NCFTOE11:1; /* NCF 11 time-out enable */
+ vuint32_t NCFTOE10:1; /* NCF 10 time-out enable */
+ vuint32_t NCFTOE9:1; /* NCF 9 time-out enable */
+ vuint32_t NCFTOE8:1; /* NCF 8 time-out enable */
+ vuint32_t NCFTOE7:1; /* NCF 7 time-out enable */
+ vuint32_t NCFTOE6:1; /* NCF 6 time-out enable */
+ vuint32_t NCFTOE5:1; /* NCF 5 time-out enable */
+ vuint32_t NCFTOE4:1; /* NCF 4 time-out enable */
+ vuint32_t NCFTOE3:1; /* NCF 3 time-out enable */
+ vuint32_t NCFTOE2:1; /* NCF 2 time-out enable */
+ vuint32_t NCFTOE1:1; /* NCF 1 time-out enable */
+ vuint32_t NCFTOE0:1; /* NCF 0 time-out enable */
+ } B;
+ } FCCU_NCF_TOE0_32B_tag;
+
+ typedef union { /* FCCU NCF Time-out Enable Register 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFTOE63:1; /* NCF 63 time-out enable */
+ vuint32_t NCFTOE62:1; /* NCF 62 time-out enable */
+ vuint32_t NCFTOE61:1; /* NCF 61 time-out enable */
+ vuint32_t NCFTOE60:1; /* NCF 60 time-out enable */
+ vuint32_t NCFTOE59:1; /* NCF 59 time-out enable */
+ vuint32_t NCFTOE58:1; /* NCF 58 time-out enable */
+ vuint32_t NCFTOE57:1; /* NCF 57 time-out enable */
+ vuint32_t NCFTOE56:1; /* NCF 56 time-out enable */
+ vuint32_t NCFTOE55:1; /* NCF 55 time-out enable */
+ vuint32_t NCFTOE54:1; /* NCF 54 time-out enable */
+ vuint32_t NCFTOE53:1; /* NCF 53 time-out enable */
+ vuint32_t NCFTOE52:1; /* NCF 52 time-out enable */
+ vuint32_t NCFTOE51:1; /* NCF 51 time-out enable */
+ vuint32_t NCFTOE50:1; /* NCF 50 time-out enable */
+ vuint32_t NCFTOE49:1; /* NCF 49 time-out enable */
+ vuint32_t NCFTOE48:1; /* NCF 48 time-out enable */
+ vuint32_t NCFTOE47:1; /* NCF 47 time-out enable */
+ vuint32_t NCFTOE46:1; /* NCF 46 time-out enable */
+ vuint32_t NCFTOE45:1; /* NCF 45 time-out enable */
+ vuint32_t NCFTOE44:1; /* NCF 44 time-out enable */
+ vuint32_t NCFTOE43:1; /* NCF 43 time-out enable */
+ vuint32_t NCFTOE42:1; /* NCF 42 time-out enable */
+ vuint32_t NCFTOE41:1; /* NCF 41 time-out enable */
+ vuint32_t NCFTOE40:1; /* NCF 40 time-out enable */
+ vuint32_t NCFTOE39:1; /* NCF 39 time-out enable */
+ vuint32_t NCFTOE38:1; /* NCF 38 time-out enable */
+ vuint32_t NCFTOE37:1; /* NCF 37 time-out enable */
+ vuint32_t NCFTOE36:1; /* NCF 36 time-out enable */
+ vuint32_t NCFTOE35:1; /* NCF 35 time-out enable */
+ vuint32_t NCFTOE34:1; /* NCF 34 time-out enable */
+ vuint32_t NCFTOE33:1; /* NCF 33 time-out enable */
+ vuint32_t NCFTOE32:1; /* NCF 32 time-out enable */
+ } B;
+ } FCCU_NCF_TOE1_32B_tag;
+
+ typedef union { /* FCCU NCF Time-out Enable Register 2 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFTOE95:1; /* NCF 95 time-out enable */
+ vuint32_t NCFTOE94:1; /* NCF 94 time-out enable */
+ vuint32_t NCFTOE93:1; /* NCF 93 time-out enable */
+ vuint32_t NCFTOE92:1; /* NCF 92 time-out enable */
+ vuint32_t NCFTOE91:1; /* NCF 91 time-out enable */
+ vuint32_t NCFTOE90:1; /* NCF 90 time-out enable */
+ vuint32_t NCFTOE89:1; /* NCF 89 time-out enable */
+ vuint32_t NCFTOE88:1; /* NCF 88 time-out enable */
+ vuint32_t NCFTOE87:1; /* NCF 87 time-out enable */
+ vuint32_t NCFTOE86:1; /* NCF 86 time-out enable */
+ vuint32_t NCFTOE85:1; /* NCF 85 time-out enable */
+ vuint32_t NCFTOE84:1; /* NCF 84 time-out enable */
+ vuint32_t NCFTOE83:1; /* NCF 83 time-out enable */
+ vuint32_t NCFTOE82:1; /* NCF 82 time-out enable */
+ vuint32_t NCFTOE81:1; /* NCF 81 time-out enable */
+ vuint32_t NCFTOE80:1; /* NCF 80 time-out enable */
+ vuint32_t NCFTOE79:1; /* NCF 79 time-out enable */
+ vuint32_t NCFTOE78:1; /* NCF 78 time-out enable */
+ vuint32_t NCFTOE77:1; /* NCF 77 time-out enable */
+ vuint32_t NCFTOE76:1; /* NCF 76 time-out enable */
+ vuint32_t NCFTOE75:1; /* NCF 75 time-out enable */
+ vuint32_t NCFTOE74:1; /* NCF 74 time-out enable */
+ vuint32_t NCFTOE73:1; /* NCF 73 time-out enable */
+ vuint32_t NCFTOE72:1; /* NCF 72 time-out enable */
+ vuint32_t NCFTOE71:1; /* NCF 71 time-out enable */
+ vuint32_t NCFTOE70:1; /* NCF 70 time-out enable */
+ vuint32_t NCFTOE69:1; /* NCF 69 time-out enable */
+ vuint32_t NCFTOE68:1; /* NCF 68 time-out enable */
+ vuint32_t NCFTOE67:1; /* NCF 67 time-out enable */
+ vuint32_t NCFTOE66:1; /* NCF 66 time-out enable */
+ vuint32_t NCFTOE65:1; /* NCF 65 time-out enable */
+ vuint32_t NCFTOE64:1; /* NCF 64 time-out enable */
+ } B;
+ } FCCU_NCF_TOE2_32B_tag;
+
+ typedef union { /* FCCU NCF Time-out Enable Register 3 */
+ vuint32_t R;
+ struct {
+ vuint32_t NCFTOE127:1; /* NCF 127 time-out enable */
+ vuint32_t NCFTOE126:1; /* NCF 126 time-out enable */
+ vuint32_t NCFTOE125:1; /* NCF 125 time-out enable */
+ vuint32_t NCFTOE124:1; /* NCF 124 time-out enable */
+ vuint32_t NCFTOE123:1; /* NCF 123 time-out enable */
+ vuint32_t NCFTOE122:1; /* NCF 122 time-out enable */
+ vuint32_t NCFTOE121:1; /* NCF 121 time-out enable */
+ vuint32_t NCFTOE120:1; /* NCF 120 time-out enable */
+ vuint32_t NCFTOE119:1; /* NCF 119 time-out enable */
+ vuint32_t NCFTOE118:1; /* NCF 118 time-out enable */
+ vuint32_t NCFTOE117:1; /* NCF 117 time-out enable */
+ vuint32_t NCFTOE116:1; /* NCF 116 time-out enable */
+ vuint32_t NCFTOE115:1; /* NCF 115 time-out enable */
+ vuint32_t NCFTOE114:1; /* NCF 114 time-out enable */
+ vuint32_t NCFTOE113:1; /* NCF 113 time-out enable */
+ vuint32_t NCFTOE112:1; /* NCF 112 time-out enable */
+ vuint32_t NCFTOE111:1; /* NCF 111 time-out enable */
+ vuint32_t NCFTOE110:1; /* NCF 110 time-out enable */
+ vuint32_t NCFTOE109:1; /* NCF 109 time-out enable */
+ vuint32_t NCFTOE108:1; /* NCF 108 time-out enable */
+ vuint32_t NCFTOE107:1; /* NCF 107 time-out enable */
+ vuint32_t NCFTOE106:1; /* NCF 106 time-out enable */
+ vuint32_t NCFTOE105:1; /* NCF 105 time-out enable */
+ vuint32_t NCFTOE104:1; /* NCF 104 time-out enable */
+ vuint32_t NCFTOE103:1; /* NCF 103 time-out enable */
+ vuint32_t NCFTOE102:1; /* NCF 102 time-out enable */
+ vuint32_t NCFTOE101:1; /* NCF 101 time-out enable */
+ vuint32_t NCFTOE100:1; /* NCF 100 time-out enable */
+ vuint32_t NCFTOE99:1; /* NCF 99 time-out enable */
+ vuint32_t NCFTOE98:1; /* NCF 98 time-out enable */
+ vuint32_t NCFTOE97:1; /* NCF 97 time-out enable */
+ vuint32_t NCFTOE96:1; /* NCF 96 time-out enable */
+ } B;
+ } FCCU_NCF_TOE3_32B_tag;
+
+ typedef union { /* FCCU_NCF_TO - FCCU NCF Time-out Register */
+ vuint32_t R;
+ } FCCU_NCF_TO_32B_tag;
+
+ typedef union { /* FCCU_CFG_TO - FCCU CFG Timeout Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t TO:3; /* Configuration time-out */
+ } B;
+ } FCCU_CFG_TO_32B_tag;
+
+ typedef union { /* FCCU_EINOUT - FCCU IO Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:26;
+ vuint32_t EIN1:1; /* Error input 1 */
+ vuint32_t EIN0:1; /* Error input 0 */
+ vuint32_t:2;
+ vuint32_t EOUT1:1; /* Error out 1 */
+ vuint32_t EOUT0:1; /* Error out 0 */
+ } B;
+ } FCCU_EINOUT_32B_tag;
+
+ typedef union { /* FCCU_STAT - FCCU Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t STATUS:3; /* FCCU status */
+ } B;
+ } FCCU_STAT_32B_tag;
+
+ typedef union { /* FCCU_NAFS - FCCU NA Freeze Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t N2AFSTATUS:8; /* Normal to Alarm Frozen Status */
+ } B;
+ } FCCU_NAFS_32B_tag;
+
+ typedef union { /* FCCU_AFFS - FCCU AF Freeze Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t AFFS_SRC:2; /* Fault source */
+ vuint32_t A2AFSTATUS:8; /* Alarm to Fault Frozen Status */
+ } B;
+ } FCCU_AFFS_32B_tag;
+
+ typedef union { /* FCCU_NFFS - FCCU NF Freeze Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:22;
+ vuint32_t NFFS_SRC:2; /* Fault source */
+ vuint32_t NFFS_NFFS:8; /* Normal to Fault Frozen Status */
+ } B;
+ } FCCU_NFFS_32B_tag;
+
+ typedef union { /* FCCU_FAFS - FCCU FA Freeze Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:24;
+ vuint32_t FAFS_FAFS:8; /* Fault to Normal Frozen Status */
+ } B;
+ } FCCU_FAFS_32B_tag;
+
+ typedef union { /* FCCU_SCFS - FCCU SC Freeze Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:30;
+ vuint32_t RCCS1:1; /* RCC1 Status */
+ vuint32_t RCCS0:1; /* RCC0 Status */
+ } B;
+ } FCCU_SCFS_32B_tag;
+
+ typedef union { /* FCCU_CFF - FCCU CF Fake Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t FCFC:7; /* Fake critical fault code */
+ } B;
+ } FCCU_CFF_32B_tag;
+
+ typedef union { /* FCCU_NCFF - FCCU NCF Fake Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:25;
+ vuint32_t FNCFC:7; /* Fake non-critical fault code */
+ } B;
+ } FCCU_NCFF_32B_tag;
+
+ typedef union { /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t NMI_STAT:1; /* NMI Interrupt Status */
+ vuint32_t ALRM_STAT:1; /* Alarm Interrupt Status */
+ vuint32_t CFG_TO_STAT:1; /* Configuration Time-out Status */
+ } B;
+ } FCCU_IRQ_STAT_32B_tag;
+
+ typedef union { /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CFG_TO_IEN:1; /* Configuration Time-out Interrupt Enable */
+ } B;
+ } FCCU_IRQ_EN_32B_tag;
+
+ typedef union { /* FCCU_XTMR - FCCU XTMR Register */
+ vuint32_t R;
+ struct {
+ vuint32_t XTMR_XTMR:32; /* Alarm/Watchdog/safe request timer */
+ } B;
+ } FCCU_XTMR_32B_tag;
+
+ typedef union { /* FCCU_MCS - FCCU MCS Register */
+ vuint32_t R;
+ struct {
+ vuint32_t VL3:1; /* Valid */
+ vuint32_t FS3:1; /* Fault Status */
+ vuint32_t:2;
+ vuint32_t MCS3:4; /* Magic Carpet oldest state */
+ vuint32_t VL2:1; /* Valid */
+ vuint32_t FS2:1; /* Fault Status */
+ vuint32_t:2;
+ vuint32_t MCS2:4; /* Magic Carpet previous-previous state */
+ vuint32_t VL1:1; /* Valid */
+ vuint32_t FS1:1; /* Fault Status */
+ vuint32_t:2;
+ vuint32_t MCS1:4; /* Magic Carpet previous state */
+ vuint32_t VL0:1; /* Valid */
+ vuint32_t FS0:1; /* Fault Status */
+ vuint32_t:2;
+ vuint32_t MCS0:4; /* Magic Carpet latest state */
+ } B;
+ } FCCU_MCS_32B_tag;
+
+
+ /* Register layout for generated register(s) CF_CFG... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_CF_CFG_32B_tag;
+
+
+ /* Register layout for generated register(s) NCF_CFG... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_NCF_CFG_32B_tag;
+
+
+ /* Register layout for generated register(s) CFS_CFG... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_CFS_CFG_32B_tag;
+
+
+ /* Register layout for generated register(s) NCFS_CFG... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_NCFS_CFG_32B_tag;
+
+
+ /* Register layout for generated register(s) CFS... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_CFS_32B_tag;
+
+
+ /* Register layout for generated register(s) NCFS... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_NCFS_32B_tag;
+
+
+ /* Register layout for generated register(s) NCFE... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_NCFE_32B_tag;
+
+
+ /* Register layout for generated register(s) NCF_TOE... */
+
+ typedef union { /* */
+ vuint32_t R;
+ } FCCU_NCF_TOE_32B_tag;
+
+
+
+ typedef struct FCCU_struct_tag { /* start of FCCU_tag */
+ /* FCCU Control Register */
+ FCCU_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */
+ /* FCCU CTRL Key Register */
+ FCCU_CTRLK_32B_tag CTRLK; /* offset: 0x0004 size: 32 bit */
+ /* FCCU Configuration Register */
+ FCCU_CFG_32B_tag CFG; /* offset: 0x0008 size: 32 bit */
+ union {
+ FCCU_CF_CFG_32B_tag CF_CFG[4]; /* offset: 0x000C (0x0004 x 4) */
+
+ struct {
+ /* FCCU CF Configuration Register 0 */
+ FCCU_CF_CFG0_32B_tag CF_CFG0; /* offset: 0x000C size: 32 bit */
+ /* FCCU CF Configuration Register 1 */
+ FCCU_CF_CFG1_32B_tag CF_CFG1; /* offset: 0x0010 size: 32 bit */
+ /* FCCU CF Configuration Register 2 */
+ FCCU_CF_CFG2_32B_tag CF_CFG2; /* offset: 0x0014 size: 32 bit */
+ /* FCCU CF Configuration Register 3 */
+ FCCU_CF_CFG3_32B_tag CF_CFG3; /* offset: 0x0018 size: 32 bit */
+ };
+
+ };
+ union {
+ FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C (0x0004 x 4) */
+
+ struct {
+ /* FCCU NCF Configuration Register 0 */
+ FCCU_NCF_CFG0_32B_tag NCF_CFG0; /* offset: 0x001C size: 32 bit */
+ /* FCCU NCF Configuration Register 1 */
+ FCCU_NCF_CFG1_32B_tag NCF_CFG1; /* offset: 0x0020 size: 32 bit */
+ /* FCCU NCF Configuration Register 2 */
+ FCCU_NCF_CFG2_32B_tag NCF_CFG2; /* offset: 0x0024 size: 32 bit */
+ /* FCCU NCF Configuration Register 3 */
+ FCCU_NCF_CFG3_32B_tag NCF_CFG3; /* offset: 0x0028 size: 32 bit */
+ };
+
+ };
+ union {
+ FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C (0x0004 x 8) */
+
+ struct {
+ /* FCCU CFS Configuration Register 0 */
+ FCCU_CFS_CFG0_32B_tag CFS_CFG0; /* offset: 0x002C size: 32 bit */
+ /* FCCU CFS Configuration Register 1 */
+ FCCU_CFS_CFG1_32B_tag CFS_CFG1; /* offset: 0x0030 size: 32 bit */
+ /* FCCU CFS Configuration Register 2 */
+ FCCU_CFS_CFG2_32B_tag CFS_CFG2; /* offset: 0x0034 size: 32 bit */
+ /* FCCU CFS Configuration Register 3 */
+ FCCU_CFS_CFG3_32B_tag CFS_CFG3; /* offset: 0x0038 size: 32 bit */
+ /* FCCU CFS Configuration Register 4 */
+ FCCU_CFS_CFG4_32B_tag CFS_CFG4; /* offset: 0x003C size: 32 bit */
+ /* FCCU CFS Configuration Register 5 */
+ FCCU_CFS_CFG5_32B_tag CFS_CFG5; /* offset: 0x0040 size: 32 bit */
+ /* FCCU CFS Configuration Register 6 */
+ FCCU_CFS_CFG6_32B_tag CFS_CFG6; /* offset: 0x0044 size: 32 bit */
+ /* FCCU CFS Configuration Register 7 */
+ FCCU_CFS_CFG7_32B_tag CFS_CFG7; /* offset: 0x0048 size: 32 bit */
+ };
+
+ };
+ union {
+ FCCU_NCFS_CFG_32B_tag NCFS_CFG[8]; /* offset: 0x004C (0x0004 x 8) */
+
+ struct {
+ /* FCCU NCFS Configuration Register 0 */
+ FCCU_NCFS_CFG0_32B_tag NCFS_CFG0; /* offset: 0x004C size: 32 bit */
+ /* FCCU NCFS Configuration Register 1 */
+ FCCU_NCFS_CFG1_32B_tag NCFS_CFG1; /* offset: 0x0050 size: 32 bit */
+ /* FCCU NCFS Configuration Register 2 */
+ FCCU_NCFS_CFG2_32B_tag NCFS_CFG2; /* offset: 0x0054 size: 32 bit */
+ /* FCCU NCFS Configuration Register 3 */
+ FCCU_NCFS_CFG3_32B_tag NCFS_CFG3; /* offset: 0x0058 size: 32 bit */
+ /* FCCU NCFS Configuration Register 4 */
+ FCCU_NCFS_CFG4_32B_tag NCFS_CFG4; /* offset: 0x005C size: 32 bit */
+ /* FCCU NCFS Configuration Register 5 */
+ FCCU_NCFS_CFG5_32B_tag NCFS_CFG5; /* offset: 0x0060 size: 32 bit */
+ /* FCCU NCFS Configuration Register 6 */
+ FCCU_NCFS_CFG6_32B_tag NCFS_CFG6; /* offset: 0x0064 size: 32 bit */
+ /* FCCU NCFS Configuration Register 7 */
+ FCCU_NCFS_CFG7_32B_tag NCFS_CFG7; /* offset: 0x0068 size: 32 bit */
+ };
+
+ };
+ union {
+ FCCU_CFS_32B_tag CFS[4]; /* offset: 0x006C (0x0004 x 4) */
+
+ struct {
+ /* FCCU CF Status Register 0 */
+ FCCU_CFS0_32B_tag CFS0; /* offset: 0x006C size: 32 bit */
+ /* FCCU CF Status Register 1 */
+ FCCU_CFS1_32B_tag CFS1; /* offset: 0x0070 size: 32 bit */
+ /* FCCU CF Status Register 2 */
+ FCCU_CFS2_32B_tag CFS2; /* offset: 0x0074 size: 32 bit */
+ /* FCCU CF Status Register 3 */
+ FCCU_CFS3_32B_tag CFS3; /* offset: 0x0078 size: 32 bit */
+ };
+
+ };
+ /* FCCU_CFK - FCCU CF Key Register */
+ FCCU_CFK_32B_tag CFK; /* offset: 0x007C size: 32 bit */
+ union {
+ FCCU_NCFS_32B_tag NCFS[4]; /* offset: 0x0080 (0x0004 x 4) */
+
+ struct {
+ /* FCCU NCF Status Register 0 */
+ FCCU_NCFS0_32B_tag NCFS0; /* offset: 0x0080 size: 32 bit */
+ /* FCCU NCF Status Register 1 */
+ FCCU_NCFS1_32B_tag NCFS1; /* offset: 0x0084 size: 32 bit */
+ /* FCCU NCF Status Register 2 */
+ FCCU_NCFS2_32B_tag NCFS2; /* offset: 0x0088 size: 32 bit */
+ /* FCCU NCF Status Register 3 */
+ FCCU_NCFS3_32B_tag NCFS3; /* offset: 0x008C size: 32 bit */
+ };
+
+ };
+ /* FCCU_NCFK - FCCU NCF Key Register */
+ FCCU_NCFK_32B_tag NCFK; /* offset: 0x0090 size: 32 bit */
+ union {
+ FCCU_NCFE_32B_tag NCFE[4]; /* offset: 0x0094 (0x0004 x 4) */
+
+ struct {
+ /* FCCU NCF Enable Register 0 */
+ FCCU_NCFE0_32B_tag NCFE0; /* offset: 0x0094 size: 32 bit */
+ /* FCCU NCF Enable Register 1 */
+ FCCU_NCFE1_32B_tag NCFE1; /* offset: 0x0098 size: 32 bit */
+ /* FCCU NCF Enable Register 2 */
+ FCCU_NCFE2_32B_tag NCFE2; /* offset: 0x009C size: 32 bit */
+ /* FCCU NCF Enable Register 3 */
+ FCCU_NCFE3_32B_tag NCFE3; /* offset: 0x00A0 size: 32 bit */
+ };
+
+ };
+ union {
+ FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4 (0x0004 x 4) */
+
+ struct {
+ /* FCCU NCF Time-out Enable Register 0 */
+ FCCU_NCF_TOE0_32B_tag NCF_TOE0; /* offset: 0x00A4 size: 32 bit */
+ /* FCCU NCF Time-out Enable Register 1 */
+ FCCU_NCF_TOE1_32B_tag NCF_TOE1; /* offset: 0x00A8 size: 32 bit */
+ /* FCCU NCF Time-out Enable Register 2 */
+ FCCU_NCF_TOE2_32B_tag NCF_TOE2; /* offset: 0x00AC size: 32 bit */
+ /* FCCU NCF Time-out Enable Register 3 */
+ FCCU_NCF_TOE3_32B_tag NCF_TOE3; /* offset: 0x00B0 size: 32 bit */
+ };
+
+ };
+ /* FCCU_NCF_TO - FCCU NCF Time-out Register */
+ FCCU_NCF_TO_32B_tag NCF_TO; /* offset: 0x00B4 size: 32 bit */
+ /* FCCU_CFG_TO - FCCU CFG Timeout Register */
+ FCCU_CFG_TO_32B_tag CFG_TO; /* offset: 0x00B8 size: 32 bit */
+ /* FCCU_EINOUT - FCCU IO Control Register */
+ FCCU_EINOUT_32B_tag EINOUT; /* offset: 0x00BC size: 32 bit */
+ /* FCCU_STAT - FCCU Status Register */
+ FCCU_STAT_32B_tag STAT; /* offset: 0x00C0 size: 32 bit */
+ /* FCCU_NAFS - FCCU NA Freeze Status Register */
+ FCCU_NAFS_32B_tag NAFS; /* offset: 0x00C4 size: 32 bit */
+ /* FCCU_AFFS - FCCU AF Freeze Status Register */
+ FCCU_AFFS_32B_tag AFFS; /* offset: 0x00C8 size: 32 bit */
+ /* FCCU_NFFS - FCCU NF Freeze Status Register */
+ FCCU_NFFS_32B_tag NFFS; /* offset: 0x00CC size: 32 bit */
+ /* FCCU_FAFS - FCCU FA Freeze Status Register */
+ FCCU_FAFS_32B_tag FAFS; /* offset: 0x00D0 size: 32 bit */
+ /* FCCU_SCFS - FCCU SC Freeze Status Register */
+ FCCU_SCFS_32B_tag SCFS; /* offset: 0x00D4 size: 32 bit */
+ /* FCCU_CFF - FCCU CF Fake Register */
+ FCCU_CFF_32B_tag CFF; /* offset: 0x00D8 size: 32 bit */
+ /* FCCU_NCFF - FCCU NCF Fake Register */
+ FCCU_NCFF_32B_tag NCFF; /* offset: 0x00DC size: 32 bit */
+ /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
+ FCCU_IRQ_STAT_32B_tag IRQ_STAT; /* offset: 0x00E0 size: 32 bit */
+ /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
+ FCCU_IRQ_EN_32B_tag IRQ_EN; /* offset: 0x00E4 size: 32 bit */
+ /* FCCU_XTMR - FCCU XTMR Register */
+ FCCU_XTMR_32B_tag XTMR; /* offset: 0x00E8 size: 32 bit */
+ /* FCCU_MCS - FCCU MCS Register */
+ FCCU_MCS_32B_tag MCS; /* offset: 0x00EC size: 32 bit */
+ } FCCU_tag;
+
+
+#define FCCU (*(volatile FCCU_tag *) 0xFFE6C000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SGENDIG */
+/* */
+/****************************************************************/
+
+ typedef union { /* SGENDIG_CTRL - SGENDIG Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t LDOS:1; /* Operation Status */
+ vuint32_t IOAMPL:5; /* Define the AMPLitude value on I/O pad */
+ vuint32_t:2;
+ vuint32_t SEMASK:1; /* Sine wave generator Error MASK interrupt register */
+ vuint32_t:5;
+ vuint32_t S0H1:1; /* Operation Status */
+ vuint32_t PDS:1; /* Operation Status */
+ vuint32_t IOFREQ:16; /* Define the FREQuency value on I/O pad */
+ } B;
+ } SGENDIG_CTRL_32B_tag;
+
+ typedef union { /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:8;
+ vuint32_t SERR:1; /* Sine wave generator Error bit */
+ vuint32_t:3;
+ vuint32_t FERR:1; /* Sine wave generator Force Error bit */
+ vuint32_t:19;
+ } B;
+ } SGENDIG_IRQE_32B_tag;
+
+
+
+ typedef struct SGENDIG_struct_tag { /* start of SGENDIG_tag */
+ /* SGENDIG_CTRL - SGENDIG Control Register */
+ SGENDIG_CTRL_32B_tag CTRL; /* offset: 0x0000 size: 32 bit */
+ /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable Register */
+ SGENDIG_IRQE_32B_tag IRQE; /* offset: 0x0004 size: 32 bit */
+ } SGENDIG_tag;
+
+
+#define SGENDIG (*(volatile SGENDIG_tag *) 0xFFE78000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: AIPS */
+/* */
+/****************************************************************/
+
+ typedef union { /* MPROT - Master Privilege Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t MPROT0_MBW:1; /* Master 0 Buffer Writes */
+ vuint32_t MPROT0_MTR:1; /* Master 0 Trusted for Reads */
+ vuint32_t MPROT0_MTW:1; /* Master 0 Trusted for Writes */
+ vuint32_t MPROT0_MPL:1; /* Master 0 Priviledge Level */
+ vuint32_t MPROT1_MBW:1; /* Master 1 Buffer Writes */
+ vuint32_t MPROT1_MTR:1; /* Master 1 Trusted for Reads */
+ vuint32_t MPROT1_MTW:1; /* Master 1 Trusted for Writes */
+ vuint32_t MPROT1_MPL:1; /* Master 1 Priviledge Level */
+ vuint32_t MPROT2_MBW:1; /* Master 2 Buffer Writes */
+ vuint32_t MPROT2_MTR:1; /* Master 2 Trusted for Reads */
+ vuint32_t MPROT2_MTW:1; /* Master 2 Trusted for Writes */
+ vuint32_t MPROT2_MPL:1; /* Master 2 Priviledge Level */
+ vuint32_t MPROT3_MBW:1; /* Master 3 Buffer Writes */
+ vuint32_t MPROT3_MTR:1; /* Master 3 Trusted for Reads */
+ vuint32_t MPROT3_MTW:1; /* Master 3 Trusted for Writes */
+ vuint32_t MPROT3_MPL:1; /* Master 3 Priviledge Level */
+ vuint32_t MPROT4_MBW:1; /* Master 4 Buffer Writes */
+ vuint32_t MPROT4_MTR:1; /* Master 4 Trusted for Reads */
+ vuint32_t MPROT4_MTW:1; /* Master 4 Trusted for Writes */
+ vuint32_t MPROT4_MPL:1; /* Master 4 Priviledge Level */
+ vuint32_t MPROT5_MBW:1; /* Master 5 Buffer Writes */
+ vuint32_t MPROT5_MTR:1; /* Master 5 Trusted for Reads */
+ vuint32_t MPROT5_MTW:1; /* Master 5 Trusted for Writes */
+ vuint32_t MPROT5_MPL:1; /* Master 5 Priviledge Level */
+ vuint32_t MPROT6_MBW:1; /* Master 6 Buffer Writes */
+ vuint32_t MPROT6_MTR:1; /* Master 6 Trusted for Reads */
+ vuint32_t MPROT6_MTW:1; /* Master 6 Trusted for Writes */
+ vuint32_t MPROT6_MPL:1; /* Master 6 Priviledge Level */
+ vuint32_t MPROT7_MBW:1; /* Master 7 Buffer Writes */
+ vuint32_t MPROT7_MTR:1; /* Master 7 Trusted for Reads */
+ vuint32_t MPROT7_MTW:1; /* Master 7 Trusted for Writes */
+ vuint32_t MPROT7_MPL:1; /* Master 7 Priviledge Level */
+ } B;
+ } AIPS_MPROT_32B_tag;
+
+ typedef union { /* PACR0_7 - Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t PACR0_BW:1; /* Buffer Writes */
+ vuint32_t PACR0_SP:1; /* Supervisor Protect */
+ vuint32_t PACR0_WP:1; /* Write Protect */
+ vuint32_t PACR0_TP:1; /* Trusted Protect */
+ vuint32_t PACR1_BW:1; /* Buffer Writes */
+ vuint32_t PACR1_SP:1; /* Supervisor Protect */
+ vuint32_t PACR1_WP:1; /* Write Protect */
+ vuint32_t PACR1_TP:1; /* Trusted Protect */
+ vuint32_t PACR2_BW:1; /* Buffer Writes */
+ vuint32_t PACR2_SP:1; /* Supervisor Protect */
+ vuint32_t PACR2_WP:1; /* Write Protect */
+ vuint32_t PACR2_TP:1; /* Trusted Protect */
+ vuint32_t PACR3_BW:1; /* Buffer Writes */
+ vuint32_t PACR3_SP:1; /* Supervisor Protect */
+ vuint32_t PACR3_WP:1; /* Write Protect */
+ vuint32_t PACR3_TP:1; /* Trusted Protect */
+ vuint32_t PACR4_BW:1; /* Buffer Writes */
+ vuint32_t PACR4_SP:1; /* Supervisor Protect */
+ vuint32_t PACR4_WP:1; /* Write Protect */
+ vuint32_t PACR4_TP:1; /* Trusted Protect */
+ vuint32_t PACR5_BW:1; /* Buffer Writes */
+ vuint32_t PACR5_SP:1; /* Supervisor Protect */
+ vuint32_t PACR5_WP:1; /* Write Protect */
+ vuint32_t PACR5_TP:1; /* Trusted Protect */
+ vuint32_t PACR6_BW:1; /* Buffer Writes */
+ vuint32_t PACR6_SP:1; /* Supervisor Protect */
+ vuint32_t PACR6_WP:1; /* Write Protect */
+ vuint32_t PACR6_TP:1; /* Trusted Protect */
+ vuint32_t PACR7_BW:1; /* Buffer Writes */
+ vuint32_t PACR7_SP:1; /* Supervisor Protect */
+ vuint32_t PACR7_WP:1; /* Write Protect */
+ vuint32_t PACR7_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_PACR0_7_32B_tag;
+
+ typedef union { /* PACR8_15 - Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t PACR8_BW:1; /* Buffer Writes */
+ vuint32_t PACR8_SP:1; /* Supervisor Protect */
+ vuint32_t PACR8_WP:1; /* Write Protect */
+ vuint32_t PACR8_TP:1; /* Trusted Protect */
+ vuint32_t PACR9_BW:1; /* Buffer Writes */
+ vuint32_t PACR9_SP:1; /* Supervisor Protect */
+ vuint32_t PACR9_WP:1; /* Write Protect */
+ vuint32_t PACR9_TP:1; /* Trusted Protect */
+ vuint32_t PACR10_BW:1; /* Buffer Writes */
+ vuint32_t PACR10_SP:1; /* Supervisor Protect */
+ vuint32_t PACR10_WP:1; /* Write Protect */
+ vuint32_t PACR10_TP:1; /* Trusted Protect */
+ vuint32_t PACR11_BW:1; /* Buffer Writes */
+ vuint32_t PACR11_SP:1; /* Supervisor Protect */
+ vuint32_t PACR11_WP:1; /* Write Protect */
+ vuint32_t PACR11_TP:1; /* Trusted Protect */
+ vuint32_t PACR12_BW:1; /* Buffer Writes */
+ vuint32_t PACR12_SP:1; /* Supervisor Protect */
+ vuint32_t PACR12_WP:1; /* Write Protect */
+ vuint32_t PACR12_TP:1; /* Trusted Protect */
+ vuint32_t PACR13_BW:1; /* Buffer Writes */
+ vuint32_t PACR13_SP:1; /* Supervisor Protect */
+ vuint32_t PACR13_WP:1; /* Write Protect */
+ vuint32_t PACR13_TP:1; /* Trusted Protect */
+ vuint32_t PACR14_BW:1; /* Buffer Writes */
+ vuint32_t PACR14_SP:1; /* Supervisor Protect */
+ vuint32_t PACR14_WP:1; /* Write Protect */
+ vuint32_t PACR14_TP:1; /* Trusted Protect */
+ vuint32_t PACR15_BW:1; /* Buffer Writes */
+ vuint32_t PACR15_SP:1; /* Supervisor Protect */
+ vuint32_t PACR15_WP:1; /* Write Protect */
+ vuint32_t PACR15_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_PACR8_15_32B_tag;
+
+ typedef union { /* PACR16_23 - Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t PACR16_BW:1; /* Buffer Writes */
+ vuint32_t PACR16_SP:1; /* Supervisor Protect */
+ vuint32_t PACR16_WP:1; /* Write Protect */
+ vuint32_t PACR16_TP:1; /* Trusted Protect */
+ vuint32_t PACR17_BW:1; /* Buffer Writes */
+ vuint32_t PACR17_SP:1; /* Supervisor Protect */
+ vuint32_t PACR17_WP:1; /* Write Protect */
+ vuint32_t PACR17_TP:1; /* Trusted Protect */
+ vuint32_t PACR18_BW:1; /* Buffer Writes */
+ vuint32_t PACR18_SP:1; /* Supervisor Protect */
+ vuint32_t PACR18_WP:1; /* Write Protect */
+ vuint32_t PACR18_TP:1; /* Trusted Protect */
+ vuint32_t PACR19_BW:1; /* Buffer Writes */
+ vuint32_t PACR19_SP:1; /* Supervisor Protect */
+ vuint32_t PACR19_WP:1; /* Write Protect */
+ vuint32_t PACR19_TP:1; /* Trusted Protect */
+ vuint32_t PACR20_BW:1; /* Buffer Writes */
+ vuint32_t PACR20_SP:1; /* Supervisor Protect */
+ vuint32_t PACR20_WP:1; /* Write Protect */
+ vuint32_t PACR20_TP:1; /* Trusted Protect */
+ vuint32_t PACR21_BW:1; /* Buffer Writes */
+ vuint32_t PACR21_SP:1; /* Supervisor Protect */
+ vuint32_t PACR21_WP:1; /* Write Protect */
+ vuint32_t PACR21_TP:1; /* Trusted Protect */
+ vuint32_t PACR22_BW:1; /* Buffer Writes */
+ vuint32_t PACR22_SP:1; /* Supervisor Protect */
+ vuint32_t PACR22_WP:1; /* Write Protect */
+ vuint32_t PACR22_TP:1; /* Trusted Protect */
+ vuint32_t PACR23_BW:1; /* Buffer Writes */
+ vuint32_t PACR23_SP:1; /* Supervisor Protect */
+ vuint32_t PACR23_WP:1; /* Write Protect */
+ vuint32_t PACR23_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_PACR16_23_32B_tag;
+
+ typedef union { /* PACR24_31 - Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t PACR24_BW:1; /* Buffer Writes */
+ vuint32_t PACR24_SP:1; /* Supervisor Protect */
+ vuint32_t PACR24_WP:1; /* Write Protect */
+ vuint32_t PACR24_TP:1; /* Trusted Protect */
+ vuint32_t PACR25_BW:1; /* Buffer Writes */
+ vuint32_t PACR25_SP:1; /* Supervisor Protect */
+ vuint32_t PACR25_WP:1; /* Write Protect */
+ vuint32_t PACR25_TP:1; /* Trusted Protect */
+ vuint32_t PACR26_BW:1; /* Buffer Writes */
+ vuint32_t PACR26_SP:1; /* Supervisor Protect */
+ vuint32_t PACR26_WP:1; /* Write Protect */
+ vuint32_t PACR26_TP:1; /* Trusted Protect */
+ vuint32_t PACR27_BW:1; /* Buffer Writes */
+ vuint32_t PACR27_SP:1; /* Supervisor Protect */
+ vuint32_t PACR27_WP:1; /* Write Protect */
+ vuint32_t PACR27_TP:1; /* Trusted Protect */
+ vuint32_t PACR28_BW:1; /* Buffer Writes */
+ vuint32_t PACR28_SP:1; /* Supervisor Protect */
+ vuint32_t PACR28_WP:1; /* Write Protect */
+ vuint32_t PACR28_TP:1; /* Trusted Protect */
+ vuint32_t PACR29_BW:1; /* Buffer Writes */
+ vuint32_t PACR29_SP:1; /* Supervisor Protect */
+ vuint32_t PACR29_WP:1; /* Write Protect */
+ vuint32_t PACR29_TP:1; /* Trusted Protect */
+ vuint32_t PACR30_BW:1; /* Buffer Writes */
+ vuint32_t PACR30_SP:1; /* Supervisor Protect */
+ vuint32_t PACR30_WP:1; /* Write Protect */
+ vuint32_t PACR30_TP:1; /* Trusted Protect */
+ vuint32_t PACR31_BW:1; /* Buffer Writes */
+ vuint32_t PACR31_SP:1; /* Supervisor Protect */
+ vuint32_t PACR31_WP:1; /* Write Protect */
+ vuint32_t PACR31_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_PACR24_31_32B_tag;
+
+ typedef union { /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR0_BW:1; /* Buffer Writes */
+ vuint32_t OPACR0_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR0_WP:1; /* Write Protect */
+ vuint32_t OPACR0_TP:1; /* Trusted Protect */
+ vuint32_t OPACR1_BW:1; /* Buffer Writes */
+ vuint32_t OPACR1_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR1_WP:1; /* Write Protect */
+ vuint32_t OPACR1_TP:1; /* Trusted Protect */
+ vuint32_t OPACR2_BW:1; /* Buffer Writes */
+ vuint32_t OPACR2_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR2_WP:1; /* Write Protect */
+ vuint32_t OPACR2_TP:1; /* Trusted Protect */
+ vuint32_t OPACR3_BW:1; /* Buffer Writes */
+ vuint32_t OPACR3_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR3_WP:1; /* Write Protect */
+ vuint32_t OPACR3_TP:1; /* Trusted Protect */
+ vuint32_t OPACR4_BW:1; /* Buffer Writes */
+ vuint32_t OPACR4_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR4_WP:1; /* Write Protect */
+ vuint32_t OPACR4_TP:1; /* Trusted Protect */
+ vuint32_t OPACR5_BW:1; /* Buffer Writes */
+ vuint32_t OPACR5_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR5_WP:1; /* Write Protect */
+ vuint32_t OPACR5_TP:1; /* Trusted Protect */
+ vuint32_t OPACR6_BW:1; /* Buffer Writes */
+ vuint32_t OPACR6_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR6_WP:1; /* Write Protect */
+ vuint32_t OPACR6_TP:1; /* Trusted Protect */
+ vuint32_t OPACR7_BW:1; /* Buffer Writes */
+ vuint32_t OPACR7_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR7_WP:1; /* Write Protect */
+ vuint32_t OPACR7_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR0_7_32B_tag;
+
+ typedef union { /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR8_BW:1; /* Buffer Writes */
+ vuint32_t OPACR8_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR8_WP:1; /* Write Protect */
+ vuint32_t OPACR8_TP:1; /* Trusted Protect */
+ vuint32_t OPACR9_BW:1; /* Buffer Writes */
+ vuint32_t OPACR9_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR9_WP:1; /* Write Protect */
+ vuint32_t OPACR9_TP:1; /* Trusted Protect */
+ vuint32_t OPACR10_BW:1; /* Buffer Writes */
+ vuint32_t OPACR10_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR10_WP:1; /* Write Protect */
+ vuint32_t OPACR10_TP:1; /* Trusted Protect */
+ vuint32_t OPACR11_BW:1; /* Buffer Writes */
+ vuint32_t OPACR11_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR11_WP:1; /* Write Protect */
+ vuint32_t OPACR11_TP:1; /* Trusted Protect */
+ vuint32_t OPACR12_BW:1; /* Buffer Writes */
+ vuint32_t OPACR12_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR12_WP:1; /* Write Protect */
+ vuint32_t OPACR12_TP:1; /* Trusted Protect */
+ vuint32_t OPACR13_BW:1; /* Buffer Writes */
+ vuint32_t OPACR13_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR13_WP:1; /* Write Protect */
+ vuint32_t OPACR13_TP:1; /* Trusted Protect */
+ vuint32_t OPACR14_BW:1; /* Buffer Writes */
+ vuint32_t OPACR14_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR14_WP:1; /* Write Protect */
+ vuint32_t OPACR14_TP:1; /* Trusted Protect */
+ vuint32_t OPACR15_BW:1; /* Buffer Writes */
+ vuint32_t OPACR15_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR15_WP:1; /* Write Protect */
+ vuint32_t OPACR15_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR8_15_32B_tag;
+
+ typedef union { /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR16_BW:1; /* Buffer Writes */
+ vuint32_t OPACR16_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR16_WP:1; /* Write Protect */
+ vuint32_t OPACR16_TP:1; /* Trusted Protect */
+ vuint32_t OPACR17_BW:1; /* Buffer Writes */
+ vuint32_t OPACR17_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR17_WP:1; /* Write Protect */
+ vuint32_t OPACR17_TP:1; /* Trusted Protect */
+ vuint32_t OPACR18_BW:1; /* Buffer Writes */
+ vuint32_t OPACR18_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR18_WP:1; /* Write Protect */
+ vuint32_t OPACR18_TP:1; /* Trusted Protect */
+ vuint32_t OPACR19_BW:1; /* Buffer Writes */
+ vuint32_t OPACR19_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR19_WP:1; /* Write Protect */
+ vuint32_t OPACR19_TP:1; /* Trusted Protect */
+ vuint32_t OPACR20_BW:1; /* Buffer Writes */
+ vuint32_t OPACR20_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR20_WP:1; /* Write Protect */
+ vuint32_t OPACR20_TP:1; /* Trusted Protect */
+ vuint32_t OPACR21_BW:1; /* Buffer Writes */
+ vuint32_t OPACR21_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR21_WP:1; /* Write Protect */
+ vuint32_t OPACR21_TP:1; /* Trusted Protect */
+ vuint32_t OPACR22_BW:1; /* Buffer Writes */
+ vuint32_t OPACR22_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR22_WP:1; /* Write Protect */
+ vuint32_t OPACR22_TP:1; /* Trusted Protect */
+ vuint32_t OPACR23_BW:1; /* Buffer Writes */
+ vuint32_t OPACR23_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR23_WP:1; /* Write Protect */
+ vuint32_t OPACR23_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR16_23_32B_tag;
+
+ typedef union { /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR24_BW:1; /* Buffer Writes */
+ vuint32_t OPACR24_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR24_WP:1; /* Write Protect */
+ vuint32_t OPACR24_TP:1; /* Trusted Protect */
+ vuint32_t OPACR25_BW:1; /* Buffer Writes */
+ vuint32_t OPACR25_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR25_WP:1; /* Write Protect */
+ vuint32_t OPACR25_TP:1; /* Trusted Protect */
+ vuint32_t OPACR26_BW:1; /* Buffer Writes */
+ vuint32_t OPACR26_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR26_WP:1; /* Write Protect */
+ vuint32_t OPACR26_TP:1; /* Trusted Protect */
+ vuint32_t OPACR27_BW:1; /* Buffer Writes */
+ vuint32_t OPACR27_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR27_WP:1; /* Write Protect */
+ vuint32_t OPACR27_TP:1; /* Trusted Protect */
+ vuint32_t OPACR28_BW:1; /* Buffer Writes */
+ vuint32_t OPACR28_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR28_WP:1; /* Write Protect */
+ vuint32_t OPACR28_TP:1; /* Trusted Protect */
+ vuint32_t OPACR29_BW:1; /* Buffer Writes */
+ vuint32_t OPACR29_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR29_WP:1; /* Write Protect */
+ vuint32_t OPACR29_TP:1; /* Trusted Protect */
+ vuint32_t OPACR30_BW:1; /* Buffer Writes */
+ vuint32_t OPACR30_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR30_WP:1; /* Write Protect */
+ vuint32_t OPACR30_TP:1; /* Trusted Protect */
+ vuint32_t OPACR31_BW:1; /* Buffer Writes */
+ vuint32_t OPACR31_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR31_WP:1; /* Write Protect */
+ vuint32_t OPACR31_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR24_31_32B_tag;
+
+ typedef union { /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR32_BW:1; /* Buffer Writes */
+ vuint32_t OPACR32_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR32_WP:1; /* Write Protect */
+ vuint32_t OPACR32_TP:1; /* Trusted Protect */
+ vuint32_t OPACR33_BW:1; /* Buffer Writes */
+ vuint32_t OPACR33_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR33_WP:1; /* Write Protect */
+ vuint32_t OPACR33_TP:1; /* Trusted Protect */
+ vuint32_t OPACR34_BW:1; /* Buffer Writes */
+ vuint32_t OPACR34_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR34_WP:1; /* Write Protect */
+ vuint32_t OPACR34_TP:1; /* Trusted Protect */
+ vuint32_t OPACR35_BW:1; /* Buffer Writes */
+ vuint32_t OPACR35_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR35_WP:1; /* Write Protect */
+ vuint32_t OPACR35_TP:1; /* Trusted Protect */
+ vuint32_t OPACR36_BW:1; /* Buffer Writes */
+ vuint32_t OPACR36_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR36_WP:1; /* Write Protect */
+ vuint32_t OPACR36_TP:1; /* Trusted Protect */
+ vuint32_t OPACR37_BW:1; /* Buffer Writes */
+ vuint32_t OPACR37_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR37_WP:1; /* Write Protect */
+ vuint32_t OPACR37_TP:1; /* Trusted Protect */
+ vuint32_t OPACR38_BW:1; /* Buffer Writes */
+ vuint32_t OPACR38_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR38_WP:1; /* Write Protect */
+ vuint32_t OPACR38_TP:1; /* Trusted Protect */
+ vuint32_t OPACR39_BW:1; /* Buffer Writes */
+ vuint32_t OPACR39_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR39_WP:1; /* Write Protect */
+ vuint32_t OPACR39_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR32_39_32B_tag;
+
+ typedef union { /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR40_BW:1; /* Buffer Writes */
+ vuint32_t OPACR40_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR40_WP:1; /* Write Protect */
+ vuint32_t OPACR40_TP:1; /* Trusted Protect */
+ vuint32_t OPACR41_BW:1; /* Buffer Writes */
+ vuint32_t OPACR41_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR41_WP:1; /* Write Protect */
+ vuint32_t OPACR41_TP:1; /* Trusted Protect */
+ vuint32_t OPACR42_BW:1; /* Buffer Writes */
+ vuint32_t OPACR42_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR42_WP:1; /* Write Protect */
+ vuint32_t OPACR42_TP:1; /* Trusted Protect */
+ vuint32_t OPACR43_BW:1; /* Buffer Writes */
+ vuint32_t OPACR43_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR43_WP:1; /* Write Protect */
+ vuint32_t OPACR43_TP:1; /* Trusted Protect */
+ vuint32_t OPACR44_BW:1; /* Buffer Writes */
+ vuint32_t OPACR44_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR44_WP:1; /* Write Protect */
+ vuint32_t OPACR44_TP:1; /* Trusted Protect */
+ vuint32_t OPACR45_BW:1; /* Buffer Writes */
+ vuint32_t OPACR45_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR45_WP:1; /* Write Protect */
+ vuint32_t OPACR45_TP:1; /* Trusted Protect */
+ vuint32_t OPACR46_BW:1; /* Buffer Writes */
+ vuint32_t OPACR46_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR46_WP:1; /* Write Protect */
+ vuint32_t OPACR46_TP:1; /* Trusted Protect */
+ vuint32_t OPACR47_BW:1; /* Buffer Writes */
+ vuint32_t OPACR47_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR47_WP:1; /* Write Protect */
+ vuint32_t OPACR47_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR40_47_32B_tag;
+
+ typedef union { /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR48_BW:1; /* Buffer Writes */
+ vuint32_t OPACR48_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR48_WP:1; /* Write Protect */
+ vuint32_t OPACR48_TP:1; /* Trusted Protect */
+ vuint32_t OPACR49_BW:1; /* Buffer Writes */
+ vuint32_t OPACR49_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR49_WP:1; /* Write Protect */
+ vuint32_t OPACR49_TP:1; /* Trusted Protect */
+ vuint32_t OPACR50_BW:1; /* Buffer Writes */
+ vuint32_t OPACR50_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR50_WP:1; /* Write Protect */
+ vuint32_t OPACR50_TP:1; /* Trusted Protect */
+ vuint32_t OPACR51_BW:1; /* Buffer Writes */
+ vuint32_t OPACR51_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR51_WP:1; /* Write Protect */
+ vuint32_t OPACR51_TP:1; /* Trusted Protect */
+ vuint32_t OPACR52_BW:1; /* Buffer Writes */
+ vuint32_t OPACR52_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR52_WP:1; /* Write Protect */
+ vuint32_t OPACR52_TP:1; /* Trusted Protect */
+ vuint32_t OPACR53_BW:1; /* Buffer Writes */
+ vuint32_t OPACR53_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR53_WP:1; /* Write Protect */
+ vuint32_t OPACR53_TP:1; /* Trusted Protect */
+ vuint32_t OPACR54_BW:1; /* Buffer Writes */
+ vuint32_t OPACR54_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR54_WP:1; /* Write Protect */
+ vuint32_t OPACR54_TP:1; /* Trusted Protect */
+ vuint32_t OPACR55_BW:1; /* Buffer Writes */
+ vuint32_t OPACR55_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR55_WP:1; /* Write Protect */
+ vuint32_t OPACR55_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR48_55_32B_tag;
+
+ typedef union { /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR56_BW:1; /* Buffer Writes */
+ vuint32_t OPACR56_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR56_WP:1; /* Write Protect */
+ vuint32_t OPACR56_TP:1; /* Trusted Protect */
+ vuint32_t OPACR57_BW:1; /* Buffer Writes */
+ vuint32_t OPACR57_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR57_WP:1; /* Write Protect */
+ vuint32_t OPACR57_TP:1; /* Trusted Protect */
+ vuint32_t OPACR58_BW:1; /* Buffer Writes */
+ vuint32_t OPACR58_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR58_WP:1; /* Write Protect */
+ vuint32_t OPACR58_TP:1; /* Trusted Protect */
+ vuint32_t OPACR59_BW:1; /* Buffer Writes */
+ vuint32_t OPACR59_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR59_WP:1; /* Write Protect */
+ vuint32_t OPACR59_TP:1; /* Trusted Protect */
+ vuint32_t OPACR60_BW:1; /* Buffer Writes */
+ vuint32_t OPACR60_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR60_WP:1; /* Write Protect */
+ vuint32_t OPACR60_TP:1; /* Trusted Protect */
+ vuint32_t OPACR61_BW:1; /* Buffer Writes */
+ vuint32_t OPACR61_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR61_WP:1; /* Write Protect */
+ vuint32_t OPACR61_TP:1; /* Trusted Protect */
+ vuint32_t OPACR62_BW:1; /* Buffer Writes */
+ vuint32_t OPACR62_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR62_WP:1; /* Write Protect */
+ vuint32_t OPACR62_TP:1; /* Trusted Protect */
+ vuint32_t OPACR63_BW:1; /* Buffer Writes */
+ vuint32_t OPACR63_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR63_WP:1; /* Write Protect */
+ vuint32_t OPACR63_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR56_63_32B_tag;
+
+ typedef union { /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR64_BW:1; /* Buffer Writes */
+ vuint32_t OPACR64_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR64_WP:1; /* Write Protect */
+ vuint32_t OPACR64_TP:1; /* Trusted Protect */
+ vuint32_t OPACR65_BW:1; /* Buffer Writes */
+ vuint32_t OPACR65_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR65_WP:1; /* Write Protect */
+ vuint32_t OPACR65_TP:1; /* Trusted Protect */
+ vuint32_t OPACR66_BW:1; /* Buffer Writes */
+ vuint32_t OPACR66_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR66_WP:1; /* Write Protect */
+ vuint32_t OPACR66_TP:1; /* Trusted Protect */
+ vuint32_t OPACR67_BW:1; /* Buffer Writes */
+ vuint32_t OPACR67_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR67_WP:1; /* Write Protect */
+ vuint32_t OPACR67_TP:1; /* Trusted Protect */
+ vuint32_t OPACR68_BW:1; /* Buffer Writes */
+ vuint32_t OPACR68_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR68_WP:1; /* Write Protect */
+ vuint32_t OPACR68_TP:1; /* Trusted Protect */
+ vuint32_t OPACR69_BW:1; /* Buffer Writes */
+ vuint32_t OPACR69_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR69_WP:1; /* Write Protect */
+ vuint32_t OPACR69_TP:1; /* Trusted Protect */
+ vuint32_t OPACR70_BW:1; /* Buffer Writes */
+ vuint32_t OPACR70_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR70_WP:1; /* Write Protect */
+ vuint32_t OPACR70_TP:1; /* Trusted Protect */
+ vuint32_t OPACR71_BW:1; /* Buffer Writes */
+ vuint32_t OPACR71_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR71_WP:1; /* Write Protect */
+ vuint32_t OPACR71_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR64_71_32B_tag;
+
+ typedef union { /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR72_BW:1; /* Buffer Writes */
+ vuint32_t OPACR72_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR72_WP:1; /* Write Protect */
+ vuint32_t OPACR72_TP:1; /* Trusted Protect */
+ vuint32_t OPACR73_BW:1; /* Buffer Writes */
+ vuint32_t OPACR73_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR73_WP:1; /* Write Protect */
+ vuint32_t OPACR73_TP:1; /* Trusted Protect */
+ vuint32_t OPACR74_BW:1; /* Buffer Writes */
+ vuint32_t OPACR74_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR74_WP:1; /* Write Protect */
+ vuint32_t OPACR74_TP:1; /* Trusted Protect */
+ vuint32_t OPACR75_BW:1; /* Buffer Writes */
+ vuint32_t OPACR75_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR75_WP:1; /* Write Protect */
+ vuint32_t OPACR75_TP:1; /* Trusted Protect */
+ vuint32_t OPACR76_BW:1; /* Buffer Writes */
+ vuint32_t OPACR76_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR76_WP:1; /* Write Protect */
+ vuint32_t OPACR76_TP:1; /* Trusted Protect */
+ vuint32_t OPACR77_BW:1; /* Buffer Writes */
+ vuint32_t OPACR77_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR77_WP:1; /* Write Protect */
+ vuint32_t OPACR77_TP:1; /* Trusted Protect */
+ vuint32_t OPACR78_BW:1; /* Buffer Writes */
+ vuint32_t OPACR78_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR78_WP:1; /* Write Protect */
+ vuint32_t OPACR78_TP:1; /* Trusted Protect */
+ vuint32_t OPACR79_BW:1; /* Buffer Writes */
+ vuint32_t OPACR79_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR79_WP:1; /* Write Protect */
+ vuint32_t OPACR79_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR72_79_32B_tag;
+
+ typedef union { /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR80_BW:1; /* Buffer Writes */
+ vuint32_t OPACR80_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR80_WP:1; /* Write Protect */
+ vuint32_t OPACR80_TP:1; /* Trusted Protect */
+ vuint32_t OPACR81_BW:1; /* Buffer Writes */
+ vuint32_t OPACR81_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR81_WP:1; /* Write Protect */
+ vuint32_t OPACR81_TP:1; /* Trusted Protect */
+ vuint32_t OPACR82_BW:1; /* Buffer Writes */
+ vuint32_t OPACR82_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR82_WP:1; /* Write Protect */
+ vuint32_t OPACR82_TP:1; /* Trusted Protect */
+ vuint32_t OPACR83_BW:1; /* Buffer Writes */
+ vuint32_t OPACR83_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR83_WP:1; /* Write Protect */
+ vuint32_t OPACR83_TP:1; /* Trusted Protect */
+ vuint32_t OPACR84_BW:1; /* Buffer Writes */
+ vuint32_t OPACR84_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR84_WP:1; /* Write Protect */
+ vuint32_t OPACR84_TP:1; /* Trusted Protect */
+ vuint32_t OPACR85_BW:1; /* Buffer Writes */
+ vuint32_t OPACR85_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR85_WP:1; /* Write Protect */
+ vuint32_t OPACR85_TP:1; /* Trusted Protect */
+ vuint32_t OPACR86_BW:1; /* Buffer Writes */
+ vuint32_t OPACR86_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR86_WP:1; /* Write Protect */
+ vuint32_t OPACR86_TP:1; /* Trusted Protect */
+ vuint32_t OPACR87_BW:1; /* Buffer Writes */
+ vuint32_t OPACR87_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR87_WP:1; /* Write Protect */
+ vuint32_t OPACR87_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR80_87_32B_tag;
+
+ typedef union { /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t OPACR88_BW:1; /* Buffer Writes */
+ vuint32_t OPACR88_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR88_WP:1; /* Write Protect */
+ vuint32_t OPACR88_TP:1; /* Trusted Protect */
+ vuint32_t OPACR89_BW:1; /* Buffer Writes */
+ vuint32_t OPACR89_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR89_WP:1; /* Write Protect */
+ vuint32_t OPACR89_TP:1; /* Trusted Protect */
+ vuint32_t OPACR90_BW:1; /* Buffer Writes */
+ vuint32_t OPACR90_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR90_WP:1; /* Write Protect */
+ vuint32_t OPACR90_TP:1; /* Trusted Protect */
+ vuint32_t OPACR91_BW:1; /* Buffer Writes */
+ vuint32_t OPACR91_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR91_WP:1; /* Write Protect */
+ vuint32_t OPACR91_TP:1; /* Trusted Protect */
+ vuint32_t OPACR92_BW:1; /* Buffer Writes */
+ vuint32_t OPACR92_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR92_WP:1; /* Write Protect */
+ vuint32_t OPACR92_TP:1; /* Trusted Protect */
+ vuint32_t OPACR93_BW:1; /* Buffer Writes */
+ vuint32_t OPACR93_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR93_WP:1; /* Write Protect */
+ vuint32_t OPACR93_TP:1; /* Trusted Protect */
+ vuint32_t OPACR94_BW:1; /* Buffer Writes */
+ vuint32_t OPACR94_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR94_WP:1; /* Write Protect */
+ vuint32_t OPACR94_TP:1; /* Trusted Protect */
+ vuint32_t OPACR95_BW:1; /* Buffer Writes */
+ vuint32_t OPACR95_SP:1; /* Supervisor Protect */
+ vuint32_t OPACR95_WP:1; /* Write Protect */
+ vuint32_t OPACR95_TP:1; /* Trusted Protect */
+ } B;
+ } AIPS_OPACR88_95_32B_tag;
+
+
+
+ typedef struct AIPS_struct_tag { /* start of AIPS_tag */
+ /* MPROT - Master Privilege Registers */
+ AIPS_MPROT_32B_tag MPROT; /* offset: 0x0000 size: 32 bit */
+ int8_t AIPS_reserved_0004[28];
+ /* PACR0_7 - Peripheral Access Control Registers */
+ AIPS_PACR0_7_32B_tag PACR0_7; /* offset: 0x0020 size: 32 bit */
+ /* PACR8_15 - Peripheral Access Control Registers */
+ AIPS_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */
+ /* PACR16_23 - Peripheral Access Control Registers */
+ AIPS_PACR16_23_32B_tag PACR16_23; /* offset: 0x0028 size: 32 bit */
+ /* PACR24_31 - Peripheral Access Control Registers */
+ AIPS_PACR24_31_32B_tag PACR24_31; /* offset: 0x002C size: 32 bit */
+ int8_t AIPS_reserved_0030[16];
+ /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */
+ /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR8_15_32B_tag OPACR8_15; /* offset: 0x0044 size: 32 bit */
+ /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR16_23_32B_tag OPACR16_23; /* offset: 0x0048 size: 32 bit */
+ /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR24_31_32B_tag OPACR24_31; /* offset: 0x004C size: 32 bit */
+ /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR32_39_32B_tag OPACR32_39; /* offset: 0x0050 size: 32 bit */
+ /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR40_47_32B_tag OPACR40_47; /* offset: 0x0054 size: 32 bit */
+ /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR48_55_32B_tag OPACR48_55; /* offset: 0x0058 size: 32 bit */
+ /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR56_63_32B_tag OPACR56_63; /* offset: 0x005C size: 32 bit */
+ /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR64_71_32B_tag OPACR64_71; /* offset: 0x0060 size: 32 bit */
+ /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR72_79_32B_tag OPACR72_79; /* offset: 0x0064 size: 32 bit */
+ /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR80_87_32B_tag OPACR80_87; /* offset: 0x0068 size: 32 bit */
+ /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
+ AIPS_OPACR88_95_32B_tag OPACR88_95; /* offset: 0x006C size: 32 bit */
+ } AIPS_tag;
+
+
+#define AIPS (*(volatile AIPS_tag *) 0xFFF00000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: MAX */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers MPR... */
+
+ typedef union { /* Master Priority Register for slave port n */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t MSTR_7:3; /* Master 7 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_6:3; /* Master 6 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_5:3; /* Master 5 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_4:3; /* Master 4 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_3:3; /* Master 3 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_2:3; /* Master 2 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_1:3; /* Master 1 Priority */
+ vuint32_t:1;
+ vuint32_t MSTR_0:3; /* Master 0 Priority */
+ } B;
+ } MAX_MPR_32B_tag;
+
+
+ /* Register layout for all registers AMPR matches xxx */
+
+
+ /* Register layout for all registers SGPCR... */
+
+ typedef union { /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ vuint32_t R;
+ struct {
+ vuint32_t RO:1; /* Read Only */
+ vuint32_t HLP:1; /* Halt Low Priority */
+ vuint32_t:6;
+ vuint32_t HPE7:1; /* High Priority Enable */
+ vuint32_t HPE6:1; /* High Priority Enable */
+ vuint32_t HPE5:1; /* High Priority Enable */
+ vuint32_t HPE4:1; /* High Priority Enable */
+ vuint32_t HPE3:1; /* High Priority Enable */
+ vuint32_t HPE2:1; /* High Priority Enable */
+ vuint32_t HPE1:1; /* High Priority Enable */
+ vuint32_t HPE0:1; /* High Priority Enable */
+ vuint32_t:6;
+ vuint32_t ARB:2; /* Arbitration Mode */
+ vuint32_t:2;
+ vuint32_t PCTL:2; /* Parking Control */
+ vuint32_t:1;
+ vuint32_t PARK:3; /* Park */
+ } B;
+ } MAX_SGPCR_32B_tag;
+
+
+ /* Register layout for all registers ASGPCR... */
+
+ typedef union { /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ vuint32_t R;
+ struct {
+ vuint32_t:1;
+ vuint32_t HLP:1; /* Halt Low Priority */
+ vuint32_t:6;
+ vuint32_t HPE7:1; /* High Priority Enable */
+ vuint32_t HPE6:1; /* High Priority Enable */
+ vuint32_t HPE5:1; /* High Priority Enable */
+ vuint32_t HPE4:1; /* High Priority Enable */
+ vuint32_t HPE3:1; /* High Priority Enable */
+ vuint32_t HPE2:1; /* High Priority Enable */
+ vuint32_t HPE1:1; /* High Priority Enable */
+ vuint32_t HPE0:1; /* High Priority Enable */
+ vuint32_t:6;
+ vuint32_t ARB:2; /* Arbitration Mode */
+ vuint32_t:2;
+ vuint32_t PCTL:2; /* Parking Control */
+ vuint32_t:1;
+ vuint32_t PARK:3; /* Park */
+ } B;
+ } MAX_ASGPCR_32B_tag;
+
+
+ /* Register layout for all registers MGPCR... */
+
+ typedef union { /* MAX_MGPCRn - Master General Purpose Control Register n */
+ vuint32_t R;
+ struct {
+ vuint32_t:29;
+ vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */
+ } B;
+ } MAX_MGPCR_32B_tag;
+
+
+ typedef struct MAX_SLAVE_PORT_struct_tag {
+
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR; /* relative offset: 0x0000 */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR; /* relative offset: 0x0004 */
+ int8_t MAX_SLAVE_PORT_reserved_0008[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR; /* relative offset: 0x0010 */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR; /* relative offset: 0x0014 */
+ int8_t MAX_SLAVE_PORT_reserved_0018[232];
+
+ } MAX_SLAVE_PORT_tag;
+
+ typedef struct MAX_MASTER_PORT_struct_tag {
+
+ /* MAX_MGPCRn - Master General Purpose Control Register n */
+ MAX_MGPCR_32B_tag MGPCR; /* relative offset: 0x0000 */
+ int8_t MAX_MASTER_PORT_reserved_0004[252];
+
+ } MAX_MASTER_PORT_tag;
+
+
+ typedef struct MAX_struct_tag { /* start of MAX_tag */
+ union {
+ /* Register set SLAVE_PORT */
+ MAX_SLAVE_PORT_tag SLAVE_PORT[8]; /* offset: 0x0000 (0x0100 x 8) */
+
+ struct {
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR0; /* offset: 0x0000 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR0; /* offset: 0x0004 size: 32 bit */
+ int8_t MAX_reserved_0008_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR0; /* offset: 0x0010 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR0; /* offset: 0x0014 size: 32 bit */
+ int8_t MAX_reserved_0018_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR1; /* offset: 0x0100 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR1; /* offset: 0x0104 size: 32 bit */
+ int8_t MAX_reserved_0108_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR1; /* offset: 0x0110 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR1; /* offset: 0x0114 size: 32 bit */
+ int8_t MAX_reserved_0118_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR2; /* offset: 0x0200 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR2; /* offset: 0x0204 size: 32 bit */
+ int8_t MAX_reserved_0208_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR2; /* offset: 0x0210 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR2; /* offset: 0x0214 size: 32 bit */
+ int8_t MAX_reserved_0218_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR3; /* offset: 0x0300 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR3; /* offset: 0x0304 size: 32 bit */
+ int8_t MAX_reserved_0308_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR3; /* offset: 0x0310 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR3; /* offset: 0x0314 size: 32 bit */
+ int8_t MAX_reserved_0318_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR4; /* offset: 0x0400 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR4; /* offset: 0x0404 size: 32 bit */
+ int8_t MAX_reserved_0408_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR4; /* offset: 0x0410 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR4; /* offset: 0x0414 size: 32 bit */
+ int8_t MAX_reserved_0418_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR5; /* offset: 0x0500 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR5; /* offset: 0x0504 size: 32 bit */
+ int8_t MAX_reserved_0508_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR5; /* offset: 0x0510 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR5; /* offset: 0x0514 size: 32 bit */
+ int8_t MAX_reserved_0518_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR6; /* offset: 0x0600 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR6; /* offset: 0x0604 size: 32 bit */
+ int8_t MAX_reserved_0608_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR6; /* offset: 0x0610 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR6; /* offset: 0x0614 size: 32 bit */
+ int8_t MAX_reserved_0618_I1[232];
+ /* Master Priority Register for slave port n */
+ MAX_MPR_32B_tag MPR7; /* offset: 0x0700 size: 32 bit */
+ /* Alternate Master Priority Register for slave port n */
+ MAX_MPR_32B_tag AMPR7; /* offset: 0x0704 size: 32 bit */
+ int8_t MAX_reserved_0708_I1[8];
+ /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
+ MAX_SGPCR_32B_tag SGPCR7; /* offset: 0x0710 size: 32 bit */
+ /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
+ MAX_ASGPCR_32B_tag ASGPCR7; /* offset: 0x0714 size: 32 bit */
+ int8_t MAX_reserved_0718_E1[232];
+ };
+
+ };
+ union {
+ /* Register set MASTER_PORT */
+ MAX_MASTER_PORT_tag MASTER_PORT[8]; /* offset: 0x0800 (0x0100 x 8) */
+
+ struct {
+ /* MAX_MGPCRn - Master General Purpose Control Register n */
+ MAX_MGPCR_32B_tag MGPCR0; /* offset: 0x0800 size: 32 bit */
+ int8_t MAX_reserved_0804_I1[252];
+ MAX_MGPCR_32B_tag MGPCR1; /* offset: 0x0900 size: 32 bit */
+ int8_t MAX_reserved_0904_I1[252];
+ MAX_MGPCR_32B_tag MGPCR2; /* offset: 0x0A00 size: 32 bit */
+ int8_t MAX_reserved_0A04_I1[252];
+ MAX_MGPCR_32B_tag MGPCR3; /* offset: 0x0B00 size: 32 bit */
+ int8_t MAX_reserved_0B04_I1[252];
+ MAX_MGPCR_32B_tag MGPCR4; /* offset: 0x0C00 size: 32 bit */
+ int8_t MAX_reserved_0C04_I1[252];
+ MAX_MGPCR_32B_tag MGPCR5; /* offset: 0x0D00 size: 32 bit */
+ int8_t MAX_reserved_0D04_I1[252];
+ MAX_MGPCR_32B_tag MGPCR6; /* offset: 0x0E00 size: 32 bit */
+ int8_t MAX_reserved_0E04_I1[252];
+ MAX_MGPCR_32B_tag MGPCR7; /* offset: 0x0F00 size: 32 bit */
+ int8_t MAX_reserved_0F04_E1[252];
+ };
+
+ };
+ } MAX_tag;
+
+
+#define MAX (*(volatile MAX_tag *) 0xFFF04000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: MPU */
+/* */
+/****************************************************************/
+
+ typedef union { /* MPU_CESR - MPU Control/Error Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t SPERR:8; /* Slave Port n Error */
+ vuint32_t:4;
+ vuint32_t HRL:4; /* Hardware Revision Level */
+ vuint32_t NSP:4; /* Number of Slave Ports */
+ vuint32_t NRGD:4; /* Number of Region Descriptors */
+ vuint32_t:7;
+ vuint32_t VLD:1; /* Valid bit */
+ } B;
+ } MPU_CESR_32B_tag;
+
+
+ /* Register layout for all registers EAR... */
+
+ typedef union { /* MPU_EARn - MPU Error Address Register, Slave Port n */
+ vuint32_t R;
+ struct {
+ vuint32_t EADDR:32; /* Error Address */
+ } B;
+ } MPU_EAR_32B_tag;
+
+
+ /* Register layout for all registers EDR... */
+
+ typedef union { /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
+ vuint32_t R;
+ struct {
+ vuint32_t EACD:16; /* Error Access Control Detail */
+ vuint32_t EPID:8; /* Error Process Identification */
+ vuint32_t EMN:4; /* Error Master Number */
+ vuint32_t EATTR:3; /* Error Attributes */
+ vuint32_t ERW:1; /* Error Read/Write */
+ } B;
+ } MPU_EDR_32B_tag;
+
+
+ /* Register layout for all registers RGD_WORD0... */
+
+ typedef union { /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ vuint32_t R;
+ struct {
+ vuint32_t SRTADDR:27; /* Start Address */
+ vuint32_t:5;
+ } B;
+ } MPU_RGD_WORD0_32B_tag;
+
+
+ /* Register layout for all registers RGD_WORD1... */
+
+ typedef union { /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ vuint32_t R;
+ struct {
+ vuint32_t ENDADDR:27; /* End Address */
+ vuint32_t:5;
+ } B;
+ } MPU_RGD_WORD1_32B_tag;
+
+
+ /* Register layout for all registers RGD_WORD2... */
+
+ typedef union { /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1; /* Bus Master 7 Read Enable */
+ vuint32_t M7WE:1; /* Bus Master 7 Write Enable */
+ vuint32_t M6RE:1; /* Bus Master 6 Read Enable */
+ vuint32_t M6WE:1; /* Bus Master 7 Write Enable */
+ vuint32_t M5RE:1; /* Bus Master 5 Read Enable */
+ vuint32_t M5WE:1; /* Bus Master 5 Write Enable */
+ vuint32_t M4RE:1; /* Bus Master 4 Read Enable */
+ vuint32_t M4WE:1; /* Bus Master 4 Write Enable */
+ vuint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */
+ vuint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */
+ vuint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */
+ vuint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */
+ vuint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */
+ vuint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */
+ vuint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */
+ vuint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */
+ vuint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */
+ vuint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */
+ vuint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */
+ vuint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */
+ } B;
+ } MPU_RGD_WORD2_32B_tag;
+
+
+ /* Register layout for all registers RGD_WORD3... */
+
+ typedef union { /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ vuint32_t R;
+ struct {
+ vuint32_t PID:8; /* Process Identifier */
+ vuint32_t PIDMASK:8; /* Process Identifier Mask */
+ vuint32_t:15;
+ vuint32_t VLD:1; /* Valid */
+ } B;
+ } MPU_RGD_WORD3_32B_tag;
+
+
+ /* Register layout for all registers RGDAAC... */
+
+ typedef union { /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
+ vuint32_t R;
+ struct {
+ vuint32_t M7RE:1; /* Bus Master 7 Read Enable */
+ vuint32_t M7WE:1; /* Bus Master 7 Write Enable */
+ vuint32_t M6RE:1; /* Bus Master 6 Read Enable */
+ vuint32_t M6WE:1; /* Bus Master 7 Write Enable */
+ vuint32_t M5RE:1; /* Bus Master 5 Read Enable */
+ vuint32_t M5WE:1; /* Bus Master 5 Write Enable */
+ vuint32_t M4RE:1; /* Bus Master 4 Read Enable */
+ vuint32_t M4WE:1; /* Bus Master 4 Write Enable */
+ vuint32_t M3PE:1; /* Bus Master 3 Process Identifier Enable */
+ vuint32_t M3SM:2; /* Bus Master 3 Supervisor Mode Access Control */
+ vuint32_t M3UM:3; /* Bus Master 3 User Mode Access Control */
+ vuint32_t M2PE:1; /* Bus Master 2 Process Identifier Enable */
+ vuint32_t M2SM:2; /* Bus Master 2 Supervisor Mode Access Control */
+ vuint32_t M2UM:3; /* Bus Master 2 User Mode Access Control */
+ vuint32_t M1PE:1; /* Bus Master 1 Process Identifier Enable */
+ vuint32_t M1SM:2; /* Bus Master 1 Supervisor Mode Access Control */
+ vuint32_t M1UM:3; /* Bus Master 1 User Mode Access Control */
+ vuint32_t M0PE:1; /* Bus Master 0 Process Identifier Enable */
+ vuint32_t M0SM:2; /* Bus Master 0 Supervisor Mode Access Control */
+ vuint32_t M0UM:3; /* Bus Master 0 User Mode Access Control */
+ } B;
+ } MPU_RGDAAC_32B_tag;
+
+
+ typedef struct MPU_SLAVE_PORT_struct_tag {
+
+ /* MPU_EARn - MPU Error Address Register, Slave Port n */
+ MPU_EAR_32B_tag EAR; /* relative offset: 0x0000 */
+ /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
+ MPU_EDR_32B_tag EDR; /* relative offset: 0x0004 */
+
+ } MPU_SLAVE_PORT_tag;
+
+ typedef struct MPU_REGION_struct_tag {
+
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD_WORD0; /* relative offset: 0x0000 */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD_WORD1; /* relative offset: 0x0004 */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD_WORD2; /* relative offset: 0x0008 */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD_WORD3; /* relative offset: 0x000C */
+
+ } MPU_REGION_tag;
+
+
+ typedef struct MPU_struct_tag { /* start of MPU_tag */
+ /* MPU_CESR - MPU Control/Error Status Register */
+ MPU_CESR_32B_tag CESR; /* offset: 0x0000 size: 32 bit */
+ int8_t MPU_reserved_0004_C[12];
+ union {
+ /* Register set SLAVE_PORT */
+ MPU_SLAVE_PORT_tag SLAVE_PORT[4]; /* offset: 0x0010 (0x0008 x 4) */
+
+ struct {
+ /* MPU_EARn - MPU Error Address Register, Slave Port n */
+ MPU_EAR_32B_tag EAR0; /* offset: 0x0010 size: 32 bit */
+ /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
+ MPU_EDR_32B_tag EDR0; /* offset: 0x0014 size: 32 bit */
+ /* MPU_EARn - MPU Error Address Register, Slave Port n */
+ MPU_EAR_32B_tag EAR1; /* offset: 0x0018 size: 32 bit */
+ /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
+ MPU_EDR_32B_tag EDR1; /* offset: 0x001C size: 32 bit */
+ /* MPU_EARn - MPU Error Address Register, Slave Port n */
+ MPU_EAR_32B_tag EAR2; /* offset: 0x0020 size: 32 bit */
+ /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
+ MPU_EDR_32B_tag EDR2; /* offset: 0x0024 size: 32 bit */
+ /* MPU_EARn - MPU Error Address Register, Slave Port n */
+ MPU_EAR_32B_tag EAR3; /* offset: 0x0028 size: 32 bit */
+ /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
+ MPU_EDR_32B_tag EDR3; /* offset: 0x002C size: 32 bit */
+ };
+
+ };
+ int8_t MPU_reserved_0030_C[976];
+ union {
+ /* Register set REGION */
+ MPU_REGION_tag REGION[16]; /* offset: 0x0400 (0x0010 x 16) */
+
+ struct {
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD0_WORD0; /* offset: 0x0400 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD0_WORD1; /* offset: 0x0404 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD0_WORD2; /* offset: 0x0408 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD0_WORD3; /* offset: 0x040C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD1_WORD0; /* offset: 0x0410 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD1_WORD1; /* offset: 0x0414 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD1_WORD2; /* offset: 0x0418 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD1_WORD3; /* offset: 0x041C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD2_WORD0; /* offset: 0x0420 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD2_WORD1; /* offset: 0x0424 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD2_WORD2; /* offset: 0x0428 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD2_WORD3; /* offset: 0x042C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD3_WORD0; /* offset: 0x0430 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD3_WORD1; /* offset: 0x0434 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD3_WORD2; /* offset: 0x0438 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD3_WORD3; /* offset: 0x043C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD4_WORD0; /* offset: 0x0440 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD4_WORD1; /* offset: 0x0444 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD4_WORD2; /* offset: 0x0448 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD4_WORD3; /* offset: 0x044C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD5_WORD0; /* offset: 0x0450 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD5_WORD1; /* offset: 0x0454 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD5_WORD2; /* offset: 0x0458 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD5_WORD3; /* offset: 0x045C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD6_WORD0; /* offset: 0x0460 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD6_WORD1; /* offset: 0x0464 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD6_WORD2; /* offset: 0x0468 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD6_WORD3; /* offset: 0x046C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD7_WORD0; /* offset: 0x0470 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD7_WORD1; /* offset: 0x0474 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD7_WORD2; /* offset: 0x0478 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD7_WORD3; /* offset: 0x047C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD8_WORD0; /* offset: 0x0480 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD8_WORD1; /* offset: 0x0484 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD8_WORD2; /* offset: 0x0488 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD8_WORD3; /* offset: 0x048C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD9_WORD0; /* offset: 0x0490 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD9_WORD1; /* offset: 0x0494 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD9_WORD2; /* offset: 0x0498 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD9_WORD3; /* offset: 0x049C size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD10_WORD0; /* offset: 0x04A0 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD10_WORD1; /* offset: 0x04A4 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD10_WORD2; /* offset: 0x04A8 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD10_WORD3; /* offset: 0x04AC size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD11_WORD0; /* offset: 0x04B0 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD11_WORD1; /* offset: 0x04B4 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD11_WORD2; /* offset: 0x04B8 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD11_WORD3; /* offset: 0x04BC size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD12_WORD0; /* offset: 0x04C0 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD12_WORD1; /* offset: 0x04C4 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD12_WORD2; /* offset: 0x04C8 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD12_WORD3; /* offset: 0x04CC size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD13_WORD0; /* offset: 0x04D0 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD13_WORD1; /* offset: 0x04D4 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD13_WORD2; /* offset: 0x04D8 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD13_WORD3; /* offset: 0x04DC size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD14_WORD0; /* offset: 0x04E0 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD14_WORD1; /* offset: 0x04E4 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD14_WORD2; /* offset: 0x04E8 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD14_WORD3; /* offset: 0x04EC size: 32 bit */
+ /* MPU_RGDn_Word0 - MPU Region Descriptor */
+ MPU_RGD_WORD0_32B_tag RGD15_WORD0; /* offset: 0x04F0 size: 32 bit */
+ /* MPU_RGDn_Word1 - MPU Region Descriptor */
+ MPU_RGD_WORD1_32B_tag RGD15_WORD1; /* offset: 0x04F4 size: 32 bit */
+ /* MPU_RGDn_Word2 - MPU Region Descriptor */
+ MPU_RGD_WORD2_32B_tag RGD15_WORD2; /* offset: 0x04F8 size: 32 bit */
+ /* MPU_RGDn_Word3 - MPU Region Descriptor */
+ MPU_RGD_WORD3_32B_tag RGD15_WORD3; /* offset: 0x04FC size: 32 bit */
+ };
+
+ };
+ int8_t MPU_reserved_0500_C[768];
+ union {
+ /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
+ MPU_RGDAAC_32B_tag RGDAAC[16]; /* offset: 0x0800 (0x0004 x 16) */
+
+ struct {
+ /* MPU_RGDAACn - MPU Region Descriptor Alternate Access Control */
+ MPU_RGDAAC_32B_tag RGDAAC0; /* offset: 0x0800 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC1; /* offset: 0x0804 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC2; /* offset: 0x0808 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC3; /* offset: 0x080C size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC4; /* offset: 0x0810 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC5; /* offset: 0x0814 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC6; /* offset: 0x0818 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC7; /* offset: 0x081C size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC8; /* offset: 0x0820 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC9; /* offset: 0x0824 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC10; /* offset: 0x0828 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC11; /* offset: 0x082C size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC12; /* offset: 0x0830 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC13; /* offset: 0x0834 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC14; /* offset: 0x0838 size: 32 bit */
+ MPU_RGDAAC_32B_tag RGDAAC15; /* offset: 0x083C size: 32 bit */
+ };
+
+ };
+ } MPU_tag;
+
+
+#define MPU (*(volatile MPU_tag *) 0xFFF10000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SEMA4 */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers GATE... */
+
+ typedef union { /* SEMA4_GATEn - Semephores Gate Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t GTFSM:2; /* Gate Finite State machine */
+ } B;
+ } SEMA4_GATE_8B_tag;
+
+ typedef union { /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
+ vuint16_t R;
+ struct {
+ vuint16_t INE:16; /* Interrupt Request Notification Enable */
+ } B;
+ } SEMA4_CP0INE_16B_tag;
+
+ typedef union { /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
+ vuint16_t R;
+ struct {
+ vuint16_t INE:16; /* Interrupt Request Notification Enable */
+ } B;
+ } SEMA4_CP1INE_16B_tag;
+
+ typedef union { /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
+ vuint16_t R;
+ struct {
+ vuint16_t GN:16; /* Gate 0 Notification */
+ } B;
+ } SEMA4_CP0NTF_16B_tag;
+
+ typedef union { /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
+ vuint16_t R;
+ struct {
+ vuint16_t GN:16; /* Gate 1 Notification */
+ } B;
+ } SEMA4_CP1NTF_16B_tag;
+
+ typedef union { /* SEMA4_RSTGT - Semaphores Reset Gate */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t RSTGSM:2; /* Reset Gate Finite State Machine */
+ vuint16_t RSTGDP:7; /* Reset Gate Data Pattern */
+ vuint16_t RSTGMS:3; /* Reset Gate Bus Master */
+ vuint16_t RSTGTN:8; /* Reset Gate Number */
+ } B;
+ } SEMA4_RSTGT_16B_tag;
+
+ typedef union { /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t RSTNSM:2; /* Reset Gate Finite State Machine */
+ vuint16_t RSTNDP:7; /* Reset Gate Data Pattern */
+ vuint16_t RSTNMS:3; /* Reset Gate Bus Master */
+ vuint16_t RSTNTN:8; /* Reset Gate Number */
+ } B;
+ } SEMA4_RSTNTF_16B_tag;
+
+
+
+ typedef struct SEMA4_struct_tag { /* start of SEMA4_tag */
+ union {
+ /* SEMA4_GATEn - Semephores Gate Register */
+ SEMA4_GATE_8B_tag GATE[16]; /* offset: 0x0000 (0x0001 x 16) */
+
+ struct {
+ /* SEMA4_GATEn - Semephores Gate Register */
+ SEMA4_GATE_8B_tag GATE0; /* offset: 0x0000 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE1; /* offset: 0x0001 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE2; /* offset: 0x0002 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE3; /* offset: 0x0003 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE4; /* offset: 0x0004 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE5; /* offset: 0x0005 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE6; /* offset: 0x0006 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE7; /* offset: 0x0007 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE8; /* offset: 0x0008 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE9; /* offset: 0x0009 size: 8 bit */
+ SEMA4_GATE_8B_tag GATE10; /* offset: 0x000A size: 8 bit */
+ SEMA4_GATE_8B_tag GATE11; /* offset: 0x000B size: 8 bit */
+ SEMA4_GATE_8B_tag GATE12; /* offset: 0x000C size: 8 bit */
+ SEMA4_GATE_8B_tag GATE13; /* offset: 0x000D size: 8 bit */
+ SEMA4_GATE_8B_tag GATE14; /* offset: 0x000E size: 8 bit */
+ SEMA4_GATE_8B_tag GATE15; /* offset: 0x000F size: 8 bit */
+ };
+
+ };
+ int8_t SEMA4_reserved_0010[48];
+ /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
+ SEMA4_CP0INE_16B_tag CP0INE; /* offset: 0x0040 size: 16 bit */
+ int8_t SEMA4_reserved_0042[6];
+ /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
+ SEMA4_CP1INE_16B_tag CP1INE; /* offset: 0x0048 size: 16 bit */
+ int8_t SEMA4_reserved_004A[54];
+ /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
+ SEMA4_CP0NTF_16B_tag CP0NTF; /* offset: 0x0080 size: 16 bit */
+ int8_t SEMA4_reserved_0082[6];
+ /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
+ SEMA4_CP1NTF_16B_tag CP1NTF; /* offset: 0x0088 size: 16 bit */
+ int8_t SEMA4_reserved_008A[118];
+ /* SEMA4_RSTGT - Semaphores Reset Gate */
+ SEMA4_RSTGT_16B_tag RSTGT; /* offset: 0x0100 size: 16 bit */
+ int8_t SEMA4_reserved_0102[2];
+ /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
+ SEMA4_RSTNTF_16B_tag RSTNTF; /* offset: 0x0104 size: 16 bit */
+ } SEMA4_tag;
+
+
+#define SEMA4 (*(volatile SEMA4_tag *) 0xFFF24000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SWT */
+/* */
+/****************************************************************/
+
+ typedef union { /* SWT_CR - Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MAP0:1; /* Master Acces Protection for Master 0 */
+ vuint32_t MAP1:1; /* Master Acces Protection for Master 1 */
+ vuint32_t MAP2:1; /* Master Acces Protection for Master 2 */
+ vuint32_t MAP3:1; /* Master Acces Protection for Master 3 */
+ vuint32_t MAP4:1; /* Master Acces Protection for Master 4 */
+ vuint32_t MAP5:1; /* Master Acces Protection for Master 5 */
+ vuint32_t MAP6:1; /* Master Acces Protection for Master 6 */
+ vuint32_t MAP7:1; /* Master Acces Protection for Master 7 */
+ vuint32_t:14;
+ vuint32_t KEY:1; /* Keyed Service Mode */
+ vuint32_t RIA:1; /* Reset on Invalid Access */
+ vuint32_t WND:1; /* Window Mode */
+ vuint32_t ITR:1; /* Interrupt Then Reset */
+ vuint32_t HLK:1; /* Hard Lock */
+ vuint32_t SLK:1; /* Soft Lock */
+ vuint32_t CSL:1; /* Clock Selection */
+ vuint32_t STP:1; /* Stop Mode Control */
+ vuint32_t FRZ:1; /* Debug Mode Control */
+ vuint32_t WEN:1; /* Watchdog Enabled */
+ } B;
+ } SWT_CR_32B_tag;
+
+ typedef union { /* SWT_IR - SWT Interrupt Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t TIF:1; /* Time Out Interrupt Flag */
+ } B;
+ } SWT_IR_32B_tag;
+
+ typedef union { /* SWT_TO - SWT Time-Out Register */
+ vuint32_t R;
+ struct {
+ vuint32_t WTO:32; /* Watchdog Time Out Period */
+ } B;
+ } SWT_TO_32B_tag;
+
+ typedef union { /* SWT_WN - SWT Window Register */
+ vuint32_t R;
+ struct {
+ vuint32_t WST:32; /* Watchdog Time Out Period */
+ } B;
+ } SWT_WN_32B_tag;
+
+ typedef union { /* SWT_SR - SWT Service Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t WSC:16; /* Watchdog Service Code */
+ } B;
+ } SWT_SR_32B_tag;
+
+ typedef union { /* SWT_CO - SWT Counter Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t CNT:32; /* Watchdog Count */
+ } B;
+ } SWT_CO_32B_tag;
+
+ typedef union { /* SWT_SK - SWT Service Key Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SERVICEKEY:16; /* Service Key */
+ } B;
+ } SWT_SK_32B_tag;
+
+
+
+ typedef struct SWT_struct_tag { /* start of SWT_tag */
+ /* SWT_CR - Control Register */
+ SWT_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
+ /* SWT_IR - SWT Interrupt Register */
+ SWT_IR_32B_tag IR; /* offset: 0x0004 size: 32 bit */
+ /* SWT_TO - SWT Time-Out Register */
+ SWT_TO_32B_tag TO; /* offset: 0x0008 size: 32 bit */
+ /* SWT_WN - SWT Window Register */
+ SWT_WN_32B_tag WN; /* offset: 0x000C size: 32 bit */
+ /* SWT_SR - SWT Service Register */
+ SWT_SR_32B_tag SR; /* offset: 0x0010 size: 32 bit */
+ /* SWT_CO - SWT Counter Output Register */
+ SWT_CO_32B_tag CO; /* offset: 0x0014 size: 32 bit */
+ /* SWT_SK - SWT Service Key Register */
+ SWT_SK_32B_tag SK; /* offset: 0x0018 size: 32 bit */
+ } SWT_tag;
+
+
+#define SWT (*(volatile SWT_tag *) 0xFFF38000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: STM */
+/* */
+/****************************************************************/
+
+ typedef union { /* STM_CR - Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t CPS:8; /* Counter Prescaler */
+ vuint32_t:6;
+ vuint32_t FRZ:1; /* Freeze Control */
+ vuint32_t TEN:1; /* Timer Counter Enabled */
+ } B;
+ } STM_CR_32B_tag;
+
+ typedef union { /* STM_CNT - STM Count Register */
+ vuint32_t R;
+ } STM_CNT_32B_tag;
+
+
+ /* Register layout for all registers CCR... */
+
+ typedef union { /* STM_CCRn - STM Channel Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CEN:1; /* Channel Enable */
+ } B;
+ } STM_CCR_32B_tag;
+
+
+ /* Register layout for all registers CIR... */
+
+ typedef union { /* STM_CIRn - STM Channel Interrupt Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:31;
+ vuint32_t CIF:1; /* Channel Interrupt Flag */
+ } B;
+ } STM_CIR_32B_tag;
+
+
+ /* Register layout for all registers CMP... */
+
+ typedef union { /* STM_CMPn - STM Channel Compare Register */
+ vuint32_t R;
+ } STM_CMP_32B_tag;
+
+
+ typedef struct STM_CHANNEL_struct_tag {
+
+ /* STM_CCRn - STM Channel Control Register */
+ STM_CCR_32B_tag CCR; /* relative offset: 0x0000 */
+ /* STM_CIRn - STM Channel Interrupt Register */
+ STM_CIR_32B_tag CIR; /* relative offset: 0x0004 */
+ /* STM_CMPn - STM Channel Compare Register */
+ STM_CMP_32B_tag CMP; /* relative offset: 0x0008 */
+ int8_t STM_CHANNEL_reserved_000C[4];
+
+ } STM_CHANNEL_tag;
+
+
+ typedef struct STM_struct_tag { /* start of STM_tag */
+ union {
+ STM_CR_32B_tag CR0; /* deprecated - please avoid */
+
+ /* STM_CR - Control Register */
+ STM_CR_32B_tag CR; /* offset: 0x0000 size: 32 bit */
+
+ };
+ union {
+ STM_CNT_32B_tag CNT0; /* deprecated - please avoid */
+
+ /* STM_CNT - STM Count Register */
+ STM_CNT_32B_tag CNT; /* offset: 0x0004 size: 32 bit */
+
+ };
+ int8_t STM_reserved_0008_C[8];
+ union {
+ /* Register set CHANNEL */
+ STM_CHANNEL_tag CHANNEL[4]; /* offset: 0x0010 (0x0010 x 4) */
+
+ struct {
+ /* STM_CCRn - STM Channel Control Register */
+ STM_CCR_32B_tag CCR0; /* offset: 0x0010 size: 32 bit */
+ /* STM_CIRn - STM Channel Interrupt Register */
+ STM_CIR_32B_tag CIR0; /* offset: 0x0014 size: 32 bit */
+ /* STM_CMPn - STM Channel Compare Register */
+ STM_CMP_32B_tag CMP0; /* offset: 0x0018 size: 32 bit */
+ int8_t STM_reserved_001C_I1[4];
+ /* STM_CCRn - STM Channel Control Register */
+ STM_CCR_32B_tag CCR1; /* offset: 0x0020 size: 32 bit */
+ /* STM_CIRn - STM Channel Interrupt Register */
+ STM_CIR_32B_tag CIR1; /* offset: 0x0024 size: 32 bit */
+ /* STM_CMPn - STM Channel Compare Register */
+ STM_CMP_32B_tag CMP1; /* offset: 0x0028 size: 32 bit */
+ int8_t STM_reserved_002C_I1[4];
+ /* STM_CCRn - STM Channel Control Register */
+ STM_CCR_32B_tag CCR2; /* offset: 0x0030 size: 32 bit */
+ /* STM_CIRn - STM Channel Interrupt Register */
+ STM_CIR_32B_tag CIR2; /* offset: 0x0034 size: 32 bit */
+ /* STM_CMPn - STM Channel Compare Register */
+ STM_CMP_32B_tag CMP2; /* offset: 0x0038 size: 32 bit */
+ int8_t STM_reserved_003C_I1[4];
+ /* STM_CCRn - STM Channel Control Register */
+ STM_CCR_32B_tag CCR3; /* offset: 0x0040 size: 32 bit */
+ /* STM_CIRn - STM Channel Interrupt Register */
+ STM_CIR_32B_tag CIR3; /* offset: 0x0044 size: 32 bit */
+ /* STM_CMPn - STM Channel Compare Register */
+ STM_CMP_32B_tag CMP3; /* offset: 0x0048 size: 32 bit */
+ int8_t STM_reserved_004C_E1[4];
+ };
+
+ };
+ } STM_tag;
+
+
+#define STM (*(volatile STM_tag *) 0xFFF3C000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SPP_MCM */
+/* */
+/****************************************************************/
+
+ typedef union { /* SPP_MCM_PCT - Processor Core Type */
+ vuint16_t R;
+ struct {
+ vuint16_t PCTYPE:16; /* Processor Core Type */
+ } B;
+ } SPP_MCM_PCT_16B_tag;
+
+ typedef union { /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
+ vuint16_t R;
+ struct {
+ vuint16_t PLREVISION:16; /* Platform Revision */
+ } B;
+ } SPP_MCM_PLREV_16B_tag;
+
+ typedef union { /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
+ vuint32_t R;
+ struct {
+ vuint32_t PMC:32; /* IPS Module Configuration */
+ } B;
+ } SPP_MCM_IOPMC_32B_tag;
+
+ typedef union { /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
+ vuint8_t R;
+ struct {
+ vuint8_t POR:1; /* Power on Reset */
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t OFPLR:1; /* Off-Platform Reset */
+#else
+ vuint8_t DIR:1; /* deprecated name - please avoid */
+#endif
+ vuint8_t:6;
+ } B;
+ } SPP_MCM_MRSR_8B_tag;
+
+ typedef union { /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
+ vuint8_t R;
+ struct {
+ vuint8_t ENBWCR:1; /* Enable WCR */
+ vuint8_t:3;
+ vuint8_t PRILVL:4; /* Interrupt Priority Level */
+ } B;
+ } SPP_MCM_MWCR_8B_tag;
+
+ typedef union { /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
+ vuint8_t R;
+ struct {
+ vuint8_t FB0AI:1; /* Flash Bank 0 Abort Interrupt */
+ vuint8_t FB0SI:1; /* Flash Bank 0 Stall Interrupt */
+ vuint8_t FB1AI:1; /* Flash Bank 1 Abort Interrupt */
+ vuint8_t FB1SI:1; /* Flash Bank 1 Stall Interrupt */
+ vuint8_t FB2AI:1; /* Flash Bank 2 Abort Interrupt */
+ vuint8_t FB2SI:1; /* Flash Bank 2 Stall Interrupt */
+ vuint8_t:2;
+ } B;
+ } SPP_MCM_MIR_8B_tag;
+
+ typedef union { /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MUSERDCR:32; /* User Defined Control Register */
+ } B;
+ } SPP_MCM_MUDCR_32B_tag;
+
+ typedef union { /* SPP_MCM_ECR - ECC Configuration Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t EPR1BR:1; /* Enable Platform RAM 1-bit Reporting */
+#else
+ vuint8_t ER1BR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t EPF1BR:1; /* Enable Platform FLASH 1-bit Reporting */
+#else
+ vuint8_t EF1BR:1; /* deprecated name - please avoid */
+#endif
+ vuint8_t:2;
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t EPRNCR:1; /* Enable Platform RAM Non-Correctable Reporting */
+#else
+ vuint8_t ERNCR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t EPFNCR:1; /* Enable Platform FLASH Non-Correctable Reporting */
+#else
+ vuint8_t EFNCR:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SPP_MCM_ECR_8B_tag;
+
+ typedef union { /* SPP_MCM_ESR - ECC Status Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:2;
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t PR1BC:1; /* Platform RAM 1-bit Correction */
+#else
+ vuint8_t R1BC:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t PF1BC:1; /* Platform FLASH 1-bit Correction */
+#else
+ vuint8_t F1BC:1; /* deprecated name - please avoid */
+#endif
+ vuint8_t:2;
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t PRNCE:1; /* Platform RAM Non-Correctable Error */
+#else
+ vuint8_t RNCE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t PFNCE:1; /* Platform FLASH Non-Correctable Error */
+#else
+ vuint8_t FNCE:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SPP_MCM_ESR_8B_tag;
+
+ typedef union { /* SPP_MCM_EEGR - ECC Error Generation Register */
+ vuint16_t R;
+ struct {
+ vuint16_t FRCAP:1; /* Force Platform RAM Error Injection Access Protection */
+ vuint16_t:1;
+ vuint16_t FRC1BI:1; /* Force Platform RAM Continuous 1-Bit Data Inversions */
+ vuint16_t FR11BI:1; /* Force Platform RAM One 1-Bit Data Inversion */
+ vuint16_t:2;
+ vuint16_t FRCNCI:1; /* Force Platform RAM Continuous Noncorrectable Data Inversions */
+ vuint16_t FR1NCI:1; /* Force Platform RAM One Noncorrectable Data Inversions */
+ vuint16_t:1;
+ vuint16_t ERRBIT:7; /* Error Bit Position */
+ } B;
+ } SPP_MCM_EEGR_16B_tag;
+
+ typedef union { /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
+ vuint32_t R;
+ } SPP_MCM_PFEAR_32B_tag;
+
+ typedef union { /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
+ vuint8_t R;
+ } SPP_MCM_PFEMR_8B_tag;
+
+ typedef union { /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
+ vuint8_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t F_WRITE:1; /* AMBA-AHBH Write */
+#else
+ vuint8_t WRITE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t F_SIZE:3; /* AMBA-AHBH Size */
+#else
+ vuint8_t SIZE:3; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t F_PROTECT:4; /* AMBA-AHBH PROT */
+#else
+ vuint8_t PROTECTION:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SPP_MCM_PFEAT_8B_tag;
+
+ typedef union { /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
+ vuint32_t R;
+ } SPP_MCM_PFEDRH_32B_tag;
+
+ typedef union { /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
+ vuint32_t R;
+ } SPP_MCM_PFEDR_32B_tag;
+
+ typedef union { /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
+ vuint32_t R;
+ } SPP_MCM_PREAR_32B_tag;
+
+ typedef union { /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
+ vuint8_t R;
+ } SPP_MCM_PRESR_8B_tag;
+
+ typedef union { /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:4;
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t PR_EMR:4; /* Platform RAM ECC Master Number */
+#else
+ vuint8_t REMR:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SPP_MCM_PREMR_8B_tag;
+
+ typedef union { /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
+ vuint8_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t R_WRITE:1; /* AMBA-AHBH Write */
+#else
+ vuint8_t WRITE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t R_SIZE:3; /* AMBA-AHBH Size */
+#else
+ vuint8_t SIZE:3; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_SPP_MCM
+ vuint8_t R_PROTECT:4; /* AMBA-AHBH PROT */
+#else
+ vuint8_t PROTECTION:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } SPP_MCM_PREAT_8B_tag;
+
+ typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
+ vuint32_t R;
+ } SPP_MCM_PREDRH_32B_tag;
+
+ typedef union { /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
+ vuint32_t R;
+ } SPP_MCM_PREDR_32B_tag;
+
+
+
+ typedef struct SPP_MCM_struct_tag { /* start of SPP_MCM_tag */
+ /* SPP_MCM_PCT - Processor Core Type */
+ SPP_MCM_PCT_16B_tag PCT; /* offset: 0x0000 size: 16 bit */
+ union {
+ SPP_MCM_PLREV_16B_tag REV; /* deprecated - please avoid */
+
+ /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
+ SPP_MCM_PLREV_16B_tag PLREV; /* offset: 0x0002 size: 16 bit */
+
+ };
+ int8_t SPP_MCM_reserved_0004_C[4];
+ union {
+ SPP_MCM_IOPMC_32B_tag MC; /* deprecated - please avoid */
+
+ /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
+ SPP_MCM_IOPMC_32B_tag IOPMC; /* offset: 0x0008 size: 32 bit */
+
+ };
+ int8_t SPP_MCM_reserved_000C[3];
+ /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
+ SPP_MCM_MRSR_8B_tag MRSR; /* offset: 0x000F size: 8 bit */
+ int8_t SPP_MCM_reserved_0010[3];
+ /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
+ SPP_MCM_MWCR_8B_tag MWCR; /* offset: 0x0013 size: 8 bit */
+ int8_t SPP_MCM_reserved_0014[11];
+ /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
+ SPP_MCM_MIR_8B_tag MIR; /* offset: 0x001F size: 8 bit */
+ int8_t SPP_MCM_reserved_0020[4];
+ /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
+ SPP_MCM_MUDCR_32B_tag MUDCR; /* offset: 0x0024 size: 32 bit */
+ int8_t SPP_MCM_reserved_0028[27];
+ /* SPP_MCM_ECR - ECC Configuration Register */
+ SPP_MCM_ECR_8B_tag ECR; /* offset: 0x0043 size: 8 bit */
+ int8_t SPP_MCM_reserved_0044[3];
+ /* SPP_MCM_ESR - ECC Status Register */
+ SPP_MCM_ESR_8B_tag ESR; /* offset: 0x0047 size: 8 bit */
+ int8_t SPP_MCM_reserved_0048[2];
+ /* SPP_MCM_EEGR - ECC Error Generation Register */
+ SPP_MCM_EEGR_16B_tag EEGR; /* offset: 0x004A size: 16 bit */
+ int8_t SPP_MCM_reserved_004C_C[4];
+ union {
+ /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
+ SPP_MCM_PFEAR_32B_tag PFEAR; /* offset: 0x0050 size: 32 bit */
+
+ SPP_MCM_PFEAR_32B_tag FEAR; /* deprecated - please avoid */
+
+ };
+ int8_t SPP_MCM_reserved_0054_C[2];
+ union {
+ /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
+ SPP_MCM_PFEMR_8B_tag PFEMR; /* offset: 0x0056 size: 8 bit */
+
+ SPP_MCM_PFEMR_8B_tag FEMR; /* deprecated - please avoid */
+
+ };
+ union {
+ /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
+ SPP_MCM_PFEAT_8B_tag PFEAT; /* offset: 0x0057 size: 8 bit */
+
+ SPP_MCM_PFEAT_8B_tag FEAT; /* deprecated - please avoid */
+
+ };
+ /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
+ SPP_MCM_PFEDRH_32B_tag PFEDRH; /* offset: 0x0058 size: 32 bit */
+ union {
+ /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
+ SPP_MCM_PFEDR_32B_tag PFEDR; /* offset: 0x005C size: 32 bit */
+
+ SPP_MCM_PFEDR_32B_tag FEDR; /* deprecated - please avoid */
+
+ };
+ union {
+ SPP_MCM_PREAR_32B_tag REAR; /* deprecated - please avoid */
+
+ /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
+ SPP_MCM_PREAR_32B_tag PREAR; /* offset: 0x0060 size: 32 bit */
+
+ };
+ int8_t SPP_MCM_reserved_0064_C;
+ union {
+ SPP_MCM_PRESR_8B_tag RESR; /* deprecated - please avoid */
+
+ /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
+ SPP_MCM_PRESR_8B_tag PRESR; /* offset: 0x0065 size: 8 bit */
+
+ };
+ union {
+ SPP_MCM_PREMR_8B_tag REMR; /* deprecated - please avoid */
+
+ /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
+ SPP_MCM_PREMR_8B_tag PREMR; /* offset: 0x0066 size: 8 bit */
+
+ };
+ union {
+ SPP_MCM_PREAT_8B_tag REAT; /* deprecated - please avoid */
+
+ /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
+ SPP_MCM_PREAT_8B_tag PREAT; /* offset: 0x0067 size: 8 bit */
+
+ };
+ /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
+ SPP_MCM_PREDRH_32B_tag PREDRH; /* offset: 0x0068 size: 32 bit */
+ union {
+ SPP_MCM_PREDR_32B_tag REDR; /* deprecated - please avoid */
+
+ /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
+ SPP_MCM_PREDR_32B_tag PREDR; /* offset: 0x006C size: 32 bit */
+
+ };
+ } SPP_MCM_tag;
+
+
+#define SPP_MCM (*(volatile SPP_MCM_tag *) 0xFFF40000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: SPP_DMA2 */
+/* */
+/****************************************************************/
+
+ typedef union { /* SPP_DMA2_DMACR - DMA Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t CX:1; /* Cancel Transfer */
+ vuint32_t ECX:1; /* Error Cancel Transfer */
+ vuint32_t GRP3PRI:2; /* Channel Group 3 Priority */
+ vuint32_t GRP2PRI:2; /* Channel Group 2 Priority */
+ vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */
+ vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */
+ vuint32_t EMLM:1; /* Enable Minor Loop Mapping */
+ vuint32_t CLM:1; /* Continuous Link Mode */
+ vuint32_t HALT:1; /* Halt DMA Operations */
+ vuint32_t HOE:1; /* Halt on Error */
+ vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */
+ vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */
+ vuint32_t EDBG:1; /* Enable Debug */
+ vuint32_t EBW:1; /* Enable Buffered Writes */
+ } B;
+ } SPP_DMA2_DMACR_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAES - DMA Error Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t VLD:1; /* Logical OR of DMAERRH and DMAERRL status bits */
+ vuint32_t:14;
+ vuint32_t ECX:1; /* Transfer Cancelled */
+ vuint32_t GPE:1; /* Group Priority Error */
+ vuint32_t CPE:1; /* Channel Priority Error */
+ vuint32_t ERRCHN:6; /* Error Channel Number or Cancelled Channel Number */
+ vuint32_t SAE:1; /* Source Address Error */
+ vuint32_t SOE:1; /* Source Offset Error */
+ vuint32_t DAE:1; /* Destination Address Error */
+ vuint32_t DOE:1; /* Destination Offset Error */
+ vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */
+ vuint32_t SGE:1; /* Scatter/Gather Configuration Error */
+ vuint32_t SBE:1; /* Source Bus Error */
+ vuint32_t DBE:1; /* Destination Bus Error */
+ } B;
+ } SPP_DMA2_DMAES_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ:32; /* DMA Enable Request */
+ } B;
+ } SPP_DMA2_DMAERQH_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
+ vuint32_t R;
+ struct {
+ vuint32_t ERQ:32; /* DMA Enable Request */
+ } B;
+ } SPP_DMA2_DMAERQL_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EEI:32; /* DMA Enable Error Interrupt */
+ } B;
+ } SPP_DMA2_DMAEEIH_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
+ vuint32_t R;
+ struct {
+ vuint32_t EEI:32; /* DMA Enable Error Interrupt */
+ } B;
+ } SPP_DMA2_DMAEEIL_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SERQ:7; /* Set Enable Request */
+ } B;
+ } SPP_DMA2_DMASERQ_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CERQ:7; /* Clear Enable Request */
+ } B;
+ } SPP_DMA2_DMACERQ_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SEEI:7; /* Set Enable Error Interrupt */
+ } B;
+ } SPP_DMA2_DMASEEI_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CEEI:7; /* Clear Enable Error Interrupt */
+ } B;
+ } SPP_DMA2_DMACEEI_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CINT:7; /* Clear Interrupt Request */
+ } B;
+ } SPP_DMA2_DMACINT_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMACERR - DMA Clear Error */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CERR:7; /* Clear Error Indicator */
+ } B;
+ } SPP_DMA2_DMACERR_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMASSRT - DMA Set START Bit */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t SSRT:7; /* Set START Bit */
+ } B;
+ } SPP_DMA2_DMASSRT_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
+ vuint8_t R;
+ struct {
+ vuint8_t:1;
+ vuint8_t CDNE:7; /* Clear DONE Status Bit */
+ } B;
+ } SPP_DMA2_DMACDNE_8B_tag;
+
+ typedef union { /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
+ vuint32_t R;
+ struct {
+ vuint32_t INT:32; /* DMA Interrupt Request */
+ } B;
+ } SPP_DMA2_DMAINTH_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
+ vuint32_t R;
+ struct {
+ vuint32_t INT:32; /* DMA Interrupt Request */
+ } B;
+ } SPP_DMA2_DMAINTL_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAERRH - DMA Error Register */
+ vuint32_t R;
+ struct {
+ vuint32_t ERR:32; /* DMA Error n */
+ } B;
+ } SPP_DMA2_DMAERRH_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAERRL - DMA Error Register */
+ vuint32_t R;
+ struct {
+ vuint32_t ERR:32; /* DMA Error n */
+ } B;
+ } SPP_DMA2_DMAERRL_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HRS:32; /* DMA Hardware Request Status */
+ } B;
+ } SPP_DMA2_DMAHRSH_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t HRS:32; /* DMA Hardware Request Status */
+ } B;
+ } SPP_DMA2_DMAHRSL_32B_tag;
+
+ typedef union { /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
+ vuint32_t R;
+ struct {
+ vuint32_t GPOR:32; /* DMA General Purpose Output */
+ } B;
+ } SPP_DMA2_DMAGPOR_32B_tag;
+
+
+ /* Register layout for all registers DCHPRI... */
+
+ typedef union { /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
+ vuint8_t R;
+ struct {
+ vuint8_t ECP:1; /* Enable Channel Preemption */
+ vuint8_t DPA:1; /* Disable Preempt Ability */
+ vuint8_t GRPPRI:2; /* Channel n Current Group Priority */
+ vuint8_t CHPRI:4; /* Channel n Arbitration Priority */
+ } B;
+ } SPP_DMA2_DCHPRI_8B_tag;
+
+
+ /* Register layout for all registers TCDWORD0_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word0 - Source Address */
+ vuint32_t R;
+ struct {
+ vuint32_t SADDR:32; /* Source Address */
+ } B;
+ } SPP_DMA2_TCDWORD0__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD4_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ vuint32_t R;
+ struct {
+ vuint32_t SMOD:5; /* Source Address Modulo */
+ vuint32_t SSIZE:3; /* Source Data Transfer Size */
+ vuint32_t DMOD:5; /* Destination Address Module */
+ vuint32_t DSIZE:3; /* Destination Data Transfer Size */
+ vuint32_t SOFF:16; /* Source Address Signed Offset */
+ } B;
+ } SPP_DMA2_TCDWORD4__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD8_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word2 - nbytes */
+ vuint32_t R;
+ struct {
+ vuint32_t SMLOE:1; /* Source Minor Loop Offset Enable */
+ vuint32_t DMLOE:1; /* Destination Minor Loop Offset Enable */
+ vuint32_t MLOFF:20; /* Minor Loop Offset */
+ vuint32_t NBYTES:10; /* Inner Minor byte transfer Count */
+ } B;
+ } SPP_DMA2_TCDWORD8__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD12_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word3 - slast */
+ vuint32_t R;
+ struct {
+ vuint32_t SLAST:32; /* Last Source Address Adjustment */
+ } B;
+ } SPP_DMA2_TCDWORD12__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD16_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word4 - daddr */
+ vuint32_t R;
+ struct {
+ vuint32_t DADDR:32; /* Destination Address */
+ } B;
+ } SPP_DMA2_TCDWORD16__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD20_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ vuint32_t R;
+ struct {
+ vuint32_t CITER_E_LINK:1; /* Enable Channel to channel linking on minor loop complete */
+ vuint32_t CITER_LINKCH:6; /* Link Channel Number */
+ vuint32_t CITER:9; /* Current Major Iteration Count */
+ vuint32_t DOFF:16; /* Destination Address Signed Offset */
+ } B;
+ } SPP_DMA2_TCDWORD20__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD24_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ vuint32_t R;
+ struct {
+ vuint32_t DLAST_SGA:32; /* Last destination address adjustment */
+ } B;
+ } SPP_DMA2_TCDWORD24__32B_tag;
+
+
+ /* Register layout for all registers TCDWORD28_... */
+
+ typedef union { /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ vuint32_t R;
+ struct {
+ vuint32_t BITER:16; /* Enable Channel to Channel linking on minor loop complete */
+ vuint32_t BWC:2; /* Bandwidth Control */
+ vuint32_t MAJOR_LINKCH:6; /* Link Channel Number */
+ vuint32_t DONE:1; /* channel done */
+ vuint32_t ACTIVE:1; /* Channel Active */
+ vuint32_t MAJOR_E_LINK:1; /* Enable Channel to Channel Linking on major loop complete */
+ vuint32_t E_SG:1; /* Enable Scatter/Gather Processing */
+ vuint32_t D_REQ:1; /* Disable Request */
+ vuint32_t INT_HALF:1; /* Enable an Interrupt when Major Counter is half complete */
+ vuint32_t INT_MAJ:1; /* Enable an Interrupt when Major Iteration count completes */
+ vuint32_t START:1; /* Channel Start */
+ } B;
+ } SPP_DMA2_TCDWORD28__32B_tag;
+
+
+ typedef struct SPP_DMA2_CHANNEL_struct_tag {
+
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_; /* relative offset: 0x0000 */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_; /* relative offset: 0x0004 */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_; /* relative offset: 0x0008 */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_; /* relative offset: 0x000C */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_; /* relative offset: 0x0010 */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_; /* relative offset: 0x0014 */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_; /* relative offset: 0x0018 */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_; /* relative offset: 0x001C */
+
+ } SPP_DMA2_CHANNEL_tag;
+
+
+ typedef struct SPP_DMA2_struct_tag { /* start of SPP_DMA2_tag */
+ /* SPP_DMA2_DMACR - DMA Control Register */
+ SPP_DMA2_DMACR_32B_tag DMACR; /* offset: 0x0000 size: 32 bit */
+ /* SPP_DMA2_DMAES - DMA Error Status Register */
+ SPP_DMA2_DMAES_32B_tag DMAES; /* offset: 0x0004 size: 32 bit */
+ /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
+ SPP_DMA2_DMAERQH_32B_tag DMAERQH; /* offset: 0x0008 size: 32 bit */
+ /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
+ SPP_DMA2_DMAERQL_32B_tag DMAERQL; /* offset: 0x000C size: 32 bit */
+ /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
+ SPP_DMA2_DMAEEIH_32B_tag DMAEEIH; /* offset: 0x0010 size: 32 bit */
+ /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
+ SPP_DMA2_DMAEEIL_32B_tag DMAEEIL; /* offset: 0x0014 size: 32 bit */
+ /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
+ SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */
+ /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
+ SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */
+ /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
+ SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */
+ /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
+ SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */
+ /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
+ SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */
+ /* SPP_DMA2_DMACERR - DMA Clear Error */
+ SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */
+ /* SPP_DMA2_DMASSRT - DMA Set START Bit */
+ SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */
+ /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
+ SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */
+ /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
+ SPP_DMA2_DMAINTH_32B_tag DMAINTH; /* offset: 0x0020 size: 32 bit */
+ /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
+ SPP_DMA2_DMAINTL_32B_tag DMAINTL; /* offset: 0x0024 size: 32 bit */
+ /* SPP_DMA2_DMAERRH - DMA Error Register */
+ SPP_DMA2_DMAERRH_32B_tag DMAERRH; /* offset: 0x0028 size: 32 bit */
+ /* SPP_DMA2_DMAERRL - DMA Error Register */
+ SPP_DMA2_DMAERRL_32B_tag DMAERRL; /* offset: 0x002C size: 32 bit */
+ /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
+ SPP_DMA2_DMAHRSH_32B_tag DMAHRSH; /* offset: 0x0030 size: 32 bit */
+ /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
+ SPP_DMA2_DMAHRSL_32B_tag DMAHRSL; /* offset: 0x0034 size: 32 bit */
+ /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
+ SPP_DMA2_DMAGPOR_32B_tag DMAGPOR; /* offset: 0x0038 size: 32 bit */
+ int8_t SPP_DMA2_reserved_003C_C[196];
+ union {
+ /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI[64]; /* offset: 0x0100 (0x0001 x 64) */
+
+ struct {
+ /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI0; /* offset: 0x0100 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI1; /* offset: 0x0101 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI2; /* offset: 0x0102 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI3; /* offset: 0x0103 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI4; /* offset: 0x0104 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI5; /* offset: 0x0105 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI6; /* offset: 0x0106 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI7; /* offset: 0x0107 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI8; /* offset: 0x0108 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI9; /* offset: 0x0109 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI10; /* offset: 0x010A size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI11; /* offset: 0x010B size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI12; /* offset: 0x010C size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI13; /* offset: 0x010D size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI14; /* offset: 0x010E size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI15; /* offset: 0x010F size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI16; /* offset: 0x0110 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI17; /* offset: 0x0111 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI18; /* offset: 0x0112 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI19; /* offset: 0x0113 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI20; /* offset: 0x0114 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI21; /* offset: 0x0115 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI22; /* offset: 0x0116 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI23; /* offset: 0x0117 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI24; /* offset: 0x0118 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI25; /* offset: 0x0119 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI26; /* offset: 0x011A size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI27; /* offset: 0x011B size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI28; /* offset: 0x011C size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI29; /* offset: 0x011D size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI30; /* offset: 0x011E size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI31; /* offset: 0x011F size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI32; /* offset: 0x0120 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI33; /* offset: 0x0121 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI34; /* offset: 0x0122 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI35; /* offset: 0x0123 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI36; /* offset: 0x0124 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI37; /* offset: 0x0125 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI38; /* offset: 0x0126 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI39; /* offset: 0x0127 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI40; /* offset: 0x0128 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI41; /* offset: 0x0129 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI42; /* offset: 0x012A size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI43; /* offset: 0x012B size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI44; /* offset: 0x012C size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI45; /* offset: 0x012D size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI46; /* offset: 0x012E size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI47; /* offset: 0x012F size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI48; /* offset: 0x0130 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI49; /* offset: 0x0131 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI50; /* offset: 0x0132 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI51; /* offset: 0x0133 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI52; /* offset: 0x0134 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI53; /* offset: 0x0135 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI54; /* offset: 0x0136 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI55; /* offset: 0x0137 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI56; /* offset: 0x0138 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI57; /* offset: 0x0139 size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI58; /* offset: 0x013A size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI59; /* offset: 0x013B size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI60; /* offset: 0x013C size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI61; /* offset: 0x013D size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI62; /* offset: 0x013E size: 8 bit */
+ SPP_DMA2_DCHPRI_8B_tag DCHPRI63; /* offset: 0x013F size: 8 bit */
+ };
+
+ };
+ int8_t SPP_DMA2_reserved_0140_C[3776];
+ union {
+ /* Register set CHANNEL */
+ SPP_DMA2_CHANNEL_tag CHANNEL[64]; /* offset: 0x1000 (0x0020 x 64) */
+
+ struct {
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0; /* offset: 0x1000 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0; /* offset: 0x1004 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0; /* offset: 0x1008 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0; /* offset: 0x100C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0; /* offset: 0x1010 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0; /* offset: 0x1014 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0; /* offset: 0x1018 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0; /* offset: 0x101C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1; /* offset: 0x1020 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1; /* offset: 0x1024 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1; /* offset: 0x1028 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1; /* offset: 0x102C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1; /* offset: 0x1030 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1; /* offset: 0x1034 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1; /* offset: 0x1038 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1; /* offset: 0x103C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2; /* offset: 0x1040 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2; /* offset: 0x1044 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2; /* offset: 0x1048 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2; /* offset: 0x104C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2; /* offset: 0x1050 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2; /* offset: 0x1054 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2; /* offset: 0x1058 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2; /* offset: 0x105C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3; /* offset: 0x1060 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3; /* offset: 0x1064 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3; /* offset: 0x1068 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3; /* offset: 0x106C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3; /* offset: 0x1070 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3; /* offset: 0x1074 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3; /* offset: 0x1078 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3; /* offset: 0x107C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4; /* offset: 0x1080 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4; /* offset: 0x1084 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4; /* offset: 0x1088 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4; /* offset: 0x108C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4; /* offset: 0x1090 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4; /* offset: 0x1094 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4; /* offset: 0x1098 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4; /* offset: 0x109C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5; /* offset: 0x10A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5; /* offset: 0x10A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5; /* offset: 0x10A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5; /* offset: 0x10AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5; /* offset: 0x10B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5; /* offset: 0x10B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5; /* offset: 0x10B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5; /* offset: 0x10BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6; /* offset: 0x10C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6; /* offset: 0x10C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6; /* offset: 0x10C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6; /* offset: 0x10CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6; /* offset: 0x10D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6; /* offset: 0x10D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6; /* offset: 0x10D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6; /* offset: 0x10DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7; /* offset: 0x10E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7; /* offset: 0x10E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7; /* offset: 0x10E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7; /* offset: 0x10EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7; /* offset: 0x10F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7; /* offset: 0x10F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7; /* offset: 0x10F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7; /* offset: 0x10FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8; /* offset: 0x1100 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8; /* offset: 0x1104 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8; /* offset: 0x1108 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8; /* offset: 0x110C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8; /* offset: 0x1110 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8; /* offset: 0x1114 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8; /* offset: 0x1118 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8; /* offset: 0x111C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9; /* offset: 0x1120 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9; /* offset: 0x1124 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9; /* offset: 0x1128 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9; /* offset: 0x112C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9; /* offset: 0x1130 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9; /* offset: 0x1134 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9; /* offset: 0x1138 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9; /* offset: 0x113C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10; /* offset: 0x1140 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10; /* offset: 0x1144 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10; /* offset: 0x1148 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10; /* offset: 0x114C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10; /* offset: 0x1150 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10; /* offset: 0x1154 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10; /* offset: 0x1158 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10; /* offset: 0x115C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11; /* offset: 0x1160 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11; /* offset: 0x1164 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11; /* offset: 0x1168 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11; /* offset: 0x116C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11; /* offset: 0x1170 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11; /* offset: 0x1174 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11; /* offset: 0x1178 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11; /* offset: 0x117C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12; /* offset: 0x1180 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12; /* offset: 0x1184 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12; /* offset: 0x1188 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12; /* offset: 0x118C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12; /* offset: 0x1190 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12; /* offset: 0x1194 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12; /* offset: 0x1198 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12; /* offset: 0x119C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13; /* offset: 0x11A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13; /* offset: 0x11A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13; /* offset: 0x11A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13; /* offset: 0x11AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13; /* offset: 0x11B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13; /* offset: 0x11B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13; /* offset: 0x11B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13; /* offset: 0x11BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14; /* offset: 0x11C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14; /* offset: 0x11C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14; /* offset: 0x11C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14; /* offset: 0x11CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14; /* offset: 0x11D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14; /* offset: 0x11D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14; /* offset: 0x11D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14; /* offset: 0x11DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15; /* offset: 0x11E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15; /* offset: 0x11E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15; /* offset: 0x11E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15; /* offset: 0x11EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15; /* offset: 0x11F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15; /* offset: 0x11F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15; /* offset: 0x11F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15; /* offset: 0x11FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16; /* offset: 0x1200 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16; /* offset: 0x1204 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16; /* offset: 0x1208 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16; /* offset: 0x120C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16; /* offset: 0x1210 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16; /* offset: 0x1214 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16; /* offset: 0x1218 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16; /* offset: 0x121C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17; /* offset: 0x1220 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17; /* offset: 0x1224 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17; /* offset: 0x1228 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17; /* offset: 0x122C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17; /* offset: 0x1230 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17; /* offset: 0x1234 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17; /* offset: 0x1238 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17; /* offset: 0x123C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18; /* offset: 0x1240 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18; /* offset: 0x1244 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18; /* offset: 0x1248 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18; /* offset: 0x124C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18; /* offset: 0x1250 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18; /* offset: 0x1254 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18; /* offset: 0x1258 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18; /* offset: 0x125C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19; /* offset: 0x1260 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19; /* offset: 0x1264 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19; /* offset: 0x1268 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19; /* offset: 0x126C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19; /* offset: 0x1270 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19; /* offset: 0x1274 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19; /* offset: 0x1278 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19; /* offset: 0x127C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20; /* offset: 0x1280 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20; /* offset: 0x1284 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20; /* offset: 0x1288 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20; /* offset: 0x128C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20; /* offset: 0x1290 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20; /* offset: 0x1294 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20; /* offset: 0x1298 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20; /* offset: 0x129C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21; /* offset: 0x12A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21; /* offset: 0x12A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21; /* offset: 0x12A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21; /* offset: 0x12AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21; /* offset: 0x12B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21; /* offset: 0x12B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21; /* offset: 0x12B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21; /* offset: 0x12BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22; /* offset: 0x12C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22; /* offset: 0x12C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22; /* offset: 0x12C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22; /* offset: 0x12CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22; /* offset: 0x12D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22; /* offset: 0x12D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22; /* offset: 0x12D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22; /* offset: 0x12DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23; /* offset: 0x12E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23; /* offset: 0x12E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23; /* offset: 0x12E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23; /* offset: 0x12EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23; /* offset: 0x12F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23; /* offset: 0x12F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23; /* offset: 0x12F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23; /* offset: 0x12FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24; /* offset: 0x1300 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24; /* offset: 0x1304 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24; /* offset: 0x1308 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24; /* offset: 0x130C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24; /* offset: 0x1310 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24; /* offset: 0x1314 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24; /* offset: 0x1318 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24; /* offset: 0x131C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25; /* offset: 0x1320 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25; /* offset: 0x1324 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25; /* offset: 0x1328 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25; /* offset: 0x132C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25; /* offset: 0x1330 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25; /* offset: 0x1334 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25; /* offset: 0x1338 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25; /* offset: 0x133C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26; /* offset: 0x1340 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26; /* offset: 0x1344 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26; /* offset: 0x1348 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26; /* offset: 0x134C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26; /* offset: 0x1350 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26; /* offset: 0x1354 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26; /* offset: 0x1358 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26; /* offset: 0x135C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27; /* offset: 0x1360 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27; /* offset: 0x1364 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27; /* offset: 0x1368 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27; /* offset: 0x136C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27; /* offset: 0x1370 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27; /* offset: 0x1374 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27; /* offset: 0x1378 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27; /* offset: 0x137C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28; /* offset: 0x1380 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28; /* offset: 0x1384 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28; /* offset: 0x1388 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28; /* offset: 0x138C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28; /* offset: 0x1390 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28; /* offset: 0x1394 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28; /* offset: 0x1398 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28; /* offset: 0x139C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29; /* offset: 0x13A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29; /* offset: 0x13A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29; /* offset: 0x13A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29; /* offset: 0x13AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29; /* offset: 0x13B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29; /* offset: 0x13B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29; /* offset: 0x13B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29; /* offset: 0x13BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30; /* offset: 0x13C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30; /* offset: 0x13C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30; /* offset: 0x13C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30; /* offset: 0x13CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30; /* offset: 0x13D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30; /* offset: 0x13D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30; /* offset: 0x13D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30; /* offset: 0x13DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31; /* offset: 0x13E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31; /* offset: 0x13E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31; /* offset: 0x13E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31; /* offset: 0x13EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31; /* offset: 0x13F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31; /* offset: 0x13F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31; /* offset: 0x13F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31; /* offset: 0x13FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32; /* offset: 0x1400 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32; /* offset: 0x1404 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32; /* offset: 0x1408 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32; /* offset: 0x140C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32; /* offset: 0x1410 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32; /* offset: 0x1414 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32; /* offset: 0x1418 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32; /* offset: 0x141C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33; /* offset: 0x1420 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33; /* offset: 0x1424 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33; /* offset: 0x1428 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33; /* offset: 0x142C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33; /* offset: 0x1430 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33; /* offset: 0x1434 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33; /* offset: 0x1438 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33; /* offset: 0x143C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34; /* offset: 0x1440 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34; /* offset: 0x1444 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34; /* offset: 0x1448 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34; /* offset: 0x144C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34; /* offset: 0x1450 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34; /* offset: 0x1454 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34; /* offset: 0x1458 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34; /* offset: 0x145C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35; /* offset: 0x1460 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35; /* offset: 0x1464 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35; /* offset: 0x1468 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35; /* offset: 0x146C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35; /* offset: 0x1470 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35; /* offset: 0x1474 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35; /* offset: 0x1478 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35; /* offset: 0x147C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36; /* offset: 0x1480 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36; /* offset: 0x1484 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36; /* offset: 0x1488 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36; /* offset: 0x148C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36; /* offset: 0x1490 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36; /* offset: 0x1494 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36; /* offset: 0x1498 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36; /* offset: 0x149C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37; /* offset: 0x14A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37; /* offset: 0x14A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37; /* offset: 0x14A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37; /* offset: 0x14AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37; /* offset: 0x14B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37; /* offset: 0x14B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37; /* offset: 0x14B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37; /* offset: 0x14BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38; /* offset: 0x14C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38; /* offset: 0x14C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38; /* offset: 0x14C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38; /* offset: 0x14CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38; /* offset: 0x14D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38; /* offset: 0x14D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38; /* offset: 0x14D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38; /* offset: 0x14DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39; /* offset: 0x14E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39; /* offset: 0x14E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39; /* offset: 0x14E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39; /* offset: 0x14EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39; /* offset: 0x14F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39; /* offset: 0x14F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39; /* offset: 0x14F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39; /* offset: 0x14FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40; /* offset: 0x1500 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40; /* offset: 0x1504 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40; /* offset: 0x1508 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40; /* offset: 0x150C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40; /* offset: 0x1510 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40; /* offset: 0x1514 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40; /* offset: 0x1518 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40; /* offset: 0x151C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41; /* offset: 0x1520 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41; /* offset: 0x1524 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41; /* offset: 0x1528 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41; /* offset: 0x152C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41; /* offset: 0x1530 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41; /* offset: 0x1534 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41; /* offset: 0x1538 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41; /* offset: 0x153C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42; /* offset: 0x1540 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42; /* offset: 0x1544 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42; /* offset: 0x1548 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42; /* offset: 0x154C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42; /* offset: 0x1550 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42; /* offset: 0x1554 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42; /* offset: 0x1558 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42; /* offset: 0x155C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43; /* offset: 0x1560 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43; /* offset: 0x1564 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43; /* offset: 0x1568 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43; /* offset: 0x156C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43; /* offset: 0x1570 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43; /* offset: 0x1574 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43; /* offset: 0x1578 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43; /* offset: 0x157C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44; /* offset: 0x1580 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44; /* offset: 0x1584 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44; /* offset: 0x1588 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44; /* offset: 0x158C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44; /* offset: 0x1590 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44; /* offset: 0x1594 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44; /* offset: 0x1598 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44; /* offset: 0x159C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45; /* offset: 0x15A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45; /* offset: 0x15A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45; /* offset: 0x15A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45; /* offset: 0x15AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45; /* offset: 0x15B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45; /* offset: 0x15B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45; /* offset: 0x15B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45; /* offset: 0x15BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46; /* offset: 0x15C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46; /* offset: 0x15C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46; /* offset: 0x15C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46; /* offset: 0x15CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46; /* offset: 0x15D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46; /* offset: 0x15D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46; /* offset: 0x15D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46; /* offset: 0x15DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47; /* offset: 0x15E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47; /* offset: 0x15E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47; /* offset: 0x15E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47; /* offset: 0x15EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47; /* offset: 0x15F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47; /* offset: 0x15F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47; /* offset: 0x15F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47; /* offset: 0x15FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48; /* offset: 0x1600 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48; /* offset: 0x1604 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48; /* offset: 0x1608 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48; /* offset: 0x160C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48; /* offset: 0x1610 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48; /* offset: 0x1614 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48; /* offset: 0x1618 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48; /* offset: 0x161C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49; /* offset: 0x1620 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49; /* offset: 0x1624 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49; /* offset: 0x1628 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49; /* offset: 0x162C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49; /* offset: 0x1630 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49; /* offset: 0x1634 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49; /* offset: 0x1638 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49; /* offset: 0x163C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50; /* offset: 0x1640 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50; /* offset: 0x1644 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50; /* offset: 0x1648 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50; /* offset: 0x164C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50; /* offset: 0x1650 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50; /* offset: 0x1654 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50; /* offset: 0x1658 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50; /* offset: 0x165C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51; /* offset: 0x1660 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51; /* offset: 0x1664 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51; /* offset: 0x1668 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51; /* offset: 0x166C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51; /* offset: 0x1670 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51; /* offset: 0x1674 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51; /* offset: 0x1678 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51; /* offset: 0x167C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52; /* offset: 0x1680 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52; /* offset: 0x1684 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52; /* offset: 0x1688 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52; /* offset: 0x168C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52; /* offset: 0x1690 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52; /* offset: 0x1694 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52; /* offset: 0x1698 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52; /* offset: 0x169C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53; /* offset: 0x16A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53; /* offset: 0x16A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53; /* offset: 0x16A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53; /* offset: 0x16AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53; /* offset: 0x16B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53; /* offset: 0x16B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53; /* offset: 0x16B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53; /* offset: 0x16BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54; /* offset: 0x16C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54; /* offset: 0x16C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54; /* offset: 0x16C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54; /* offset: 0x16CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54; /* offset: 0x16D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54; /* offset: 0x16D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54; /* offset: 0x16D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54; /* offset: 0x16DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55; /* offset: 0x16E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55; /* offset: 0x16E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55; /* offset: 0x16E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55; /* offset: 0x16EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55; /* offset: 0x16F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55; /* offset: 0x16F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55; /* offset: 0x16F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55; /* offset: 0x16FC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56; /* offset: 0x1700 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56; /* offset: 0x1704 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56; /* offset: 0x1708 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56; /* offset: 0x170C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56; /* offset: 0x1710 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56; /* offset: 0x1714 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56; /* offset: 0x1718 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56; /* offset: 0x171C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57; /* offset: 0x1720 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57; /* offset: 0x1724 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57; /* offset: 0x1728 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57; /* offset: 0x172C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57; /* offset: 0x1730 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57; /* offset: 0x1734 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57; /* offset: 0x1738 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57; /* offset: 0x173C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58; /* offset: 0x1740 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58; /* offset: 0x1744 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58; /* offset: 0x1748 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58; /* offset: 0x174C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58; /* offset: 0x1750 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58; /* offset: 0x1754 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58; /* offset: 0x1758 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58; /* offset: 0x175C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59; /* offset: 0x1760 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59; /* offset: 0x1764 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59; /* offset: 0x1768 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59; /* offset: 0x176C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59; /* offset: 0x1770 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59; /* offset: 0x1774 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59; /* offset: 0x1778 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59; /* offset: 0x177C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60; /* offset: 0x1780 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60; /* offset: 0x1784 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60; /* offset: 0x1788 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60; /* offset: 0x178C size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60; /* offset: 0x1790 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60; /* offset: 0x1794 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60; /* offset: 0x1798 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60; /* offset: 0x179C size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61; /* offset: 0x17A0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61; /* offset: 0x17A4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61; /* offset: 0x17A8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61; /* offset: 0x17AC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61; /* offset: 0x17B0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61; /* offset: 0x17B4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61; /* offset: 0x17B8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61; /* offset: 0x17BC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62; /* offset: 0x17C0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62; /* offset: 0x17C4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62; /* offset: 0x17C8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62; /* offset: 0x17CC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62; /* offset: 0x17D0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62; /* offset: 0x17D4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62; /* offset: 0x17D8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62; /* offset: 0x17DC size: 32 bit */
+ /* SPP_DMA2_TCDn Word0 - Source Address */
+ SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63; /* offset: 0x17E0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
+ SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63; /* offset: 0x17E4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word2 - nbytes */
+ SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63; /* offset: 0x17E8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word3 - slast */
+ SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63; /* offset: 0x17EC size: 32 bit */
+ /* SPP_DMA2_TCDn Word4 - daddr */
+ SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63; /* offset: 0x17F0 size: 32 bit */
+ /* SPP_DMA2_TCDn Word5 - citer.e_link, citer, doff */
+ SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63; /* offset: 0x17F4 size: 32 bit */
+ /* SPP_DMA2_TCDn Word6 - dlast_sga */
+ SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63; /* offset: 0x17F8 size: 32 bit */
+ /* SPP_DMA2_TCDn Word7 - biter, etc. */
+ SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63; /* offset: 0x17FC size: 32 bit */
+ };
+
+ };
+ } SPP_DMA2_tag;
+
+
+#define SPP_DMA2 (*(volatile SPP_DMA2_tag *) 0xFFF44000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: INTC */
+/* */
+/****************************************************************/
+
+ typedef union { /* BCR - Block Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:18;
+ vuint32_t VTES_PRC1:1; /* Vector Table Entry Size - Processor 1 */
+ vuint32_t:4;
+ vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable - Processor 1 */
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_INTC
+ vuint32_t VTES_PRC0:1; /* Vector Table Entry Size - Processor 0 */
+#else
+ vuint32_t VTES:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:4;
+#ifndef USE_FIELD_ALIASES_INTC
+ vuint32_t HVEN_PRC0:1; /* Hardware Vector Enable - Processor 0 */
+#else
+ vuint32_t HVEN:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } INTC_BCR_32B_tag;
+
+ typedef union { /* CPR - Current Priority Register - Processor 0 */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4; /* Priority Bits */
+ } B;
+ } INTC_CPR_PRC0_32B_tag;
+
+ typedef union { /* CPR - Current Priority Register - Processor 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t:28;
+ vuint32_t PRI:4; /* Priority Bits */
+ } B;
+ } INTC_CPR_PRC1_32B_tag;
+
+ typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 0 */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_INTC
+ vuint32_t VTBA_PRC0:21; /* Vector Table Base Address - Processor 0 */
+#else
+ vuint32_t VTBA:21; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_INTC
+ vuint32_t INTEC_PRC0:9; /* Interrupt Vector - Processor 0 */
+#else
+ vuint32_t INTVEC:9; /* deprecated name - please avoid */
+#endif
+ vuint32_t:2;
+ } B;
+ } INTC_IACKR_PRC0_32B_tag;
+
+ typedef union { /* IACKR- Interrupt Acknowledge Register - Processor 1 */
+ vuint32_t R;
+ struct {
+ vuint32_t VTBA_PRC1:21; /* Vector Table Base Address - Processor 1 */
+ vuint32_t INTEC_PRC1:9; /* Interrupt Vector - Processor 1 */
+ vuint32_t:2;
+ } B;
+ } INTC_IACKR_PRC1_32B_tag;
+
+ typedef union { /* EOIR- End of Interrupt Register - Processor 0 */
+ vuint32_t R;
+ } INTC_EOIR_PRC0_32B_tag;
+
+ typedef union { /* EOIR- End of Interrupt Register - Processor 1 */
+ vuint32_t R;
+ } INTC_EOIR_PRC1_32B_tag;
+
+
+ /* Register layout for all registers SSCIR... */
+
+ typedef union { /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t:6;
+ vuint8_t SET:1; /* Set Flag bit */
+ vuint8_t CLR:1; /* Clear Flag bit */
+ } B;
+ } INTC_SSCIR_8B_tag;
+
+ typedef union { /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t SET0:1; /* Set Flag 0 bit */
+ vuint32_t CLR0:1; /* Clear Flag 0 bit */
+ vuint32_t:6;
+ vuint32_t SET1:1; /* Set Flag 1 bit */
+ vuint32_t CLR1:1; /* Clear Flag 1 bit */
+ vuint32_t:6;
+ vuint32_t SET2:1; /* Set Flag 2 bit */
+ vuint32_t CLR2:1; /* Clear Flag 2 bit */
+ vuint32_t:6;
+ vuint32_t SET3:1; /* Set Flag 3 bit */
+ vuint32_t CLR3:1; /* Clear Flag 3 bit */
+ } B;
+ } INTC_SSCIR0_3_32B_tag;
+
+ typedef union { /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t:6;
+ vuint32_t SET4:1; /* Set Flag 4 bit */
+ vuint32_t CLR4:1; /* Clear Flag 4 bit */
+ vuint32_t:6;
+ vuint32_t SET5:1; /* Set Flag 5 bit */
+ vuint32_t CLR5:1; /* Clear Flag 5 bit */
+ vuint32_t:6;
+ vuint32_t SET6:1; /* Set Flag 6 bit */
+ vuint32_t CLR6:1; /* Clear Flag 6 bit */
+ vuint32_t:6;
+ vuint32_t SET7:1; /* Set Flag 7 bit */
+ vuint32_t CLR7:1; /* Clear Flag 7 bit */
+ } B;
+ } INTC_SSCIR4_7_32B_tag;
+
+
+ /* Register layout for all registers PSR... */
+
+ typedef union { /* PSR0-511 - Priority Select Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t PRC_SEL:2; /* Processor Select */
+ vuint8_t:2;
+ vuint8_t PRI:4; /* Priority Select */
+ } B;
+ } INTC_PSR_8B_tag;
+
+
+ /* Register layout for all registers PSR... */
+
+ typedef union { /* PSR0_3 - 508_511 - Priority Select Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t PRC_SEL0:2; /* Processor Select - Entry 0 */
+ vuint32_t:2;
+ vuint32_t PRI0:4; /* Priority Select - Entry 0 */
+ vuint32_t PRC_SEL1:2; /* Processor Select - Entry 1 */
+ vuint32_t:2;
+ vuint32_t PRI1:4; /* Priority Select - Entry 1 */
+ vuint32_t PRC_SEL2:2; /* Processor Select - Entry 2 */
+ vuint32_t:2;
+ vuint32_t PRI2:4; /* Priority Select - Entry 2 */
+ vuint32_t PRC_SEL3:2; /* Processor Select - Entry 3 */
+ vuint32_t:2;
+ vuint32_t PRI3:4; /* Priority Select - Entry 3 */
+ } B;
+ } INTC_PSR_32B_tag;
+
+
+
+ typedef struct INTC_struct_tag { /* start of INTC_tag */
+ union {
+ INTC_BCR_32B_tag MCR; /* deprecated - please avoid */
+
+ /* BCR - Block Configuration Register */
+ INTC_BCR_32B_tag BCR; /* offset: 0x0000 size: 32 bit */
+
+ };
+ int8_t INTC_reserved_0004_C[4];
+ union {
+ /* CPR - Current Priority Register - Processor 0 */
+ INTC_CPR_PRC0_32B_tag CPR_PRC0; /* offset: 0x0008 size: 32 bit */
+
+ INTC_CPR_PRC0_32B_tag CPR; /* deprecated - please avoid */
+
+ };
+ /* CPR - Current Priority Register - Processor 1 */
+ INTC_CPR_PRC1_32B_tag CPR_PRC1; /* offset: 0x000C size: 32 bit */
+ union {
+ /* IACKR- Interrupt Acknowledge Register - Processor 0 */
+ INTC_IACKR_PRC0_32B_tag IACKR_PRC0; /* offset: 0x0010 size: 32 bit */
+
+ INTC_IACKR_PRC0_32B_tag IACKR; /* deprecated - please avoid */
+
+ };
+ /* IACKR- Interrupt Acknowledge Register - Processor 1 */
+ INTC_IACKR_PRC1_32B_tag IACKR_PRC1; /* offset: 0x0014 size: 32 bit */
+ union {
+ /* EOIR- End of Interrupt Register - Processor 0 */
+ INTC_EOIR_PRC0_32B_tag EOIR_PRC0; /* offset: 0x0018 size: 32 bit */
+
+ INTC_EOIR_PRC0_32B_tag EOIR; /* deprecated - please avoid */
+
+ };
+ /* EOIR- End of Interrupt Register - Processor 1 */
+ INTC_EOIR_PRC1_32B_tag EOIR_PRC1; /* offset: 0x001C size: 32 bit */
+ union {
+ /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
+ INTC_SSCIR_8B_tag SSCIR[8]; /* offset: 0x0020 (0x0001 x 8) */
+
+ struct {
+ /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
+ INTC_SSCIR_8B_tag SSCIR0; /* offset: 0x0020 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR1; /* offset: 0x0021 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR2; /* offset: 0x0022 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR3; /* offset: 0x0023 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR4; /* offset: 0x0024 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR5; /* offset: 0x0025 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR6; /* offset: 0x0026 size: 8 bit */
+ INTC_SSCIR_8B_tag SSCIR7; /* offset: 0x0027 size: 8 bit */
+ };
+
+ struct {
+ /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
+ INTC_SSCIR0_3_32B_tag SSCIR0_3; /* offset: 0x0020 size: 32 bit */
+ /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
+ INTC_SSCIR4_7_32B_tag SSCIR4_7; /* offset: 0x0024 size: 32 bit */
+ };
+
+ };
+ int8_t INTC_reserved_0028_C[24];
+ union {
+ /* PSR0_3 - 508_511 - Priority Select Registers */
+ INTC_PSR_32B_tag PSR_32B[128]; /* offset: 0x0040 (0x0004 x 128) */
+
+ /* PSR0-511 - Priority Select Registers */
+ INTC_PSR_8B_tag PSR[512]; /* offset: 0x0040 (0x0001 x 512) */
+
+ struct {
+ /* PSR0_3 - 508_511 - Priority Select Registers */
+ INTC_PSR_32B_tag PSR0_3; /* offset: 0x0040 size: 32 bit */
+ INTC_PSR_32B_tag PSR4_7; /* offset: 0x0044 size: 32 bit */
+ INTC_PSR_32B_tag PSR8_11; /* offset: 0x0048 size: 32 bit */
+ INTC_PSR_32B_tag PSR12_15; /* offset: 0x004C size: 32 bit */
+ INTC_PSR_32B_tag PSR16_19; /* offset: 0x0050 size: 32 bit */
+ INTC_PSR_32B_tag PSR20_23; /* offset: 0x0054 size: 32 bit */
+ INTC_PSR_32B_tag PSR24_27; /* offset: 0x0058 size: 32 bit */
+ INTC_PSR_32B_tag PSR28_31; /* offset: 0x005C size: 32 bit */
+ INTC_PSR_32B_tag PSR32_35; /* offset: 0x0060 size: 32 bit */
+ INTC_PSR_32B_tag PSR36_39; /* offset: 0x0064 size: 32 bit */
+ INTC_PSR_32B_tag PSR40_43; /* offset: 0x0068 size: 32 bit */
+ INTC_PSR_32B_tag PSR44_47; /* offset: 0x006C size: 32 bit */
+ INTC_PSR_32B_tag PSR48_51; /* offset: 0x0070 size: 32 bit */
+ INTC_PSR_32B_tag PSR52_55; /* offset: 0x0074 size: 32 bit */
+ INTC_PSR_32B_tag PSR56_59; /* offset: 0x0078 size: 32 bit */
+ INTC_PSR_32B_tag PSR60_63; /* offset: 0x007C size: 32 bit */
+ INTC_PSR_32B_tag PSR64_67; /* offset: 0x0080 size: 32 bit */
+ INTC_PSR_32B_tag PSR68_71; /* offset: 0x0084 size: 32 bit */
+ INTC_PSR_32B_tag PSR72_75; /* offset: 0x0088 size: 32 bit */
+ INTC_PSR_32B_tag PSR76_79; /* offset: 0x008C size: 32 bit */
+ INTC_PSR_32B_tag PSR80_83; /* offset: 0x0090 size: 32 bit */
+ INTC_PSR_32B_tag PSR84_87; /* offset: 0x0094 size: 32 bit */
+ INTC_PSR_32B_tag PSR88_91; /* offset: 0x0098 size: 32 bit */
+ INTC_PSR_32B_tag PSR92_95; /* offset: 0x009C size: 32 bit */
+ INTC_PSR_32B_tag PSR96_99; /* offset: 0x00A0 size: 32 bit */
+ INTC_PSR_32B_tag PSR100_103; /* offset: 0x00A4 size: 32 bit */
+ INTC_PSR_32B_tag PSR104_107; /* offset: 0x00A8 size: 32 bit */
+ INTC_PSR_32B_tag PSR108_111; /* offset: 0x00AC size: 32 bit */
+ INTC_PSR_32B_tag PSR112_115; /* offset: 0x00B0 size: 32 bit */
+ INTC_PSR_32B_tag PSR116_119; /* offset: 0x00B4 size: 32 bit */
+ INTC_PSR_32B_tag PSR120_123; /* offset: 0x00B8 size: 32 bit */
+ INTC_PSR_32B_tag PSR124_127; /* offset: 0x00BC size: 32 bit */
+ INTC_PSR_32B_tag PSR128_131; /* offset: 0x00C0 size: 32 bit */
+ INTC_PSR_32B_tag PSR132_135; /* offset: 0x00C4 size: 32 bit */
+ INTC_PSR_32B_tag PSR136_139; /* offset: 0x00C8 size: 32 bit */
+ INTC_PSR_32B_tag PSR140_143; /* offset: 0x00CC size: 32 bit */
+ INTC_PSR_32B_tag PSR144_147; /* offset: 0x00D0 size: 32 bit */
+ INTC_PSR_32B_tag PSR148_151; /* offset: 0x00D4 size: 32 bit */
+ INTC_PSR_32B_tag PSR152_155; /* offset: 0x00D8 size: 32 bit */
+ INTC_PSR_32B_tag PSR156_159; /* offset: 0x00DC size: 32 bit */
+ INTC_PSR_32B_tag PSR160_163; /* offset: 0x00E0 size: 32 bit */
+ INTC_PSR_32B_tag PSR164_167; /* offset: 0x00E4 size: 32 bit */
+ INTC_PSR_32B_tag PSR168_171; /* offset: 0x00E8 size: 32 bit */
+ INTC_PSR_32B_tag PSR172_175; /* offset: 0x00EC size: 32 bit */
+ INTC_PSR_32B_tag PSR176_179; /* offset: 0x00F0 size: 32 bit */
+ INTC_PSR_32B_tag PSR180_183; /* offset: 0x00F4 size: 32 bit */
+ INTC_PSR_32B_tag PSR184_187; /* offset: 0x00F8 size: 32 bit */
+ INTC_PSR_32B_tag PSR188_191; /* offset: 0x00FC size: 32 bit */
+ INTC_PSR_32B_tag PSR192_195; /* offset: 0x0100 size: 32 bit */
+ INTC_PSR_32B_tag PSR196_199; /* offset: 0x0104 size: 32 bit */
+ INTC_PSR_32B_tag PSR200_203; /* offset: 0x0108 size: 32 bit */
+ INTC_PSR_32B_tag PSR204_207; /* offset: 0x010C size: 32 bit */
+ INTC_PSR_32B_tag PSR208_211; /* offset: 0x0110 size: 32 bit */
+ INTC_PSR_32B_tag PSR212_215; /* offset: 0x0114 size: 32 bit */
+ INTC_PSR_32B_tag PSR216_219; /* offset: 0x0118 size: 32 bit */
+ INTC_PSR_32B_tag PSR220_223; /* offset: 0x011C size: 32 bit */
+ INTC_PSR_32B_tag PSR224_227; /* offset: 0x0120 size: 32 bit */
+ INTC_PSR_32B_tag PSR228_231; /* offset: 0x0124 size: 32 bit */
+ INTC_PSR_32B_tag PSR232_235; /* offset: 0x0128 size: 32 bit */
+ INTC_PSR_32B_tag PSR236_239; /* offset: 0x012C size: 32 bit */
+ INTC_PSR_32B_tag PSR240_243; /* offset: 0x0130 size: 32 bit */
+ INTC_PSR_32B_tag PSR244_247; /* offset: 0x0134 size: 32 bit */
+ INTC_PSR_32B_tag PSR248_251; /* offset: 0x0138 size: 32 bit */
+ INTC_PSR_32B_tag PSR252_255; /* offset: 0x013C size: 32 bit */
+ INTC_PSR_32B_tag PSR256_259; /* offset: 0x0140 size: 32 bit */
+ INTC_PSR_32B_tag PSR260_263; /* offset: 0x0144 size: 32 bit */
+ INTC_PSR_32B_tag PSR264_267; /* offset: 0x0148 size: 32 bit */
+ INTC_PSR_32B_tag PSR268_271; /* offset: 0x014C size: 32 bit */
+ INTC_PSR_32B_tag PSR272_275; /* offset: 0x0150 size: 32 bit */
+ INTC_PSR_32B_tag PSR276_279; /* offset: 0x0154 size: 32 bit */
+ INTC_PSR_32B_tag PSR280_283; /* offset: 0x0158 size: 32 bit */
+ INTC_PSR_32B_tag PSR284_287; /* offset: 0x015C size: 32 bit */
+ INTC_PSR_32B_tag PSR288_291; /* offset: 0x0160 size: 32 bit */
+ INTC_PSR_32B_tag PSR292_295; /* offset: 0x0164 size: 32 bit */
+ INTC_PSR_32B_tag PSR296_299; /* offset: 0x0168 size: 32 bit */
+ INTC_PSR_32B_tag PSR300_303; /* offset: 0x016C size: 32 bit */
+ INTC_PSR_32B_tag PSR304_307; /* offset: 0x0170 size: 32 bit */
+ INTC_PSR_32B_tag PSR308_311; /* offset: 0x0174 size: 32 bit */
+ INTC_PSR_32B_tag PSR312_315; /* offset: 0x0178 size: 32 bit */
+ INTC_PSR_32B_tag PSR316_319; /* offset: 0x017C size: 32 bit */
+ INTC_PSR_32B_tag PSR320_323; /* offset: 0x0180 size: 32 bit */
+ INTC_PSR_32B_tag PSR324_327; /* offset: 0x0184 size: 32 bit */
+ INTC_PSR_32B_tag PSR328_331; /* offset: 0x0188 size: 32 bit */
+ INTC_PSR_32B_tag PSR332_335; /* offset: 0x018C size: 32 bit */
+ INTC_PSR_32B_tag PSR336_339; /* offset: 0x0190 size: 32 bit */
+ INTC_PSR_32B_tag PSR340_343; /* offset: 0x0194 size: 32 bit */
+ INTC_PSR_32B_tag PSR344_347; /* offset: 0x0198 size: 32 bit */
+ INTC_PSR_32B_tag PSR348_351; /* offset: 0x019C size: 32 bit */
+ INTC_PSR_32B_tag PSR352_355; /* offset: 0x01A0 size: 32 bit */
+ INTC_PSR_32B_tag PSR356_359; /* offset: 0x01A4 size: 32 bit */
+ INTC_PSR_32B_tag PSR360_363; /* offset: 0x01A8 size: 32 bit */
+ INTC_PSR_32B_tag PSR364_367; /* offset: 0x01AC size: 32 bit */
+ INTC_PSR_32B_tag PSR368_371; /* offset: 0x01B0 size: 32 bit */
+ INTC_PSR_32B_tag PSR372_375; /* offset: 0x01B4 size: 32 bit */
+ INTC_PSR_32B_tag PSR376_379; /* offset: 0x01B8 size: 32 bit */
+ INTC_PSR_32B_tag PSR380_383; /* offset: 0x01BC size: 32 bit */
+ INTC_PSR_32B_tag PSR384_387; /* offset: 0x01C0 size: 32 bit */
+ INTC_PSR_32B_tag PSR388_391; /* offset: 0x01C4 size: 32 bit */
+ INTC_PSR_32B_tag PSR392_395; /* offset: 0x01C8 size: 32 bit */
+ INTC_PSR_32B_tag PSR396_399; /* offset: 0x01CC size: 32 bit */
+ INTC_PSR_32B_tag PSR400_403; /* offset: 0x01D0 size: 32 bit */
+ INTC_PSR_32B_tag PSR404_407; /* offset: 0x01D4 size: 32 bit */
+ INTC_PSR_32B_tag PSR408_411; /* offset: 0x01D8 size: 32 bit */
+ INTC_PSR_32B_tag PSR412_415; /* offset: 0x01DC size: 32 bit */
+ INTC_PSR_32B_tag PSR416_419; /* offset: 0x01E0 size: 32 bit */
+ INTC_PSR_32B_tag PSR420_423; /* offset: 0x01E4 size: 32 bit */
+ INTC_PSR_32B_tag PSR424_427; /* offset: 0x01E8 size: 32 bit */
+ INTC_PSR_32B_tag PSR428_431; /* offset: 0x01EC size: 32 bit */
+ INTC_PSR_32B_tag PSR432_435; /* offset: 0x01F0 size: 32 bit */
+ INTC_PSR_32B_tag PSR436_439; /* offset: 0x01F4 size: 32 bit */
+ INTC_PSR_32B_tag PSR440_443; /* offset: 0x01F8 size: 32 bit */
+ INTC_PSR_32B_tag PSR444_447; /* offset: 0x01FC size: 32 bit */
+ INTC_PSR_32B_tag PSR448_451; /* offset: 0x0200 size: 32 bit */
+ INTC_PSR_32B_tag PSR452_455; /* offset: 0x0204 size: 32 bit */
+ INTC_PSR_32B_tag PSR456_459; /* offset: 0x0208 size: 32 bit */
+ INTC_PSR_32B_tag PSR460_463; /* offset: 0x020C size: 32 bit */
+ INTC_PSR_32B_tag PSR464_467; /* offset: 0x0210 size: 32 bit */
+ INTC_PSR_32B_tag PSR468_471; /* offset: 0x0214 size: 32 bit */
+ INTC_PSR_32B_tag PSR472_475; /* offset: 0x0218 size: 32 bit */
+ INTC_PSR_32B_tag PSR476_479; /* offset: 0x021C size: 32 bit */
+ INTC_PSR_32B_tag PSR480_483; /* offset: 0x0220 size: 32 bit */
+ INTC_PSR_32B_tag PSR484_487; /* offset: 0x0224 size: 32 bit */
+ INTC_PSR_32B_tag PSR488_491; /* offset: 0x0228 size: 32 bit */
+ INTC_PSR_32B_tag PSR492_495; /* offset: 0x022C size: 32 bit */
+ INTC_PSR_32B_tag PSR496_499; /* offset: 0x0230 size: 32 bit */
+ INTC_PSR_32B_tag PSR500_503; /* offset: 0x0234 size: 32 bit */
+ INTC_PSR_32B_tag PSR504_507; /* offset: 0x0238 size: 32 bit */
+ INTC_PSR_32B_tag PSR508_511; /* offset: 0x023C size: 32 bit */
+ };
+
+ struct {
+ /* PSR0-511 - Priority Select Registers */
+ INTC_PSR_8B_tag PSR0; /* offset: 0x0040 size: 8 bit */
+ INTC_PSR_8B_tag PSR1; /* offset: 0x0041 size: 8 bit */
+ INTC_PSR_8B_tag PSR2; /* offset: 0x0042 size: 8 bit */
+ INTC_PSR_8B_tag PSR3; /* offset: 0x0043 size: 8 bit */
+ INTC_PSR_8B_tag PSR4; /* offset: 0x0044 size: 8 bit */
+ INTC_PSR_8B_tag PSR5; /* offset: 0x0045 size: 8 bit */
+ INTC_PSR_8B_tag PSR6; /* offset: 0x0046 size: 8 bit */
+ INTC_PSR_8B_tag PSR7; /* offset: 0x0047 size: 8 bit */
+ INTC_PSR_8B_tag PSR8; /* offset: 0x0048 size: 8 bit */
+ INTC_PSR_8B_tag PSR9; /* offset: 0x0049 size: 8 bit */
+ INTC_PSR_8B_tag PSR10; /* offset: 0x004A size: 8 bit */
+ INTC_PSR_8B_tag PSR11; /* offset: 0x004B size: 8 bit */
+ INTC_PSR_8B_tag PSR12; /* offset: 0x004C size: 8 bit */
+ INTC_PSR_8B_tag PSR13; /* offset: 0x004D size: 8 bit */
+ INTC_PSR_8B_tag PSR14; /* offset: 0x004E size: 8 bit */
+ INTC_PSR_8B_tag PSR15; /* offset: 0x004F size: 8 bit */
+ INTC_PSR_8B_tag PSR16; /* offset: 0x0050 size: 8 bit */
+ INTC_PSR_8B_tag PSR17; /* offset: 0x0051 size: 8 bit */
+ INTC_PSR_8B_tag PSR18; /* offset: 0x0052 size: 8 bit */
+ INTC_PSR_8B_tag PSR19; /* offset: 0x0053 size: 8 bit */
+ INTC_PSR_8B_tag PSR20; /* offset: 0x0054 size: 8 bit */
+ INTC_PSR_8B_tag PSR21; /* offset: 0x0055 size: 8 bit */
+ INTC_PSR_8B_tag PSR22; /* offset: 0x0056 size: 8 bit */
+ INTC_PSR_8B_tag PSR23; /* offset: 0x0057 size: 8 bit */
+ INTC_PSR_8B_tag PSR24; /* offset: 0x0058 size: 8 bit */
+ INTC_PSR_8B_tag PSR25; /* offset: 0x0059 size: 8 bit */
+ INTC_PSR_8B_tag PSR26; /* offset: 0x005A size: 8 bit */
+ INTC_PSR_8B_tag PSR27; /* offset: 0x005B size: 8 bit */
+ INTC_PSR_8B_tag PSR28; /* offset: 0x005C size: 8 bit */
+ INTC_PSR_8B_tag PSR29; /* offset: 0x005D size: 8 bit */
+ INTC_PSR_8B_tag PSR30; /* offset: 0x005E size: 8 bit */
+ INTC_PSR_8B_tag PSR31; /* offset: 0x005F size: 8 bit */
+ INTC_PSR_8B_tag PSR32; /* offset: 0x0060 size: 8 bit */
+ INTC_PSR_8B_tag PSR33; /* offset: 0x0061 size: 8 bit */
+ INTC_PSR_8B_tag PSR34; /* offset: 0x0062 size: 8 bit */
+ INTC_PSR_8B_tag PSR35; /* offset: 0x0063 size: 8 bit */
+ INTC_PSR_8B_tag PSR36; /* offset: 0x0064 size: 8 bit */
+ INTC_PSR_8B_tag PSR37; /* offset: 0x0065 size: 8 bit */
+ INTC_PSR_8B_tag PSR38; /* offset: 0x0066 size: 8 bit */
+ INTC_PSR_8B_tag PSR39; /* offset: 0x0067 size: 8 bit */
+ INTC_PSR_8B_tag PSR40; /* offset: 0x0068 size: 8 bit */
+ INTC_PSR_8B_tag PSR41; /* offset: 0x0069 size: 8 bit */
+ INTC_PSR_8B_tag PSR42; /* offset: 0x006A size: 8 bit */
+ INTC_PSR_8B_tag PSR43; /* offset: 0x006B size: 8 bit */
+ INTC_PSR_8B_tag PSR44; /* offset: 0x006C size: 8 bit */
+ INTC_PSR_8B_tag PSR45; /* offset: 0x006D size: 8 bit */
+ INTC_PSR_8B_tag PSR46; /* offset: 0x006E size: 8 bit */
+ INTC_PSR_8B_tag PSR47; /* offset: 0x006F size: 8 bit */
+ INTC_PSR_8B_tag PSR48; /* offset: 0x0070 size: 8 bit */
+ INTC_PSR_8B_tag PSR49; /* offset: 0x0071 size: 8 bit */
+ INTC_PSR_8B_tag PSR50; /* offset: 0x0072 size: 8 bit */
+ INTC_PSR_8B_tag PSR51; /* offset: 0x0073 size: 8 bit */
+ INTC_PSR_8B_tag PSR52; /* offset: 0x0074 size: 8 bit */
+ INTC_PSR_8B_tag PSR53; /* offset: 0x0075 size: 8 bit */
+ INTC_PSR_8B_tag PSR54; /* offset: 0x0076 size: 8 bit */
+ INTC_PSR_8B_tag PSR55; /* offset: 0x0077 size: 8 bit */
+ INTC_PSR_8B_tag PSR56; /* offset: 0x0078 size: 8 bit */
+ INTC_PSR_8B_tag PSR57; /* offset: 0x0079 size: 8 bit */
+ INTC_PSR_8B_tag PSR58; /* offset: 0x007A size: 8 bit */
+ INTC_PSR_8B_tag PSR59; /* offset: 0x007B size: 8 bit */
+ INTC_PSR_8B_tag PSR60; /* offset: 0x007C size: 8 bit */
+ INTC_PSR_8B_tag PSR61; /* offset: 0x007D size: 8 bit */
+ INTC_PSR_8B_tag PSR62; /* offset: 0x007E size: 8 bit */
+ INTC_PSR_8B_tag PSR63; /* offset: 0x007F size: 8 bit */
+ INTC_PSR_8B_tag PSR64; /* offset: 0x0080 size: 8 bit */
+ INTC_PSR_8B_tag PSR65; /* offset: 0x0081 size: 8 bit */
+ INTC_PSR_8B_tag PSR66; /* offset: 0x0082 size: 8 bit */
+ INTC_PSR_8B_tag PSR67; /* offset: 0x0083 size: 8 bit */
+ INTC_PSR_8B_tag PSR68; /* offset: 0x0084 size: 8 bit */
+ INTC_PSR_8B_tag PSR69; /* offset: 0x0085 size: 8 bit */
+ INTC_PSR_8B_tag PSR70; /* offset: 0x0086 size: 8 bit */
+ INTC_PSR_8B_tag PSR71; /* offset: 0x0087 size: 8 bit */
+ INTC_PSR_8B_tag PSR72; /* offset: 0x0088 size: 8 bit */
+ INTC_PSR_8B_tag PSR73; /* offset: 0x0089 size: 8 bit */
+ INTC_PSR_8B_tag PSR74; /* offset: 0x008A size: 8 bit */
+ INTC_PSR_8B_tag PSR75; /* offset: 0x008B size: 8 bit */
+ INTC_PSR_8B_tag PSR76; /* offset: 0x008C size: 8 bit */
+ INTC_PSR_8B_tag PSR77; /* offset: 0x008D size: 8 bit */
+ INTC_PSR_8B_tag PSR78; /* offset: 0x008E size: 8 bit */
+ INTC_PSR_8B_tag PSR79; /* offset: 0x008F size: 8 bit */
+ INTC_PSR_8B_tag PSR80; /* offset: 0x0090 size: 8 bit */
+ INTC_PSR_8B_tag PSR81; /* offset: 0x0091 size: 8 bit */
+ INTC_PSR_8B_tag PSR82; /* offset: 0x0092 size: 8 bit */
+ INTC_PSR_8B_tag PSR83; /* offset: 0x0093 size: 8 bit */
+ INTC_PSR_8B_tag PSR84; /* offset: 0x0094 size: 8 bit */
+ INTC_PSR_8B_tag PSR85; /* offset: 0x0095 size: 8 bit */
+ INTC_PSR_8B_tag PSR86; /* offset: 0x0096 size: 8 bit */
+ INTC_PSR_8B_tag PSR87; /* offset: 0x0097 size: 8 bit */
+ INTC_PSR_8B_tag PSR88; /* offset: 0x0098 size: 8 bit */
+ INTC_PSR_8B_tag PSR89; /* offset: 0x0099 size: 8 bit */
+ INTC_PSR_8B_tag PSR90; /* offset: 0x009A size: 8 bit */
+ INTC_PSR_8B_tag PSR91; /* offset: 0x009B size: 8 bit */
+ INTC_PSR_8B_tag PSR92; /* offset: 0x009C size: 8 bit */
+ INTC_PSR_8B_tag PSR93; /* offset: 0x009D size: 8 bit */
+ INTC_PSR_8B_tag PSR94; /* offset: 0x009E size: 8 bit */
+ INTC_PSR_8B_tag PSR95; /* offset: 0x009F size: 8 bit */
+ INTC_PSR_8B_tag PSR96; /* offset: 0x00A0 size: 8 bit */
+ INTC_PSR_8B_tag PSR97; /* offset: 0x00A1 size: 8 bit */
+ INTC_PSR_8B_tag PSR98; /* offset: 0x00A2 size: 8 bit */
+ INTC_PSR_8B_tag PSR99; /* offset: 0x00A3 size: 8 bit */
+ INTC_PSR_8B_tag PSR100; /* offset: 0x00A4 size: 8 bit */
+ INTC_PSR_8B_tag PSR101; /* offset: 0x00A5 size: 8 bit */
+ INTC_PSR_8B_tag PSR102; /* offset: 0x00A6 size: 8 bit */
+ INTC_PSR_8B_tag PSR103; /* offset: 0x00A7 size: 8 bit */
+ INTC_PSR_8B_tag PSR104; /* offset: 0x00A8 size: 8 bit */
+ INTC_PSR_8B_tag PSR105; /* offset: 0x00A9 size: 8 bit */
+ INTC_PSR_8B_tag PSR106; /* offset: 0x00AA size: 8 bit */
+ INTC_PSR_8B_tag PSR107; /* offset: 0x00AB size: 8 bit */
+ INTC_PSR_8B_tag PSR108; /* offset: 0x00AC size: 8 bit */
+ INTC_PSR_8B_tag PSR109; /* offset: 0x00AD size: 8 bit */
+ INTC_PSR_8B_tag PSR110; /* offset: 0x00AE size: 8 bit */
+ INTC_PSR_8B_tag PSR111; /* offset: 0x00AF size: 8 bit */
+ INTC_PSR_8B_tag PSR112; /* offset: 0x00B0 size: 8 bit */
+ INTC_PSR_8B_tag PSR113; /* offset: 0x00B1 size: 8 bit */
+ INTC_PSR_8B_tag PSR114; /* offset: 0x00B2 size: 8 bit */
+ INTC_PSR_8B_tag PSR115; /* offset: 0x00B3 size: 8 bit */
+ INTC_PSR_8B_tag PSR116; /* offset: 0x00B4 size: 8 bit */
+ INTC_PSR_8B_tag PSR117; /* offset: 0x00B5 size: 8 bit */
+ INTC_PSR_8B_tag PSR118; /* offset: 0x00B6 size: 8 bit */
+ INTC_PSR_8B_tag PSR119; /* offset: 0x00B7 size: 8 bit */
+ INTC_PSR_8B_tag PSR120; /* offset: 0x00B8 size: 8 bit */
+ INTC_PSR_8B_tag PSR121; /* offset: 0x00B9 size: 8 bit */
+ INTC_PSR_8B_tag PSR122; /* offset: 0x00BA size: 8 bit */
+ INTC_PSR_8B_tag PSR123; /* offset: 0x00BB size: 8 bit */
+ INTC_PSR_8B_tag PSR124; /* offset: 0x00BC size: 8 bit */
+ INTC_PSR_8B_tag PSR125; /* offset: 0x00BD size: 8 bit */
+ INTC_PSR_8B_tag PSR126; /* offset: 0x00BE size: 8 bit */
+ INTC_PSR_8B_tag PSR127; /* offset: 0x00BF size: 8 bit */
+ INTC_PSR_8B_tag PSR128; /* offset: 0x00C0 size: 8 bit */
+ INTC_PSR_8B_tag PSR129; /* offset: 0x00C1 size: 8 bit */
+ INTC_PSR_8B_tag PSR130; /* offset: 0x00C2 size: 8 bit */
+ INTC_PSR_8B_tag PSR131; /* offset: 0x00C3 size: 8 bit */
+ INTC_PSR_8B_tag PSR132; /* offset: 0x00C4 size: 8 bit */
+ INTC_PSR_8B_tag PSR133; /* offset: 0x00C5 size: 8 bit */
+ INTC_PSR_8B_tag PSR134; /* offset: 0x00C6 size: 8 bit */
+ INTC_PSR_8B_tag PSR135; /* offset: 0x00C7 size: 8 bit */
+ INTC_PSR_8B_tag PSR136; /* offset: 0x00C8 size: 8 bit */
+ INTC_PSR_8B_tag PSR137; /* offset: 0x00C9 size: 8 bit */
+ INTC_PSR_8B_tag PSR138; /* offset: 0x00CA size: 8 bit */
+ INTC_PSR_8B_tag PSR139; /* offset: 0x00CB size: 8 bit */
+ INTC_PSR_8B_tag PSR140; /* offset: 0x00CC size: 8 bit */
+ INTC_PSR_8B_tag PSR141; /* offset: 0x00CD size: 8 bit */
+ INTC_PSR_8B_tag PSR142; /* offset: 0x00CE size: 8 bit */
+ INTC_PSR_8B_tag PSR143; /* offset: 0x00CF size: 8 bit */
+ INTC_PSR_8B_tag PSR144; /* offset: 0x00D0 size: 8 bit */
+ INTC_PSR_8B_tag PSR145; /* offset: 0x00D1 size: 8 bit */
+ INTC_PSR_8B_tag PSR146; /* offset: 0x00D2 size: 8 bit */
+ INTC_PSR_8B_tag PSR147; /* offset: 0x00D3 size: 8 bit */
+ INTC_PSR_8B_tag PSR148; /* offset: 0x00D4 size: 8 bit */
+ INTC_PSR_8B_tag PSR149; /* offset: 0x00D5 size: 8 bit */
+ INTC_PSR_8B_tag PSR150; /* offset: 0x00D6 size: 8 bit */
+ INTC_PSR_8B_tag PSR151; /* offset: 0x00D7 size: 8 bit */
+ INTC_PSR_8B_tag PSR152; /* offset: 0x00D8 size: 8 bit */
+ INTC_PSR_8B_tag PSR153; /* offset: 0x00D9 size: 8 bit */
+ INTC_PSR_8B_tag PSR154; /* offset: 0x00DA size: 8 bit */
+ INTC_PSR_8B_tag PSR155; /* offset: 0x00DB size: 8 bit */
+ INTC_PSR_8B_tag PSR156; /* offset: 0x00DC size: 8 bit */
+ INTC_PSR_8B_tag PSR157; /* offset: 0x00DD size: 8 bit */
+ INTC_PSR_8B_tag PSR158; /* offset: 0x00DE size: 8 bit */
+ INTC_PSR_8B_tag PSR159; /* offset: 0x00DF size: 8 bit */
+ INTC_PSR_8B_tag PSR160; /* offset: 0x00E0 size: 8 bit */
+ INTC_PSR_8B_tag PSR161; /* offset: 0x00E1 size: 8 bit */
+ INTC_PSR_8B_tag PSR162; /* offset: 0x00E2 size: 8 bit */
+ INTC_PSR_8B_tag PSR163; /* offset: 0x00E3 size: 8 bit */
+ INTC_PSR_8B_tag PSR164; /* offset: 0x00E4 size: 8 bit */
+ INTC_PSR_8B_tag PSR165; /* offset: 0x00E5 size: 8 bit */
+ INTC_PSR_8B_tag PSR166; /* offset: 0x00E6 size: 8 bit */
+ INTC_PSR_8B_tag PSR167; /* offset: 0x00E7 size: 8 bit */
+ INTC_PSR_8B_tag PSR168; /* offset: 0x00E8 size: 8 bit */
+ INTC_PSR_8B_tag PSR169; /* offset: 0x00E9 size: 8 bit */
+ INTC_PSR_8B_tag PSR170; /* offset: 0x00EA size: 8 bit */
+ INTC_PSR_8B_tag PSR171; /* offset: 0x00EB size: 8 bit */
+ INTC_PSR_8B_tag PSR172; /* offset: 0x00EC size: 8 bit */
+ INTC_PSR_8B_tag PSR173; /* offset: 0x00ED size: 8 bit */
+ INTC_PSR_8B_tag PSR174; /* offset: 0x00EE size: 8 bit */
+ INTC_PSR_8B_tag PSR175; /* offset: 0x00EF size: 8 bit */
+ INTC_PSR_8B_tag PSR176; /* offset: 0x00F0 size: 8 bit */
+ INTC_PSR_8B_tag PSR177; /* offset: 0x00F1 size: 8 bit */
+ INTC_PSR_8B_tag PSR178; /* offset: 0x00F2 size: 8 bit */
+ INTC_PSR_8B_tag PSR179; /* offset: 0x00F3 size: 8 bit */
+ INTC_PSR_8B_tag PSR180; /* offset: 0x00F4 size: 8 bit */
+ INTC_PSR_8B_tag PSR181; /* offset: 0x00F5 size: 8 bit */
+ INTC_PSR_8B_tag PSR182; /* offset: 0x00F6 size: 8 bit */
+ INTC_PSR_8B_tag PSR183; /* offset: 0x00F7 size: 8 bit */
+ INTC_PSR_8B_tag PSR184; /* offset: 0x00F8 size: 8 bit */
+ INTC_PSR_8B_tag PSR185; /* offset: 0x00F9 size: 8 bit */
+ INTC_PSR_8B_tag PSR186; /* offset: 0x00FA size: 8 bit */
+ INTC_PSR_8B_tag PSR187; /* offset: 0x00FB size: 8 bit */
+ INTC_PSR_8B_tag PSR188; /* offset: 0x00FC size: 8 bit */
+ INTC_PSR_8B_tag PSR189; /* offset: 0x00FD size: 8 bit */
+ INTC_PSR_8B_tag PSR190; /* offset: 0x00FE size: 8 bit */
+ INTC_PSR_8B_tag PSR191; /* offset: 0x00FF size: 8 bit */
+ INTC_PSR_8B_tag PSR192; /* offset: 0x0100 size: 8 bit */
+ INTC_PSR_8B_tag PSR193; /* offset: 0x0101 size: 8 bit */
+ INTC_PSR_8B_tag PSR194; /* offset: 0x0102 size: 8 bit */
+ INTC_PSR_8B_tag PSR195; /* offset: 0x0103 size: 8 bit */
+ INTC_PSR_8B_tag PSR196; /* offset: 0x0104 size: 8 bit */
+ INTC_PSR_8B_tag PSR197; /* offset: 0x0105 size: 8 bit */
+ INTC_PSR_8B_tag PSR198; /* offset: 0x0106 size: 8 bit */
+ INTC_PSR_8B_tag PSR199; /* offset: 0x0107 size: 8 bit */
+ INTC_PSR_8B_tag PSR200; /* offset: 0x0108 size: 8 bit */
+ INTC_PSR_8B_tag PSR201; /* offset: 0x0109 size: 8 bit */
+ INTC_PSR_8B_tag PSR202; /* offset: 0x010A size: 8 bit */
+ INTC_PSR_8B_tag PSR203; /* offset: 0x010B size: 8 bit */
+ INTC_PSR_8B_tag PSR204; /* offset: 0x010C size: 8 bit */
+ INTC_PSR_8B_tag PSR205; /* offset: 0x010D size: 8 bit */
+ INTC_PSR_8B_tag PSR206; /* offset: 0x010E size: 8 bit */
+ INTC_PSR_8B_tag PSR207; /* offset: 0x010F size: 8 bit */
+ INTC_PSR_8B_tag PSR208; /* offset: 0x0110 size: 8 bit */
+ INTC_PSR_8B_tag PSR209; /* offset: 0x0111 size: 8 bit */
+ INTC_PSR_8B_tag PSR210; /* offset: 0x0112 size: 8 bit */
+ INTC_PSR_8B_tag PSR211; /* offset: 0x0113 size: 8 bit */
+ INTC_PSR_8B_tag PSR212; /* offset: 0x0114 size: 8 bit */
+ INTC_PSR_8B_tag PSR213; /* offset: 0x0115 size: 8 bit */
+ INTC_PSR_8B_tag PSR214; /* offset: 0x0116 size: 8 bit */
+ INTC_PSR_8B_tag PSR215; /* offset: 0x0117 size: 8 bit */
+ INTC_PSR_8B_tag PSR216; /* offset: 0x0118 size: 8 bit */
+ INTC_PSR_8B_tag PSR217; /* offset: 0x0119 size: 8 bit */
+ INTC_PSR_8B_tag PSR218; /* offset: 0x011A size: 8 bit */
+ INTC_PSR_8B_tag PSR219; /* offset: 0x011B size: 8 bit */
+ INTC_PSR_8B_tag PSR220; /* offset: 0x011C size: 8 bit */
+ INTC_PSR_8B_tag PSR221; /* offset: 0x011D size: 8 bit */
+ INTC_PSR_8B_tag PSR222; /* offset: 0x011E size: 8 bit */
+ INTC_PSR_8B_tag PSR223; /* offset: 0x011F size: 8 bit */
+ INTC_PSR_8B_tag PSR224; /* offset: 0x0120 size: 8 bit */
+ INTC_PSR_8B_tag PSR225; /* offset: 0x0121 size: 8 bit */
+ INTC_PSR_8B_tag PSR226; /* offset: 0x0122 size: 8 bit */
+ INTC_PSR_8B_tag PSR227; /* offset: 0x0123 size: 8 bit */
+ INTC_PSR_8B_tag PSR228; /* offset: 0x0124 size: 8 bit */
+ INTC_PSR_8B_tag PSR229; /* offset: 0x0125 size: 8 bit */
+ INTC_PSR_8B_tag PSR230; /* offset: 0x0126 size: 8 bit */
+ INTC_PSR_8B_tag PSR231; /* offset: 0x0127 size: 8 bit */
+ INTC_PSR_8B_tag PSR232; /* offset: 0x0128 size: 8 bit */
+ INTC_PSR_8B_tag PSR233; /* offset: 0x0129 size: 8 bit */
+ INTC_PSR_8B_tag PSR234; /* offset: 0x012A size: 8 bit */
+ INTC_PSR_8B_tag PSR235; /* offset: 0x012B size: 8 bit */
+ INTC_PSR_8B_tag PSR236; /* offset: 0x012C size: 8 bit */
+ INTC_PSR_8B_tag PSR237; /* offset: 0x012D size: 8 bit */
+ INTC_PSR_8B_tag PSR238; /* offset: 0x012E size: 8 bit */
+ INTC_PSR_8B_tag PSR239; /* offset: 0x012F size: 8 bit */
+ INTC_PSR_8B_tag PSR240; /* offset: 0x0130 size: 8 bit */
+ INTC_PSR_8B_tag PSR241; /* offset: 0x0131 size: 8 bit */
+ INTC_PSR_8B_tag PSR242; /* offset: 0x0132 size: 8 bit */
+ INTC_PSR_8B_tag PSR243; /* offset: 0x0133 size: 8 bit */
+ INTC_PSR_8B_tag PSR244; /* offset: 0x0134 size: 8 bit */
+ INTC_PSR_8B_tag PSR245; /* offset: 0x0135 size: 8 bit */
+ INTC_PSR_8B_tag PSR246; /* offset: 0x0136 size: 8 bit */
+ INTC_PSR_8B_tag PSR247; /* offset: 0x0137 size: 8 bit */
+ INTC_PSR_8B_tag PSR248; /* offset: 0x0138 size: 8 bit */
+ INTC_PSR_8B_tag PSR249; /* offset: 0x0139 size: 8 bit */
+ INTC_PSR_8B_tag PSR250; /* offset: 0x013A size: 8 bit */
+ INTC_PSR_8B_tag PSR251; /* offset: 0x013B size: 8 bit */
+ INTC_PSR_8B_tag PSR252; /* offset: 0x013C size: 8 bit */
+ INTC_PSR_8B_tag PSR253; /* offset: 0x013D size: 8 bit */
+ INTC_PSR_8B_tag PSR254; /* offset: 0x013E size: 8 bit */
+ INTC_PSR_8B_tag PSR255; /* offset: 0x013F size: 8 bit */
+ INTC_PSR_8B_tag PSR256; /* offset: 0x0140 size: 8 bit */
+ INTC_PSR_8B_tag PSR257; /* offset: 0x0141 size: 8 bit */
+ INTC_PSR_8B_tag PSR258; /* offset: 0x0142 size: 8 bit */
+ INTC_PSR_8B_tag PSR259; /* offset: 0x0143 size: 8 bit */
+ INTC_PSR_8B_tag PSR260; /* offset: 0x0144 size: 8 bit */
+ INTC_PSR_8B_tag PSR261; /* offset: 0x0145 size: 8 bit */
+ INTC_PSR_8B_tag PSR262; /* offset: 0x0146 size: 8 bit */
+ INTC_PSR_8B_tag PSR263; /* offset: 0x0147 size: 8 bit */
+ INTC_PSR_8B_tag PSR264; /* offset: 0x0148 size: 8 bit */
+ INTC_PSR_8B_tag PSR265; /* offset: 0x0149 size: 8 bit */
+ INTC_PSR_8B_tag PSR266; /* offset: 0x014A size: 8 bit */
+ INTC_PSR_8B_tag PSR267; /* offset: 0x014B size: 8 bit */
+ INTC_PSR_8B_tag PSR268; /* offset: 0x014C size: 8 bit */
+ INTC_PSR_8B_tag PSR269; /* offset: 0x014D size: 8 bit */
+ INTC_PSR_8B_tag PSR270; /* offset: 0x014E size: 8 bit */
+ INTC_PSR_8B_tag PSR271; /* offset: 0x014F size: 8 bit */
+ INTC_PSR_8B_tag PSR272; /* offset: 0x0150 size: 8 bit */
+ INTC_PSR_8B_tag PSR273; /* offset: 0x0151 size: 8 bit */
+ INTC_PSR_8B_tag PSR274; /* offset: 0x0152 size: 8 bit */
+ INTC_PSR_8B_tag PSR275; /* offset: 0x0153 size: 8 bit */
+ INTC_PSR_8B_tag PSR276; /* offset: 0x0154 size: 8 bit */
+ INTC_PSR_8B_tag PSR277; /* offset: 0x0155 size: 8 bit */
+ INTC_PSR_8B_tag PSR278; /* offset: 0x0156 size: 8 bit */
+ INTC_PSR_8B_tag PSR279; /* offset: 0x0157 size: 8 bit */
+ INTC_PSR_8B_tag PSR280; /* offset: 0x0158 size: 8 bit */
+ INTC_PSR_8B_tag PSR281; /* offset: 0x0159 size: 8 bit */
+ INTC_PSR_8B_tag PSR282; /* offset: 0x015A size: 8 bit */
+ INTC_PSR_8B_tag PSR283; /* offset: 0x015B size: 8 bit */
+ INTC_PSR_8B_tag PSR284; /* offset: 0x015C size: 8 bit */
+ INTC_PSR_8B_tag PSR285; /* offset: 0x015D size: 8 bit */
+ INTC_PSR_8B_tag PSR286; /* offset: 0x015E size: 8 bit */
+ INTC_PSR_8B_tag PSR287; /* offset: 0x015F size: 8 bit */
+ INTC_PSR_8B_tag PSR288; /* offset: 0x0160 size: 8 bit */
+ INTC_PSR_8B_tag PSR289; /* offset: 0x0161 size: 8 bit */
+ INTC_PSR_8B_tag PSR290; /* offset: 0x0162 size: 8 bit */
+ INTC_PSR_8B_tag PSR291; /* offset: 0x0163 size: 8 bit */
+ INTC_PSR_8B_tag PSR292; /* offset: 0x0164 size: 8 bit */
+ INTC_PSR_8B_tag PSR293; /* offset: 0x0165 size: 8 bit */
+ INTC_PSR_8B_tag PSR294; /* offset: 0x0166 size: 8 bit */
+ INTC_PSR_8B_tag PSR295; /* offset: 0x0167 size: 8 bit */
+ INTC_PSR_8B_tag PSR296; /* offset: 0x0168 size: 8 bit */
+ INTC_PSR_8B_tag PSR297; /* offset: 0x0169 size: 8 bit */
+ INTC_PSR_8B_tag PSR298; /* offset: 0x016A size: 8 bit */
+ INTC_PSR_8B_tag PSR299; /* offset: 0x016B size: 8 bit */
+ INTC_PSR_8B_tag PSR300; /* offset: 0x016C size: 8 bit */
+ INTC_PSR_8B_tag PSR301; /* offset: 0x016D size: 8 bit */
+ INTC_PSR_8B_tag PSR302; /* offset: 0x016E size: 8 bit */
+ INTC_PSR_8B_tag PSR303; /* offset: 0x016F size: 8 bit */
+ INTC_PSR_8B_tag PSR304; /* offset: 0x0170 size: 8 bit */
+ INTC_PSR_8B_tag PSR305; /* offset: 0x0171 size: 8 bit */
+ INTC_PSR_8B_tag PSR306; /* offset: 0x0172 size: 8 bit */
+ INTC_PSR_8B_tag PSR307; /* offset: 0x0173 size: 8 bit */
+ INTC_PSR_8B_tag PSR308; /* offset: 0x0174 size: 8 bit */
+ INTC_PSR_8B_tag PSR309; /* offset: 0x0175 size: 8 bit */
+ INTC_PSR_8B_tag PSR310; /* offset: 0x0176 size: 8 bit */
+ INTC_PSR_8B_tag PSR311; /* offset: 0x0177 size: 8 bit */
+ INTC_PSR_8B_tag PSR312; /* offset: 0x0178 size: 8 bit */
+ INTC_PSR_8B_tag PSR313; /* offset: 0x0179 size: 8 bit */
+ INTC_PSR_8B_tag PSR314; /* offset: 0x017A size: 8 bit */
+ INTC_PSR_8B_tag PSR315; /* offset: 0x017B size: 8 bit */
+ INTC_PSR_8B_tag PSR316; /* offset: 0x017C size: 8 bit */
+ INTC_PSR_8B_tag PSR317; /* offset: 0x017D size: 8 bit */
+ INTC_PSR_8B_tag PSR318; /* offset: 0x017E size: 8 bit */
+ INTC_PSR_8B_tag PSR319; /* offset: 0x017F size: 8 bit */
+ INTC_PSR_8B_tag PSR320; /* offset: 0x0180 size: 8 bit */
+ INTC_PSR_8B_tag PSR321; /* offset: 0x0181 size: 8 bit */
+ INTC_PSR_8B_tag PSR322; /* offset: 0x0182 size: 8 bit */
+ INTC_PSR_8B_tag PSR323; /* offset: 0x0183 size: 8 bit */
+ INTC_PSR_8B_tag PSR324; /* offset: 0x0184 size: 8 bit */
+ INTC_PSR_8B_tag PSR325; /* offset: 0x0185 size: 8 bit */
+ INTC_PSR_8B_tag PSR326; /* offset: 0x0186 size: 8 bit */
+ INTC_PSR_8B_tag PSR327; /* offset: 0x0187 size: 8 bit */
+ INTC_PSR_8B_tag PSR328; /* offset: 0x0188 size: 8 bit */
+ INTC_PSR_8B_tag PSR329; /* offset: 0x0189 size: 8 bit */
+ INTC_PSR_8B_tag PSR330; /* offset: 0x018A size: 8 bit */
+ INTC_PSR_8B_tag PSR331; /* offset: 0x018B size: 8 bit */
+ INTC_PSR_8B_tag PSR332; /* offset: 0x018C size: 8 bit */
+ INTC_PSR_8B_tag PSR333; /* offset: 0x018D size: 8 bit */
+ INTC_PSR_8B_tag PSR334; /* offset: 0x018E size: 8 bit */
+ INTC_PSR_8B_tag PSR335; /* offset: 0x018F size: 8 bit */
+ INTC_PSR_8B_tag PSR336; /* offset: 0x0190 size: 8 bit */
+ INTC_PSR_8B_tag PSR337; /* offset: 0x0191 size: 8 bit */
+ INTC_PSR_8B_tag PSR338; /* offset: 0x0192 size: 8 bit */
+ INTC_PSR_8B_tag PSR339; /* offset: 0x0193 size: 8 bit */
+ INTC_PSR_8B_tag PSR340; /* offset: 0x0194 size: 8 bit */
+ INTC_PSR_8B_tag PSR341; /* offset: 0x0195 size: 8 bit */
+ INTC_PSR_8B_tag PSR342; /* offset: 0x0196 size: 8 bit */
+ INTC_PSR_8B_tag PSR343; /* offset: 0x0197 size: 8 bit */
+ INTC_PSR_8B_tag PSR344; /* offset: 0x0198 size: 8 bit */
+ INTC_PSR_8B_tag PSR345; /* offset: 0x0199 size: 8 bit */
+ INTC_PSR_8B_tag PSR346; /* offset: 0x019A size: 8 bit */
+ INTC_PSR_8B_tag PSR347; /* offset: 0x019B size: 8 bit */
+ INTC_PSR_8B_tag PSR348; /* offset: 0x019C size: 8 bit */
+ INTC_PSR_8B_tag PSR349; /* offset: 0x019D size: 8 bit */
+ INTC_PSR_8B_tag PSR350; /* offset: 0x019E size: 8 bit */
+ INTC_PSR_8B_tag PSR351; /* offset: 0x019F size: 8 bit */
+ INTC_PSR_8B_tag PSR352; /* offset: 0x01A0 size: 8 bit */
+ INTC_PSR_8B_tag PSR353; /* offset: 0x01A1 size: 8 bit */
+ INTC_PSR_8B_tag PSR354; /* offset: 0x01A2 size: 8 bit */
+ INTC_PSR_8B_tag PSR355; /* offset: 0x01A3 size: 8 bit */
+ INTC_PSR_8B_tag PSR356; /* offset: 0x01A4 size: 8 bit */
+ INTC_PSR_8B_tag PSR357; /* offset: 0x01A5 size: 8 bit */
+ INTC_PSR_8B_tag PSR358; /* offset: 0x01A6 size: 8 bit */
+ INTC_PSR_8B_tag PSR359; /* offset: 0x01A7 size: 8 bit */
+ INTC_PSR_8B_tag PSR360; /* offset: 0x01A8 size: 8 bit */
+ INTC_PSR_8B_tag PSR361; /* offset: 0x01A9 size: 8 bit */
+ INTC_PSR_8B_tag PSR362; /* offset: 0x01AA size: 8 bit */
+ INTC_PSR_8B_tag PSR363; /* offset: 0x01AB size: 8 bit */
+ INTC_PSR_8B_tag PSR364; /* offset: 0x01AC size: 8 bit */
+ INTC_PSR_8B_tag PSR365; /* offset: 0x01AD size: 8 bit */
+ INTC_PSR_8B_tag PSR366; /* offset: 0x01AE size: 8 bit */
+ INTC_PSR_8B_tag PSR367; /* offset: 0x01AF size: 8 bit */
+ INTC_PSR_8B_tag PSR368; /* offset: 0x01B0 size: 8 bit */
+ INTC_PSR_8B_tag PSR369; /* offset: 0x01B1 size: 8 bit */
+ INTC_PSR_8B_tag PSR370; /* offset: 0x01B2 size: 8 bit */
+ INTC_PSR_8B_tag PSR371; /* offset: 0x01B3 size: 8 bit */
+ INTC_PSR_8B_tag PSR372; /* offset: 0x01B4 size: 8 bit */
+ INTC_PSR_8B_tag PSR373; /* offset: 0x01B5 size: 8 bit */
+ INTC_PSR_8B_tag PSR374; /* offset: 0x01B6 size: 8 bit */
+ INTC_PSR_8B_tag PSR375; /* offset: 0x01B7 size: 8 bit */
+ INTC_PSR_8B_tag PSR376; /* offset: 0x01B8 size: 8 bit */
+ INTC_PSR_8B_tag PSR377; /* offset: 0x01B9 size: 8 bit */
+ INTC_PSR_8B_tag PSR378; /* offset: 0x01BA size: 8 bit */
+ INTC_PSR_8B_tag PSR379; /* offset: 0x01BB size: 8 bit */
+ INTC_PSR_8B_tag PSR380; /* offset: 0x01BC size: 8 bit */
+ INTC_PSR_8B_tag PSR381; /* offset: 0x01BD size: 8 bit */
+ INTC_PSR_8B_tag PSR382; /* offset: 0x01BE size: 8 bit */
+ INTC_PSR_8B_tag PSR383; /* offset: 0x01BF size: 8 bit */
+ INTC_PSR_8B_tag PSR384; /* offset: 0x01C0 size: 8 bit */
+ INTC_PSR_8B_tag PSR385; /* offset: 0x01C1 size: 8 bit */
+ INTC_PSR_8B_tag PSR386; /* offset: 0x01C2 size: 8 bit */
+ INTC_PSR_8B_tag PSR387; /* offset: 0x01C3 size: 8 bit */
+ INTC_PSR_8B_tag PSR388; /* offset: 0x01C4 size: 8 bit */
+ INTC_PSR_8B_tag PSR389; /* offset: 0x01C5 size: 8 bit */
+ INTC_PSR_8B_tag PSR390; /* offset: 0x01C6 size: 8 bit */
+ INTC_PSR_8B_tag PSR391; /* offset: 0x01C7 size: 8 bit */
+ INTC_PSR_8B_tag PSR392; /* offset: 0x01C8 size: 8 bit */
+ INTC_PSR_8B_tag PSR393; /* offset: 0x01C9 size: 8 bit */
+ INTC_PSR_8B_tag PSR394; /* offset: 0x01CA size: 8 bit */
+ INTC_PSR_8B_tag PSR395; /* offset: 0x01CB size: 8 bit */
+ INTC_PSR_8B_tag PSR396; /* offset: 0x01CC size: 8 bit */
+ INTC_PSR_8B_tag PSR397; /* offset: 0x01CD size: 8 bit */
+ INTC_PSR_8B_tag PSR398; /* offset: 0x01CE size: 8 bit */
+ INTC_PSR_8B_tag PSR399; /* offset: 0x01CF size: 8 bit */
+ INTC_PSR_8B_tag PSR400; /* offset: 0x01D0 size: 8 bit */
+ INTC_PSR_8B_tag PSR401; /* offset: 0x01D1 size: 8 bit */
+ INTC_PSR_8B_tag PSR402; /* offset: 0x01D2 size: 8 bit */
+ INTC_PSR_8B_tag PSR403; /* offset: 0x01D3 size: 8 bit */
+ INTC_PSR_8B_tag PSR404; /* offset: 0x01D4 size: 8 bit */
+ INTC_PSR_8B_tag PSR405; /* offset: 0x01D5 size: 8 bit */
+ INTC_PSR_8B_tag PSR406; /* offset: 0x01D6 size: 8 bit */
+ INTC_PSR_8B_tag PSR407; /* offset: 0x01D7 size: 8 bit */
+ INTC_PSR_8B_tag PSR408; /* offset: 0x01D8 size: 8 bit */
+ INTC_PSR_8B_tag PSR409; /* offset: 0x01D9 size: 8 bit */
+ INTC_PSR_8B_tag PSR410; /* offset: 0x01DA size: 8 bit */
+ INTC_PSR_8B_tag PSR411; /* offset: 0x01DB size: 8 bit */
+ INTC_PSR_8B_tag PSR412; /* offset: 0x01DC size: 8 bit */
+ INTC_PSR_8B_tag PSR413; /* offset: 0x01DD size: 8 bit */
+ INTC_PSR_8B_tag PSR414; /* offset: 0x01DE size: 8 bit */
+ INTC_PSR_8B_tag PSR415; /* offset: 0x01DF size: 8 bit */
+ INTC_PSR_8B_tag PSR416; /* offset: 0x01E0 size: 8 bit */
+ INTC_PSR_8B_tag PSR417; /* offset: 0x01E1 size: 8 bit */
+ INTC_PSR_8B_tag PSR418; /* offset: 0x01E2 size: 8 bit */
+ INTC_PSR_8B_tag PSR419; /* offset: 0x01E3 size: 8 bit */
+ INTC_PSR_8B_tag PSR420; /* offset: 0x01E4 size: 8 bit */
+ INTC_PSR_8B_tag PSR421; /* offset: 0x01E5 size: 8 bit */
+ INTC_PSR_8B_tag PSR422; /* offset: 0x01E6 size: 8 bit */
+ INTC_PSR_8B_tag PSR423; /* offset: 0x01E7 size: 8 bit */
+ INTC_PSR_8B_tag PSR424; /* offset: 0x01E8 size: 8 bit */
+ INTC_PSR_8B_tag PSR425; /* offset: 0x01E9 size: 8 bit */
+ INTC_PSR_8B_tag PSR426; /* offset: 0x01EA size: 8 bit */
+ INTC_PSR_8B_tag PSR427; /* offset: 0x01EB size: 8 bit */
+ INTC_PSR_8B_tag PSR428; /* offset: 0x01EC size: 8 bit */
+ INTC_PSR_8B_tag PSR429; /* offset: 0x01ED size: 8 bit */
+ INTC_PSR_8B_tag PSR430; /* offset: 0x01EE size: 8 bit */
+ INTC_PSR_8B_tag PSR431; /* offset: 0x01EF size: 8 bit */
+ INTC_PSR_8B_tag PSR432; /* offset: 0x01F0 size: 8 bit */
+ INTC_PSR_8B_tag PSR433; /* offset: 0x01F1 size: 8 bit */
+ INTC_PSR_8B_tag PSR434; /* offset: 0x01F2 size: 8 bit */
+ INTC_PSR_8B_tag PSR435; /* offset: 0x01F3 size: 8 bit */
+ INTC_PSR_8B_tag PSR436; /* offset: 0x01F4 size: 8 bit */
+ INTC_PSR_8B_tag PSR437; /* offset: 0x01F5 size: 8 bit */
+ INTC_PSR_8B_tag PSR438; /* offset: 0x01F6 size: 8 bit */
+ INTC_PSR_8B_tag PSR439; /* offset: 0x01F7 size: 8 bit */
+ INTC_PSR_8B_tag PSR440; /* offset: 0x01F8 size: 8 bit */
+ INTC_PSR_8B_tag PSR441; /* offset: 0x01F9 size: 8 bit */
+ INTC_PSR_8B_tag PSR442; /* offset: 0x01FA size: 8 bit */
+ INTC_PSR_8B_tag PSR443; /* offset: 0x01FB size: 8 bit */
+ INTC_PSR_8B_tag PSR444; /* offset: 0x01FC size: 8 bit */
+ INTC_PSR_8B_tag PSR445; /* offset: 0x01FD size: 8 bit */
+ INTC_PSR_8B_tag PSR446; /* offset: 0x01FE size: 8 bit */
+ INTC_PSR_8B_tag PSR447; /* offset: 0x01FF size: 8 bit */
+ INTC_PSR_8B_tag PSR448; /* offset: 0x0200 size: 8 bit */
+ INTC_PSR_8B_tag PSR449; /* offset: 0x0201 size: 8 bit */
+ INTC_PSR_8B_tag PSR450; /* offset: 0x0202 size: 8 bit */
+ INTC_PSR_8B_tag PSR451; /* offset: 0x0203 size: 8 bit */
+ INTC_PSR_8B_tag PSR452; /* offset: 0x0204 size: 8 bit */
+ INTC_PSR_8B_tag PSR453; /* offset: 0x0205 size: 8 bit */
+ INTC_PSR_8B_tag PSR454; /* offset: 0x0206 size: 8 bit */
+ INTC_PSR_8B_tag PSR455; /* offset: 0x0207 size: 8 bit */
+ INTC_PSR_8B_tag PSR456; /* offset: 0x0208 size: 8 bit */
+ INTC_PSR_8B_tag PSR457; /* offset: 0x0209 size: 8 bit */
+ INTC_PSR_8B_tag PSR458; /* offset: 0x020A size: 8 bit */
+ INTC_PSR_8B_tag PSR459; /* offset: 0x020B size: 8 bit */
+ INTC_PSR_8B_tag PSR460; /* offset: 0x020C size: 8 bit */
+ INTC_PSR_8B_tag PSR461; /* offset: 0x020D size: 8 bit */
+ INTC_PSR_8B_tag PSR462; /* offset: 0x020E size: 8 bit */
+ INTC_PSR_8B_tag PSR463; /* offset: 0x020F size: 8 bit */
+ INTC_PSR_8B_tag PSR464; /* offset: 0x0210 size: 8 bit */
+ INTC_PSR_8B_tag PSR465; /* offset: 0x0211 size: 8 bit */
+ INTC_PSR_8B_tag PSR466; /* offset: 0x0212 size: 8 bit */
+ INTC_PSR_8B_tag PSR467; /* offset: 0x0213 size: 8 bit */
+ INTC_PSR_8B_tag PSR468; /* offset: 0x0214 size: 8 bit */
+ INTC_PSR_8B_tag PSR469; /* offset: 0x0215 size: 8 bit */
+ INTC_PSR_8B_tag PSR470; /* offset: 0x0216 size: 8 bit */
+ INTC_PSR_8B_tag PSR471; /* offset: 0x0217 size: 8 bit */
+ INTC_PSR_8B_tag PSR472; /* offset: 0x0218 size: 8 bit */
+ INTC_PSR_8B_tag PSR473; /* offset: 0x0219 size: 8 bit */
+ INTC_PSR_8B_tag PSR474; /* offset: 0x021A size: 8 bit */
+ INTC_PSR_8B_tag PSR475; /* offset: 0x021B size: 8 bit */
+ INTC_PSR_8B_tag PSR476; /* offset: 0x021C size: 8 bit */
+ INTC_PSR_8B_tag PSR477; /* offset: 0x021D size: 8 bit */
+ INTC_PSR_8B_tag PSR478; /* offset: 0x021E size: 8 bit */
+ INTC_PSR_8B_tag PSR479; /* offset: 0x021F size: 8 bit */
+ INTC_PSR_8B_tag PSR480; /* offset: 0x0220 size: 8 bit */
+ INTC_PSR_8B_tag PSR481; /* offset: 0x0221 size: 8 bit */
+ INTC_PSR_8B_tag PSR482; /* offset: 0x0222 size: 8 bit */
+ INTC_PSR_8B_tag PSR483; /* offset: 0x0223 size: 8 bit */
+ INTC_PSR_8B_tag PSR484; /* offset: 0x0224 size: 8 bit */
+ INTC_PSR_8B_tag PSR485; /* offset: 0x0225 size: 8 bit */
+ INTC_PSR_8B_tag PSR486; /* offset: 0x0226 size: 8 bit */
+ INTC_PSR_8B_tag PSR487; /* offset: 0x0227 size: 8 bit */
+ INTC_PSR_8B_tag PSR488; /* offset: 0x0228 size: 8 bit */
+ INTC_PSR_8B_tag PSR489; /* offset: 0x0229 size: 8 bit */
+ INTC_PSR_8B_tag PSR490; /* offset: 0x022A size: 8 bit */
+ INTC_PSR_8B_tag PSR491; /* offset: 0x022B size: 8 bit */
+ INTC_PSR_8B_tag PSR492; /* offset: 0x022C size: 8 bit */
+ INTC_PSR_8B_tag PSR493; /* offset: 0x022D size: 8 bit */
+ INTC_PSR_8B_tag PSR494; /* offset: 0x022E size: 8 bit */
+ INTC_PSR_8B_tag PSR495; /* offset: 0x022F size: 8 bit */
+ INTC_PSR_8B_tag PSR496; /* offset: 0x0230 size: 8 bit */
+ INTC_PSR_8B_tag PSR497; /* offset: 0x0231 size: 8 bit */
+ INTC_PSR_8B_tag PSR498; /* offset: 0x0232 size: 8 bit */
+ INTC_PSR_8B_tag PSR499; /* offset: 0x0233 size: 8 bit */
+ INTC_PSR_8B_tag PSR500; /* offset: 0x0234 size: 8 bit */
+ INTC_PSR_8B_tag PSR501; /* offset: 0x0235 size: 8 bit */
+ INTC_PSR_8B_tag PSR502; /* offset: 0x0236 size: 8 bit */
+ INTC_PSR_8B_tag PSR503; /* offset: 0x0237 size: 8 bit */
+ INTC_PSR_8B_tag PSR504; /* offset: 0x0238 size: 8 bit */
+ INTC_PSR_8B_tag PSR505; /* offset: 0x0239 size: 8 bit */
+ INTC_PSR_8B_tag PSR506; /* offset: 0x023A size: 8 bit */
+ INTC_PSR_8B_tag PSR507; /* offset: 0x023B size: 8 bit */
+ INTC_PSR_8B_tag PSR508; /* offset: 0x023C size: 8 bit */
+ INTC_PSR_8B_tag PSR509; /* offset: 0x023D size: 8 bit */
+ INTC_PSR_8B_tag PSR510; /* offset: 0x023E size: 8 bit */
+ INTC_PSR_8B_tag PSR511; /* offset: 0x023F size: 8 bit */
+ };
+
+ };
+ } INTC_tag;
+
+
+#define INTC (*(volatile INTC_tag *) 0xFFF48000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: DSPI */
+/* */
+/****************************************************************/
+
+ typedef union { /* MCR - Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MSTR:1; /* Master/Slave mode select */
+ vuint32_t CONT_SCKE:1; /* Continuous SCK Enable */
+ vuint32_t DCONF:2; /* DSPI Configuration */
+ vuint32_t FRZ:1; /* Freeze */
+ vuint32_t MTFE:1; /* Modified Timing Format Enable */
+ vuint32_t PCSSE:1; /* Peripheral Chip Select Strobe Enable */
+ vuint32_t ROOE:1; /* Receive FIFO Overflow Overwrite Enable */
+ vuint32_t PCSIS7:1; /* Peripheral Chip Select 7 Inactive State */
+ vuint32_t PCSIS6:1; /* Peripheral Chip Select 6 Inactive State */
+ vuint32_t PCSIS5:1; /* Peripheral Chip Select 5 Inactive State */
+ vuint32_t PCSIS4:1; /* Peripheral Chip Select 4 Inactive State */
+ vuint32_t PCSIS3:1; /* Peripheral Chip Select 3 Inactive State */
+ vuint32_t PCSIS2:1; /* Peripheral Chip Select 2 Inactive State */
+ vuint32_t PCSIS1:1; /* Peripheral Chip Select 1 Inactive State */
+ vuint32_t PCSIS0:1; /* Peripheral Chip Select 0 Inactive State */
+ vuint32_t DOZE:1; /* Doze Enable */
+ vuint32_t MDIS:1; /* Module Disable */
+ vuint32_t DIS_TXF:1; /* Disable Transmit FIFO */
+ vuint32_t DIS_RXF:1; /* Disable Receive FIFO */
+ vuint32_t CLR_TXF:1; /* Clear TX FIFO */
+ vuint32_t CLR_RXF:1; /* Clear RX FIFO */
+ vuint32_t SMPL_PT:2; /* Sample Point */
+ vuint32_t:7;
+ vuint32_t HALT:1; /* Halt */
+ } B;
+ } DSPI_MCR_32B_tag;
+
+ typedef union { /* TCR - Transfer Count Register */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t SPI_TCNT:16; /* SPI Transfer Counter */
+#else
+ vuint32_t TCNT:16; /* deprecated name - please avoid */
+#endif
+ vuint32_t:16;
+ } B;
+ } DSPI_TCR_32B_tag;
+
+
+ /* Register layout for all registers CTAR... */
+
+ typedef union { /* CTAR0-7 - Clock and Transfer Attribute Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t DBR:1; /* Double Baud Rate */
+ vuint32_t FMSZ:4; /* Frame Size */
+ vuint32_t CPOL:1; /* Clock Polarity */
+ vuint32_t CPHA:1; /* Clock Phase */
+ vuint32_t LSBFE:1; /* LSB First Enable */
+ vuint32_t PCSSCK:2; /* PCS to SCK Delay Prescaler */
+ vuint32_t PASC:2; /* After SCK Delay Prescaler */
+ vuint32_t PDT:2; /* Delay after Transfer Prescaler */
+ vuint32_t PBR:2; /* Baud Rate Prescaler */
+ vuint32_t CSSCK:4; /* PCS to SCK Delay Scaler */
+ vuint32_t ASC:4; /* After SCK Delay Scaler */
+ vuint32_t DT:4; /* Delay after Transfer Scaler */
+ vuint32_t BR:4; /* Baud Rate Scaler */
+ } B;
+ } DSPI_CTAR_32B_tag;
+
+ typedef union { /* SR - Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t TCF:1; /* Transfer Complete Flag */
+ vuint32_t TXRXS:1; /* TX & RX Status */
+ vuint32_t:1;
+ vuint32_t EOQF:1; /* End of queue Flag */
+ vuint32_t TFUF:1; /* Transmit FIFO Underflow Flag */
+ vuint32_t:1;
+ vuint32_t TFFF:1; /* Transmit FIFO FIll Flag */
+ vuint32_t:5;
+ vuint32_t RFOF:1; /* Receive FIFO Overflow Flag */
+ vuint32_t:1;
+ vuint32_t RFDF:1; /* Receive FIFO Drain Flag */
+ vuint32_t:1;
+ vuint32_t TXCTR:4; /* TX FIFO Counter */
+ vuint32_t TXNXTPTR:4; /* Transmit Next Pointer */
+ vuint32_t RXCTR:4; /* RX FIFO Counter */
+ vuint32_t POPNXTPTR:4; /* Pop Next Pointer */
+ } B;
+ } DSPI_SR_32B_tag;
+
+ typedef union { /* RSER - DMA/Interrupt Request Register */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t TCF_RE:1; /* Transmission Complete Request Enable */
+#else
+ vuint32_t TCFRE:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:2;
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t EOQF_RE:1; /* DSPI Finished Request Enable */
+#else
+ vuint32_t EOQFRE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t TFUF_RE:1; /* Transmit FIFO Underflow Request Enable */
+#else
+ vuint32_t TFUFRE:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:1;
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t TFFF_RE:1; /* Transmit FIFO Fill Request Enable */
+#else
+ vuint32_t TFFFRE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t TFFF_DIRS:1; /* Transmit FIFO Fill DMA or Interrupt Request Select */
+#else
+ vuint32_t TFFFDIRS:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:4;
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t RFOF_RE:1; /* Receive FIFO overflow Request Enable */
+#else
+ vuint32_t RFOFRE:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:1;
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t RFDF_RE:1; /* Receive FIFO Drain Request Enable */
+#else
+ vuint32_t RFDFRE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t RFDF_DIRS:1; /* Receive FIFO Drain DMA or Interrupt Request Select */
+#else
+ vuint32_t RFDFDIRS:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:16;
+ } B;
+ } DSPI_RSER_32B_tag;
+
+ typedef union { /* PUSHR - PUSH TX FIFO Register */
+ vuint32_t R;
+ struct {
+ vuint32_t CONT:1; /* Continuous Peripheral Chip Select Enable */
+ vuint32_t CTAS:3; /* Clock and Transfer Attributes Select */
+ vuint32_t EOQ:1; /* End of Queue */
+ vuint32_t CTCNT:1; /* Clear SPI_TCNT */
+ vuint32_t:2;
+ vuint32_t PCS7:1; /* Peripheral Chip Select 7 */
+ vuint32_t PCS6:1; /* Peripheral Chip Select 6 */
+ vuint32_t PCS5:1; /* Peripheral Chip Select 5 */
+ vuint32_t PCS4:1; /* Peripheral Chip Select 4 */
+ vuint32_t PCS3:1; /* Peripheral Chip Select 3 */
+ vuint32_t PCS2:1; /* Peripheral Chip Select 2 */
+ vuint32_t PCS1:1; /* Peripheral Chip Select 1 */
+ vuint32_t PCS0:1; /* Peripheral Chip Select 0 */
+ vuint32_t TXDATA:16; /* Transmit Data */
+ } B;
+ } DSPI_PUSHR_32B_tag;
+
+ typedef union { /* POPR - POP RX FIFO Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXDATA:16; /* Receive Data */
+ } B;
+ } DSPI_POPR_32B_tag;
+
+
+ /* Register layout for all registers TXFR... */
+
+ typedef union { /* Transmit FIFO Registers */
+ vuint32_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t FIFO_TXCMD:16; /* Transmit Command */
+#else
+ vuint32_t TXCMD:16; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t FIFO_TXDATA:16; /* Transmit Data */
+#else
+ vuint32_t TXDATA:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } DSPI_TXFR_32B_tag;
+
+
+ /* Register layout for all registers RXFR... */
+
+ typedef union { /* Receive FIFO Registers */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+#ifndef USE_FIELD_ALIASES_DSPI
+ vuint32_t FIFO_RXDATA:16; /* Transmit Data */
+#else
+ vuint32_t RXDATA:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } DSPI_RXFR_32B_tag;
+
+ typedef union { /* DSICR - DSI Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MTOE:1; /* Multiple Transfer Operation Enable */
+ vuint32_t:1;
+ vuint32_t MTOCNT:6; /* Multiple Transfer Operation Count */
+ vuint32_t:4;
+ vuint32_t TXSS:1; /* Transmit Data Source Select */
+ vuint32_t TPOL:1; /* Trigger Polarity */
+ vuint32_t TRRE:1; /* Trigger Reception Enable */
+ vuint32_t CID:1; /* Change in Data Transfer Enable */
+ vuint32_t DCONT:1; /* DSI Continuous Peripheral Chip Select Enable */
+ vuint32_t DSICTAS:3; /* DSI CLock and Transfer Attributes Select */
+ vuint32_t:4;
+ vuint32_t DPCS7:1; /* DSI Peripheral Chip Select 7 */
+ vuint32_t DPCS6:1; /* DSI Peripheral Chip Select 6 */
+ vuint32_t DPCS5:1; /* DSI Peripheral Chip Select 5 */
+ vuint32_t DPCS4:1; /* DSI Peripheral Chip Select 4 */
+ vuint32_t DPCS3:1; /* DSI Peripheral Chip Select 3 */
+ vuint32_t DPCS2:1; /* DSI Peripheral Chip Select 2 */
+ vuint32_t DPCS1:1; /* DSI Peripheral Chip Select 1 */
+ vuint32_t DPCS0:1; /* DSI Peripheral Chip Select 0 */
+ } B;
+ } DSPI_DSICR_32B_tag;
+
+ typedef union { /* SDR - DSI Serialization Data Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t SER_DATA:16; /* Serialized Data */
+ } B;
+ } DSPI_SDR_32B_tag;
+
+ typedef union { /* ASDR - DSI Alternate Serialization Data Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t ASER_DATA:16; /* Alternate Serialized Data */
+ } B;
+ } DSPI_ASDR_32B_tag;
+
+ typedef union { /* COMPR - DSI Transmit Comparison Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t COMP_DATA:16; /* Compare Data */
+ } B;
+ } DSPI_COMPR_32B_tag;
+
+ typedef union { /* DDR - DSI Deserialization Data Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t DESER_DATA:16; /* Deserialized Data */
+ } B;
+ } DSPI_DDR_32B_tag;
+
+ typedef union { /* DSICR1 - DSI Configuration Register 1 */
+ vuint32_t R;
+ } DSPI_DSICR1_32B_tag;
+
+
+
+ typedef struct DSPI_struct_tag { /* start of DSPI_tag */
+ /* MCR - Module Configuration Register */
+ DSPI_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
+ int8_t DSPI_reserved_0004[4];
+ /* TCR - Transfer Count Register */
+ DSPI_TCR_32B_tag TCR; /* offset: 0x0008 size: 32 bit */
+ union {
+ /* CTAR0-7 - Clock and Transfer Attribute Registers */
+ DSPI_CTAR_32B_tag CTAR[8]; /* offset: 0x000C (0x0004 x 8) */
+
+ struct {
+ /* CTAR0-7 - Clock and Transfer Attribute Registers */
+ DSPI_CTAR_32B_tag CTAR0; /* offset: 0x000C size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR1; /* offset: 0x0010 size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR2; /* offset: 0x0014 size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR3; /* offset: 0x0018 size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR4; /* offset: 0x001C size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR5; /* offset: 0x0020 size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR6; /* offset: 0x0024 size: 32 bit */
+ DSPI_CTAR_32B_tag CTAR7; /* offset: 0x0028 size: 32 bit */
+ };
+
+ };
+ /* SR - Status Register */
+ DSPI_SR_32B_tag SR; /* offset: 0x002C size: 32 bit */
+ /* RSER - DMA/Interrupt Request Register */
+ DSPI_RSER_32B_tag RSER; /* offset: 0x0030 size: 32 bit */
+ /* PUSHR - PUSH TX FIFO Register */
+ DSPI_PUSHR_32B_tag PUSHR; /* offset: 0x0034 size: 32 bit */
+ /* POPR - POP RX FIFO Register */
+ DSPI_POPR_32B_tag POPR; /* offset: 0x0038 size: 32 bit */
+ union {
+ /* Transmit FIFO Registers */
+ DSPI_TXFR_32B_tag TXFR[5]; /* offset: 0x003C (0x0004 x 5) */
+
+ struct {
+ /* Transmit FIFO Registers */
+ DSPI_TXFR_32B_tag TXFR0; /* offset: 0x003C size: 32 bit */
+ DSPI_TXFR_32B_tag TXFR1; /* offset: 0x0040 size: 32 bit */
+ DSPI_TXFR_32B_tag TXFR2; /* offset: 0x0044 size: 32 bit */
+ DSPI_TXFR_32B_tag TXFR3; /* offset: 0x0048 size: 32 bit */
+ DSPI_TXFR_32B_tag TXFR4; /* offset: 0x004C size: 32 bit */
+ };
+
+ };
+ int8_t DSPI_reserved_0050_C[44];
+ union {
+ /* Receive FIFO Registers */
+ DSPI_RXFR_32B_tag RXFR[5]; /* offset: 0x007C (0x0004 x 5) */
+
+ struct {
+ /* Receive FIFO Registers */
+ DSPI_RXFR_32B_tag RXFR0; /* offset: 0x007C size: 32 bit */
+ DSPI_RXFR_32B_tag RXFR1; /* offset: 0x0080 size: 32 bit */
+ DSPI_RXFR_32B_tag RXFR2; /* offset: 0x0084 size: 32 bit */
+ DSPI_RXFR_32B_tag RXFR3; /* offset: 0x0088 size: 32 bit */
+ DSPI_RXFR_32B_tag RXFR4; /* offset: 0x008C size: 32 bit */
+ };
+
+ };
+ int8_t DSPI_reserved_0090[44];
+ /* DSICR - DSI Configuration Register */
+ DSPI_DSICR_32B_tag DSICR; /* offset: 0x00BC size: 32 bit */
+ /* SDR - DSI Serialization Data Register */
+ DSPI_SDR_32B_tag SDR; /* offset: 0x00C0 size: 32 bit */
+ /* ASDR - DSI Alternate Serialization Data Register */
+ DSPI_ASDR_32B_tag ASDR; /* offset: 0x00C4 size: 32 bit */
+ /* COMPR - DSI Transmit Comparison Register */
+ DSPI_COMPR_32B_tag COMPR; /* offset: 0x00C8 size: 32 bit */
+ /* DDR - DSI Deserialization Data Register */
+ DSPI_DDR_32B_tag DDR; /* offset: 0x00CC size: 32 bit */
+ /* DSICR1 - DSI Configuration Register 1 */
+ DSPI_DSICR1_32B_tag DSICR1; /* offset: 0x00D0 size: 32 bit */
+ } DSPI_tag;
+
+
+#define DSPI_A (*(volatile DSPI_tag *) 0xFFF90000UL)
+#define DSPI_B (*(volatile DSPI_tag *) 0xFFF94000UL)
+#define DSPI_C (*(volatile DSPI_tag *) 0xFFF98000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: FLEXCAN */
+/* */
+/****************************************************************/
+
+ typedef union { /* MCR - Module Configuration Register */
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1; /* Module Disable */
+ vuint32_t FRZ:1; /* Freeze Enable */
+ vuint32_t FEN:1; /* FIFO Enable */
+ vuint32_t HALT:1; /* Halt Flexcan */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t NOT_RDY:1; /* Flexcan Not Ready */
+#else
+ vuint32_t NOTRDY:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t WAK_MSK:1; /* Wake Up Interrupt Mask */
+#else
+ vuint32_t WAKMSK:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t SOFT_RST:1; /* Soft Reset */
+#else
+ vuint32_t SOFTRST:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t FRZ_ACK:1; /* Freeze Mode Acknowledge */
+#else
+ vuint32_t FRZACK:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t SUPV:1; /* Supervisor Mode */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t SLF_WAK:1; /* Self Wake Up */
+#else
+ vuint32_t SLFWAK:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t WRN_EN:1; /* Warning Interrupt Enable */
+#else
+ vuint32_t WRNEN:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t LPM_ACK:1; /* Low Power Mode Acknowledge */
+#else
+ vuint32_t LPMACK:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t WAK_SRC:1; /* Wake Up Source */
+#else
+ vuint32_t WAKSRC:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t DOZE:1; /* Doze Mode Enable */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t SRX_DIS:1; /* Self Reception Disable */
+#else
+ vuint32_t SRXDIS:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t BCC:1; /* Backwards Compatibility Configuration */
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1; /* Local Priority Enable */
+ vuint32_t AEN:1; /* Abort Enable */
+ vuint32_t:2;
+ vuint32_t IDAM:2; /* ID Acceptance Mode */
+ vuint32_t:2;
+ vuint32_t MAXMB:6; /* Maximum Number of Message Buffers */
+ } B;
+ } FLEXCAN_MCR_32B_tag;
+
+ typedef union { /* CTRL - Control Register */
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8; /* Prescaler Divsion Factor */
+ vuint32_t RJW:2; /* Resync Jump Width */
+ vuint32_t PSEG1:3; /* Phase Segment 1 */
+ vuint32_t PSEG2:3; /* Phase Segment 2 */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BOFF_MSK:1; /* Bus Off Mask */
+#else
+ vuint32_t BOFFMSK:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t ERR_MSK:1; /* Error Mask */
+#else
+ vuint32_t ERRMSK:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t CLK_SRC:1; /* CAN Engine Clock Source */
+#else
+ vuint32_t CLKSRC:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t LPB:1; /* Loop Back */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t TWRN_MSK:1; /* Tx Warning Interrupt Mask */
+#else
+ vuint32_t TWRNMSK:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t RWRN_MSK:1; /* Rx Warning Interrupt Mask */
+#else
+ vuint32_t RWRNMSK:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t:2;
+ vuint32_t SMP:1; /* Sampling Mode */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BOFF_REC:1; /* Bus Off Recovery Mode */
+#else
+ vuint32_t BOFFREC:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t TSYN:1; /* Timer Sync Mode */
+ vuint32_t LBUF:1; /* Lowest Buffer Transmitted First */
+ vuint32_t LOM:1; /* Listen-Only Mode */
+ vuint32_t PROPSEG:3; /* Propagation Segment */
+ } B;
+ } FLEXCAN_CTRL_32B_tag;
+
+ typedef union { /* TIMER - Free Running Timer */
+ vuint32_t R;
+ } FLEXCAN_TIMER_32B_tag;
+
+ typedef union { /* RXGMASK - Rx Global Mask Register */
+ vuint32_t R;
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ struct {
+ vuint32_t MI:32; /* deprecated field -- do not use */
+ } B;
+#endif
+ } FLEXCAN_RXGMASK_32B_tag;
+
+ typedef union { /* RX14MASK - Rx 14 Mask Register */
+ vuint32_t R;
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ struct {
+ vuint32_t MI:32; /* deprecated field -- do not use */
+ } B;
+#endif
+ } FLEXCAN_RX14MASK_32B_tag;
+
+ typedef union { /* RX15MASK - Rx 15 Mask Register */
+ vuint32_t R;
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ struct {
+ vuint32_t MI:32; /* deprecated field -- do not use */
+ } B;
+#endif
+ } FLEXCAN_RX15MASK_32B_tag;
+
+ typedef union { /* ECR - Error Counter Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t RX_ERR_COUNTER:8; /* Rx Error Counter */
+#else
+ vuint32_t RXECNT:8; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t TX_ERR_COUNTER:8; /* Tx Error Counter */
+#else
+ vuint32_t TXECNT:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FLEXCAN_ECR_32B_tag;
+
+ typedef union { /* ESR - Error and Status Register */
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t TWRN_INT:1; /* Tx Warning Interrupt Flag */
+#else
+ vuint32_t TWRNINT:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t RWRN_INT:1; /* Rx Warning Interrupt Flag */
+#else
+ vuint32_t RWRNINT:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BIT1_ERR:1; /* Bit 1 Error */
+#else
+ vuint32_t BIT1ERR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BIT0_ERR:1; /* Bit 0 Error */
+#else
+ vuint32_t BIT0ERR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t ACK_ERR:1; /* Acknowledge Error */
+#else
+ vuint32_t ACKERR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t CRC_ERR:1; /* Cyclic Redundancy Check Error */
+#else
+ vuint32_t CRCERR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t FRM_ERR:1; /* Form Error */
+#else
+ vuint32_t FRMERR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t STF_ERR:1; /* Stuffing Error */
+#else
+ vuint32_t STFERR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t TX_WRN:1; /* Tx Error Counter */
+#else
+ vuint32_t TXWRN:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t RX_WRN:1; /* Rx Error Counter */
+#else
+ vuint32_t RXWRN:1; /* deprecated name - please avoid */
+#endif
+ vuint32_t IDLE:1; /* CAN bus Idle State */
+ vuint32_t TXRX:1; /* Current Flexcan Status */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t FLT_CONF:2; /* Fault Confinement State */
+#else
+ vuint32_t FLTCONF:2; /* deprecated name - please avoid */
+#endif
+ vuint32_t:1;
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BOFF_INT:1; /* Bus Off Interrupt */
+#else
+ vuint32_t BOFFINT:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t ERR_INT:1; /* Error Interrupt */
+#else
+ vuint32_t ERRINT:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t WAK_INT:1; /* Wake-Up Interrupt */
+#else
+ vuint32_t WAKINT:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FLEXCAN_ESR_32B_tag;
+
+ typedef union { /* IMASK2 - Interrupt Masks 2 Register */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1; /* Buffer MB Mask 63 Bit */
+ vuint32_t BUF62M:1; /* Buffer MB Mask 62 Bit */
+ vuint32_t BUF61M:1; /* Buffer MB Mask 61 Bit */
+ vuint32_t BUF60M:1; /* Buffer MB Mask 60 Bit */
+ vuint32_t BUF59M:1; /* Buffer MB Mask 59 Bit */
+ vuint32_t BUF58M:1; /* Buffer MB Mask 58 Bit */
+ vuint32_t BUF57M:1; /* Buffer MB Mask 57 Bit */
+ vuint32_t BUF56M:1; /* Buffer MB Mask 56 Bit */
+ vuint32_t BUF55M:1; /* Buffer MB Mask 55 Bit */
+ vuint32_t BUF54M:1; /* Buffer MB Mask 54 Bit */
+ vuint32_t BUF53M:1; /* Buffer MB Mask 53 Bit */
+ vuint32_t BUF52M:1; /* Buffer MB Mask 52 Bit */
+ vuint32_t BUF51M:1; /* Buffer MB Mask 51 Bit */
+ vuint32_t BUF50M:1; /* Buffer MB Mask 50 Bit */
+ vuint32_t BUF49M:1; /* Buffer MB Mask 49 Bit */
+ vuint32_t BUF48M:1; /* Buffer MB Mask 48 Bit */
+ vuint32_t BUF47M:1; /* Buffer MB Mask 47 Bit */
+ vuint32_t BUF46M:1; /* Buffer MB Mask 46 Bit */
+ vuint32_t BUF45M:1; /* Buffer MB Mask 45 Bit */
+ vuint32_t BUF44M:1; /* Buffer MB Mask 44 Bit */
+ vuint32_t BUF43M:1; /* Buffer MB Mask 43 Bit */
+ vuint32_t BUF42M:1; /* Buffer MB Mask 42 Bit */
+ vuint32_t BUF41M:1; /* Buffer MB Mask 41 Bit */
+ vuint32_t BUF40M:1; /* Buffer MB Mask 40 Bit */
+ vuint32_t BUF39M:1; /* Buffer MB Mask 39 Bit */
+ vuint32_t BUF38M:1; /* Buffer MB Mask 38 Bit */
+ vuint32_t BUF37M:1; /* Buffer MB Mask 37 Bit */
+ vuint32_t BUF36M:1; /* Buffer MB Mask 36 Bit */
+ vuint32_t BUF35M:1; /* Buffer MB Mask 35 Bit */
+ vuint32_t BUF34M:1; /* Buffer MB Mask 34 Bit */
+ vuint32_t BUF33M:1; /* Buffer MB Mask 33 Bit */
+ vuint32_t BUF32M:1; /* Buffer MB Mask 32 Bit */
+ } B;
+ } FLEXCAN_IMASK2_32B_tag;
+
+ typedef union { /* IMASK1 - Interrupt Masks 1 Register */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1; /* Buffer MB Mask 31 Bit */
+ vuint32_t BUF30M:1; /* Buffer MB Mask 30 Bit */
+ vuint32_t BUF29M:1; /* Buffer MB Mask 29 Bit */
+ vuint32_t BUF28M:1; /* Buffer MB Mask 28 Bit */
+ vuint32_t BUF27M:1; /* Buffer MB Mask 27 Bit */
+ vuint32_t BUF26M:1; /* Buffer MB Mask 26 Bit */
+ vuint32_t BUF25M:1; /* Buffer MB Mask 25 Bit */
+ vuint32_t BUF24M:1; /* Buffer MB Mask 24 Bit */
+ vuint32_t BUF23M:1; /* Buffer MB Mask 23 Bit */
+ vuint32_t BUF22M:1; /* Buffer MB Mask 22 Bit */
+ vuint32_t BUF21M:1; /* Buffer MB Mask 21 Bit */
+ vuint32_t BUF20M:1; /* Buffer MB Mask 20 Bit */
+ vuint32_t BUF19M:1; /* Buffer MB Mask 19 Bit */
+ vuint32_t BUF18M:1; /* Buffer MB Mask 18 Bit */
+ vuint32_t BUF17M:1; /* Buffer MB Mask 17 Bit */
+ vuint32_t BUF16M:1; /* Buffer MB Mask 16 Bit */
+ vuint32_t BUF15M:1; /* Buffer MB Mask 15 Bit */
+ vuint32_t BUF14M:1; /* Buffer MB Mask 14 Bit */
+ vuint32_t BUF13M:1; /* Buffer MB Mask 13 Bit */
+ vuint32_t BUF12M:1; /* Buffer MB Mask 12 Bit */
+ vuint32_t BUF11M:1; /* Buffer MB Mask 11 Bit */
+ vuint32_t BUF10M:1; /* Buffer MB Mask 10 Bit */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF9M:1; /* Buffer MB Mask 9 Bit */
+#else
+ vuint32_t BUF09M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF8M:1; /* Buffer MB Mask 8 Bit */
+#else
+ vuint32_t BUF08M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF7M:1; /* Buffer MB Mask 7 Bit */
+#else
+ vuint32_t BUF07M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF6M:1; /* Buffer MB Mask 6 Bit */
+#else
+ vuint32_t BUF06M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF5M:1; /* Buffer MB Mask 5 Bit */
+#else
+ vuint32_t BUF05M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF4M:1; /* Buffer MB Mask 4 Bit */
+#else
+ vuint32_t BUF04M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF3M:1; /* Buffer MB Mask 3 Bit */
+#else
+ vuint32_t BUF03M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF2M:1; /* Buffer MB Mask 2 Bit */
+#else
+ vuint32_t BUF02M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF1M:1; /* Buffer MB Mask 1 Bit */
+#else
+ vuint32_t BUF01M:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF0M:1; /* Buffer MB Mask 0 Bit */
+#else
+ vuint32_t BUF00M:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FLEXCAN_IMASK1_32B_tag;
+
+ typedef union { /* IFLAG2 - Interrupt Flags 2 Register */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1; /* Buffer MB Interrupt 63 Bit */
+ vuint32_t BUF62I:1; /* Buffer MB Interrupt 62 Bit */
+ vuint32_t BUF61I:1; /* Buffer MB Interrupt 61 Bit */
+ vuint32_t BUF60I:1; /* Buffer MB Interrupt 60 Bit */
+ vuint32_t BUF59I:1; /* Buffer MB Interrupt 59 Bit */
+ vuint32_t BUF58I:1; /* Buffer MB Interrupt 58 Bit */
+ vuint32_t BUF57I:1; /* Buffer MB Interrupt 57 Bit */
+ vuint32_t BUF56I:1; /* Buffer MB Interrupt 56 Bit */
+ vuint32_t BUF55I:1; /* Buffer MB Interrupt 55 Bit */
+ vuint32_t BUF54I:1; /* Buffer MB Interrupt 54 Bit */
+ vuint32_t BUF53I:1; /* Buffer MB Interrupt 53 Bit */
+ vuint32_t BUF52I:1; /* Buffer MB Interrupt 52 Bit */
+ vuint32_t BUF51I:1; /* Buffer MB Interrupt 51 Bit */
+ vuint32_t BUF50I:1; /* Buffer MB Interrupt 50 Bit */
+ vuint32_t BUF49I:1; /* Buffer MB Interrupt 49 Bit */
+ vuint32_t BUF48I:1; /* Buffer MB Interrupt 48 Bit */
+ vuint32_t BUF47I:1; /* Buffer MB Interrupt 47 Bit */
+ vuint32_t BUF46I:1; /* Buffer MB Interrupt 46 Bit */
+ vuint32_t BUF45I:1; /* Buffer MB Interrupt 45 Bit */
+ vuint32_t BUF44I:1; /* Buffer MB Interrupt 44 Bit */
+ vuint32_t BUF43I:1; /* Buffer MB Interrupt 43 Bit */
+ vuint32_t BUF42I:1; /* Buffer MB Interrupt 42 Bit */
+ vuint32_t BUF41I:1; /* Buffer MB Interrupt 41 Bit */
+ vuint32_t BUF40I:1; /* Buffer MB Interrupt 40 Bit */
+ vuint32_t BUF39I:1; /* Buffer MB Interrupt 39 Bit */
+ vuint32_t BUF38I:1; /* Buffer MB Interrupt 38 Bit */
+ vuint32_t BUF37I:1; /* Buffer MB Interrupt 37 Bit */
+ vuint32_t BUF36I:1; /* Buffer MB Interrupt 36 Bit */
+ vuint32_t BUF35I:1; /* Buffer MB Interrupt 35 Bit */
+ vuint32_t BUF34I:1; /* Buffer MB Interrupt 34 Bit */
+ vuint32_t BUF33I:1; /* Buffer MB Interrupt 33 Bit */
+ vuint32_t BUF32I:1; /* Buffer MB Interrupt 32 Bit */
+ } B;
+ } FLEXCAN_IFLAG2_32B_tag;
+
+ typedef union { /* IFLAG1 - Interrupt Flags 1 Register */
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1; /* Buffer MB Interrupt 31 Bit */
+ vuint32_t BUF30I:1; /* Buffer MB Interrupt 30 Bit */
+ vuint32_t BUF29I:1; /* Buffer MB Interrupt 29 Bit */
+ vuint32_t BUF28I:1; /* Buffer MB Interrupt 28 Bit */
+ vuint32_t BUF27I:1; /* Buffer MB Interrupt 27 Bit */
+ vuint32_t BUF26I:1; /* Buffer MB Interrupt 26 Bit */
+ vuint32_t BUF25I:1; /* Buffer MB Interrupt 25 Bit */
+ vuint32_t BUF24I:1; /* Buffer MB Interrupt 24 Bit */
+ vuint32_t BUF23I:1; /* Buffer MB Interrupt 23 Bit */
+ vuint32_t BUF22I:1; /* Buffer MB Interrupt 22 Bit */
+ vuint32_t BUF21I:1; /* Buffer MB Interrupt 21 Bit */
+ vuint32_t BUF20I:1; /* Buffer MB Interrupt 20 Bit */
+ vuint32_t BUF19I:1; /* Buffer MB Interrupt 19 Bit */
+ vuint32_t BUF18I:1; /* Buffer MB Interrupt 18 Bit */
+ vuint32_t BUF17I:1; /* Buffer MB Interrupt 17 Bit */
+ vuint32_t BUF16I:1; /* Buffer MB Interrupt 16 Bit */
+ vuint32_t BUF15I:1; /* Buffer MB Interrupt 15 Bit */
+ vuint32_t BUF14I:1; /* Buffer MB Interrupt 14 Bit */
+ vuint32_t BUF13I:1; /* Buffer MB Interrupt 13 Bit */
+ vuint32_t BUF12I:1; /* Buffer MB Interrupt 12 Bit */
+ vuint32_t BUF11I:1; /* Buffer MB Interrupt 11 Bit */
+ vuint32_t BUF10I:1; /* Buffer MB Interrupt 10 Bit */
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF9I:1; /* Buffer MB Interrupt 9 Bit */
+#else
+ vuint32_t BUF09I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF8I:1; /* Buffer MB Interrupt 8 Bit */
+#else
+ vuint32_t BUF08I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF7I:1; /* Buffer MB Interrupt 7 Bit */
+#else
+ vuint32_t BUF07I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF6I:1; /* Buffer MB Interrupt 6 Bit */
+#else
+ vuint32_t BUF06I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF5I:1; /* Buffer MB Interrupt 5 Bit */
+#else
+ vuint32_t BUF05I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF4I:1; /* Buffer MB Interrupt 4 Bit */
+#else
+ vuint32_t BUF04I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF3I:1; /* Buffer MB Interrupt 3 Bit */
+#else
+ vuint32_t BUF03I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF2I:1; /* Buffer MB Interrupt 2 Bit */
+#else
+ vuint32_t BUF02I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF1I:1; /* Buffer MB Interrupt 1 Bit */
+#else
+ vuint32_t BUF01I:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FLEXCAN
+ vuint32_t BUF0I:1; /* Buffer MB Interrupt 0 Bit */
+#else
+ vuint32_t BUF00I:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FLEXCAN_IFLAG1_32B_tag;
+
+
+ /* Register layout for all registers MSG_CS... */
+
+ typedef union { /* Message Buffer Control and Status */
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4; /* Message Buffer Code */
+ vuint32_t:1;
+ vuint32_t SRR:1; /* Substitute Remote Request */
+ vuint32_t IDE:1; /* ID Extended Bit */
+ vuint32_t RTR:1; /* Remote Transmission Request */
+ vuint32_t LENGTH:4; /* Length of Data in Bytes */
+ vuint32_t TIMESTAMP:16; /* Free-Running Counter Time Stamp */
+ } B;
+ } FLEXCAN_MSG_CS_32B_tag;
+
+
+ /* Register layout for all registers MSG_ID... */
+
+ typedef union { /* Message Buffer Identifier Field */
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3; /* Local Priority */
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } FLEXCAN_MSG_ID_32B_tag;
+
+
+ /* Register layout for all registers MSG_BYTE0_3... */
+
+ typedef union { /* Message Buffer Data Register */
+ vuint32_t R;
+ vuint8_t BYTE[4]; /* individual bytes can be accessed */
+ vuint32_t WORD; /* individual words can be accessed */
+ } FLEXCAN_MSG_DATA_32B_tag;
+
+ typedef union {
+ vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */
+ vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ vuint32_t R[2]; /* Data buffer in words (32 bits) */
+ } FLEXCAN_MSG_DATA2_32B_tag;
+
+ /* Register layout for all registers MSG_BYTE4_7 matches xxx */
+
+
+ /* Register layout for all registers RXIMR... */
+
+ typedef union { /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
+ vuint32_t R;
+ } FLEXCAN_RXIMR_32B_tag;
+
+
+ typedef struct FLEXCAN_MB_struct_tag {
+
+ union {
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG_CS; /* relative offset: 0x0000 */
+ FLEXCAN_MSG_CS_32B_tag CS; /* deprecated - please avoid */
+ };
+ union {
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG_ID; /* relative offset: 0x0004 */
+ FLEXCAN_MSG_ID_32B_tag ID; /* deprecated - please avoid */
+ };
+ union { /* Message Buffer Data Register */
+
+ struct {
+ FLEXCAN_MSG_DATA_32B_tag MSG_BYTE0_3; /* relative offset: 0x0008 */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG_BYTE4_7; /* relative offset: 0x000C */
+ };
+
+ FLEXCAN_MSG_DATA2_32B_tag DATA; /* relative offset: 0x000C */
+
+ };
+
+ } FLEXCAN_MB_tag;
+
+
+ typedef struct FLEXCAN_struct_tag { /* start of FLEXCAN_tag */
+ /* MCR - Module Configuration Register */
+ FLEXCAN_MCR_32B_tag MCR; /* offset: 0x0000 size: 32 bit */
+ union {
+ /* CTRL - Control Register */
+ FLEXCAN_CTRL_32B_tag CTRL; /* offset: 0x0004 size: 32 bit */
+
+ FLEXCAN_CTRL_32B_tag CR; /* deprecated - please avoid */
+
+ };
+ /* TIMER - Free Running Timer */
+ FLEXCAN_TIMER_32B_tag TIMER; /* offset: 0x0008 size: 32 bit */
+ int8_t FLEXCAN_reserved_000C[4];
+ /* RXGMASK - Rx Global Mask Register */
+ FLEXCAN_RXGMASK_32B_tag RXGMASK; /* offset: 0x0010 size: 32 bit */
+ /* RX14MASK - Rx 14 Mask Register */
+ FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */
+ /* RX15MASK - Rx 15 Mask Register */
+ FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */
+ /* ECR - Error Counter Register */
+ FLEXCAN_ECR_32B_tag ECR; /* offset: 0x001C size: 32 bit */
+ /* ESR - Error and Status Register */
+ FLEXCAN_ESR_32B_tag ESR; /* offset: 0x0020 size: 32 bit */
+ union {
+ FLEXCAN_IMASK2_32B_tag IMRH; /* deprecated - please avoid */
+
+ /* IMASK2 - Interrupt Masks 2 Register */
+ FLEXCAN_IMASK2_32B_tag IMASK2; /* offset: 0x0024 size: 32 bit */
+
+ };
+ union {
+ FLEXCAN_IMASK1_32B_tag IMRL; /* deprecated - please avoid */
+
+ /* IMASK1 - Interrupt Masks 1 Register */
+ FLEXCAN_IMASK1_32B_tag IMASK1; /* offset: 0x0028 size: 32 bit */
+
+ };
+ union {
+ FLEXCAN_IFLAG2_32B_tag IFRH; /* deprecated - please avoid */
+
+ /* IFLAG2 - Interrupt Flags 2 Register */
+ FLEXCAN_IFLAG2_32B_tag IFLAG2; /* offset: 0x002C size: 32 bit */
+
+ };
+ union {
+ FLEXCAN_IFLAG1_32B_tag IFRL; /* deprecated - please avoid */
+
+ /* IFLAG1 - Interrupt Flags 1 Register */
+ FLEXCAN_IFLAG1_32B_tag IFLAG1; /* offset: 0x0030 size: 32 bit */
+
+ };
+ int8_t FLEXCAN_reserved_0034_C[76];
+ union {
+ /* Register set MB */
+ FLEXCAN_MB_tag MB[64]; /* offset: 0x0080 (0x0010 x 64) */
+
+ /* Alias name for MB */
+ FLEXCAN_MB_tag BUF[64]; /* deprecated - please avoid */
+
+ struct {
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG0_CS; /* offset: 0x0080 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG0_ID; /* offset: 0x0084 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3; /* offset: 0x0088 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7; /* offset: 0x008C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG1_CS; /* offset: 0x0090 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG1_ID; /* offset: 0x0094 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3; /* offset: 0x0098 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7; /* offset: 0x009C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG2_CS; /* offset: 0x00A0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG2_ID; /* offset: 0x00A4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3; /* offset: 0x00A8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7; /* offset: 0x00AC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG3_CS; /* offset: 0x00B0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG3_ID; /* offset: 0x00B4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3; /* offset: 0x00B8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7; /* offset: 0x00BC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG4_CS; /* offset: 0x00C0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG4_ID; /* offset: 0x00C4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3; /* offset: 0x00C8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7; /* offset: 0x00CC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG5_CS; /* offset: 0x00D0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG5_ID; /* offset: 0x00D4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3; /* offset: 0x00D8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7; /* offset: 0x00DC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG6_CS; /* offset: 0x00E0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG6_ID; /* offset: 0x00E4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3; /* offset: 0x00E8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7; /* offset: 0x00EC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG7_CS; /* offset: 0x00F0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG7_ID; /* offset: 0x00F4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3; /* offset: 0x00F8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7; /* offset: 0x00FC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG8_CS; /* offset: 0x0100 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG8_ID; /* offset: 0x0104 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3; /* offset: 0x0108 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7; /* offset: 0x010C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG9_CS; /* offset: 0x0110 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG9_ID; /* offset: 0x0114 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3; /* offset: 0x0118 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7; /* offset: 0x011C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG10_CS; /* offset: 0x0120 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG10_ID; /* offset: 0x0124 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3; /* offset: 0x0128 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7; /* offset: 0x012C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG11_CS; /* offset: 0x0130 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG11_ID; /* offset: 0x0134 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3; /* offset: 0x0138 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7; /* offset: 0x013C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG12_CS; /* offset: 0x0140 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG12_ID; /* offset: 0x0144 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3; /* offset: 0x0148 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7; /* offset: 0x014C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG13_CS; /* offset: 0x0150 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG13_ID; /* offset: 0x0154 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3; /* offset: 0x0158 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7; /* offset: 0x015C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG14_CS; /* offset: 0x0160 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG14_ID; /* offset: 0x0164 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3; /* offset: 0x0168 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7; /* offset: 0x016C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG15_CS; /* offset: 0x0170 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG15_ID; /* offset: 0x0174 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3; /* offset: 0x0178 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7; /* offset: 0x017C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG16_CS; /* offset: 0x0180 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG16_ID; /* offset: 0x0184 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3; /* offset: 0x0188 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7; /* offset: 0x018C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG17_CS; /* offset: 0x0190 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG17_ID; /* offset: 0x0194 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3; /* offset: 0x0198 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7; /* offset: 0x019C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG18_CS; /* offset: 0x01A0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG18_ID; /* offset: 0x01A4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3; /* offset: 0x01A8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7; /* offset: 0x01AC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG19_CS; /* offset: 0x01B0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG19_ID; /* offset: 0x01B4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3; /* offset: 0x01B8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7; /* offset: 0x01BC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG20_CS; /* offset: 0x01C0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG20_ID; /* offset: 0x01C4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3; /* offset: 0x01C8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7; /* offset: 0x01CC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG21_CS; /* offset: 0x01D0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG21_ID; /* offset: 0x01D4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3; /* offset: 0x01D8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7; /* offset: 0x01DC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG22_CS; /* offset: 0x01E0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG22_ID; /* offset: 0x01E4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3; /* offset: 0x01E8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7; /* offset: 0x01EC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG23_CS; /* offset: 0x01F0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG23_ID; /* offset: 0x01F4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3; /* offset: 0x01F8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7; /* offset: 0x01FC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG24_CS; /* offset: 0x0200 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG24_ID; /* offset: 0x0204 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3; /* offset: 0x0208 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7; /* offset: 0x020C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG25_CS; /* offset: 0x0210 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG25_ID; /* offset: 0x0214 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3; /* offset: 0x0218 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7; /* offset: 0x021C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG26_CS; /* offset: 0x0220 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG26_ID; /* offset: 0x0224 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3; /* offset: 0x0228 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7; /* offset: 0x022C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG27_CS; /* offset: 0x0230 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG27_ID; /* offset: 0x0234 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3; /* offset: 0x0238 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7; /* offset: 0x023C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG28_CS; /* offset: 0x0240 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG28_ID; /* offset: 0x0244 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3; /* offset: 0x0248 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7; /* offset: 0x024C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG29_CS; /* offset: 0x0250 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG29_ID; /* offset: 0x0254 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3; /* offset: 0x0258 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7; /* offset: 0x025C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG30_CS; /* offset: 0x0260 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG30_ID; /* offset: 0x0264 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3; /* offset: 0x0268 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7; /* offset: 0x026C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG31_CS; /* offset: 0x0270 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG31_ID; /* offset: 0x0274 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3; /* offset: 0x0278 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7; /* offset: 0x027C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG32_CS; /* offset: 0x0280 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG32_ID; /* offset: 0x0284 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3; /* offset: 0x0288 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7; /* offset: 0x028C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG33_CS; /* offset: 0x0290 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG33_ID; /* offset: 0x0294 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3; /* offset: 0x0298 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7; /* offset: 0x029C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG34_CS; /* offset: 0x02A0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG34_ID; /* offset: 0x02A4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3; /* offset: 0x02A8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7; /* offset: 0x02AC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG35_CS; /* offset: 0x02B0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG35_ID; /* offset: 0x02B4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3; /* offset: 0x02B8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7; /* offset: 0x02BC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG36_CS; /* offset: 0x02C0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG36_ID; /* offset: 0x02C4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3; /* offset: 0x02C8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7; /* offset: 0x02CC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG37_CS; /* offset: 0x02D0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG37_ID; /* offset: 0x02D4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3; /* offset: 0x02D8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7; /* offset: 0x02DC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG38_CS; /* offset: 0x02E0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG38_ID; /* offset: 0x02E4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3; /* offset: 0x02E8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7; /* offset: 0x02EC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG39_CS; /* offset: 0x02F0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG39_ID; /* offset: 0x02F4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3; /* offset: 0x02F8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7; /* offset: 0x02FC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG40_CS; /* offset: 0x0300 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG40_ID; /* offset: 0x0304 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3; /* offset: 0x0308 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7; /* offset: 0x030C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG41_CS; /* offset: 0x0310 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG41_ID; /* offset: 0x0314 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3; /* offset: 0x0318 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7; /* offset: 0x031C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG42_CS; /* offset: 0x0320 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG42_ID; /* offset: 0x0324 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3; /* offset: 0x0328 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7; /* offset: 0x032C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG43_CS; /* offset: 0x0330 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG43_ID; /* offset: 0x0334 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3; /* offset: 0x0338 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7; /* offset: 0x033C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG44_CS; /* offset: 0x0340 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG44_ID; /* offset: 0x0344 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3; /* offset: 0x0348 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7; /* offset: 0x034C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG45_CS; /* offset: 0x0350 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG45_ID; /* offset: 0x0354 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3; /* offset: 0x0358 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7; /* offset: 0x035C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG46_CS; /* offset: 0x0360 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG46_ID; /* offset: 0x0364 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3; /* offset: 0x0368 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7; /* offset: 0x036C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG47_CS; /* offset: 0x0370 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG47_ID; /* offset: 0x0374 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3; /* offset: 0x0378 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7; /* offset: 0x037C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG48_CS; /* offset: 0x0380 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG48_ID; /* offset: 0x0384 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3; /* offset: 0x0388 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7; /* offset: 0x038C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG49_CS; /* offset: 0x0390 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG49_ID; /* offset: 0x0394 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3; /* offset: 0x0398 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7; /* offset: 0x039C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG50_CS; /* offset: 0x03A0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG50_ID; /* offset: 0x03A4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3; /* offset: 0x03A8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7; /* offset: 0x03AC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG51_CS; /* offset: 0x03B0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG51_ID; /* offset: 0x03B4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3; /* offset: 0x03B8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7; /* offset: 0x03BC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG52_CS; /* offset: 0x03C0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG52_ID; /* offset: 0x03C4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3; /* offset: 0x03C8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7; /* offset: 0x03CC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG53_CS; /* offset: 0x03D0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG53_ID; /* offset: 0x03D4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3; /* offset: 0x03D8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7; /* offset: 0x03DC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG54_CS; /* offset: 0x03E0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG54_ID; /* offset: 0x03E4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3; /* offset: 0x03E8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7; /* offset: 0x03EC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG55_CS; /* offset: 0x03F0 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG55_ID; /* offset: 0x03F4 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3; /* offset: 0x03F8 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7; /* offset: 0x03FC size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG56_CS; /* offset: 0x0400 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG56_ID; /* offset: 0x0404 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3; /* offset: 0x0408 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7; /* offset: 0x040C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG57_CS; /* offset: 0x0410 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG57_ID; /* offset: 0x0414 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3; /* offset: 0x0418 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7; /* offset: 0x041C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG58_CS; /* offset: 0x0420 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG58_ID; /* offset: 0x0424 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3; /* offset: 0x0428 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7; /* offset: 0x042C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG59_CS; /* offset: 0x0430 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG59_ID; /* offset: 0x0434 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3; /* offset: 0x0438 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7; /* offset: 0x043C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG60_CS; /* offset: 0x0440 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG60_ID; /* offset: 0x0444 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3; /* offset: 0x0448 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7; /* offset: 0x044C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG61_CS; /* offset: 0x0450 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG61_ID; /* offset: 0x0454 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3; /* offset: 0x0458 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7; /* offset: 0x045C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG62_CS; /* offset: 0x0460 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG62_ID; /* offset: 0x0464 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3; /* offset: 0x0468 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7; /* offset: 0x046C size: 32 bit */
+ /* Message Buffer Control and Status */
+ FLEXCAN_MSG_CS_32B_tag MSG63_CS; /* offset: 0x0470 size: 32 bit */
+ /* Message Buffer Identifier Field */
+ FLEXCAN_MSG_ID_32B_tag MSG63_ID; /* offset: 0x0474 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3; /* offset: 0x0478 size: 32 bit */
+ /* Message Buffer Data Register */
+ FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7; /* offset: 0x047C size: 32 bit */
+ };
+
+ };
+ int8_t FLEXCAN_reserved_0480_C[1024];
+ union {
+ /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
+ FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880 (0x0004 x 64) */
+
+ struct {
+ /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
+ FLEXCAN_RXIMR_32B_tag RXIMR0; /* offset: 0x0880 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR1; /* offset: 0x0884 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR2; /* offset: 0x0888 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR3; /* offset: 0x088C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR4; /* offset: 0x0890 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR5; /* offset: 0x0894 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR6; /* offset: 0x0898 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR7; /* offset: 0x089C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR8; /* offset: 0x08A0 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR9; /* offset: 0x08A4 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */
+ FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */
+ };
+
+ };
+ } FLEXCAN_tag;
+
+
+#define FLEXCAN_A (*(volatile FLEXCAN_tag *) 0xFFFC0000UL)
+#define FLEXCAN_B (*(volatile FLEXCAN_tag *) 0xFFFC4000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: DMA_CH_MUX */
+/* */
+/****************************************************************/
+
+
+ /* Register layout for all registers CHCONFIG... */
+
+ typedef union { /* CHCONFIG[0-15] - Channel Configuration Registers */
+ vuint8_t R;
+ struct {
+ vuint8_t ENBL:1; /* DMA Channel Enable */
+ vuint8_t TRIG:1; /* DMA Channel Trigger Enable */
+ vuint8_t SOURCE:6; /* DMA Channel Source */
+ } B;
+ } DMA_CH_MUX_CHCONFIG_8B_tag;
+
+
+
+ typedef struct DMA_CH_MUX_struct_tag { /* start of DMA_CH_MUX_tag */
+ union {
+ /* CHCONFIG[0-15] - Channel Configuration Registers */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16]; /* offset: 0x0000 (0x0001 x 16) */
+
+ struct {
+ /* CHCONFIG[0-15] - Channel Configuration Registers */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0; /* offset: 0x0000 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1; /* offset: 0x0001 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2; /* offset: 0x0002 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3; /* offset: 0x0003 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4; /* offset: 0x0004 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5; /* offset: 0x0005 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6; /* offset: 0x0006 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7; /* offset: 0x0007 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8; /* offset: 0x0008 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9; /* offset: 0x0009 size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10; /* offset: 0x000A size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11; /* offset: 0x000B size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12; /* offset: 0x000C size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13; /* offset: 0x000D size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14; /* offset: 0x000E size: 8 bit */
+ DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15; /* offset: 0x000F size: 8 bit */
+ };
+
+ };
+ } DMA_CH_MUX_tag;
+
+
+#define DMA_CH_MUX (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL)
+
+
+
+/****************************************************************/
+/* */
+/* Module: FR */
+/* */
+/****************************************************************/
+
+ typedef union { /* Module Version Number */
+ vuint16_t R;
+ struct {
+ vuint16_t CHIVER:8; /* VERSION NUMBER OF CHI */
+ vuint16_t PEVER:8; /* VERSION NUMBER OF PE */
+ } B;
+ } FR_MVR_16B_tag;
+
+ typedef union { /* Module Configuration Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MEN:1; /* Module Enable */
+ vuint16_t SBFF:1; /* System Bus Failure Freeze */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SCM:1; /* single channel device mode */
+#else
+ vuint16_t SCMD:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t CHB:1; /* Channel B enable */
+ vuint16_t CHA:1; /* channel A enable */
+ vuint16_t SFFE:1; /* Sync. frame filter Enable */
+ vuint16_t ECCE:1; /* ECC Functionlity Enable */
+ vuint16_t TMODER:1; /* Functional Test mode */
+ vuint16_t FUM:1; /* FIFO Update Mode */
+ vuint16_t FAM:1; /* FIFO Address Mode */
+ vuint16_t:1;
+ vuint16_t CLKSEL:1; /* Protocol Engine clock source select */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t BITRATE:3; /* Bus bit rate */
+#else
+ vuint16_t PRESCALE:3; /* deprecated name - please avoid */
+#endif
+ vuint16_t:1;
+ } B;
+ } FR_MCR_16B_tag;
+
+ typedef union { /* SYSTEM MEMORY BASE ADD HIGH REG */
+ vuint16_t R;
+ struct {
+ vuint16_t SMBA_31_16:16; /* SYS_MEM_BASE_ADDR[31:16] */
+ } B;
+ } FR_SYMBADHR_16B_tag;
+
+ typedef union { /* SYSTEM MEMORY BASE ADD LOW REG */
+ vuint16_t R;
+ struct {
+ vuint16_t SMBA_15_4:12; /* SYS_MEM_BASE_ADDR[15:4] */
+ vuint16_t:4;
+ } B;
+ } FR_SYMBADLR_16B_tag;
+
+ typedef union { /* STROBE SIGNAL CONTROL REGISTER */
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* DEFINES WRITE MODE OF REG */
+ vuint16_t:3;
+ vuint16_t SEL:4; /* STROBE SIGNSL SELECT */
+ vuint16_t:3;
+ vuint16_t ENB:1; /* STROBE SIGNAL ENABLE */
+ vuint16_t:2;
+ vuint16_t STBPSEL:2; /* STROBE PORT SELECT */
+ } B;
+ } FR_STBSCR_16B_tag;
+
+ typedef union { /* MESSAGE BUFFER DATA SIZE REGISTER */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t MBSEG2DS:7; /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */
+ vuint16_t:1;
+ vuint16_t MBSEG1DS:7; /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */
+ } B;
+ } FR_MBDSR_16B_tag;
+
+ typedef union { /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t LAST_MB_SEG1:6; /* LAST MESS BUFFER IN SEG 1 */
+ vuint16_t:2;
+ vuint16_t LAST_MB_UTIL:6; /* LAST MESSAGE BUFFER UTILISED */
+ } B;
+ } FR_MBSSUTR_16B_tag;
+
+ typedef union { /* PE DRAM ACCESS REGISTER */
+ vuint16_t R;
+ struct {
+ vuint16_t INST:4; /* PE DRAM ACCESS INSTRUCTION */
+ vuint16_t ADDR:11; /* PE DRAM ACCESS ADDRESS */
+ vuint16_t DAD:1; /* PE DRAM ACCESS DONE */
+ } B;
+ } FR_PEDRAR_16B_tag;
+
+ typedef union { /* PE DRAM DATA REGISTER */
+ vuint16_t R;
+ struct {
+ vuint16_t DATA:16; /* DATA TO BE READ OR WRITTEN */
+ } B;
+ } FR_PEDRDR_16B_tag;
+
+ typedef union { /* PROTOCOL OPERATION CONTROL REG */
+ vuint16_t R;
+ struct {
+ vuint16_t WME:1; /* WRITE MODE EXTERNAL CORRECTION */
+ vuint16_t:3;
+ vuint16_t EOC_AP:2; /* EXTERNAL OFFSET CORRECTION APPLICATION */
+ vuint16_t ERC_AP:2; /* EXTERNAL RATE CORRECTION APPLICATION */
+ vuint16_t BSY:1; /* PROTOCOL CONTROL COMMAND WRITE BUSY */
+ vuint16_t:3;
+ vuint16_t POCCMD:4; /* PROTOCOL CONTROL COMMAND */
+ } B;
+ } FR_POCR_16B_tag;
+
+ typedef union { /* GLOBAL INTERRUPT FLAG & ENABLE REG */
+ vuint16_t R;
+ struct {
+ vuint16_t MIF:1; /* MODULE INTERRUPT FLAG */
+ vuint16_t PRIF:1; /* PROTOCOL INTERRUPT FLAG */
+ vuint16_t CHIF:1; /* CHI INTERRUPT FLAG */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t WUPIF:1; /* WAKEUP INTERRUPT FLAG */
+#else
+ vuint16_t WKUPIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FAFBIF:1; /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */
+#else
+ vuint16_t FNEBIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FAFAIF:1; /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */
+#else
+ vuint16_t FNEAIF:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t RBIF:1; /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */
+ vuint16_t TBIF:1; /* TRANSMIT BUFFER INTERRUPT FLAG */
+ vuint16_t MIE:1; /* MODULE INTERRUPT ENABLE */
+ vuint16_t PRIE:1; /* PROTOCOL INTERRUPT ENABLE */
+ vuint16_t CHIE:1; /* CHI INTERRUPT ENABLE */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t WUPIE:1; /* WAKEUP INTERRUPT ENABLE */
+#else
+ vuint16_t WKUPIE:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t FNEBIE:1; /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */
+ vuint16_t FNEAIE:1; /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */
+ vuint16_t RBIE:1; /* RECEIVE BUFFER INTERRUPT ENABLE */
+ vuint16_t TBIE:1; /* TRANSMIT BUFFER INTERRUPT ENABLE */
+ } B;
+ } FR_GIFER_16B_tag;
+
+ typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FATL_IF:1; /* FATAL PROTOCOL ERROR INTERRUPT FLAG */
+#else
+ vuint16_t FATLIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t INTL_IF:1; /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */
+#else
+ vuint16_t INTLIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t ILCF_IF:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */
+#else
+ vuint16_t ILCFIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CSA_IF:1; /* COLDSTART ABORT INTERRUPT FLAG */
+#else
+ vuint16_t CSAIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MRC_IF:1; /* MISSING RATE CORRECTION INTERRUPT FLAG */
+#else
+ vuint16_t MRCIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MOC_IF:1; /* MISSING OFFSET CORRECTION INTERRUPT FLAG */
+#else
+ vuint16_t MOCIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CCL_IF:1; /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */
+#else
+ vuint16_t CCLIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MXS_IF:1; /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */
+#else
+ vuint16_t MXSIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MTX_IF:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */
+#else
+ vuint16_t MTXIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LTXB_IF:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */
+#else
+ vuint16_t LTXBIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LTXA_IF:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */
+#else
+ vuint16_t LTXAIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TBVB_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */
+#else
+ vuint16_t TBVBIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TBVA_IF:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */
+#else
+ vuint16_t TBVAIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TI2_IF:1; /* TIMER 2 EXPIRED INTERRUPT FLAG */
+#else
+ vuint16_t TI2IF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TI1_IF:1; /* TIMER 1 EXPIRED INTERRUPT FLAG */
+#else
+ vuint16_t TI1IF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CYS_IF:1; /* CYCLE START INTERRUPT FLAG */
+#else
+ vuint16_t CYSIF:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PIFR0_16B_tag;
+
+ typedef union { /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t EMC_IF:1; /* ERROR MODE CHANGED INTERRUPT FLAG */
+#else
+ vuint16_t EMCIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t IPC_IF:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */
+#else
+ vuint16_t IPCIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t PECF_IF:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */
+#else
+ vuint16_t PECFIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t PSC_IF:1; /* PROTOCOL STATE CHANGED INTERRUPT FLAG */
+#else
+ vuint16_t PSCIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SSI3_IF:1; /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */
+#else
+ vuint16_t SSI3IF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SSI2_IF:1; /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */
+#else
+ vuint16_t SSI2IF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SSI1_IF:1; /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */
+#else
+ vuint16_t SSI1IF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SSI0_IF:1; /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */
+#else
+ vuint16_t SSI0IF:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t:2;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t EVT_IF:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */
+#else
+ vuint16_t EVTIF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t ODT_IF:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */
+#else
+ vuint16_t ODTIF:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t:4;
+ } B;
+ } FR_PIFR1_16B_tag;
+
+ typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FATL_IE:1; /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */
+#else
+ vuint16_t FATLIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t INTL_IE:1; /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */
+#else
+ vuint16_t INTLIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t ILCF_IE:1; /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */
+#else
+ vuint16_t ILCFIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CSA_IE:1; /* COLDSTART ABORT INTERRUPT ENABLE */
+#else
+ vuint16_t CSAIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MRC_IE:1; /* MISSING RATE CORRECTION INTERRUPT ENABLE */
+#else
+ vuint16_t MRCIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MOC_IE:1; /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */
+#else
+ vuint16_t MOCIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CCL_IE:1; /* CLOCK CORRECTION LIMIT REACHED */
+#else
+ vuint16_t CCLIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MXS_IE:1; /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */
+#else
+ vuint16_t MXSIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MTX_IE:1; /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */
+#else
+ vuint16_t MTXIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LTXB_IE:1; /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */
+#else
+ vuint16_t LTXBIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LTXA_IE:1; /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */
+#else
+ vuint16_t LTXAIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TBVB_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */
+#else
+ vuint16_t TBVBIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TBVA_IE:1; /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */
+#else
+ vuint16_t TBVAIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TI2_IE:1; /* TIMER 2 EXPIRED INTERRUPT ENABLE */
+#else
+ vuint16_t TI2IE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TI1_IE:1; /* TIMER 1 EXPIRED INTERRUPT ENABLE */
+#else
+ vuint16_t TI1IE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CYS_IE:1; /* CYCLE START INTERRUPT ENABLE */
+#else
+ vuint16_t CYSIE:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PIER0_16B_tag;
+
+ typedef union { /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t EMC_IE:1; /* ERROR MODE CHANGED INTERRUPT Enable */
+#else
+ vuint16_t EMCIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t IPC_IE:1; /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */
+#else
+ vuint16_t IPCIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t PECF_IE:1; /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */
+#else
+ vuint16_t PECFIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t PSC_IE:1; /* PROTOCOL STATE CHANGED INTERRUPT Enable */
+#else
+ vuint16_t PSCIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SSI_3_0_IE:4; /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */
+#else
+ vuint16_t SSI3IE:1;
+ vuint16_t SSI2IE:1;
+ vuint16_t SSI1IE:1;
+ vuint16_t SSI0IE:1;
+#endif
+
+ vuint16_t:2;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t EVT_IE:1; /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */
+#else
+ vuint16_t EVTIE:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t ODT_IE:1; /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */
+#else
+ vuint16_t ODTIE:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t:4;
+ } B;
+ } FR_PIER1_16B_tag;
+
+ typedef union { /* CHI ERROR FLAG REGISTER */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FRLB_EF:1; /* FRAME LOST CHANNEL B ERROR FLAG */
+#else
+ vuint16_t FRLBEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FRLA_EF:1; /* FRAME LOST CHANNEL A ERROR FLAG */
+#else
+ vuint16_t FRLAEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t PCMI_EF:1; /* PROTOCOL COMMAND IGNORED ERROR FLAG */
+#else
+ vuint16_t PCMIEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FOVB_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */
+#else
+ vuint16_t FOVBEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FOVA_EF:1; /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */
+#else
+ vuint16_t FOVAEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MBS_EF:1; /* MESSAGE BUFFER SEARCH ERROR FLAG */
+#else
+ vuint16_t MSBEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MBU_EF:1; /* MESSAGE BUFFER UTILIZATION ERROR FLAG */
+#else
+ vuint16_t MBUEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LCK_EF:1; /* LOCK ERROR FLAG */
+#else
+ vuint16_t LCKEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t DBL_EF:1; /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */
+#else
+ vuint16_t DBLEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SBCF_EF:1; /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */
+#else
+ vuint16_t SBCFEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FID_EF:1; /* FRAME ID ERROR FLAG */
+#else
+ vuint16_t FIDEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t DPL_EF:1; /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */
+#else
+ vuint16_t DPLEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SPL_EF:1; /* STATIC PAYLOAD LENGTH ERROR FLAG */
+#else
+ vuint16_t SPLEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t NML_EF:1; /* NETWORK MANAGEMENT LENGTH ERROR FLAG */
+#else
+ vuint16_t NMLEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t NMF_EF:1; /* NETWORK MANAGEMENT FRAME ERROR FLAG */
+#else
+ vuint16_t NMFEF:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t ILSA_EF:1; /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */
+#else
+ vuint16_t ILSAEF:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_CHIERFR_16B_tag;
+
+ typedef union { /* Message Buffer Interrupt Vector Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t TBIVEC:6; /* Transmit Buffer Interrupt Vector */
+ vuint16_t:2;
+ vuint16_t RBIVEC:6; /* Receive Buffer Interrupt Vector */
+ } B;
+ } FR_MBIVEC_16B_tag;
+
+ typedef union { /* Channel A Status Error Counter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */
+ } B;
+ } FR_CASERCR_16B_tag;
+
+ typedef union { /* Channel B Status Error Counter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t STATUS_ERR_CNT:16; /* Channel Status Error Counter */
+ } B;
+ } FR_CBSERCR_16B_tag;
+
+ typedef union { /* Protocol Status Register 0 */
+ vuint16_t R;
+ struct {
+ vuint16_t ERRMODE:2; /* Error Mode */
+ vuint16_t SLOTMODE:2; /* Slot Mode */
+ vuint16_t:1;
+ vuint16_t PROTSTATE:3; /* Protocol State */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t STARTUPSTATE:4; /* Startup State */
+#else
+ vuint16_t SUBSTATE:4; /* deprecated name - please avoid */
+#endif
+ vuint16_t WAKEUPSTATE:4; /* Wakeup Status */
+ } B;
+ } FR_PSR0_16B_tag;
+
+ typedef union { /* Protocol Status Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t CSAA:1; /* Coldstart Attempt Aborted Flag */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CSP:1; /* Leading Coldstart Path */
+#else
+ vuint16_t SCP:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t:1;
+ vuint16_t REMCSAT:5; /* Remaining Coldstart Attempts */
+ vuint16_t CPN:1; /* Leading Coldstart Path Noise */
+ vuint16_t HHR:1; /* Host Halt Request Pending */
+ vuint16_t FRZ:1; /* Freeze Occurred */
+ vuint16_t APTAC:5; /* Allow Passive to Active Counter */
+ } B;
+ } FR_PSR1_16B_tag;
+
+ typedef union { /* Protocol Status Register 2 */
+ vuint16_t R;
+ struct {
+ vuint16_t NBVB:1; /* NIT Boundary Violation on Channel B */
+ vuint16_t NSEB:1; /* NIT Syntax Error on Channel B */
+ vuint16_t STCB:1; /* Symbol Window Transmit Conflict on Channel B */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SSVB:1; /* Symbol Window Boundary Violation on Channel B */
+#else
+ vuint16_t SBVB:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t SSEB:1; /* Symbol Window Syntax Error on Channel B */
+ vuint16_t MTB:1; /* Media Access Test Symbol MTS Received on Channel B */
+ vuint16_t NBVA:1; /* NIT Boundary Violation on Channel A */
+ vuint16_t NSEA:1; /* NIT Syntax Error on Channel A */
+ vuint16_t STCA:1; /* Symbol Window Transmit Conflict on Channel A */
+ vuint16_t SBVA:1; /* Symbol Window Boundary Violation on Channel A */
+ vuint16_t SSEA:1; /* Symbol Window Syntax Error on Channel A */
+ vuint16_t MTA:1; /* Media Access Test Symbol MTS Received on Channel A */
+ vuint16_t CLKCORRFAILCNT:4; /* Clock Correction Failed Counter */
+ } B;
+ } FR_PSR2_16B_tag;
+
+ typedef union { /* Protocol Status Register 3 */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t WUB:1; /* Wakeup Symbol Received on Channel B */
+ vuint16_t ABVB:1; /* Aggregated Boundary Violation on Channel B */
+ vuint16_t AACB:1; /* Aggregated Additional Communication on Channel B */
+ vuint16_t ACEB:1; /* Aggregated Content Error on Channel B */
+ vuint16_t ASEB:1; /* Aggregated Syntax Error on Channel B */
+ vuint16_t AVFB:1; /* Aggregated Valid Frame on Channel B */
+ vuint16_t:2;
+ vuint16_t WUA:1; /* Wakeup Symbol Received on Channel A */
+ vuint16_t ABVA:1; /* Aggregated Boundary Violation on Channel A */
+ vuint16_t AACA:1; /* Aggregated Additional Communication on Channel A */
+ vuint16_t ACEA:1; /* Aggregated Content Error on Channel A */
+ vuint16_t ASEA:1; /* Aggregated Syntax Error on Channel A */
+ vuint16_t AVFA:1; /* Aggregated Valid Frame on Channel A */
+ } B;
+ } FR_PSR3_16B_tag;
+
+ typedef union { /* Macrotick Counter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t MTCT:14; /* Macrotick Counter */
+ } B;
+ } FR_MTCTR_16B_tag;
+
+ typedef union { /* Cycle Counter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:10;
+ vuint16_t CYCCNT:6; /* Cycle Counter */
+ } B;
+ } FR_CYCTR_16B_tag;
+
+ typedef union { /* Slot Counter Channel A Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t SLOTCNTA:11; /* Slot Counter Value for Channel A */
+ } B;
+ } FR_SLTCTAR_16B_tag;
+
+ typedef union { /* Slot Counter Channel B Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t SLOTCNTB:11; /* Slot Counter Value for Channel B */
+ } B;
+ } FR_SLTCTBR_16B_tag;
+
+ typedef union { /* Rate Correction Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t RATECORR:16; /* Rate Correction Value */
+ } B;
+ } FR_RTCORVR_16B_tag;
+
+ typedef union { /* Offset Correction Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t OFFSETCORR:10; /* Offset Correction Value */
+ } B;
+ } FR_OFCORVR_16B_tag;
+
+ typedef union { /* Combined Interrupt Flag Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MIF:1; /* Module Interrupt Flag */
+#else
+ vuint16_t MIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t PRIF:1; /* Protocol Interrupt Flag */
+#else
+ vuint16_t PRIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CHIF:1; /* CHI Interrupt Flag */
+#else
+ vuint16_t CHIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t WUPIF:1; /* Wakeup Interrupt Flag */
+#else
+ vuint16_t WUPIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FAFBIF:1; /* Receive FIFO channel B Almost Full Interrupt Flag */
+#else
+ vuint16_t FNEBIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FAFAIF:1; /* Receive FIFO channel A Almost Full Interrupt Flag */
+#else
+ vuint16_t FNEAIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t RBIF:1; /* Receive Message Buffer Interrupt Flag */
+#else
+ vuint16_t RBIFR:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t TBIF:1; /* Transmit Message Buffer Interrupt Flag */
+#else
+ vuint16_t TBIFR:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_CIFR_16B_tag;
+
+ typedef union { /* System Memory Access Time-Out Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:8;
+ vuint16_t TIMEOUT:8; /* Time-Out */
+ } B;
+ } FR_SYMATOR_16B_tag;
+
+ typedef union { /* Sync Frame Counter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t SFEVB:4; /* Sync Frames Channel B, even cycle */
+ vuint16_t SFEVA:4; /* Sync Frames Channel A, even cycle */
+ vuint16_t SFODB:4; /* Sync Frames Channel B, odd cycle */
+ vuint16_t SFODA:4; /* Sync Frames Channel A, odd cycle */
+ } B;
+ } FR_SFCNTR_16B_tag;
+
+ typedef union { /* Sync Frame Table Offset Register */
+ vuint16_t R;
+ struct {
+ vuint16_t SFT_OFFSET_15_1:15; /* Sync Frame Table Offset */
+ vuint16_t:1;
+ } B;
+ } FR_SFTOR_16B_tag;
+
+ typedef union { /* Sync Frame Table Configuration, Control, Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t ELKT:1; /* Even Cycle Tables Lock/Unlock Trigger */
+ vuint16_t OLKT:1; /* Odd Cycle Tables Lock/Unlock Trigger */
+ vuint16_t CYCNUM:6; /* Cycle Number */
+ vuint16_t ELKS:1; /* Even Cycle Tables Lock Status */
+ vuint16_t OLKS:1; /* Odd Cycle Tables Lock Status */
+ vuint16_t EVAL:1; /* Even Cycle Tables Valid */
+ vuint16_t OVAL:1; /* Odd Cycle Tables Valid */
+ vuint16_t:1;
+ vuint16_t OPT:1; /* One Pair Trigger */
+ vuint16_t SDVEN:1; /* Sync Frame Deviation Table Enable */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t SIVEN:1; /* Sync Frame ID Table Enable */
+#else
+ vuint16_t SIDEN:1; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_SFTCCSR_16B_tag;
+
+ typedef union { /* Sync Frame ID Rejection Filter */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t SYNFRID:10; /* Sync Frame Rejection ID */
+ } B;
+ } FR_SFIDRFR_16B_tag;
+
+ typedef union { /* Sync Frame ID Acceptance Filter Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t FVAL:10; /* Filter Value */
+ } B;
+ } FR_SFIDAFVR_16B_tag;
+
+ typedef union { /* Sync Frame ID Acceptance Filter Mask Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t FMSK:10; /* Filter Mask */
+ } B;
+ } FR_SFIDAFMR_16B_tag;
+
+ typedef union { /* Network Management Vector Register0 */
+ vuint16_t R;
+ struct {
+ vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
+ vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
+ } B;
+ } FR_NMVR0_16B_tag;
+
+ typedef union { /* Network Management Vector Register1 */
+ vuint16_t R;
+ struct {
+ vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
+ vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
+ } B;
+ } FR_NMVR1_16B_tag;
+
+ typedef union { /* Network Management Vector Register2 */
+ vuint16_t R;
+ struct {
+ vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
+ vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
+ } B;
+ } FR_NMVR2_16B_tag;
+
+ typedef union { /* Network Management Vector Register3 */
+ vuint16_t R;
+ struct {
+ vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
+ vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
+ } B;
+ } FR_NMVR3_16B_tag;
+
+ typedef union { /* Network Management Vector Register4 */
+ vuint16_t R;
+ struct {
+ vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
+ vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
+ } B;
+ } FR_NMVR4_16B_tag;
+
+ typedef union { /* Network Management Vector Register5 */
+ vuint16_t R;
+ struct {
+ vuint16_t NMVP_15_8:8; /* Network Management Vector Part */
+ vuint16_t NMVP_7_0:8; /* Network Management Vector Part */
+ } B;
+ } FR_NMVR5_16B_tag;
+
+ typedef union { /* Network Management Vector Length Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t NMVL:4; /* Network Management Vector Length */
+ } B;
+ } FR_NMVLR_16B_tag;
+
+ typedef union { /* Timer Configuration and Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t T2_CFG:1; /* Timer T2 Configuration */
+#else
+ vuint16_t T2CFG:1; /* Timer T2 Configuration */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t T2_REP:1; /* Timer T2 Repetitive Mode */
+#else
+ vuint16_t T2REP:1; /* Timer T2 Configuration */
+#endif
+ vuint16_t:1;
+ vuint16_t T2SP:1; /* Timer T2 Stop */
+ vuint16_t T2TR:1; /* Timer T2 Trigger */
+ vuint16_t T2ST:1; /* Timer T2 State */
+ vuint16_t:3;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t T1_REP:1; /* Timer T1 Repetitive Mode */
+#else
+ vuint16_t T1REP:1;
+#endif
+ vuint16_t:1;
+ vuint16_t T1SP:1; /* Timer T1 Stop */
+ vuint16_t T1TR:1; /* Timer T1 Trigger */
+ vuint16_t T1ST:1; /* Timer T1 State */
+ } B;
+ } FR_TICCR_16B_tag;
+
+ typedef union { /* Timer 1 Cycle Set Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t T1_CYC_VAL:6; /* Timer T1 Cycle Filter Value */
+#else
+ vuint16_t TI1CYCVAL:1; /* Timer T1 Cycle Filter Value */
+#endif
+ vuint16_t:2;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t T1_CYC_MSK:6; /* Timer T1 Cycle Filter Mask */
+#else
+ vuint16_t TI1CYCMSK:1; /* Timer T1 Cycle Filter Mask */
+#endif
+ } B;
+ } FR_TI1CYSR_16B_tag;
+
+ typedef union { /* Timer 1 Macrotick Offset Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t T1_MTOFFSET:14; /* Timer 1 Macrotick Offset */
+ } B;
+ } FR_TI1MTOR_16B_tag;
+
+ typedef union { /* Timer 2 Configuration Register 0 */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t T2_CYC_VAL:6; /* Timer T2 Cycle Filter Value */
+ vuint16_t:2;
+ vuint16_t T2_CYC_MSK:6; /* Timer T2 Cycle Filter Mask */
+ } B;
+ } FR_TI2CR0_16B_tag;
+
+ typedef union { /* Timer 2 Configuration Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t T2_MTCNT:16; /* Timer T2 Macrotick Offset */
+ } B;
+ } FR_TI2CR1_16B_tag;
+
+ typedef union { /* Slot Status Selection Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* Write Mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* Selector */
+ vuint16_t:1;
+ vuint16_t SLOTNUMBER:11; /* Slot Number */
+ } B;
+ } FR_SSSR_16B_tag;
+
+ typedef union { /* Slot Status Counter Condition Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* Write Mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* Selector */
+ vuint16_t:1;
+ vuint16_t CNTCFG:2; /* Counter Configuration */
+ vuint16_t MCY:1; /* Multi Cycle Selection */
+ vuint16_t VFR:1; /* Valid Frame Restriction */
+ vuint16_t SYF:1; /* Sync Frame Restriction */
+ vuint16_t NUF:1; /* Null Frame Restriction */
+ vuint16_t SUF:1; /* Startup Frame Restriction */
+ vuint16_t STATUSMASK:4; /* Slot Status Mask */
+ } B;
+ } FR_SSCCR_16B_tag;
+
+ typedef union { /* Slot Status Register0 */
+ vuint16_t R;
+ struct {
+ vuint16_t VFB:1; /* Valid Frame on Channel B */
+ vuint16_t SYB:1; /* Sync Frame Indicator Channel B */
+ vuint16_t NFB:1; /* Null Frame Indicator Channel B */
+ vuint16_t SUB:1; /* Startup Frame Indicator Channel B */
+ vuint16_t SEB:1; /* Syntax Error on Channel B */
+ vuint16_t CEB:1; /* Content Error on Channel B */
+ vuint16_t BVB:1; /* Boundary Violation on Channel B */
+ vuint16_t TCB:1; /* Transmission Conflict on Channel B */
+ vuint16_t VFA:1; /* Valid Frame on Channel A */
+ vuint16_t SYA:1; /* Sync Frame Indicator Channel A */
+ vuint16_t NFA:1; /* Null Frame Indicator Channel A */
+ vuint16_t SUA:1; /* Startup Frame Indicator Channel A */
+ vuint16_t SEA:1; /* Syntax Error on Channel A */
+ vuint16_t CEA:1; /* Content Error on Channel A */
+ vuint16_t BVA:1; /* Boundary Violation on Channel A */
+ vuint16_t TCA:1; /* Transmission Conflict on Channel A */
+ } B;
+ } FR_SSR_16B_tag;
+
+
+
+ typedef union { /* Slot Status Counter Register0 */
+ vuint16_t R;
+ struct {
+ vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
+ } B;
+ } FR_SSCR0_16B_tag;
+
+ typedef union { /* Slot Status Counter Register1 */
+ vuint16_t R;
+ struct {
+ vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
+ } B;
+ } FR_SSCR1_16B_tag;
+
+ typedef union { /* Slot Status Counter Register2 */
+ vuint16_t R;
+ struct {
+ vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
+ } B;
+ } FR_SSCR2_16B_tag;
+
+ typedef union { /* Slot Status Counter Register3 */
+ vuint16_t R;
+ struct {
+ vuint16_t SLOTSTSTUSCNT:16; /* Slot Status Counter */
+ } B;
+ } FR_SSCR3_16B_tag;
+
+ typedef union { /* MTS A Configuration Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */
+ vuint16_t:1;
+ vuint16_t CYCCNTMSK:6; /* Cycle Counter Mask */
+ vuint16_t:2;
+ vuint16_t CYCCNTVAL:6; /* Cycle Counter Value */
+ } B;
+ } FR_MTSACFR_16B_tag;
+
+ typedef union { /* MTS B Configuration Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MTE:1; /* Media Access Test Symbol Transmission Enable */
+ vuint16_t:1;
+ vuint16_t CYCCNTMSK:6; /* Cycle Counter Mask */
+ vuint16_t:2;
+ vuint16_t CYCCNTVAL:6; /* Cycle Counter Value */
+ } B;
+ } FR_MTSBCFR_16B_tag;
+
+ typedef union { /* Receive Shadow Buffer Index Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* Write Mode */
+ vuint16_t:1;
+ vuint16_t SEL:2; /* Selector */
+ vuint16_t:5;
+ vuint16_t RSBIDX:7; /* Receive Shadow Buffer Index */
+ } B;
+ } FR_RSBIR_16B_tag;
+
+ typedef union { /* Receive FIFO Watermark and Selection Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WM:8; /* Watermark Value */
+ vuint16_t:7;
+ vuint16_t SEL:1; /* Select */
+ } B;
+ } FR_RFWMSR_16B_tag;
+
+ typedef union { /* Receive FIFO Start Index Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t SIDX:10; /* Start Index */
+ } B;
+ } FR_RF_RFSIR_16B_tag;
+
+ typedef union { /* Receive FIFO Depth and Size Register */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t FIFO_DEPTH:8; /* FIFO Depth */
+#else
+ vuint16_t FIFODEPTH:8; /* deprecated name - please avoid */
+#endif
+ vuint16_t:1;
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t ENTRY_SIZE:7; /* Entry Size */
+#else
+ vuint16_t ENTRYSIZE:7; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_RFDSR_16B_tag;
+
+ typedef union { /* Receive FIFO A Read Index Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t RDIDX:10; /* Read Index */
+ } B;
+ } FR_RFARIR_16B_tag;
+
+ typedef union { /* Receive FIFO B Read Index Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:6;
+ vuint16_t RDIDX:10; /* Read Index */
+ } B;
+ } FR_RFBRIR_16B_tag;
+
+ typedef union { /* Receive FIFO Message ID Acceptance Filter Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MIDAFVAL:16; /* Message ID Acceptance Filter Value */
+ } B;
+ } FR_RFMIDAFVR_16B_tag;
+
+ typedef union { /* Receive FIFO Message ID Acceptance Filter Mask Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MIDAFMSK:16; /* Message ID Acceptance Filter Mask */
+ } B;
+ } FR_RFMIDAFMR_16B_tag;
+
+ typedef union { /* Receive FIFO Frame ID Rejection Filter Value Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FIDRFVAL:11; /* Frame ID Rejection Filter Value */
+ } B;
+ } FR_RFFIDRFVR_16B_tag;
+
+ typedef union { /* Receive FIFO Frame ID Rejection Filter Mask Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FIDRFMSK:11; /* Frame ID Rejection Filter Mask */
+ } B;
+ } FR_RFFIDRFMR_16B_tag;
+
+ typedef union { /* Receive FIFO Range Filter Configuration Register */
+ vuint16_t R;
+ struct {
+ vuint16_t WMD:1; /* Write Mode */
+ vuint16_t IBD:1; /* Interval Boundary */
+ vuint16_t SEL:2; /* Filter Selector */
+ vuint16_t:1;
+ vuint16_t SID:11; /* Slot ID */
+ } B;
+ } FR_RFRFCFR_16B_tag;
+
+ typedef union { /* Receive FIFO Range Filter Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t F3MD:1; /* Range Filter 3 Mode */
+ vuint16_t F2MD:1; /* Range Filter 2 Mode */
+ vuint16_t F1MD:1; /* Range Filter 1 Mode */
+ vuint16_t F0MD:1; /* Range Filter 0 Mode */
+ vuint16_t:4;
+ vuint16_t F3EN:1; /* Range Filter 3 Enable */
+ vuint16_t F2EN:1; /* Range Filter 2 Enable */
+ vuint16_t F1EN:1; /* Range Filter 1 Enable */
+ vuint16_t F0EN:1; /* Range Filter 0 Enable */
+ } B;
+ } FR_RFRFCTR_16B_tag;
+
+ typedef union { /* Last Dynamic Transmit Slot Channel A Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t LASTDYNTXSLOTA:11; /* Last Dynamic Transmission Slot Channel A */
+ } B;
+ } FR_LDTXSLAR_16B_tag;
+
+ typedef union { /* Last Dynamic Transmit Slot Channel B Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t LASTDYNTXSLOTB:11; /* Last Dynamic Transmission Slot Channel B */
+ } B;
+ } FR_LDTXSLBR_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 0 */
+ vuint16_t R;
+ struct {
+ vuint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */
+ vuint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */
+ } B;
+ } FR_PCR0_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 1 */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14; /* gMacroPerCycle - gdStaticSlot */
+ } B;
+ } FR_PCR1_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 2 */
+ vuint16_t R;
+ struct {
+ vuint16_t MINISLOT_AFTER_ACTION_POINT:6; /* gdMinislot - gdMinislotActionPointOffset - 1 */
+ vuint16_t NUMBER_OF_STATIC_SLOTS:10; /* gNumberOfStaticSlots */
+ } B;
+ } FR_PCR2_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 3 */
+ vuint16_t R;
+ struct {
+ vuint16_t WAKEUP_SYMBOL_RX_LOW:6; /* gdWakeupSymbolRxLow */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5; /* gdMinislotActionPointOffset - 1 */
+#else
+ vuint16_t MINISLOT_ACTION_POINT_OFFSET:5; /* deprecated name - please avoid */
+#endif
+ vuint16_t COLDSTART_ATTEMPTS:5; /* gColdstartAttempts */
+ } B;
+ } FR_PCR3_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 4 */
+ vuint16_t R;
+ struct {
+ vuint16_t CAS_RX_LOW_MAX:7; /* gdCASRxLowMax - 1 */
+ vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9; /* gdWakeupSymbolRxWindow */
+ } B;
+ } FR_PCR4_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 5 */
+ vuint16_t R;
+ struct {
+ vuint16_t TSS_TRANSMITTER:4; /* gdTSSTransmitter */
+ vuint16_t WAKEUP_SYMBOL_TX_LOW:6; /* gdWakeupSymbolTxLow */
+ vuint16_t WAKEUP_SYMBOL_RX_IDLE:6; /* gdWakeupSymbolRxIdle */
+ } B;
+ } FR_PCR5_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 6 */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8; /* gdSymbolWindow - gdActionPointOffset - 1 */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MACRO_INITIAL_OFFSET_A:7; /* pMacroInitialOffset[A] */
+#else
+ vuint16_t MICRO_INITIAL_OFFSET_A:7; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR6_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 7 */
+ vuint16_t R;
+ struct {
+ vuint16_t DECODING_CORRECTION_B:9; /* pDecodingCorrection + pDelayCompensation[B] + 2 */
+ vuint16_t MICRO_PER_MACRO_NOM_HALF:7; /* round(pMicroPerMacroNom / 2) */
+ } B;
+ } FR_PCR7_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 8 */
+ vuint16_t R;
+ struct {
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4; /* gMaxWithoutClockCorrectionFatal */
+ vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4; /* gMaxWithoutClockCorrectionPassive */
+ vuint16_t WAKEUP_SYMBOL_TX_IDLE:8; /* gdWakeupSymbolTxIdle */
+ } B;
+ } FR_PCR8_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 9 */
+ vuint16_t R;
+ struct {
+ vuint16_t MINISLOT_EXISTS:1; /* gNumberOfMinislots!=0 */
+ vuint16_t SYMBOL_WINDOW_EXISTS:1; /* gdSymbolWindow!=0 */
+ vuint16_t OFFSET_CORRECTION_OUT:14; /* pOffsetCorrectionOut */
+ } B;
+ } FR_PCR9_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 10 */
+ vuint16_t R;
+ struct {
+ vuint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */
+ vuint16_t WAKEUP_CHANNEL:1; /* pWakeupChannel */
+ vuint16_t MACRO_PER_CYCLE:14; /* pMicroPerCycle */
+ } B;
+ } FR_PCR10_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 11 */
+ vuint16_t R;
+ struct {
+ vuint16_t KEY_SLOT_USED_FOR_STARTUP:1; /* pKeySlotUsedForStartup */
+ vuint16_t KEY_SLOT_USED_FOR_SYNC:1; /* pKeySlotUsedForSync */
+ vuint16_t OFFSET_CORRECTION_START:14; /* gOffsetCorrectionStart */
+ } B;
+ } FR_PCR11_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 12 */
+ vuint16_t R;
+ struct {
+ vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5; /* pAllowPassiveToActive */
+ vuint16_t KEY_SLOT_HEADER_CRC:11; /* header CRC for key slot */
+ } B;
+ } FR_PCR12_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 13 */
+ vuint16_t R;
+ struct {
+ vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6; /* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */
+ vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10; /* gdStaticSlot - gdActionPointOffset - 1 */
+ } B;
+ } FR_PCR13_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 14 */
+ vuint16_t R;
+ struct {
+ vuint16_t RATE_CORRECTION_OUT:11; /* pRateCorrectionOut */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LISTEN_TIMEOUT_20_16:5; /* pdListenTimeout - 1 */
+#else
+ vuint16_t LISTEN_TIMEOUT_H:5; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR14_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 15 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t LISTEN_TIMEOUT_15_0:16; /* pdListenTimeout - 1 */
+#else
+ vuint16_t LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR15_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 16 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MACRO_INITIAL_OFFSET_B:7; /* pMacroInitialOffset[B] */
+#else
+ vuint16_t MICRO_INITIAL_OFFSET_B:7; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t NOISE_LISTEN_TIMEOUT_24_16:9; /* (gListenNoise * pdListenTimeout) - 1 */
+#else
+ vuint16_t NOISE_LISTEN_TIMEOUT_H:9; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR16_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 17 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t NOISE_LISTEN_TIMEOUT_15_0:16; /* (gListenNoise * pdListenTimeout) - 1 */
+#else
+ vuint16_t NOISE_LISTEN_TIMEOUT_L:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR17_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 18 */
+ vuint16_t R;
+ struct {
+ vuint16_t WAKEUP_PATTERN:6; /* pWakeupPattern */
+ vuint16_t KEY_SLOT_ID:10; /* pKeySlotId */
+ } B;
+ } FR_PCR18_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 19 */
+ vuint16_t R;
+ struct {
+ vuint16_t DECODING_CORRECTION_A:9; /* pDecodingCorrection + pDelayCompensation[A] + 2 */
+ vuint16_t PAYLOAD_LENGTH_STATIC:7; /* gPayloadLengthStatic */
+ } B;
+ } FR_PCR19_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 20 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MACRO_INITIAL_OFFSET_B:8; /* pMicroInitialOffset[B] */
+#else
+ vuint16_t MICRO_INITIAL_OFFSET_B:8; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MACRO_INITIAL_OFFSET_A:8; /* pMicroInitialOffset[A] */
+#else
+ vuint16_t MICRO_INITIAL_OFFSET_A:8; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR20_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 21 */
+ vuint16_t R;
+ struct {
+ vuint16_t EXTERN_RATE_CORRECTION:3; /* pExternRateCorrection */
+ vuint16_t LATEST_TX:13; /* gNumberOfMinislots - pLatestTx */
+ } B;
+ } FR_PCR21_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 22 */
+ vuint16_t R;
+ struct {
+ vuint16_t R:1; /* Reserved bit */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11; /* pdAcceptedStartupRange - pDelayCompensationChA */
+#else
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MICRO_PER_CYCLE_19_16:4; /* gMicroPerCycle */
+#else
+ vuint16_t MICRO_PER_CYCLE_H:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR22_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 23 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MICRO_PER_CYCLE_15_0:16; /* pMicroPerCycle */
+#else
+ vuint16_t micro_per_cycle_l:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR23_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 24 */
+ vuint16_t R;
+ struct {
+ vuint16_t CLUSTER_DRIFT_DAMPING:5; /* pClusterDriftDamping */
+ vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7; /* pPayloadLengthDynMax */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MICRO_PER_CYCLE_MIN_19_16:4; /* pMicroPerCycle - pdMaxDrift */
+#else
+ vuint16_t MICRO_PER_CYCLE_MIN_H:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR24_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 25 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MICRO_PER_CYCLE_MIN_15_0:16; /* pMicroPerCycle - pdMaxDrift */
+#else
+ vuint16_t MICRO_PER_CYCLE_MIN_L:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR25_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 26 */
+ vuint16_t R;
+ struct {
+ vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1; /* pAllowHaltDueToClock */
+ vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11; /* pdAcceptedStartupRange - pDelayCompensationChB */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MICRO_PER_CYCLE_MAX_19_16:4; /* pMicroPerCycle + pdMaxDrift */
+#else
+ vuint16_t MICRO_PER_CYCLE_MAX_H:4; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR26_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 27 */
+ vuint16_t R;
+ struct {
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t MICRO_PER_CYCLE_MAX_15_0:16; /* pMicroPerCycle + pdMaxDrift */
+#else
+ vuint16_t MICRO_PER_CYCLE_MAX_L:16; /* deprecated name - please avoid */
+#endif
+ } B;
+ } FR_PCR27_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 28 */
+ vuint16_t R;
+ struct {
+ vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2; /* gdDynamicSlotIdlePhase */
+ vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14; /* gMacroPerCycle - gOffsetCorrectionStart */
+ } B;
+ } FR_PCR28_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 29 */
+ vuint16_t R;
+ struct {
+ vuint16_t EXTERN_OFFSET_CORRECTION:3; /* pExternOffsetCorrection */
+ vuint16_t MINISLOTS_MAX:13; /* gNumberOfMinislots - 1 */
+ } B;
+ } FR_PCR29_16B_tag;
+
+ typedef union { /* Protocol Configuration Register 30 */
+ vuint16_t R;
+ struct {
+ vuint16_t:12;
+ vuint16_t SYNC_NODE_MAX:4; /* gSyncNodeMax */
+ } B;
+ } FR_PCR30_16B_tag;
+
+ typedef union { /* Receive FIFO System Memory Base Address High Register */
+ vuint16_t R;
+ struct {
+ vuint16_t SMBA_31_16:16; /* System Memory Base Address */
+ } B;
+ } FR_RFSYMBHADR_16B_tag;
+
+ typedef union { /* Receive FIFO System Memory Base Address Low Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:4;
+ vuint16_t SMBA_15_4:12; /* System Memory Base Address */
+ } B;
+ } FR_RFSYMBLADR_16B_tag;
+
+ typedef union { /* Receive FIFO Periodic Timer Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:2;
+ vuint16_t PTD:14; /* Periodic Timer Duration */
+ } B;
+ } FR_RFPTR_16B_tag;
+
+ typedef union { /* Receive FIFO Fill Level and Pop Count Register */
+ vuint16_t R;
+ struct {
+ vuint16_t FLPCB:8; /* Fill Level and Pop Count Channel B */
+ vuint16_t FLPCA:8; /* Fill Level and Pop Count Channel A */
+ } B;
+ } FR_RFFLPCR_16B_tag;
+
+ typedef union { /* ECC Error Interrupt Flag and Enable Register */
+ vuint16_t R;
+ struct {
+ vuint16_t LRNE_OF:1; /* LRAM Non-Corrected Error Overflow Flag */
+ vuint16_t LRCE_OF:1; /* LRAM Corrected Error Overflow Flag */
+ vuint16_t DRNE_OF:1; /* DRAM Non-Corrected Error Overflow Flag */
+ vuint16_t DRCE_OF:1; /* DRAM Corrected Error Overflow Flag */
+ vuint16_t LRNE_IF:1; /* LRAM Non-Corrected Error Interrupt Flag */
+ vuint16_t LRCE_IF:1; /* LRAM Corrected Error Interrupt Flag */
+ vuint16_t DRNE_IF:1; /* DRAM Non-Corrected Error Interrupt Flag */
+ vuint16_t DRCE_IF:1; /* DRAM Corrected Error Interrupt Flag */
+ vuint16_t:4;
+ vuint16_t LRNE_IE:1; /* LRAM Non-Corrected Error Interrupt Enable */
+ vuint16_t LRCE_IE:1; /* LRAM Corrected Error Interrupt Enable */
+ vuint16_t DRNE_IE:1; /* DRAM Non-Corrected Error Interrupt Enable */
+ vuint16_t DRCE_IE:1; /* DRAM Corrected Error Interrupt Enable */
+ } B;
+ } FR_EEIFER_16B_tag;
+
+ typedef union { /* ECC Error Report and Injection Control Register */
+ vuint16_t R;
+ struct {
+ vuint16_t BSY:1; /* Register Update Busy */
+ vuint16_t:5;
+ vuint16_t ERS:2; /* Error Report Select */
+ vuint16_t:3;
+ vuint16_t ERM:1; /* Error Report Mode */
+ vuint16_t:2;
+ vuint16_t EIM:1; /* Error Injection Mode */
+ vuint16_t EIE:1; /* Error Injection Enable */
+ } B;
+ } FR_EERICR_16B_tag;
+
+ typedef union { /* ECC Error Report Adress Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MID:1; /* Memory Identifier */
+ vuint16_t BANK:3; /* Memory Bank */
+ vuint16_t ADDR:12; /* Memory Address */
+ } B;
+ } FR_EERAR_16B_tag;
+
+ typedef union { /* ECC Error Report Data Register */
+ vuint16_t R;
+ struct {
+ vuint16_t DATA:16; /* Data */
+ } B;
+ } FR_EERDR_16B_tag;
+
+ typedef union { /* ECC Error Report Code Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t CODE:5; /* Code */
+ } B;
+ } FR_EERCR_16B_tag;
+
+ typedef union { /* ECC Error Injection Address Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MID:1; /* Memory Identifier */
+ vuint16_t BANK:3; /* Memory Bank */
+ vuint16_t ADDR:12; /* Memory Address */
+ } B;
+ } FR_EEIAR_16B_tag;
+
+ typedef union { /* ECC Error Injection Data Register */
+ vuint16_t R;
+ struct {
+ vuint16_t DATA:16; /* Data */
+ } B;
+ } FR_EEIDR_16B_tag;
+
+ typedef union { /* ECC Error Injection Code Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:11;
+ vuint16_t CODE:5; /* Code */
+ } B;
+ } FR_EEICR_16B_tag;
+
+
+ /* Register layout for all registers MBCCSR... */
+
+ typedef union { /* Message Buffer Configuration Control Status Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:1;
+ vuint16_t MCM:1; /* Message Buffer Commit Mode */
+ vuint16_t MBT:1; /* Message Buffer Type */
+ vuint16_t MTD:1; /* Message Buffer Transfer Direction */
+ vuint16_t CMT:1; /* Commit for Transmission */
+ vuint16_t EDT:1; /* Enable/Disable Trigger */
+ vuint16_t LCKT:1; /* Lock/Unlock Trigger */
+ vuint16_t MBIE:1; /* Message Buffer Interrupt Enable */
+ vuint16_t:3;
+ vuint16_t DUP:1; /* Data Updated */
+ vuint16_t DVAL:1; /* DataValid */
+ vuint16_t EDS:1; /* Enable/Disable Status */
+ vuint16_t LCKS:1; /* LockStatus */
+ vuint16_t MBIF:1; /* Message Buffer Interrupt Flag */
+ } B;
+ } FR_MBCCSR_16B_tag;
+
+
+ /* Register layout for all registers MBCCFR... */
+
+ typedef union { /* Message Buffer Cycle Counter Filter Register */
+ vuint16_t R;
+ struct {
+ vuint16_t MTM:1; /* Message Buffer Transmission Mode */
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CHA:1; /* Channel Assignment */
+#else
+ vuint16_t CHNLA:1; /* deprecated name - please avoid */
+#endif
+#ifndef USE_FIELD_ALIASES_FR
+ vuint16_t CHB:1; /* Channel Assignment */
+#else
+ vuint16_t CHNLB:1; /* deprecated name - please avoid */
+#endif
+ vuint16_t CCFE:1; /* Cycle Counter Filtering Enable */
+ vuint16_t CCFMSK:6; /* Cycle Counter Filtering Mask */
+ vuint16_t CCFVAL:6; /* Cycle Counter Filtering Value */
+ } B;
+ } FR_MBCCFR_16B_tag;
+
+
+ /* Register layout for all registers MBFIDR... */
+
+ typedef union { /* Message Buffer Frame ID Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:5;
+ vuint16_t FID:11; /* Frame ID */
+ } B;
+ } FR_MBFIDR_16B_tag;
+
+
+ /* Register layout for all registers MBIDXR... */
+
+ typedef union { /* Message Buffer Index Register */
+ vuint16_t R;
+ struct {
+ vuint16_t:9;
+ vuint16_t MBIDX:7; /* Message Buffer Index */
+ } B;
+ } FR_MBIDXR_16B_tag;
+
+
+ /* Register layout for generated register(s) NMVR... */
+
+ typedef union { /* */
+ vuint16_t R;
+ } FR_NMVR_16B_tag;
+
+
+
+
+ /* Register layout for generated register(s) SSCR... */
+
+ typedef union { /* */
+ vuint16_t R;
+ } FR_SSCR_16B_tag;
+
+
+ typedef struct FR_MB_struct_tag {
+
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR; /* relative offset: 0x0000 */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR; /* relative offset: 0x0002 */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR; /* relative offset: 0x0004 */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR; /* relative offset: 0x0006 */
+
+ } FR_MB_tag;
+
+
+ typedef struct FR_struct_tag { /* start of FR_tag */
+ /* Module Version Number */
+ FR_MVR_16B_tag MVR; /* offset: 0x0000 size: 16 bit */
+ /* Module Configuration Register */
+ FR_MCR_16B_tag MCR; /* offset: 0x0002 size: 16 bit */
+ union {
+ FR_SYMBADHR_16B_tag SYSBADHR; /* deprecated - please avoid */
+
+ /* SYSTEM MEMORY BASE ADD HIGH REG */
+ FR_SYMBADHR_16B_tag SYMBADHR; /* offset: 0x0004 size: 16 bit */
+
+ };
+ union {
+ FR_SYMBADLR_16B_tag SYSBADLR; /* deprecated - please avoid */
+
+ /* SYSTEM MEMORY BASE ADD LOW REG */
+ FR_SYMBADLR_16B_tag SYMBADLR; /* offset: 0x0006 size: 16 bit */
+
+ };
+ /* STROBE SIGNAL CONTROL REGISTER */
+ FR_STBSCR_16B_tag STBSCR; /* offset: 0x0008 size: 16 bit */
+ int8_t FR_reserved_000A[2];
+ /* MESSAGE BUFFER DATA SIZE REGISTER */
+ FR_MBDSR_16B_tag MBDSR; /* offset: 0x000C size: 16 bit */
+ /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
+ FR_MBSSUTR_16B_tag MBSSUTR; /* offset: 0x000E size: 16 bit */
+ union {
+ /* PE DRAM ACCESS REGISTER */
+ FR_PEDRAR_16B_tag PEDRAR; /* offset: 0x0010 size: 16 bit */
+
+ FR_PEDRAR_16B_tag PADR; /* deprecated - please avoid */
+
+ };
+ union {
+ /* PE DRAM DATA REGISTER */
+ FR_PEDRDR_16B_tag PEDRDR; /* offset: 0x0012 size: 16 bit */
+
+ FR_PEDRDR_16B_tag PDAR; /* deprecated - please avoid */
+
+ };
+ /* PROTOCOL OPERATION CONTROL REG */
+ FR_POCR_16B_tag POCR; /* offset: 0x0014 size: 16 bit */
+ /* GLOBAL INTERRUPT FLAG & ENABLE REG */
+ FR_GIFER_16B_tag GIFER; /* offset: 0x0016 size: 16 bit */
+ /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
+ FR_PIFR0_16B_tag PIFR0; /* offset: 0x0018 size: 16 bit */
+ /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
+ FR_PIFR1_16B_tag PIFR1; /* offset: 0x001A size: 16 bit */
+ /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
+ FR_PIER0_16B_tag PIER0; /* offset: 0x001C size: 16 bit */
+ /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
+ FR_PIER1_16B_tag PIER1; /* offset: 0x001E size: 16 bit */
+ /* CHI ERROR FLAG REGISTER */
+ FR_CHIERFR_16B_tag CHIERFR; /* offset: 0x0020 size: 16 bit */
+ /* Message Buffer Interrupt Vector Register */
+ FR_MBIVEC_16B_tag MBIVEC; /* offset: 0x0022 size: 16 bit */
+ /* Channel A Status Error Counter Register */
+ FR_CASERCR_16B_tag CASERCR; /* offset: 0x0024 size: 16 bit */
+ /* Channel B Status Error Counter Register */
+ FR_CBSERCR_16B_tag CBSERCR; /* offset: 0x0026 size: 16 bit */
+ /* Protocol Status Register 0 */
+ FR_PSR0_16B_tag PSR0; /* offset: 0x0028 size: 16 bit */
+ /* Protocol Status Register 1 */
+ FR_PSR1_16B_tag PSR1; /* offset: 0x002A size: 16 bit */
+ /* Protocol Status Register 2 */
+ FR_PSR2_16B_tag PSR2; /* offset: 0x002C size: 16 bit */
+ /* Protocol Status Register 3 */
+ FR_PSR3_16B_tag PSR3; /* offset: 0x002E size: 16 bit */
+ /* Macrotick Counter Register */
+ FR_MTCTR_16B_tag MTCTR; /* offset: 0x0030 size: 16 bit */
+ /* Cycle Counter Register */
+ FR_CYCTR_16B_tag CYCTR; /* offset: 0x0032 size: 16 bit */
+ /* Slot Counter Channel A Register */
+ FR_SLTCTAR_16B_tag SLTCTAR; /* offset: 0x0034 size: 16 bit */
+ /* Slot Counter Channel B Register */
+ FR_SLTCTBR_16B_tag SLTCTBR; /* offset: 0x0036 size: 16 bit */
+ /* Rate Correction Value Register */
+ FR_RTCORVR_16B_tag RTCORVR; /* offset: 0x0038 size: 16 bit */
+ /* Offset Correction Value Register */
+ FR_OFCORVR_16B_tag OFCORVR; /* offset: 0x003A size: 16 bit */
+ union {
+ FR_CIFR_16B_tag CIFRR; /* deprecated - please avoid */
+
+ /* Combined Interrupt Flag Register */
+ FR_CIFR_16B_tag CIFR; /* offset: 0x003C size: 16 bit */
+
+ };
+ /* System Memory Access Time-Out Register */
+ FR_SYMATOR_16B_tag SYMATOR; /* offset: 0x003E size: 16 bit */
+ /* Sync Frame Counter Register */
+ FR_SFCNTR_16B_tag SFCNTR; /* offset: 0x0040 size: 16 bit */
+ /* Sync Frame Table Offset Register */
+ FR_SFTOR_16B_tag SFTOR; /* offset: 0x0042 size: 16 bit */
+ /* Sync Frame Table Configuration, Control, Status Register */
+ FR_SFTCCSR_16B_tag SFTCCSR; /* offset: 0x0044 size: 16 bit */
+ /* Sync Frame ID Rejection Filter */
+ FR_SFIDRFR_16B_tag SFIDRFR; /* offset: 0x0046 size: 16 bit */
+ /* Sync Frame ID Acceptance Filter Value Register */
+ FR_SFIDAFVR_16B_tag SFIDAFVR; /* offset: 0x0048 size: 16 bit */
+ /* Sync Frame ID Acceptance Filter Mask Register */
+ FR_SFIDAFMR_16B_tag SFIDAFMR; /* offset: 0x004A size: 16 bit */
+ union {
+ FR_NMVR_16B_tag NMVR[6]; /* offset: 0x004C (0x0002 x 6) */
+
+ struct {
+ /* Network Management Vector Register0 */
+ FR_NMVR0_16B_tag NMVR0; /* offset: 0x004C size: 16 bit */
+ /* Network Management Vector Register1 */
+ FR_NMVR1_16B_tag NMVR1; /* offset: 0x004E size: 16 bit */
+ /* Network Management Vector Register2 */
+ FR_NMVR2_16B_tag NMVR2; /* offset: 0x0050 size: 16 bit */
+ /* Network Management Vector Register3 */
+ FR_NMVR3_16B_tag NMVR3; /* offset: 0x0052 size: 16 bit */
+ /* Network Management Vector Register4 */
+ FR_NMVR4_16B_tag NMVR4; /* offset: 0x0054 size: 16 bit */
+ /* Network Management Vector Register5 */
+ FR_NMVR5_16B_tag NMVR5; /* offset: 0x0056 size: 16 bit */
+ };
+
+ };
+ /* Network Management Vector Length Register */
+ FR_NMVLR_16B_tag NMVLR; /* offset: 0x0058 size: 16 bit */
+ /* Timer Configuration and Control Register */
+ FR_TICCR_16B_tag TICCR; /* offset: 0x005A size: 16 bit */
+ /* Timer 1 Cycle Set Register */
+ FR_TI1CYSR_16B_tag TI1CYSR; /* offset: 0x005C size: 16 bit */
+ union {
+ /* Timer 1 Macrotick Offset Register */
+ FR_TI1MTOR_16B_tag TI1MTOR; /* offset: 0x005E size: 16 bit */
+
+ FR_TI1MTOR_16B_tag T1MTOR; /* deprecated - please avoid */
+
+ };
+ /* Timer 2 Configuration Register 0 */
+ FR_TI2CR0_16B_tag TI2CR0; /* offset: 0x0060 size: 16 bit */
+ /* Timer 2 Configuration Register 1 */
+ FR_TI2CR1_16B_tag TI2CR1; /* offset: 0x0062 size: 16 bit */
+ /* Slot Status Selection Register */
+ FR_SSSR_16B_tag SSSR; /* offset: 0x0064 size: 16 bit */
+ /* Slot Status Counter Condition Register */
+ FR_SSCCR_16B_tag SSCCR; /* offset: 0x0066 size: 16 bit */
+ union {
+ FR_SSR_16B_tag SSR[8]; /* offset: 0x0068 (0x0002 x 8) */
+
+ struct {
+ /* Slot Status Register0 */
+ FR_SSR_16B_tag SSR0; /* offset: 0x0068 size: 16 bit */
+ /* Slot Status Register1 */
+ FR_SSR_16B_tag SSR1; /* offset: 0x006A size: 16 bit */
+ /* Slot Status Register2 */
+ FR_SSR_16B_tag SSR2; /* offset: 0x006C size: 16 bit */
+ /* Slot Status Register3 */
+ FR_SSR_16B_tag SSR3; /* offset: 0x006E size: 16 bit */
+ /* Slot Status Register4 */
+ FR_SSR_16B_tag SSR4; /* offset: 0x0070 size: 16 bit */
+ /* Slot Status Register5 */
+ FR_SSR_16B_tag SSR5; /* offset: 0x0072 size: 16 bit */
+ /* Slot Status Register6 */
+ FR_SSR_16B_tag SSR6; /* offset: 0x0074 size: 16 bit */
+ /* Slot Status Register7 */
+ FR_SSR_16B_tag SSR7; /* offset: 0x0076 size: 16 bit */
+ };
+
+ };
+ union {
+ FR_SSCR_16B_tag SSCR[4]; /* offset: 0x0078 (0x0002 x 4) */
+
+ struct {
+ /* Slot Status Counter Register0 */
+ FR_SSCR0_16B_tag SSCR0; /* offset: 0x0078 size: 16 bit */
+ /* Slot Status Counter Register1 */
+ FR_SSCR1_16B_tag SSCR1; /* offset: 0x007A size: 16 bit */
+ /* Slot Status Counter Register2 */
+ FR_SSCR2_16B_tag SSCR2; /* offset: 0x007C size: 16 bit */
+ /* Slot Status Counter Register3 */
+ FR_SSCR3_16B_tag SSCR3; /* offset: 0x007E size: 16 bit */
+ };
+
+ };
+ /* MTS A Configuration Register */
+ FR_MTSACFR_16B_tag MTSACFR; /* offset: 0x0080 size: 16 bit */
+ /* MTS B Configuration Register */
+ FR_MTSBCFR_16B_tag MTSBCFR; /* offset: 0x0082 size: 16 bit */
+ /* Receive Shadow Buffer Index Register */
+ FR_RSBIR_16B_tag RSBIR; /* offset: 0x0084 size: 16 bit */
+ union {
+ /* Receive FIFO Watermark and Selection Register */
+ FR_RFWMSR_16B_tag RFWMSR; /* offset: 0x0086 size: 16 bit */
+
+ FR_RFWMSR_16B_tag RFSR; /* deprecated - please avoid */
+
+ };
+ union {
+ FR_RF_RFSIR_16B_tag RFSIR; /* deprecated - please avoid */
+
+ /* Receive FIFO Start Index Register */
+ FR_RF_RFSIR_16B_tag RF_RFSIR; /* offset: 0x0088 size: 16 bit */
+
+ };
+ /* Receive FIFO Depth and Size Register */
+ FR_RFDSR_16B_tag RFDSR; /* offset: 0x008A size: 16 bit */
+ /* Receive FIFO A Read Index Register */
+ FR_RFARIR_16B_tag RFARIR; /* offset: 0x008C size: 16 bit */
+ /* Receive FIFO B Read Index Register */
+ FR_RFBRIR_16B_tag RFBRIR; /* offset: 0x008E size: 16 bit */
+ /* Receive FIFO Message ID Acceptance Filter Value Register */
+ FR_RFMIDAFVR_16B_tag RFMIDAFVR; /* offset: 0x0090 size: 16 bit */
+ union {
+ /* Receive FIFO Message ID Acceptance Filter Mask Register */
+ FR_RFMIDAFMR_16B_tag RFMIDAFMR; /* offset: 0x0092 size: 16 bit */
+
+ FR_RFMIDAFMR_16B_tag RFMIAFMR; /* deprecated - please avoid */
+
+ };
+ /* Receive FIFO Frame ID Rejection Filter Value Register */
+ FR_RFFIDRFVR_16B_tag RFFIDRFVR; /* offset: 0x0094 size: 16 bit */
+ /* Receive FIFO Frame ID Rejection Filter Mask Register */
+ FR_RFFIDRFMR_16B_tag RFFIDRFMR; /* offset: 0x0096 size: 16 bit */
+ /* Receive FIFO Range Filter Configuration Register */
+ FR_RFRFCFR_16B_tag RFRFCFR; /* offset: 0x0098 size: 16 bit */
+ /* Receive FIFO Range Filter Control Register */
+ FR_RFRFCTR_16B_tag RFRFCTR; /* offset: 0x009A size: 16 bit */
+ /* Last Dynamic Transmit Slot Channel A Register */
+ FR_LDTXSLAR_16B_tag LDTXSLAR; /* offset: 0x009C size: 16 bit */
+ /* Last Dynamic Transmit Slot Channel B Register */
+ FR_LDTXSLBR_16B_tag LDTXSLBR; /* offset: 0x009E size: 16 bit */
+ /* Protocol Configuration Register 0 */
+ FR_PCR0_16B_tag PCR0; /* offset: 0x00A0 size: 16 bit */
+ /* Protocol Configuration Register 1 */
+ FR_PCR1_16B_tag PCR1; /* offset: 0x00A2 size: 16 bit */
+ /* Protocol Configuration Register 2 */
+ FR_PCR2_16B_tag PCR2; /* offset: 0x00A4 size: 16 bit */
+ /* Protocol Configuration Register 3 */
+ FR_PCR3_16B_tag PCR3; /* offset: 0x00A6 size: 16 bit */
+ /* Protocol Configuration Register 4 */
+ FR_PCR4_16B_tag PCR4; /* offset: 0x00A8 size: 16 bit */
+ /* Protocol Configuration Register 5 */
+ FR_PCR5_16B_tag PCR5; /* offset: 0x00AA size: 16 bit */
+ /* Protocol Configuration Register 6 */
+ FR_PCR6_16B_tag PCR6; /* offset: 0x00AC size: 16 bit */
+ /* Protocol Configuration Register 7 */
+ FR_PCR7_16B_tag PCR7; /* offset: 0x00AE size: 16 bit */
+ /* Protocol Configuration Register 8 */
+ FR_PCR8_16B_tag PCR8; /* offset: 0x00B0 size: 16 bit */
+ /* Protocol Configuration Register 9 */
+ FR_PCR9_16B_tag PCR9; /* offset: 0x00B2 size: 16 bit */
+ /* Protocol Configuration Register 10 */
+ FR_PCR10_16B_tag PCR10; /* offset: 0x00B4 size: 16 bit */
+ /* Protocol Configuration Register 11 */
+ FR_PCR11_16B_tag PCR11; /* offset: 0x00B6 size: 16 bit */
+ /* Protocol Configuration Register 12 */
+ FR_PCR12_16B_tag PCR12; /* offset: 0x00B8 size: 16 bit */
+ /* Protocol Configuration Register 13 */
+ FR_PCR13_16B_tag PCR13; /* offset: 0x00BA size: 16 bit */
+ /* Protocol Configuration Register 14 */
+ FR_PCR14_16B_tag PCR14; /* offset: 0x00BC size: 16 bit */
+ /* Protocol Configuration Register 15 */
+ FR_PCR15_16B_tag PCR15; /* offset: 0x00BE size: 16 bit */
+ /* Protocol Configuration Register 16 */
+ FR_PCR16_16B_tag PCR16; /* offset: 0x00C0 size: 16 bit */
+ /* Protocol Configuration Register 17 */
+ FR_PCR17_16B_tag PCR17; /* offset: 0x00C2 size: 16 bit */
+ /* Protocol Configuration Register 18 */
+ FR_PCR18_16B_tag PCR18; /* offset: 0x00C4 size: 16 bit */
+ /* Protocol Configuration Register 19 */
+ FR_PCR19_16B_tag PCR19; /* offset: 0x00C6 size: 16 bit */
+ /* Protocol Configuration Register 20 */
+ FR_PCR20_16B_tag PCR20; /* offset: 0x00C8 size: 16 bit */
+ /* Protocol Configuration Register 21 */
+ FR_PCR21_16B_tag PCR21; /* offset: 0x00CA size: 16 bit */
+ /* Protocol Configuration Register 22 */
+ FR_PCR22_16B_tag PCR22; /* offset: 0x00CC size: 16 bit */
+ /* Protocol Configuration Register 23 */
+ FR_PCR23_16B_tag PCR23; /* offset: 0x00CE size: 16 bit */
+ /* Protocol Configuration Register 24 */
+ FR_PCR24_16B_tag PCR24; /* offset: 0x00D0 size: 16 bit */
+ /* Protocol Configuration Register 25 */
+ FR_PCR25_16B_tag PCR25; /* offset: 0x00D2 size: 16 bit */
+ /* Protocol Configuration Register 26 */
+ FR_PCR26_16B_tag PCR26; /* offset: 0x00D4 size: 16 bit */
+ /* Protocol Configuration Register 27 */
+ FR_PCR27_16B_tag PCR27; /* offset: 0x00D6 size: 16 bit */
+ /* Protocol Configuration Register 28 */
+ FR_PCR28_16B_tag PCR28; /* offset: 0x00D8 size: 16 bit */
+ /* Protocol Configuration Register 29 */
+ FR_PCR29_16B_tag PCR29; /* offset: 0x00DA size: 16 bit */
+ /* Protocol Configuration Register 30 */
+ FR_PCR30_16B_tag PCR30; /* offset: 0x00DC size: 16 bit */
+ int8_t FR_reserved_00DE[10];
+ /* Receive FIFO System Memory Base Address High Register */
+ FR_RFSYMBHADR_16B_tag RFSYMBHADR; /* offset: 0x00E8 size: 16 bit */
+ /* Receive FIFO System Memory Base Address Low Register */
+ FR_RFSYMBLADR_16B_tag RFSYMBLADR; /* offset: 0x00EA size: 16 bit */
+ /* Receive FIFO Periodic Timer Register */
+ FR_RFPTR_16B_tag RFPTR; /* offset: 0x00EC size: 16 bit */
+ /* Receive FIFO Fill Level and Pop Count Register */
+ FR_RFFLPCR_16B_tag RFFLPCR; /* offset: 0x00EE size: 16 bit */
+ /* ECC Error Interrupt Flag and Enable Register */
+ FR_EEIFER_16B_tag EEIFER; /* offset: 0x00F0 size: 16 bit */
+ /* ECC Error Report and Injection Control Register */
+ FR_EERICR_16B_tag EERICR; /* offset: 0x00F2 size: 16 bit */
+ /* ECC Error Report Adress Register */
+ FR_EERAR_16B_tag EERAR; /* offset: 0x00F4 size: 16 bit */
+ /* ECC Error Report Data Register */
+ FR_EERDR_16B_tag EERDR; /* offset: 0x00F6 size: 16 bit */
+ /* ECC Error Report Code Register */
+ FR_EERCR_16B_tag EERCR; /* offset: 0x00F8 size: 16 bit */
+ /* ECC Error Injection Address Register */
+ FR_EEIAR_16B_tag EEIAR; /* offset: 0x00FA size: 16 bit */
+ /* ECC Error Injection Data Register */
+ FR_EEIDR_16B_tag EEIDR; /* offset: 0x00FC size: 16 bit */
+ /* ECC Error Injection Code Register */
+ FR_EEICR_16B_tag EEICR; /* offset: 0x00FE size: 16 bit */
+ union {
+ /* Register set MB */
+ FR_MB_tag MB[64]; /* offset: 0x0100 (0x0008 x 64) */
+
+ struct {
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR0; /* offset: 0x0100 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR0; /* offset: 0x0102 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR0; /* offset: 0x0104 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR0; /* offset: 0x0106 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR1; /* offset: 0x0108 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR1; /* offset: 0x010A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR1; /* offset: 0x010C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR1; /* offset: 0x010E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR2; /* offset: 0x0110 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR2; /* offset: 0x0112 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR2; /* offset: 0x0114 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR2; /* offset: 0x0116 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR3; /* offset: 0x0118 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR3; /* offset: 0x011A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR3; /* offset: 0x011C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR3; /* offset: 0x011E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR4; /* offset: 0x0120 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR4; /* offset: 0x0122 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR4; /* offset: 0x0124 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR4; /* offset: 0x0126 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR5; /* offset: 0x0128 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR5; /* offset: 0x012A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR5; /* offset: 0x012C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR5; /* offset: 0x012E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR6; /* offset: 0x0130 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR6; /* offset: 0x0132 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR6; /* offset: 0x0134 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR6; /* offset: 0x0136 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR7; /* offset: 0x0138 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR7; /* offset: 0x013A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR7; /* offset: 0x013C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR7; /* offset: 0x013E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR8; /* offset: 0x0140 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR8; /* offset: 0x0142 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR8; /* offset: 0x0144 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR8; /* offset: 0x0146 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR9; /* offset: 0x0148 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR9; /* offset: 0x014A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR9; /* offset: 0x014C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR9; /* offset: 0x014E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR10; /* offset: 0x0150 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR10; /* offset: 0x0152 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR10; /* offset: 0x0154 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR10; /* offset: 0x0156 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR11; /* offset: 0x0158 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR11; /* offset: 0x015A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR11; /* offset: 0x015C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR11; /* offset: 0x015E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR12; /* offset: 0x0160 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR12; /* offset: 0x0162 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR12; /* offset: 0x0164 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR12; /* offset: 0x0166 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR13; /* offset: 0x0168 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR13; /* offset: 0x016A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR13; /* offset: 0x016C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR13; /* offset: 0x016E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR14; /* offset: 0x0170 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR14; /* offset: 0x0172 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR14; /* offset: 0x0174 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR14; /* offset: 0x0176 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR15; /* offset: 0x0178 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR15; /* offset: 0x017A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR15; /* offset: 0x017C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR15; /* offset: 0x017E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR16; /* offset: 0x0180 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR16; /* offset: 0x0182 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR16; /* offset: 0x0184 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR16; /* offset: 0x0186 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR17; /* offset: 0x0188 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR17; /* offset: 0x018A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR17; /* offset: 0x018C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR17; /* offset: 0x018E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR18; /* offset: 0x0190 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR18; /* offset: 0x0192 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR18; /* offset: 0x0194 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR18; /* offset: 0x0196 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR19; /* offset: 0x0198 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR19; /* offset: 0x019A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR19; /* offset: 0x019C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR19; /* offset: 0x019E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR20; /* offset: 0x01A0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR20; /* offset: 0x01A2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR20; /* offset: 0x01A4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR20; /* offset: 0x01A6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR21; /* offset: 0x01A8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR21; /* offset: 0x01AA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR21; /* offset: 0x01AC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR21; /* offset: 0x01AE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR22; /* offset: 0x01B0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR22; /* offset: 0x01B2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR22; /* offset: 0x01B4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR22; /* offset: 0x01B6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR23; /* offset: 0x01B8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR23; /* offset: 0x01BA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR23; /* offset: 0x01BC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR23; /* offset: 0x01BE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR24; /* offset: 0x01C0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR24; /* offset: 0x01C2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR24; /* offset: 0x01C4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR24; /* offset: 0x01C6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR25; /* offset: 0x01C8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR25; /* offset: 0x01CA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR25; /* offset: 0x01CC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR25; /* offset: 0x01CE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR26; /* offset: 0x01D0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR26; /* offset: 0x01D2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR26; /* offset: 0x01D4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR26; /* offset: 0x01D6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR27; /* offset: 0x01D8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR27; /* offset: 0x01DA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR27; /* offset: 0x01DC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR27; /* offset: 0x01DE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR28; /* offset: 0x01E0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR28; /* offset: 0x01E2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR28; /* offset: 0x01E4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR28; /* offset: 0x01E6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR29; /* offset: 0x01E8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR29; /* offset: 0x01EA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR29; /* offset: 0x01EC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR29; /* offset: 0x01EE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR30; /* offset: 0x01F0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR30; /* offset: 0x01F2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR30; /* offset: 0x01F4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR30; /* offset: 0x01F6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR31; /* offset: 0x01F8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR31; /* offset: 0x01FA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR31; /* offset: 0x01FC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR31; /* offset: 0x01FE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR32; /* offset: 0x0200 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR32; /* offset: 0x0202 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR32; /* offset: 0x0204 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR32; /* offset: 0x0206 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR33; /* offset: 0x0208 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR33; /* offset: 0x020A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR33; /* offset: 0x020C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR33; /* offset: 0x020E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR34; /* offset: 0x0210 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR34; /* offset: 0x0212 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR34; /* offset: 0x0214 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR34; /* offset: 0x0216 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR35; /* offset: 0x0218 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR35; /* offset: 0x021A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR35; /* offset: 0x021C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR35; /* offset: 0x021E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR36; /* offset: 0x0220 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR36; /* offset: 0x0222 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR36; /* offset: 0x0224 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR36; /* offset: 0x0226 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR37; /* offset: 0x0228 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR37; /* offset: 0x022A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR37; /* offset: 0x022C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR37; /* offset: 0x022E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR38; /* offset: 0x0230 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR38; /* offset: 0x0232 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR38; /* offset: 0x0234 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR38; /* offset: 0x0236 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR39; /* offset: 0x0238 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR39; /* offset: 0x023A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR39; /* offset: 0x023C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR39; /* offset: 0x023E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR40; /* offset: 0x0240 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR40; /* offset: 0x0242 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR40; /* offset: 0x0244 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR40; /* offset: 0x0246 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR41; /* offset: 0x0248 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR41; /* offset: 0x024A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR41; /* offset: 0x024C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR41; /* offset: 0x024E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR42; /* offset: 0x0250 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR42; /* offset: 0x0252 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR42; /* offset: 0x0254 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR42; /* offset: 0x0256 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR43; /* offset: 0x0258 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR43; /* offset: 0x025A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR43; /* offset: 0x025C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR43; /* offset: 0x025E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR44; /* offset: 0x0260 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR44; /* offset: 0x0262 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR44; /* offset: 0x0264 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR44; /* offset: 0x0266 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR45; /* offset: 0x0268 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR45; /* offset: 0x026A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR45; /* offset: 0x026C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR45; /* offset: 0x026E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR46; /* offset: 0x0270 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR46; /* offset: 0x0272 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR46; /* offset: 0x0274 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR46; /* offset: 0x0276 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR47; /* offset: 0x0278 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR47; /* offset: 0x027A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR47; /* offset: 0x027C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR47; /* offset: 0x027E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR48; /* offset: 0x0280 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR48; /* offset: 0x0282 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR48; /* offset: 0x0284 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR48; /* offset: 0x0286 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR49; /* offset: 0x0288 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR49; /* offset: 0x028A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR49; /* offset: 0x028C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR49; /* offset: 0x028E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR50; /* offset: 0x0290 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR50; /* offset: 0x0292 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR50; /* offset: 0x0294 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR50; /* offset: 0x0296 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR51; /* offset: 0x0298 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR51; /* offset: 0x029A size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR51; /* offset: 0x029C size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR51; /* offset: 0x029E size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR52; /* offset: 0x02A0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR52; /* offset: 0x02A2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR52; /* offset: 0x02A4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR52; /* offset: 0x02A6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR53; /* offset: 0x02A8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR53; /* offset: 0x02AA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR53; /* offset: 0x02AC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR53; /* offset: 0x02AE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR54; /* offset: 0x02B0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR54; /* offset: 0x02B2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR54; /* offset: 0x02B4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR54; /* offset: 0x02B6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR55; /* offset: 0x02B8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR55; /* offset: 0x02BA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR55; /* offset: 0x02BC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR55; /* offset: 0x02BE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR56; /* offset: 0x02C0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR56; /* offset: 0x02C2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR56; /* offset: 0x02C4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR56; /* offset: 0x02C6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR57; /* offset: 0x02C8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR57; /* offset: 0x02CA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR57; /* offset: 0x02CC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR57; /* offset: 0x02CE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR58; /* offset: 0x02D0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR58; /* offset: 0x02D2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR58; /* offset: 0x02D4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR58; /* offset: 0x02D6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR59; /* offset: 0x02D8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR59; /* offset: 0x02DA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR59; /* offset: 0x02DC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR59; /* offset: 0x02DE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR60; /* offset: 0x02E0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR60; /* offset: 0x02E2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR60; /* offset: 0x02E4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR60; /* offset: 0x02E6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR61; /* offset: 0x02E8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR61; /* offset: 0x02EA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR61; /* offset: 0x02EC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR61; /* offset: 0x02EE size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR62; /* offset: 0x02F0 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR62; /* offset: 0x02F2 size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR62; /* offset: 0x02F4 size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR62; /* offset: 0x02F6 size: 16 bit */
+ /* Message Buffer Configuration Control Status Register */
+ FR_MBCCSR_16B_tag MBCCSR63; /* offset: 0x02F8 size: 16 bit */
+ /* Message Buffer Cycle Counter Filter Register */
+ FR_MBCCFR_16B_tag MBCCFR63; /* offset: 0x02FA size: 16 bit */
+ /* Message Buffer Frame ID Register */
+ FR_MBFIDR_16B_tag MBFIDR63; /* offset: 0x02FC size: 16 bit */
+ /* Message Buffer Index Register */
+ FR_MBIDXR_16B_tag MBIDXR63; /* offset: 0x02FE size: 16 bit */
+ };
+
+ };
+ } FR_tag;
+
+
+#define FR (*(volatile FR_tag *) 0xFFFE0000UL)
+
+
+
+
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _leopard_H_*/
+/* End of file */
+
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