diff options
| author | acirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-01 14:55:08 +0000 |
|---|---|---|
| committer | acirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-06-01 14:55:08 +0000 |
| commit | d82fa57b9cfb363cc6cc030c8d95f3d58fd5bfdb (patch) | |
| tree | 2bc2e0915fbfb82830a644b430e1b144e69b1d2c /os | |
| parent | bea1f59f1407b52fd68727c665723105dbb8f715 (diff) | |
| download | ChibiOS-d82fa57b9cfb363cc6cc030c8d95f3d58fd5bfdb.tar.gz ChibiOS-d82fa57b9cfb363cc6cc030c8d95f3d58fd5bfdb.tar.bz2 ChibiOS-d82fa57b9cfb363cc6cc030c8d95f3d58fd5bfdb.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5790 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/SPC560BCxx/spc560bc_registry.h | 121 | ||||
| -rw-r--r-- | os/hal/platforms/SPC560Pxx/spc560p_registry.h | 21 | ||||
| -rw-r--r-- | os/hal/platforms/SPC56ELxx/spc56el_registry.h | 41 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c | 1618 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h | 520 | ||||
| -rw-r--r-- | os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h | 442 |
6 files changed, 2763 insertions, 0 deletions
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h index cfad96b5f..2d449a5b6 100644 --- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h +++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h @@ -88,6 +88,127 @@ #define SPC5_SIUL_NUM_PCRS 123
#define SPC5_SIUL_NUM_PADSELS 32
#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 64
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER vector73
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_NUMBER 73
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 64
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER vector93
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_NUMBER 93
+
+#define SPC5_HAS_FLEXCAN2 TRUE
+#define SPC5_FLEXCAN2_PCTL 18
+#define SPC5_FLEXCAN2_MB 64
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER vector105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER vector106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER vector108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER vector109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER vector110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER vector111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER vector112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER vector113
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER 105
+#define SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER 106
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER 108
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER 109
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER 110
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER 111
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER 112
+#define SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_NUMBER 113
+
+#define SPC5_HAS_FLEXCAN3 TRUE
+#define SPC5_FLEXCAN3_PCTL 19
+#define SPC5_FLEXCAN3_MB 64
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER vector173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER vector174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER vector176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER vector177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER vector178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER vector179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER vector180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER vector181
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER 173
+#define SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER 174
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER 176
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER 177
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER 178
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER 179
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER 180
+#define SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_NUMBER 181
+
+#define SPC5_HAS_FLEXCAN4 TRUE
+#define SPC5_FLEXCAN4_PCTL 20
+#define SPC5_FLEXCAN4_MB 64
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER vector190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER vector191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER vector193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER vector194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER vector195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER vector196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER vector197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER vector198
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER 190
+#define SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER 191
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER 193
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER 194
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER 195
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER 196
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER 197
+#define SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_NUMBER 198
+
+#define SPC5_HAS_FLEXCAN5 TRUE
+#define SPC5_FLEXCAN5_PCTL 21
+#define SPC5_FLEXCAN5_MB 64
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER vector202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER vector203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER vector205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER vector206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER vector207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER vector208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER vector209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER vector210
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER 202
+#define SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER 203
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER 205
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER 206
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER 207
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER 208
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER 209
+#define SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_NUMBER 210
/** @} */
#endif /* _SPC560BC_REGISTRY_H_ */
diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 077679ab1..a43b0ef2b 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -144,6 +144,27 @@ #define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
#define SPC5_HAS_ETIMER2 FALSE
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 32
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
/** @} */
#endif /* _SPC560P_REGISTRY_H_ */
diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h index 5b7bd34e3..8d5dd45fd 100644 --- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h +++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h @@ -193,6 +193,47 @@ #define SPC5_ETIMER2_TC5IR_NUMBER 227
#define SPC5_ETIMER2_RCF_NUMBER 232
#define SPC5_ETIMER2_CLK SPC5_MCONTROL_CLK
+
+/* FlexCAN attributes.*/
+#define SPC5_HAS_FLEXCAN0 TRUE
+#define SPC5_FLEXCAN0_PCTL 16
+#define SPC5_FLEXCAN0_MB 32
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER vector65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER vector66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_HANDLER vector67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER vector68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER vector69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER vector70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER vector71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER vector72
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER 65
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER 66
+#define SPC5_FLEXCAN0_FLEXCAN_ESR_WAK_NUMBER 67
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER 68
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER 69
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER 70
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER 71
+#define SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER 72
+
+#define SPC5_HAS_FLEXCAN1 TRUE
+#define SPC5_FLEXCAN1_PCTL 17
+#define SPC5_FLEXCAN1_MB 32
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER vector85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER vector86
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_HANDLER vector87
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER vector88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER vector89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER vector90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER vector91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER vector92
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER 85
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER 86
+#define SPC5_FLEXCAN1_FLEXCAN_ESR_WAK_NUMBER 87
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER 88
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER 89
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER 90
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER 91
+#define SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER 92
/** @} */
#endif /* _SPC56EL_REGISTRY_H_ */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c new file mode 100644 index 000000000..2d8ceda5c --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.c @@ -0,0 +1,1618 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FlexCAN_v1/can_lld.c
+ * @brief SPC5xx CAN subsystem low level driver source.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_CAN || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief CAN1 driver identifier.*/
+#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__)
+CANDriver CAND1;
+#endif
+
+/** @brief CAN2 driver identifier.*/
+#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__)
+CANDriver CAND2;
+#endif
+
+/** @brief CAN3 driver identifier.*/
+#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__)
+CANDriver CAND3;
+#endif
+
+/** @brief CAN4 driver identifier.*/
+#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__)
+CANDriver CAND4;
+#endif
+
+/** @brief CAN5 driver identifier.*/
+#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__)
+CANDriver CAND5;
+#endif
+
+/** @brief CAN6 driver identifier.*/
+#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__)
+CANDriver CAND6;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Common TX ISR handler.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_tx_handler(CANDriver *canp) {
+ uint32_t iflag1;
+
+ iflag1 = canp->flexcan->IFRL.R;
+ /* No more events until a message is transmitted.*/
+ canp->flexcan->IFRL.R |= iflag1 & 0xFFFFFF00;
+ canp->flexcan->IFRH.R |= canp->flexcan->IFRH.R & 0xFFFFFFFF;
+ chSysLockFromIsr();
+ while (chSemGetCounterI(&canp->txsem) < 0)
+ chSemSignalI(&canp->txsem);
+ chEvtBroadcastFlagsI(&canp->txempty_event, iflag1 & 0xFFFFFF00);
+ chSysUnlockFromIsr();
+}
+
+/**
+ * @brief Common RX ISR handler.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_rx_handler(CANDriver *canp) {
+ uint32_t iflag1;
+
+ iflag1 = canp->flexcan->IFRL.R;
+ if ((iflag1 & 0x000000FF) != 0) {
+ chSysLockFromIsr();
+ while (chSemGetCounterI(&canp->rxsem) < 0)
+ chSemSignalI(&canp->rxsem);
+ chEvtBroadcastFlagsI(&canp->rxfull_event, iflag1 & 0x000000FF);
+ chSysUnlockFromIsr();
+
+ /* Release the mailbox.*/
+ canp->flexcan->IFRL.R |= iflag1 & 0x000000FF;
+ }
+}
+
+/**
+ * @brief Common error ISR handler.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_err_handler(CANDriver *canp) {
+
+ uint32_t esr = canp->flexcan->ESR.R;
+ flagsmask_t flags = 0;
+
+ /* Error event.*/
+ if ((esr & CAN_ESR_TWRN_INT) || (esr & CAN_ESR_RWRN_INT)) {
+ canp->flexcan->ESR.B.TXWRN = 1U;
+ canp->flexcan->ESR.B.RXWRN = 1U;
+ flags |= CAN_LIMIT_WARNING;
+ }
+
+ if (esr & CAN_ESR_BOFF_INT) {
+ canp->flexcan->ESR.B.BOFFINT = 1U;
+ flags |= CAN_BUS_OFF_ERROR;
+ }
+
+ if (esr & CAN_ESR_ERR_INT) {
+ canp->flexcan->ESR.B.ERRINT = 1U;
+ flags |= CAN_FRAMING_ERROR;
+ }
+ chSysLockFromIsr();
+ chEvtBroadcastFlagsI(&canp->error_event, flags);
+ chSysUnlockFromIsr();
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if SPC5_CAN_USE_FLEXCAN0 || defined(__DOXYGEN__)
+/**
+ * @brief CAN1 TX interrupt handler for MB 8-11.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_HANDLER) {
+
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN1 TX interrupt handler for MB 12-15.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN1 TX interrupt handler for MB 16-31.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if (SPC5_FLEXCAN0_MB == 64)
+/**
+ * @brief CAN1 TX interrupt handler for MB 32-63.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_32_63_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*
+ * @brief CAN1 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief CAN1 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN1 ESR_ERR_INT interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN1 ESR_BOFF interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND1);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_CAN_USE_FLEXCAN0 */
+
+#if SPC5_CAN_USE_FLEXCAN1 || defined(__DOXYGEN__)
+/**
+ * @brief CAN2 TX interrupt handler for MB 8-11.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN2 TX interrupt handler for MB 12-15.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN2 TX interrupt handler for MB 16-31.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if (SPC5_FLEXCAN1_MB == 64)
+/**
+ * @brief CAN2 TX interrupt handler for MB 32-63.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_32_63_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*
+ * @brief CAN2 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief CAN2 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN2 ESR_ERR_INT interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN2 ESR_BOFF interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND2);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_CAN_USE_FLEXCAN1 */
+
+#if SPC5_CAN_USE_FLEXCAN2 || defined(__DOXYGEN__)
+/**
+ * @brief CAN3 TX interrupt handler for MB 8-11.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN3 TX interrupt handler for MB 12-15.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN3 TX interrupt handler for MB 16-31.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if (SPC5_FLEXCAN2_MB == 64)
+/**
+ * @brief CAN3 TX interrupt handler for MB 32-63.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_32_63_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*
+ * @brief CAN3 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief CAN3 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN3 ESR_ERR_INT interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN3 ESR_BOFF interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND3);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_CAN_USE_FLEXCAN2 */
+
+#if SPC5_CAN_USE_FLEXCAN3 || defined(__DOXYGEN__)
+/**
+ * @brief CAN4 TX interrupt handler for MB 8-11.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN4 TX interrupt handler for MB 12-15.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN4 TX interrupt handler for MB 16-31.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if (SPC5_FLEXCAN3_MB == 64)
+/**
+ * @brief CAN4 TX interrupt handler for MB 32-63.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_32_63_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*
+ * @brief CAN4 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief CAN4 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN4 ESR_ERR_INT interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN4 ESR_BOFF interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND4);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_CAN_USE_FLEXCAN3 */
+
+#if SPC5_CAN_USE_FLEXCAN4 || defined(__DOXYGEN__)
+/**
+ * @brief CAN5 TX interrupt handler for MB 8-11.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN5 TX interrupt handler for MB 12-15.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN5 TX interrupt handler for MB 16-31.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if (SPC5_FLEXCAN4_MB == 64)
+/**
+ * @brief CAN5 TX interrupt handler for MB 32-63.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_32_63_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*
+ * @brief CAN5 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief CAN5 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN5 ESR_ERR_INT interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN5 ESR_BOFF interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND5);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_CAN_USE_FLEXCAN4 */
+
+#if SPC5_CAN_USE_FLEXCAN5 || defined(__DOXYGEN__)
+/**
+ * @brief CAN6 TX interrupt handler for MB 8-11.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN6 TX interrupt handler for MB 12-15.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN6 TX interrupt handler for MB 16-31.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+
+#if (SPC5_FLEXCAN5_MB == 64)
+/**
+ * @brief CAN6 TX interrupt handler for MB 32-63.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_32_63_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_tx_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*
+ * @brief CAN6 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * @brief CAN6 RX interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_rx_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN6 ESR_ERR_INT interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief CAN6 ESR_BOFF interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_HANDLER) {
+
+ CH_IRQ_PROLOGUE();
+
+ can_lld_err_handler(&CAND6);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* SPC5_CAN_USE_FLEXCAN5 */
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level CAN driver initialization.
+ *
+ * @notapi
+ */
+void can_lld_init(void) {
+
+#if SPC5_CAN_USE_FLEXCAN0
+ /* Driver initialization.*/
+ canObjectInit(&CAND1);
+ CAND1.flexcan = &SPC5_FLEXCAN_0;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_ERR_INT_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_ESR_BOFF_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_00_03_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_04_07_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_08_11_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_12_15_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN0_FLEXCAN_BUF_16_31_NUMBER].R =
+ SPC5_CAN_FLEXCAN0_IRQ_PRIORITY;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN1
+ /* Driver initialization.*/
+ canObjectInit(&CAND2);
+ CAND2.flexcan = &SPC5_FLEXCAN_1;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_ERR_INT_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_ESR_BOFF_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_00_03_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_04_07_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_08_11_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_12_15_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN1_FLEXCAN_BUF_16_31_NUMBER].R =
+ SPC5_CAN_FLEXCAN1_IRQ_PRIORITY;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN2
+ /* Driver initialization.*/
+ canObjectInit(&CAND3);
+ CAND3.flexcan = &SPC5_FLEXCAN_2;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_ERR_INT_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_ESR_BOFF_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_00_03_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_04_07_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_08_11_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_12_15_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN2_FLEXCAN_BUF_16_31_NUMBER].R =
+ SPC5_CAN_FLEXCAN2_IRQ_PRIORITY;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN3
+ /* Driver initialization.*/
+ canObjectInit(&CAND4);
+ CAND4.flexcan = &SPC5_FLEXCAN_3;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_ERR_INT_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_BOFF_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_ESR_WAK_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_00_03_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_04_07_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_08_11_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_12_15_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN3_FLEXCAN_BUF_16_31_NUMBER].R =
+ SPC5_CAN_FLEXCAN3_IRQ_PRIORITY;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN4
+ /* Driver initialization.*/
+ canObjectInit(&CAND5);
+ CAND5.flexcan = &SPC5_FLEXCAN_4;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_ERR_INT_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_ESR_BOFF_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_00_03_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_04_07_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_08_11_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_12_15_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN4_FLEXCAN_BUF_16_31_NUMBER].R =
+ SPC5_CAN_FLEXCAN4_IRQ_PRIORITY;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN5
+ /* Driver initialization.*/
+ canObjectInit(&CAND6);
+ CAND6.flexcan = &SPC5_FLEXCAN_5;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_ERR_INT_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_ESR_BOFF_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_00_03_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_04_07_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_08_11_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_12_15_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+ INTC.PSR[SPC5_FLEXCAN5_FLEXCAN_BUF_16_31_NUMBER].R =
+ SPC5_CAN_FLEXCAN5_IRQ_PRIORITY;
+#endif
+}
+
+/**
+ * @brief Configures and activates the CAN peripheral.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_start(CANDriver *canp) {
+
+ uint8_t mb_index = 0, id = 0;
+
+ /* Clock activation.*/
+#if SPC5_CAN_USE_FLEXCAN0
+ /* Set peripheral clock mode.*/
+ if(&CAND1 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL,
+ SPC5_CAN_FLEXCAN0_START_PCTL);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN1
+ /* Set peripheral clock mode.*/
+ if(&CAND2 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL,
+ SPC5_CAN_FLEXCAN1_START_PCTL);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN2
+ /* Set peripheral clock mode.*/
+ if(&CAND3 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL,
+ SPC5_CAN_FLEXCAN2_START_PCTL);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN3
+ /* Set peripheral clock mode.*/
+ if(&CAND4 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL,
+ SPC5_CAN_FLEXCAN3_START_PCTL);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN4
+ /* Set peripheral clock mode.*/
+ if(&CAND5 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL,
+ SPC5_CAN_FLEXCAN4_START_PCTL);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN5
+ /* Set peripheral clock mode.*/
+ if(&CAND6 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL,
+ SPC5_CAN_FLEXCAN5_START_PCTL);
+#endif
+
+ /* Entering initialization mode. */
+ canp->state = CAN_STARTING;
+ canp->flexcan->CR.R |= CAN_CTRL_CLK_SRC;
+ canp->flexcan->MCR.R &= ~CAN_MCR_MDIS;
+
+ /*
+ * Individual filtering per MB, disable frame self reception,
+ * disable the FIFO, enable SuperVisor mode.
+ */
+#if SPC5_CAN_USE_FLEXCAN0
+ if(&CAND1 == canp)
+ canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN0_MB - 1);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN1
+ if(&CAND2 == canp)
+ canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN1_MB - 1);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN2
+ if(&CAND3 == canp)
+ canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN2_MB - 1);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN3
+ if(&CAND4 == canp)
+ canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN3_MB - 1);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN4
+ if(&CAND5 == canp)
+ canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN4_MB - 1);
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN5
+ if(&CAND6 == canp)
+ canp->flexcan->MCR.R |= CAN_MCR_SUPV | CAN_MCR_MAXMB(SPC5_FLEXCAN5_MB - 1);
+#endif
+
+ canp->flexcan->CR.R |= CAN_CTRL_TSYN | CAN_CTRL_RJW(3);
+
+ /* TX MB initialization.*/
+#if SPC5_CAN_USE_FLEXCAN0
+ if(&CAND1 == canp) {
+ for(mb_index = 0; mb_index < (SPC5_FLEXCAN0_MB - CAN_RX_MAILBOXES);
+ mb_index++) {
+ canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN1
+ if(&CAND2 == canp) {
+ for(mb_index = 0; mb_index < (SPC5_FLEXCAN1_MB - CAN_RX_MAILBOXES);
+ mb_index++) {
+ canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN2
+ if(&CAND3 == canp) {
+ for(mb_index = 0; mb_index < (SPC5_FLEXCAN2_MB - CAN_RX_MAILBOXES);
+ mb_index++) {
+ canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN3
+ if(&CAND4 == canp) {
+ for(mb_index = 0; mb_index < (SPC5_FLEXCAN3_MB - CAN_RX_MAILBOXES);
+ mb_index++) {
+ canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN4
+ if(&CAND5 == canp) {
+ for(mb_index = 0; mb_index < (SPC5_FLEXCAN4_MB - CAN_RX_MAILBOXES);
+ mb_index++) {
+ canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN5
+ if(&CAND6 == canp) {
+ for(mb_index = 0; mb_index < (SPC5_FLEXCAN5_MB - CAN_RX_MAILBOXES);
+ mb_index++) {
+ canp->flexcan->BUF[mb_index + CAN_RX_MAILBOXES].CS.B.CODE = 8U;
+ }
+ }
+#endif
+
+ /* Unlock Message buffers.*/
+ (void) canp->flexcan->TIMER.R;
+
+ /* MCR initialization.*/
+ canp->flexcan->MCR.R |= canp->config->mcr;
+
+ /* CTRL initialization.*/
+ canp->flexcan->CR.R |= canp->config->ctrl;
+
+ /* Interrupt sources initialization.*/
+ canp->flexcan->MCR.R |= CAN_MCR_WRN_EN;
+
+ canp->flexcan->CR.R |= CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK |
+ CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK;
+
+#if !SPC5_CAN_USE_FILTERS
+ /* RX MB initialization.*/
+ for(mb_index = 0; mb_index < CAN_RX_MAILBOXES; mb_index++) {
+ canp->flexcan->BUF[mb_index].CS.B.CODE = 0U;
+ canp->flexcan->BUF[mb_index].ID.R = 0U;
+ canp->flexcan->BUF[mb_index].CS.B.CODE = 4U;
+ }
+
+ /* Receive all.*/
+ canp->flexcan->RXGMASK.R = 0x00000000;
+#else
+ for (id = 0; id < CAN_RX_MAILBOXES; id++) {
+ canp->flexcan->BUF[id].CS.B.CODE = 0U;
+ if (canp->config->RxFilter[id].scale) {
+ canp->flexcan->BUF[id].CS.B.IDE = 1U;
+ canp->flexcan->BUF[id].ID.R = canp->config->RxFilter[id].register1;
+ }
+ else {
+ canp->flexcan->BUF[id].CS.B.IDE = 0U;
+ canp->flexcan->BUF[id].ID.B.STD_ID = canp->config->RxFilter[id].register1;
+ canp->flexcan->BUF[id].ID.B.EXT_ID = 0U;
+ }
+ /* RX MB initialization.*/
+ canp->flexcan->BUF[id].CS.B.CODE = 4U;
+ }
+ canp->flexcan->RXGMASK.R = 0x0FFFFFFF;
+#endif
+
+ /* Enable MBs interrupts.*/
+#if SPC5_CAN_USE_FLEXCAN0
+ if(&CAND1 == canp) {
+ if(SPC5_FLEXCAN0_MB == 32) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ }
+ else if(SPC5_FLEXCAN0_MB == 64) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ canp->flexcan->IMRH.R = 0xFFFFFFFF;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN1
+ if(&CAND2 == canp) {
+ if(SPC5_FLEXCAN1_MB == 32) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ }
+ else if(SPC5_FLEXCAN1_MB == 64) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ canp->flexcan->IMRH.R = 0xFFFFFFFF;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN2
+ if(&CAND3 == canp) {
+ if(SPC5_FLEXCAN2_MB == 32) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ }
+ else if(SPC5_FLEXCAN2_MB == 64) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ canp->flexcan->IMRH.R = 0xFFFFFFFF;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN3
+ if(&CAND4 == canp) {
+ if(SPC5_FLEXCAN3_MB == 32) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ }
+ else if(SPC5_FLEXCAN3_MB == 64) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ canp->flexcan->IMRH.R = 0xFFFFFFFF;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN4
+ if(&CAND5 == canp) {
+ if(SPC5_FLEXCAN4_MB == 32) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ }
+ else if(SPC5_FLEXCAN4_MB == 64) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ canp->flexcan->IMRH.R = 0xFFFFFFFF;
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN5
+ if(&CAND6 == canp) {
+ if(SPC5_FLEXCAN5_MB == 32) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ }
+ else if(SPC5_FLEXCAN5_MB == 64) {
+ canp->flexcan->IMRL.R = 0xFFFFFFFF;
+ canp->flexcan->IMRH.R = 0xFFFFFFFF;
+ }
+ }
+#endif
+
+ /* CAN BUS synchronization.*/
+ canp->flexcan->MCR.B.HALT = 0;
+}
+
+/**
+ * @brief Deactivates the CAN peripheral.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_stop(CANDriver *canp) {
+
+ /* If in ready state then disables the CAN peripheral.*/
+ if (canp->state == CAN_READY) {
+
+ /* Disable Interrupt sources.*/
+ canp->flexcan->MCR.R &= ~CAN_MCR_WRN_EN;
+ canp->flexcan->CR.R &= ~(CAN_CTRL_BOFF_MSK | CAN_CTRL_ERR_MSK |
+ CAN_CTRL_TWRN_MSK | CAN_CTRL_RWRN_MSK);
+ canp->flexcan->IMRL.R = 0x00000000;
+
+ canp->flexcan->MCR.R &= ~CAN_MCR_MDIS;
+
+#if SPC5_CAN_USE_FLEXCAN0
+ /* Set peripheral clock mode.*/
+ if(&CAND1 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN0_PCTL,
+ SPC5_CAN_FLEXCAN0_STOP_PCTL);
+#endif
+#if SPC5_CAN_USE_FLEXCAN1
+ /* Set peripheral clock mode.*/
+ if(&CAND2 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN1_PCTL,
+ SPC5_CAN_FLEXCAN1_STOP_PCTL);
+#endif
+#if SPC5_CAN_USE_FLEXCAN2
+ /* Set peripheral clock mode.*/
+ if(&CAND3 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN2_PCTL,
+ SPC5_CAN_FLEXCAN2_STOP_PCTL);
+#endif
+#if SPC5_CAN_USE_FLEXCAN3
+ /* Set peripheral clock mode.*/
+ if(&CAND4 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN3_PCTL,
+ SPC5_CAN_FLEXCAN3_STOP_PCTL);
+#endif
+#if SPC5_CAN_USE_FLEXCAN4
+ /* Set peripheral clock mode.*/
+ if(&CAND5 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN4_PCTL,
+ SPC5_CAN_FLEXCAN4_STOP_PCTL);
+#endif
+#if SPC5_CAN_USE_FLEXCAN5
+ /* Set peripheral clock mode.*/
+ if(&CAND6 == canp)
+ halSPCSetPeripheralClockMode(SPC5_FLEXCAN5_PCTL,
+ SPC5_CAN_FLEXCAN5_STOP_PCTL);
+#endif
+ }
+}
+
+/**
+ * @brief Determines whether a frame can be transmitted.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @return The queue space availability.
+ * @retval FALSE no space in the transmit queue.
+ * @retval TRUE transmit slot available.
+ *
+ * @notapi
+ */
+bool_t can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
+
+ uint8_t mbid = 0;
+
+ if(mailbox == CAN_ANY_MAILBOX) {
+#if SPC5_CAN_USE_FLEXCAN0
+ if(&CAND1 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) {
+ if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
+ return TRUE;
+ }
+ }
+ return FALSE;
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN1
+ if(&CAND2 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) {
+ if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
+ return TRUE;
+ }
+ }
+ return FALSE;
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN2
+ if(&CAND3 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) {
+ if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
+ return TRUE;
+ }
+ }
+ return FALSE;
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN3
+ if(&CAND4 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) {
+ if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
+ return TRUE;
+ }
+ }
+ return FALSE;
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN4
+ if(&CAND5 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) {
+ if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
+ return TRUE;
+ }
+ }
+ return FALSE;
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN5
+ if(&CAND6 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) {
+ if (canp->flexcan->BUF[mbid].CS.B.CODE == 0x08) {
+ return TRUE;
+ }
+ }
+ return FALSE;
+ }
+#endif
+ }
+ else {
+ return canp->flexcan->BUF[mailbox + 7].CS.B.CODE == 0x08;
+ }
+ return FALSE;
+}
+
+/**
+ * @brief Inserts a frame into the transmit queue.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] ctfp pointer to the CAN frame to be transmitted
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @notapi
+ */
+void can_lld_transmit(CANDriver *canp,
+ canmbx_t mailbox,
+ const CANTxFrame *ctfp) {
+
+ CAN_TxMailBox_TypeDef *tmbp = NULL;
+ uint8_t mbid = 0;
+
+ /* Pointer to a free transmission mailbox.*/
+ if (mailbox == CAN_ANY_MAILBOX) {
+#if SPC5_CAN_USE_FLEXCAN0
+ if(&CAND1 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN0_MB; mbid++) {
+ if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
+ break;
+ }
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN1
+ if(&CAND2 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN1_MB; mbid++) {
+ if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
+ break;
+ }
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN2
+ if(&CAND3 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN2_MB; mbid++) {
+ if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
+ break;
+ }
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN3
+ if(&CAND4 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN3_MB; mbid++) {
+ if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
+ break;
+ }
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN4
+ if(&CAND5 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN4_MB; mbid++) {
+ if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
+ break;
+ }
+ }
+ }
+#endif
+#if SPC5_CAN_USE_FLEXCAN5
+ if(&CAND6 == canp) {
+ for (mbid = 8; mbid < SPC5_FLEXCAN5_MB; mbid++) {
+ if ((canp->flexcan->BUF[mbid].CS.B.CODE & 8U) == 1) {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mbid];
+ break;
+ }
+ }
+ }
+#endif
+ }
+ else {
+ tmbp = (CAN_TxMailBox_TypeDef *)&canp->flexcan->BUF[mailbox + 7];
+ }
+
+ /* Preparing the message.*/
+ if (ctfp->IDE) {
+ tmbp->CS.B.IDE = 1U;
+ tmbp->CS.B.RTR = 0U;
+ tmbp->ID.R = ctfp->EID;
+ }
+ else {
+ tmbp->CS.B.IDE = 0U;
+ tmbp->CS.B.RTR = 0U;
+ tmbp->ID.R = ctfp->SID << 18;
+ }
+ tmbp->CS.B.LENGTH = ctfp->LENGTH;
+ tmbp->DATA[0] = ctfp->data32[0];
+ tmbp->DATA[1] = ctfp->data32[1];
+ tmbp->CS.B.CODE = 0x0C;
+}
+
+/**
+ *
+ * @brief Determines whether a frame has been received.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @return The queue space availability.
+ * @retval FALSE no space in the transmit queue.
+ * @retval TRUE transmit slot available.
+ *
+ * @notapi
+ */
+
+bool_t can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
+
+ uint8_t mbid = 0;
+ bool_t mb_status = FALSE;
+
+ switch (mailbox) {
+ case CAN_ANY_MAILBOX:
+ for (mbid = 0; mbid < CAN_RX_MAILBOXES; mbid++) {
+ if(canp->flexcan->BUF[mbid].CS.B.CODE == 2U) {
+ mb_status = TRUE;
+ }
+ }
+ return mb_status;
+ case 1:
+ return (canp->flexcan->BUF[0].CS.B.CODE == 2U);
+ case 2:
+ return (canp->flexcan->BUF[1].CS.B.CODE == 2U);
+ case 3:
+ return (canp->flexcan->BUF[2].CS.B.CODE == 2U);
+ case 4:
+ return (canp->flexcan->BUF[3].CS.B.CODE == 2U);
+ case 5:
+ return (canp->flexcan->BUF[4].CS.B.CODE == 2U);
+ case 6:
+ return (canp->flexcan->BUF[5].CS.B.CODE == 2U);
+ case 7:
+ return (canp->flexcan->BUF[6].CS.B.CODE == 2U);
+ case 8:
+ return (canp->flexcan->BUF[7].CS.B.CODE == 2U);
+ default:
+ return FALSE;
+ }
+}
+
+/**
+ * @brief Receives a frame from the input queue.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[out] crfp pointer to the buffer where the CAN frame is copied
+ *
+ * @notapi
+ */
+void can_lld_receive(CANDriver *canp,
+ canmbx_t mailbox,
+ CANRxFrame *crfp) {
+
+ uint32_t mbid = 0, index = 0;
+
+ if(mailbox != CAN_ANY_MAILBOX) {
+ mbid = mailbox;
+ }
+ else {
+ for (index = 0; index < CAN_RX_MAILBOXES; index++) {
+ if(canp->flexcan->BUF[index].CS.B.CODE == 2U) {
+ mbid = index;
+ break;
+ }
+ }
+ }
+
+ /* Lock the RX MB.*/
+ (void) canp->flexcan->BUF[mbid].CS.B.CODE;
+
+ /* Fetches the message.*/
+ crfp->data32[0] = canp->flexcan->BUF[mbid].DATA.W[0];
+ crfp->data32[1] = canp->flexcan->BUF[mbid].DATA.W[1];
+
+ /* Decodes the various fields in the RX frame.*/
+ crfp->RTR = canp->flexcan->BUF[mbid].CS.B.RTR;
+ crfp->IDE = canp->flexcan->BUF[mbid].CS.B.IDE;
+ if (crfp->IDE)
+ crfp->EID = canp->flexcan->BUF[mbid].ID.B.EXT_ID;
+ else
+ crfp->SID = canp->flexcan->BUF[mbid].ID.B.STD_ID;
+ crfp->LENGTH = canp->flexcan->BUF[mbid].CS.B.LENGTH;
+ crfp->TIME = canp->flexcan->BUF[mbid].CS.B.TIMESTAMP;
+
+ /* Unlock the RX MB.*/
+ (void) canp->flexcan->TIMER.R;
+
+ /* Reconfigure the RX MB in empty status.*/
+ canp->flexcan->BUF[mbid].CS.B.CODE = 4U;
+}
+
+#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
+/**
+ * @brief Enters the sleep mode.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_sleep(CANDriver *canp) {
+
+ /*canp->can->MCR |= CAN_MCR_SLEEP;*/
+}
+
+/**
+ * @brief Enforces leaving the sleep mode.
+ *
+ * @param[in] canp pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_wakeup(CANDriver *canp) {
+
+ /*canp->can->MCR &= ~CAN_MCR_SLEEP;*/
+}
+#endif /* CAN_USE_SLEEP_MODE */
+
+#endif /* HAL_USE_CAN */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h new file mode 100644 index 000000000..ad67c97da --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/can_lld.h @@ -0,0 +1,520 @@ +/*
+ SPC5 HAL - Copyright (C) 2013 STMicroelectronics
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file FlexCAN_v1/can_lld.h
+ * @brief SPC5xx CAN subsystem low level driver header.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#ifndef _CAN_LLD_H_
+#define _CAN_LLD_H_
+
+#if HAL_USE_CAN || defined(__DOXYGEN__)
+
+#include "spc5_flexcan.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief This switch defines whether the driver implementation supports
+ * a low power switch mode with an automatic wakeup feature.
+ */
+#define CAN_SUPPORTS_SLEEP FALSE
+
+/**
+ * @brief This implementation supports 24 transmit mailboxes.
+ */
+#define CAN_TX_MAILBOXES 24
+
+/**
+ * @brief This implementation supports one FIFO receive mailbox.
+ */
+#define CAN_RX_MAILBOXES 8
+
+/**
+ * @brief This implementation supports eight FIFO receive filters.
+ */
+#define SPC5_CAN_MAX_FILTERS 8
+
+/**
+ * @brief Enable filters.
+ */
+#define SPC5_CAN_FILTER_ON 1
+
+/**
+ * @brief Disable filters.
+ */
+#define SPC5_CAN_FILTER_OFF 0
+/**
+ * @name CAN registers helper macros
+ * @{
+ */
+#define CAN_MCR_MAXMB(n) (n)
+#define CAN_MCR_AEN (1 << 12)
+#define CAN_MCR_LPRIO_EN (1 << 13)
+#define CAN_MCR_BCC (1 << 16)
+#define CAN_MCR_SRX_DIS (1 << 17)
+#define CAN_MCR_LPM_ACK (1 << 20)
+#define CAN_MCR_WRN_EN (1 << 21)
+#define CAN_MCR_SUPV (1 << 23)
+#define CAN_MCR_FRZ_ACK (1 << 24)
+#define CAN_MCR_WAK_MSK (1 << 26)
+#define CAN_MCR_NOT_RDY (1 << 27)
+#define CAN_MCR_HALT (1 << 28)
+#define CAN_MCR_FEN (1 << 29)
+#define CAN_MCR_FRZ (1 << 30)
+#define CAN_MCR_MDIS (1 << 31)
+
+#define CAN_CTRL_PROPSEG(n) (n)
+#define CAN_CTRL_LOM (1 << 3)
+#define CAN_CTRL_TSYN (1 << 5)
+#define CAN_CTRL_BOFF_REC (1 << 6)
+#define CAN_CTRL_SMP (1 << 7)
+#define CAN_CTRL_RWRN_MSK (1 << 10)
+#define CAN_CTRL_TWRN_MSK (1 << 11)
+#define CAN_CTRL_LPB (1 << 12)
+#define CAN_CTRL_CLK_SRC (1 << 13)
+#define CAN_CTRL_ERR_MSK (1 << 14)
+#define CAN_CTRL_BOFF_MSK (1 << 15)
+#define CAN_CTRL_PSEG2(n) ((n) << 16)
+#define CAN_CTRL_PSEG1(n) ((n) << 19)
+#define CAN_CTRL_RJW(n) ((n) << 22)
+#define CAN_CTRL_PRESDIV(n) ((n) << 24)
+
+#define CAN_IDE_STD 0 /**< @brief Standard id. */
+#define CAN_IDE_EXT 1 /**< @brief Extended id. */
+
+#define CAN_RTR_DATA 0 /**< @brief Data frame. */
+#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */
+
+#define CAN_ESR_ERR_INT (1 << 1)
+#define CAN_ESR_BOFF_INT (1 << 2)
+#define CAN_ESR_TWRN_INT (1 << 14)
+#define CAN_ESR_RWRN_INT (1 << 15)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief CAN1 driver enable switch.
+ * @details If set to @p TRUE the support for CAN1 is included.
+ */
+#if !defined(SPC5_CAN_USE_FLEXCAN0) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FLEXCAN0 FALSE
+#endif
+
+/**
+ * @brief CAN2 driver enable switch.
+ * @details If set to @p TRUE the support for CAN2 is included.
+ */
+#if !defined(SPC5_CAN_USE_FLEXCAN1) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FLEXCAN1 FALSE
+#endif
+
+/**
+ * @brief CAN3 driver enable switch.
+ * @details If set to @p TRUE the support for CAN3 is included.
+ */
+#if !defined(SPC5_CAN_USE_FLEXCAN2) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FLEXCAN2 FALSE
+#endif
+
+/**
+ * @brief CAN4 driver enable switch.
+ * @details If set to @p TRUE the support for CAN4 is included.
+ */
+#if !defined(SPC5_CAN_USE_FLEXCAN3) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FLEXCAN3 FALSE
+#endif
+
+/**
+ * @brief CAN5 driver enable switch.
+ * @details If set to @p TRUE the support for CAN5 is included.
+ */
+#if !defined(SPC5_CAN_USE_FLEXCAN4) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FLEXCAN4 FALSE
+#endif
+
+/**
+ * @brief CAN6 driver enable switch.
+ * @details If set to @p TRUE the support for CAN6 is included.
+ */
+#if !defined(SPC5_CAN_USE_FLEXCAN5) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FLEXCAN5 FALSE
+#endif
+
+/**
+ * @brief CAN1 interrupt priority level setting.
+ */
+#if !defined(SPC5_CAN_FLEXCAN0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY 11
+#endif
+/** @} */
+
+/**
+ * @brief CAN2 interrupt priority level setting.
+ */
+#if !defined(SPC5_CAN_FLEXCAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY 11
+#endif
+/** @} */
+
+/**
+ * @brief CAN3 interrupt priority level setting.
+ */
+#if !defined(SPC5_CAN_FLEXCAN2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_CAN_FLEXCAN2_IRQ_PRIORITY 11
+#endif
+/** @} */
+
+/**
+ * @brief CAN4 interrupt priority level setting.
+ */
+#if !defined(SPC5_CAN_FLEXCAN3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_CAN_FLEXCAN3_IRQ_PRIORITY 11
+#endif
+/** @} */
+
+/**
+ * @brief CAN5 interrupt priority level setting.
+ */
+#if !defined(SPC5_CAN_FLEXCAN4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_CAN_FLEXCAN4_IRQ_PRIORITY 11
+#endif
+/** @} */
+
+/**
+ * @brief CAN6 interrupt priority level setting.
+ */
+#if !defined(SPC5_CAN_FLEXCAN5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_CAN_FLEXCAN5_IRQ_PRIORITY 11
+#endif
+/** @} */
+
+/**
+ * @brief CAN filters enable setting.
+ */
+#if !defined(SPC5_CAN_USE_FILTERS) || defined(__DOXYGEN__)
+#define SPC5_CAN_USE_FILTERS FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if SPC5_CAN_USE_FLEXCAN0 && !SPC5_HAS_FLEXCAN0
+#error "CAN1 not present in the selected device"
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN1 && !SPC5_HAS_FLEXCAN1
+#error "CAN2 not present in the selected device"
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN2 && !SPC5_HAS_FLEXCAN2
+#error "CAN3 not present in the selected device"
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN3 && !SPC5_HAS_FLEXCAN3
+#error "CAN4 not present in the selected device"
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN4 && !SPC5_HAS_FLEXCAN4
+#error "CAN5 not present in the selected device"
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN5 && !SPC5_HAS_FLEXCAN5
+#error "CAN6 not present in the selected device"
+#endif
+
+#if !SPC5_CAN_USE_FLEXCAN0 && !SPC5_CAN_USE_FLEXCAN1 \
+ && !SPC5_CAN_USE_FLEXCAN2 && !SPC5_CAN_USE_FLEXCAN3 \
+ && !SPC5_CAN_USE_FLEXCAN4 && !SPC5_CAN_USE_FLEXCAN5
+#error "CAN driver activated but no CAN peripheral assigned"
+#endif
+
+#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
+#error "CAN sleep mode not supported in this architecture"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of a transmission mailbox index.
+ */
+typedef uint32_t canmbx_t;
+
+/**
+ * @brief CAN TX MB structure.
+ */
+typedef struct {
+ union {
+ vuint32_t R;
+ struct {
+ vuint8_t:4;
+ vuint8_t CODE:4;
+ vuint8_t:1;
+ vuint8_t SRR:1;
+ vuint8_t IDE:1;
+ vuint8_t RTR:1;
+ vuint8_t LENGTH:4;
+ vuint16_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint8_t PRIO:3;
+ vuint32_t ID:29;
+ } B;
+ } ID;
+ vuint32_t DATA[2]; /* Data buffer in words (32 bits) */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief CAN transmission frame.
+ * @note Accessing the frame data as word16 or word32 is not portable because
+ * machine data endianness, it can be still useful for a quick filling.
+ */
+typedef struct {
+ struct {
+ uint8_t LENGTH:4; /**< @brief Data length. */
+ uint8_t RTR:1; /**< @brief Frame type. */
+ uint8_t IDE:1; /**< @brief Identifier type. */
+ };
+ union {
+ struct {
+ uint32_t SID:11; /**< @brief Standard identifier.*/
+ };
+ struct {
+ uint32_t EID:29; /**< @brief Extended identifier.*/
+ };
+ };
+ union {
+ uint8_t data8[8]; /**< @brief Frame data. */
+ uint16_t data16[4]; /**< @brief Frame data. */
+ uint32_t data32[2]; /**< @brief Frame data. */
+ };
+} CANTxFrame;
+
+/**
+ * @brief CAN received frame.
+ * @note Accessing the frame data as word16 or word32 is not portable because
+ * machine data endianness, it can be still useful for a quick filling.
+ */
+typedef struct {
+ struct {
+ uint16_t TIME; /**< @brief Time stamp. */
+ };
+ struct {
+ uint8_t LENGTH:4; /**< @brief Data length. */
+ uint8_t RTR:1; /**< @brief Frame type. */
+ uint8_t IDE:1; /**< @brief Identifier type. */
+ };
+ union {
+ struct {
+ uint32_t SID:11; /**< @brief Standard identifier.*/
+ };
+ struct {
+ uint32_t EID:29; /**< @brief Extended identifier.*/
+ };
+ };
+ union {
+ uint8_t data8[8]; /**< @brief Frame data. */
+ uint16_t data16[4]; /**< @brief Frame data. */
+ uint32_t data32[2]; /**< @brief Frame data. */
+ };
+} CANRxFrame;
+
+/**
+ * @brief CAN filter.
+ * @note Refer to the SPC5 reference manual for info about filters.
+ */
+typedef struct {
+ /**
+ * @brief Filter scale.
+ * @note This bit represents the EXT bit associated to this
+ * filter (0=standard ID mode, 1=extended ID mode).
+ */
+ uint32_t scale:1;
+ /**
+ * @brief Filter register (identifier).
+ */
+ uint32_t register1;
+} CANFilter;
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief CAN MCR register initialization data.
+ * @note Some bits in this register are enforced by the driver regardless
+ * their status in this field.
+ */
+ uint32_t mcr;
+ /**
+ * @brief CAN CTRL register initialization data.
+ * @note Some bits in this register are enforced by the driver regardless
+ * their status in this field.
+ */
+ uint32_t ctrl;
+#if SPC5_CAN_USE_FILTERS
+ /**
+ * @brief CAN filters structure.
+ */
+ CANFilter RxFilter[CAN_RX_MAILBOXES];
+#endif
+} CANConfig;
+
+/**
+ * @brief Structure representing an CAN driver.
+ */
+typedef struct {
+ /**
+ * @brief Driver state.
+ */
+ canstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const CANConfig *config;
+ /**
+ * @brief Transmission queue semaphore.
+ */
+ Semaphore txsem;
+ /**
+ * @brief Receive queue semaphore.
+ */
+ Semaphore rxsem;
+ /**
+ * @brief One or more frames become available.
+ * @note After broadcasting this event it will not be broadcasted again
+ * until the received frames queue has been completely emptied. It
+ * is <b>not</b> broadcasted for each received frame. It is
+ * responsibility of the application to empty the queue by
+ * repeatedly invoking @p chReceive() when listening to this event.
+ * This behavior minimizes the interrupt served by the system
+ * because CAN traffic.
+ * @note The flags associated to the listeners will indicate which
+ * receive mailboxes become non-empty.
+ */
+ EventSource rxfull_event;
+ /**
+ * @brief One or more transmission mailbox become available.
+ * @note The flags associated to the listeners will indicate which
+ * transmit mailboxes become empty.
+ *
+ */
+ EventSource txempty_event;
+ /**
+ * @brief A CAN bus error happened.
+ * @note The flags associated to the listeners will indicate the
+ * error(s) that have occurred.
+ */
+ EventSource error_event;
+#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
+ /**
+ * @brief Entering sleep state event.
+ */
+ EventSource sleep_event;
+ /**
+ * @brief Exiting sleep state event.
+ */
+ EventSource wakeup_event;
+#endif /* CAN_USE_SLEEP_MODE */
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the CAN registers.
+ */
+ volatile struct spc5_flexcan *flexcan;
+} CANDriver;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if SPC5_CAN_USE_FLEXCAN0 && !defined(__DOXYGEN__)
+extern CANDriver CAND1;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN1 && !defined(__DOXYGEN__)
+extern CANDriver CAND2;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN2 && !defined(__DOXYGEN__)
+extern CANDriver CAND3;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN3 && !defined(__DOXYGEN__)
+extern CANDriver CAND4;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN4 && !defined(__DOXYGEN__)
+extern CANDriver CAND5;
+#endif
+
+#if SPC5_CAN_USE_FLEXCAN5 && !defined(__DOXYGEN__)
+extern CANDriver CAND6;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void can_lld_init(void);
+ void can_lld_start(CANDriver *canp);
+ void can_lld_stop(CANDriver *canp);
+ bool_t can_lld_is_tx_empty(CANDriver *canp,
+ canmbx_t mailbox);
+ void can_lld_transmit(CANDriver *canp,
+ canmbx_t mailbox,
+ const CANTxFrame *crfp);
+ bool_t can_lld_is_rx_nonempty(CANDriver *canp,
+ canmbx_t mailbox);
+ void can_lld_receive(CANDriver *canp,
+ canmbx_t mailbox,
+ CANRxFrame *ctfp);
+#if CAN_USE_SLEEP_MODE
+ void can_lld_sleep(CANDriver *canp);
+ void can_lld_wakeup(CANDriver *canp);
+#endif /* CAN_USE_SLEEP_MODE */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_CAN */
+
+#endif /* _CAN_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h new file mode 100644 index 000000000..580f78827 --- /dev/null +++ b/os/hal/platforms/SPC5xx/FlexCAN_v1/spc5_flexcan.h @@ -0,0 +1,442 @@ +/*
+ * Licensed under ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file FlexCAN_v1/spc5_flexcan.h
+ * @brief SPC5xx FlexCAN header file.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef _SPC5_FLEXCAN_H_
+#define _SPC5_FLEXCAN_H_
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief SPC5 FlexCAN registers block.
+ * @note Redefined from the SPC5 headers because the non uniform
+ * declaration of the SubModules registers among the various
+ * sub-families.
+ */
+struct FLEXCAN_BUFFER_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:4;
+ vuint32_t CODE:4;
+ vuint32_t:1;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRIO:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+}; /* end of FLEXCAN_BUF_t */
+
+struct FLEXCAN_RXFIFO_BUFFER_t {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:9;
+ vuint32_t SRR:1;
+ vuint32_t IDE:1;
+ vuint32_t RTR:1;
+ vuint32_t LENGTH:4;
+ vuint32_t TIMESTAMP:16;
+ } B;
+ } CS;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:3;
+ vuint32_t STD_ID:11;
+ vuint32_t EXT_ID:18;
+ } B;
+ } ID;
+
+ union {
+ /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) */
+ /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) */
+ vuint32_t W[2]; /* Data buffer in words (32 bits) */
+ /*vuint32_t R[2]; *//* Data buffer in words (32 bits) */
+ } DATA;
+
+ uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */
+
+ union {
+ vuint32_t R;
+ } IDTABLE[8];
+
+}; /* end of FLEXCAN_RXFIFO_t */
+
+struct spc5_flexcan {
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MDIS:1;
+ vuint32_t FRZ:1;
+ vuint32_t FEN:1;
+ vuint32_t HALT:1;
+ vuint32_t NOTRDY:1;
+ vuint32_t WAKMSK:1;
+ vuint32_t SOFTRST:1;
+ vuint32_t FRZACK:1;
+ vuint32_t SUPV:1;
+ vuint32_t SLFWAK:1;
+ vuint32_t WRNEN:1;
+ vuint32_t LPMACK:1;
+ vuint32_t WAKSRC:1;
+ vuint32_t:1;
+ vuint32_t SRXDIS:1;
+ vuint32_t BCC:1;
+ vuint32_t:2;
+ vuint32_t LPRIO_EN:1;
+ vuint32_t AEN:1;
+ vuint32_t:2;
+ vuint32_t IDAM:2;
+ vuint32_t:2;
+ vuint32_t MAXMB:6;
+ } B;
+ } MCR; /* Module Configuration Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t PRESDIV:8;
+ vuint32_t RJW:2;
+ vuint32_t PSEG1:3;
+ vuint32_t PSEG2:3;
+ vuint32_t BOFFMSK:1;
+ vuint32_t ERRMSK:1;
+ vuint32_t CLKSRC:1;
+ vuint32_t LPB:1;
+ vuint32_t TWRNMSK:1;
+ vuint32_t RWRNMSK:1;
+ vuint32_t:2;
+ vuint32_t SMP:1;
+ vuint32_t BOFFREC:1;
+ vuint32_t TSYN:1;
+ vuint32_t LBUF:1;
+ vuint32_t LOM:1;
+ vuint32_t PROPSEG:3;
+ } B;
+ } CR; /* Control Register */
+
+ union {
+ vuint32_t R;
+ } TIMER; /* Free Running Timer */
+
+ uint32_t FLEXCAN_reserved1;
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXGMASK; /* RX Global Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX14MASK; /* RX 14 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RX15MASK; /* RX 15 Mask */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:16;
+ vuint32_t RXECNT:8;
+ vuint32_t TXECNT:8;
+ } B;
+ } ECR; /* Error Counter Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t:14;
+ vuint32_t TWRNINT:1;
+ vuint32_t RWRNINT:1;
+ vuint32_t BIT1ERR:1;
+ vuint32_t BIT0ERR:1;
+ vuint32_t ACKERR:1;
+ vuint32_t CRCERR:1;
+ vuint32_t FRMERR:1;
+ vuint32_t STFERR:1;
+ vuint32_t TXWRN:1;
+ vuint32_t RXWRN:1;
+ vuint32_t IDLE:1;
+ vuint32_t TXRX:1;
+ vuint32_t FLTCONF:2;
+ vuint32_t:1;
+ vuint32_t BOFFINT:1;
+ vuint32_t ERRINT:1;
+ vuint32_t WAKINT:1;
+ } B;
+ } ESR; /* Error and Status Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63M:1;
+ vuint32_t BUF62M:1;
+ vuint32_t BUF61M:1;
+ vuint32_t BUF60M:1;
+ vuint32_t BUF59M:1;
+ vuint32_t BUF58M:1;
+ vuint32_t BUF57M:1;
+ vuint32_t BUF56M:1;
+ vuint32_t BUF55M:1;
+ vuint32_t BUF54M:1;
+ vuint32_t BUF53M:1;
+ vuint32_t BUF52M:1;
+ vuint32_t BUF51M:1;
+ vuint32_t BUF50M:1;
+ vuint32_t BUF49M:1;
+ vuint32_t BUF48M:1;
+ vuint32_t BUF47M:1;
+ vuint32_t BUF46M:1;
+ vuint32_t BUF45M:1;
+ vuint32_t BUF44M:1;
+ vuint32_t BUF43M:1;
+ vuint32_t BUF42M:1;
+ vuint32_t BUF41M:1;
+ vuint32_t BUF40M:1;
+ vuint32_t BUF39M:1;
+ vuint32_t BUF38M:1;
+ vuint32_t BUF37M:1;
+ vuint32_t BUF36M:1;
+ vuint32_t BUF35M:1;
+ vuint32_t BUF34M:1;
+ vuint32_t BUF33M:1;
+ vuint32_t BUF32M:1;
+ } B;
+ } IMRH; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31M:1;
+ vuint32_t BUF30M:1;
+ vuint32_t BUF29M:1;
+ vuint32_t BUF28M:1;
+ vuint32_t BUF27M:1;
+ vuint32_t BUF26M:1;
+ vuint32_t BUF25M:1;
+ vuint32_t BUF24M:1;
+ vuint32_t BUF23M:1;
+ vuint32_t BUF22M:1;
+ vuint32_t BUF21M:1;
+ vuint32_t BUF20M:1;
+ vuint32_t BUF19M:1;
+ vuint32_t BUF18M:1;
+ vuint32_t BUF17M:1;
+ vuint32_t BUF16M:1;
+ vuint32_t BUF15M:1;
+ vuint32_t BUF14M:1;
+ vuint32_t BUF13M:1;
+ vuint32_t BUF12M:1;
+ vuint32_t BUF11M:1;
+ vuint32_t BUF10M:1;
+ vuint32_t BUF09M:1;
+ vuint32_t BUF08M:1;
+ vuint32_t BUF07M:1;
+ vuint32_t BUF06M:1;
+ vuint32_t BUF05M:1;
+ vuint32_t BUF04M:1;
+ vuint32_t BUF03M:1;
+ vuint32_t BUF02M:1;
+ vuint32_t BUF01M:1;
+ vuint32_t BUF00M:1;
+ } B;
+ } IMRL; /* Interruput Masks Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF63I:1;
+ vuint32_t BUF62I:1;
+ vuint32_t BUF61I:1;
+ vuint32_t BUF60I:1;
+ vuint32_t BUF59I:1;
+ vuint32_t BUF58I:1;
+ vuint32_t BUF57I:1;
+ vuint32_t BUF56I:1;
+ vuint32_t BUF55I:1;
+ vuint32_t BUF54I:1;
+ vuint32_t BUF53I:1;
+ vuint32_t BUF52I:1;
+ vuint32_t BUF51I:1;
+ vuint32_t BUF50I:1;
+ vuint32_t BUF49I:1;
+ vuint32_t BUF48I:1;
+ vuint32_t BUF47I:1;
+ vuint32_t BUF46I:1;
+ vuint32_t BUF45I:1;
+ vuint32_t BUF44I:1;
+ vuint32_t BUF43I:1;
+ vuint32_t BUF42I:1;
+ vuint32_t BUF41I:1;
+ vuint32_t BUF40I:1;
+ vuint32_t BUF39I:1;
+ vuint32_t BUF38I:1;
+ vuint32_t BUF37I:1;
+ vuint32_t BUF36I:1;
+ vuint32_t BUF35I:1;
+ vuint32_t BUF34I:1;
+ vuint32_t BUF33I:1;
+ vuint32_t BUF32I:1;
+ } B;
+ } IFRH; /* Interruput Flag Register */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t BUF31I:1;
+ vuint32_t BUF30I:1;
+ vuint32_t BUF29I:1;
+ vuint32_t BUF28I:1;
+ vuint32_t BUF27I:1;
+ vuint32_t BUF26I:1;
+ vuint32_t BUF25I:1;
+ vuint32_t BUF24I:1;
+ vuint32_t BUF23I:1;
+ vuint32_t BUF22I:1;
+ vuint32_t BUF21I:1;
+ vuint32_t BUF20I:1;
+ vuint32_t BUF19I:1;
+ vuint32_t BUF18I:1;
+ vuint32_t BUF17I:1;
+ vuint32_t BUF16I:1;
+ vuint32_t BUF15I:1;
+ vuint32_t BUF14I:1;
+ vuint32_t BUF13I:1;
+ vuint32_t BUF12I:1;
+ vuint32_t BUF11I:1;
+ vuint32_t BUF10I:1;
+ vuint32_t BUF09I:1;
+ vuint32_t BUF08I:1;
+ vuint32_t BUF07I:1;
+ vuint32_t BUF06I:1;
+ vuint32_t BUF05I:1;
+ vuint32_t BUF04I:1;
+ vuint32_t BUF03I:1;
+ vuint32_t BUF02I:1;
+ vuint32_t BUF01I:1;
+ vuint32_t BUF00I:1;
+ } B;
+ } IFRL; /* Interruput Flag Register */
+
+ uint32_t FLEXCAN_reserved2[19]; /* {0x0080-0x0034}/0x4 = 0x13 */
+
+/****************************************************************************/
+/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */
+/****************************************************************************/
+ /* Standard Buffer Structure */
+ struct FLEXCAN_BUFFER_t BUF[64];
+
+ /* RX FIFO and Buffer Structure */
+ /*struct FLEXCAN_RXFIFO_BUFFER_t RXFIFO;
+ struct FLEXCAN_BUFFER_t BUF[56];*/
+/****************************************************************************/
+
+ uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 */
+
+ union {
+ vuint32_t R;
+ struct {
+ vuint32_t MI:32;
+ } B;
+ } RXIMR[64]; /* RX Individual Mask Registers */
+
+ }; /* end of FLEXCAN_tag */
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name FlexCAN units references
+ * @{
+ */
+#if SPC5_HAS_FLEXCAN0 || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_0 (*(volatile struct spc5_flexcan *)0xFFFC0000UL)
+#endif
+
+#if SPC5_HAS_FLEXCAN1 || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_1 (*(volatile struct spc5_flexcan *)0xFFFC4000UL)
+#endif
+
+#if SPC5_HAS_FLEXCAN2 || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_2 (*(volatile struct spc5_flexcan *)0xFFFC8000UL)
+#endif
+
+#if SPC5_HAS_FLEXCAN3 || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_3 (*(volatile struct spc5_flexcan *)0xFFFCC000UL)
+#endif
+
+#if SPC5_HAS_FLEXCAN4 || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_4 (*(volatile struct spc5_flexcan *)0xFFFD0000UL)
+#endif
+
+#if SPC5_HAS_FLEXCAN5 || defined(__DOXYGEN__)
+#define SPC5_FLEXCAN_5 (*(volatile struct spc5_flexcan *)0xFFFD4000UL)
+#endif
+/** @} */
+
+#endif /* _SPC5_FLEXCAN_H_ */
+
+/** @} */
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