I2C. After comparing of two drivers decided to start of importing features from Alberto driver to mine.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2712 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 1090 insertions, 0 deletions

diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h
new file mode 100644
index 000000000..64816186b
--- /dev/null
+++ b/os/hal/include/i2c.h
@@ -0,0 +1,146 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    i2c.h

+ * @brief   I2C Driver macros and structures.

+ *

+ * @addtogroup I2C

+ * @{

+ */

+

+#ifndef _I2C_H_

+#define _I2C_H_

+

+#if HAL_USE_I2C || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver constants.                                                         */

+/*===========================================================================*/

+

+

+/*===========================================================================*/

+/* Driver pre-compile time settings.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Enables the mutual exclusion APIs on the I2C bus.

+ */

+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)

+#define I2C_USE_MUTUAL_EXCLUSION    TRUE

+#endif

+

+/*===========================================================================*/

+/* Derived constants and error checks.                                       */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver data structures and types.                                         */

+/*===========================================================================*/

+

+/**

+ * @brief   Driver state machine possible states.

+ */

+typedef enum {

+  I2C_UNINIT = 0,                   /**< Not initialized.                   */

+  I2C_STOP = 1,                     /**< Stopped.                           */

+  I2C_READY = 2,                    /**< Ready.                             */

+  I2C_MACTIVE = 3,                  /**< START condition sent.              */

+  I2C_MTRANSMIT = 4,                /**< Master transmitting.               */

+  I2C_MRECEIVE = 5,                 /**< Master receiving.                  */

+  I2C_MWAIT_TF = 6,                 /**< Master wait Transmission Finished  */

+  I2C_MERROR = 7                    /**< Error condition.                   */

+} i2cstate_t;

+

+#include "i2c_lld.h"

+

+/*===========================================================================*/

+/* Driver macros.                                                            */

+/*===========================================================================*/

+

+/**

+ * @brief   Read mode.

+ */

+#define I2C_READ                            1

+

+/**

+ * @brief   Write mode.

+ */

+#define I2C_WRITE                           0

+

+/**

+ * @brief   Seven bits addresses header builder.

+ *

+ * @param[in] addr      seven bits address value

+ * @param[in] rw        read/write flag

+ *

+ * @return              A 16 bit value representing the header, the most

+ *                      significant byte is always zero.

+ */

+#define I2C_ADDR7(addr, rw) (uint16_t)((addr) << 1 | (rw))

+

+

+/**

+ * @brief   Ten bits addresses header builder.

+ *

+ * @param[in] addr      ten bits address value

+ * @param[in] rw        read/write flag

+ *

+ * @return              A 16 bit value representing the header, the most

+ *                      significant byte is the first one to be transmitted.

+ */

+#define I2C_ADDR10(addr, rw)                                                \

+    (uint16_t)(0xF000 |                                                     \

+               (((addr) & 0x0300) << 1) |                                   \

+               (((rw) << 8)) |                                              \

+               ((addr) & 0x00FF))

+

+/*===========================================================================*/

+/* External declarations.                                                    */

+/*===========================================================================*/

+#ifdef __cplusplus

+extern "C" {

+#endif

+  void i2cInit(void);

+  void i2cObjectInit(I2CDriver *i2cp);

+  void i2cStart(I2CDriver *i2cp, I2CConfig *config);

+  void i2cStop(I2CDriver *i2cp);

+  void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);

+  void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);

+

+

+

+  void i2cMasterStartI(I2CDriver *i2cp,uint16_t header);

+  void i2cMasterStopI(I2CDriver *i2cp);

+  void i2cMasterRestartI(I2CDriver *i2cp);

+  void i2cMasterTransmitI(I2CDriver *i2cp, size_t n, const uint8_t *txbuf);

+  void i2cMasterReceiveI(I2CDriver *i2cp, size_t n, uint8_t *rxbuf);

+#if I2C_USE_MUTUAL_EXCLUSION

+  void i2cAcquireBus(I2CDriver *i2cp);

+  void i2cReleaseBus(I2CDriver *i2cp);

+#endif /* I2C_USE_MUTUAL_EXCLUSION */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* HAL_USE_I2C */

+

+#endif /* _I2C_H_ */

+

+/** @} */

diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c
new file mode 100644
index 000000000..9e519d412
--- /dev/null
+++ b/os/hal/platforms/STM32/i2c_lld.c
@@ -0,0 +1,462 @@
+/**
+ * @file STM32/i2c_lld.c
+ * @brief STM32 I2C subsystem low level driver source. Slave mode not implemented.
+ * @addtogroup STM32_I2C
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+#include "i2c_lld.h"
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief I2C1 driver identifier.*/
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+I2CDriver I2CD1;
+#endif
+
+/** @brief I2C2 driver identifier.*/
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+I2CDriver I2CD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   TODO: Status bits translation.
+ *
+ * @param[in] sr        USART SR register value
+ *
+ * @return  The error flags.
+ */
+static i2cflags_t translate_i2c_errors(uint16_t sr) {
+  i2cflags_t sts = 0;
+
+  if (sr & USART_SR_ORE)
+    sts |= UART_OVERRUN_ERROR;
+  if (sr & USART_SR_PE)
+    sts |= UART_PARITY_ERROR;
+  if (sr & USART_SR_FE)
+    sts |= UART_FRAMING_ERROR;
+  if (sr & USART_SR_NE)
+    sts |= UART_NOISE_ERROR;
+  if (sr & USART_SR_LBD)
+    sts |= UART_BREAK_DETECTED;
+  return sts;
+}
+
+
+static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
+  // TODO:remove this stub and write normal handler
+  // this is simply trap for errors
+  while TRUE{
+    translate_i2c_errors(i2cp->id_i2c->SR1);
+  }
+}
+
+/* This function handle all regular interrupt conditions
+ * TODO: 10 bit address handling here
+ */
+static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
+  int i = 0;
+  int n = 0;
+  int m = 0;
+
+  if ((i2cp->id_state == I2C_READY) && (i2cp->id_i2c->SR1 & I2C_SR1_SB)){// start bit sent
+    //i = i2cp->id_i2c->SR1;
+    i2cp->id_state = I2C_MACTIVE;
+    i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) |
+                        i2cp->id_slave_config->rw_bit; // write slave address in DR
+    return;
+  }
+
+  // now "wait" interrupt with ADDR flag
+  if ((i2cp->id_state == I2C_MACTIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){// address successfully sent
+    if(i2cp->id_i2c->SR2 & I2C_SR2_TRA){
+      i2c_lld_txbyte(i2cp); // send first byte
+      i2cp->id_state = I2C_MTRANSMIT; // change state
+      return;
+    }
+    else {
+      /* In order to generate the non-acknowledge pulse after the last received
+       * data byte, the ACK bit must be cleared just after reading the second
+       * last data byte (after second last RxNE event).
+       */
+      if (i2cp->id_slave_config->rxbytes > 1)
+        i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // set ACK bit
+      i2cp->id_state = I2C_MRECEIVE; // change status
+      return;
+    }
+  }
+
+  // transmitting bytes one by one
+  if ((i2cp->id_state == I2C_MTRANSMIT) && (i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
+    if (i2c_lld_txbyte(i2cp))
+      i2cp->id_state = I2C_MWAIT_TF; // last byte written
+    return;
+  }
+
+  //receiving bytes one by one
+  if ((i2cp->id_state == I2C_MRECEIVE) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
+//    i = i2cp->id_i2c->SR1;
+//    n = i2cp->id_i2c->SR2;
+    if (i2c_lld_rxbyte(i2cp))
+      i2cp->id_state = I2C_MWAIT_TF; // last byte read
+//    i = i2cp->id_i2c->SR1;
+//    n = i2cp->id_i2c->SR2;
+    return;
+  }
+
+  // "wait" BTF bit in status register
+//  if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
+  if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE | I2C_SR1_BTF | I2C_SR1_TXE)){
+    chSysLockFromIsr();
+    i2cp->id_slave_config->id_callback(i2cp, i2cp->id_slave_config);
+
+    i = i2cp->id_i2c->SR1;
+    n = i2cp->id_i2c->SR2;
+    m = i2cp->id_i2c->CR1;
+
+    chSysUnlockFromIsr();
+    return;
+  }
+  else{ // trap
+    i = i2cp->id_i2c->SR1;
+    n = i2cp->id_i2c->SR2;
+    m = i2cp->id_i2c->CR1;
+    return;
+  }
+}
+
+
+#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
+/**
+ * @brief I2C1 event interrupt handler.
+ */
+CH_IRQ_HANDLER(VectorBC) {
+
+  CH_IRQ_PROLOGUE();
+  i2c_serve_event_interrupt(&I2CD1);
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief I2C1 error interrupt handler.
+ */
+CH_IRQ_HANDLER(VectorC0) {
+
+  CH_IRQ_PROLOGUE();
+  i2c_serve_error_interrupt(&I2CD1);
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
+/**
+ * @brief I2C2 event interrupt handler.
+ */
+CH_IRQ_HANDLER(VectorC4) {
+
+  CH_IRQ_PROLOGUE();
+  i2c_serve_event_interrupt(&I2CD2);
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief I2C2 error interrupt handler.
+ */
+CH_IRQ_HANDLER(VectorC8) {
+
+  CH_IRQ_PROLOGUE();
+  i2c_serve_error_interrupt(&I2CD2);
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/**
+ * @brief Low level I2C driver initialization.
+ */
+void i2c_lld_init(void) {
+
+#if STM32_I2C_USE_I2C1
+  RCC->APB1RSTR     = RCC_APB1RSTR_I2C1RST;           // reset I2C 1
+  RCC->APB1RSTR     = 0;
+  i2cObjectInit(&I2CD1);
+  I2CD1.id_i2c     = I2C1;
+#endif
+
+#if STM32_I2C_USE_I2C2
+  RCC->APB1RSTR     = RCC_APB1RSTR_I2C2RST;           // reset I2C 2
+  RCC->APB1RSTR     = 0;
+  i2cObjectInit(&I2CD2);
+  I2CD2.id_i2c     = I2C2;
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ */
+void i2c_lld_start(I2CDriver *i2cp) {
+
+  /* If in stopped state then enables the I2C clock.*/
+  if (i2cp->id_state == I2C_STOP) {
+#if STM32_I2C_USE_I2C1
+    if (&I2CD1 == i2cp) {
+      NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+      NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
+      RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable
+    }
+#endif
+#if STM32_I2C_USE_I2C2
+    if (&I2CD2 == i2cp) {
+      NVICEnableVector(I2C2_EV_IRQn, STM32_I2C2_IRQ_PRIORITY);
+      NVICEnableVector(I2C2_ER_IRQn, STM32_I2C2_IRQ_PRIORITY);
+      RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable
+    }
+#endif
+  }
+
+  /* I2C setup.*/
+  i2cp->id_i2c->CR1 = I2C_CR1_SWRST; // reset i2c peripherial
+  i2cp->id_i2c->CR1 = 0;
+
+  i2cp->id_i2c->CR1 = i2cp->id_config->i2cc_cr1;
+  i2cp->id_i2c->CR2 = i2cp->id_config->i2cc_cr2 |
+                            I2C_CR2_ITERREN |
+                            I2C_CR2_ITEVTEN |
+                            I2C_CR2_ITBUFEN |
+                            36; //TODO: replace this by macro calculation
+  /* TODO:
+   * 1. macro timing calculator
+   * 2. parameter checker
+   * 3. definitions in halconf.h: i2c-freq, i2c_mode, etc
+   * 4. trise time calculator/checker
+   */
+  i2cp->id_i2c->CCR = i2cp->id_config->i2cc_ccr | 180;
+  i2cp->id_i2c->TRISE = i2cp->id_config->i2cc_trise | 37;
+  i2cp->id_i2c->CR1 |= 1; // enable interface
+}
+
+/**
+ * @brief Deactivates the I2C peripheral.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object
+ */
+void i2c_lld_stop(I2CDriver *i2cp) {
+
+  /* If in ready state then disables the I2C clock.*/
+  if (i2cp->id_state == I2C_READY) {
+#if STM32_I2C_USE_I2C1
+    if (&I2CD1 == i2cp) {
+      NVICDisableVector(I2C1_EV_IRQn);
+      NVICDisableVector(I2C1_ER_IRQn);
+      RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
+    }
+#endif
+#if STM32_I2C_USE_I2C2
+    if (&I2CD2 == i2cp) {
+      NVICDisableVector(I2C2_EV_IRQn);
+      NVICDisableVector(I2C2_ER_IRQn);
+      RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
+    }
+#endif
+  }
+  i2cp->id_state = I2C_STOP;
+}
+
+
+/* helper function, not API
+ * write bytes in DR register
+ * return TRUE if last byte written
+ */
+bool_t i2c_lld_txbyte(I2CDriver *i2cp) {
+  if (i2cp->id_slave_config->txbufhead < i2cp->id_slave_config->txbytes){
+    i2cp->id_i2c->DR = i2cp->id_slave_config->txbuf[i2cp->id_slave_config->txbufhead];
+    (i2cp->id_slave_config->txbufhead)++;
+    return(FALSE);
+  }
+  i2cp->id_slave_config->txbufhead = 0;
+  return(TRUE); // last byte written
+}
+
+
+/* helper function, not API
+ * read bytes from DR register
+ * return TRUE if last byte read
+ */
+bool_t i2c_lld_rxbyte(I2CDriver *i2cp) {
+  // temporal variables
+  #define rxbuf     i2cp->id_slave_config->rxbuf
+  #define rxbufhead i2cp->id_slave_config->rxbufhead
+  #define rxdepth   i2cp->id_slave_config->rxdepth
+  #define rxbytes   i2cp->id_slave_config->rxbytes
+
+  /* In order to generate the non-acknowledge pulse after the last received
+   * data byte, the ACK bit must be cleared just after reading the second
+   * last data byte (after second last RxNE event).
+   */
+  if (rxbufhead < rxbytes){
+    rxbuf[rxbufhead] = i2cp->id_i2c->DR;
+    if ((rxbytes - rxbufhead) <= 2){
+      i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);// clear ACK bit for automatically send NACK
+    }
+    rxbufhead++;
+    return(FALSE);
+  }
+
+  rxbuf[rxbufhead] = i2cp->id_i2c->DR; // read last byte
+  rxbufhead = 0;
+  #undef rxbuf
+  #undef rxbufhead
+  #undef rxdepth
+  #undef rxbytes
+
+  return(TRUE); // last byte read
+}
+
+
+void i2c_lld_master_start(I2CDriver *i2cp){
+  i2cp->id_i2c->CR1 |= I2C_CR1_START;
+}
+
+void i2c_lld_master_stop(I2CDriver *i2cp){
+  i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
+  chSysLock();
+  while (i2cp->id_i2c->CR1 & I2C_CR1_STOP);
+  chSysUnlock();
+}
+
+
+void i2c_lld_master_transmitI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+  //TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
+
+  i2cp->id_slave_config = i2cscfg;
+  i2cp->id_slave_config->rw_bit = I2C_WRITE;
+
+  // generate start condition. Later transmission goes in background
+  i2c_lld_master_start(i2cp);
+}
+
+void i2c_lld_master_receiveI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
+  //TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
+
+  i2cp->id_slave_config = i2cscfg;
+  i2cp->id_slave_config->rw_bit = I2C_READ;
+
+  // generate (re)start condition. Later connection goes asynchronously
+  i2c_lld_master_start(i2cp);
+}
+
+
+
+/**
+ * @brief Transmits data ever the I2C bus as masteri2cp.
+ *
+ * @param[in] i2cp          pointer to the @p I2CDriver object
+ * @param[in] i2cscfg       pointer to the @p I2CSlaveConfig object
+ * @param[in] restart       bool. If TRUE then generate restart condition insted of stop
+ */
+void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart) {
+	//TODO: check txbytes <= sizeof(i2cscfg->txbuf) here, or in hylevel API
+
+  int i = 0;
+
+  i2cp->id_slave_config = i2cscfg;
+  i2cp->id_slave_config->rw_bit = I2C_WRITE;
+
+
+  i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate start condition
+  while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
+    i++; // wait Address sent
+  }
+
+  i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_WRITE; // write slave addres in DR
+  while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
+    i++; // wait Address sent
+  }
+  i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
+  i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
+
+  // now write data byte by byte in DR register
+  uint32_t n = 0;
+  for (n = 0; n < i2cp->id_slave_config->txbytes; n++){
+  	i2cp->id_i2c->DR = i2cscfg->txbuf[n];
+  	while (!(i2cp->id_i2c->SR1 & I2C_SR1_TXE)){
+  	  i++;
+  	}
+  }
+
+  while (!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)){
+    i++;
+  }
+
+  if (restart){
+    i2cp->id_i2c->CR1 |= I2C_CR1_START; // generate restart condition
+    while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)){
+      i++; // wait start bit
+    }
+  }
+  else i2cp->id_i2c->CR1 |= I2C_CR1_STOP; // generate stop condition
+}
+
+
+/**
+ * @brief   Receives data from the I2C bus.
+ * @details Before receive data from I2C slave you must manually sent them some
+ *          control bytes first (refer to you device datasheet).
+ *
+ * @param[in] i2cp          pointer to the @p I2CDriver object
+ * @param[in] i2cscfg       pointer to the @p I2CSlaveConfig object
+ */
+void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
+
+  chSysLock();
+
+  i2cp->id_slave_config = i2cscfg;
+
+  uint16_t i = 0;
+  uint16_t tmp = 0;
+
+  // send slave addres with read-bit
+  i2cp->id_i2c->DR = (i2cp->id_slave_config->slave_addr1 << 1) | I2C_READ;
+  while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)){
+    i++; // wait Address sent
+  }
+  i = i2cp->id_i2c->SR2; // TODO: check is it need to read this register for I2C to proper functionality
+  i = i2cp->id_i2c->SR1; //i2cp->id_i2c->SR1 &= (~I2C_SR1_ADDR); // clear ADDR bit
+
+  // set ACK bit
+  i2cp->id_i2c->CR1 |= I2C_CR1_ACK;
+
+  // collect data from slave
+  for (i = 0; i < i2cp->id_slave_config->rxbytes; i++){
+    if ((i2cp->id_slave_config->rxbytes - i) == 1){ // TODO: is it better <= in place of == ?
+        // clear ACK bit for automatically send NACK
+        i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);}
+    while (!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)){
+      tmp++;
+    }
+    i2cp->id_slave_config->rxbuf[i] = i2cp->id_i2c->DR;
+  }
+  // generate STOP
+  i2cp->id_i2c->CR1 |= I2C_CR1_STOP;
+
+  chSysUnlock();
+}
+
+
+
+#endif // HAL_USE_I2C
diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h
new file mode 100644
index 000000000..bac1dfff0
--- /dev/null
+++ b/os/hal/platforms/STM32/i2c_lld.h
@@ -0,0 +1,267 @@
+/**
+ * @file STM32/i2c_lld.h
+ * @brief STM32 I2C subsystem low level driver header.
+ * @addtogroup STM32_I2C
+ * @{
+ */
+
+#ifndef _I2C_LLD_H_
+#define _I2C_LLD_H_
+
+#if HAL_USE_I2C || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief I2C1 driver enable switch.
+ * @details If set to @p TRUE the support for I2C1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C1              TRUE
+#endif
+
+/**
+ * @brief I2C2 driver enable switch.
+ * @details If set to @p TRUE the support for I2C2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
+#define STM32_I2C_USE_I2C2              TRUE
+#endif
+
+/**
+ * @brief I2C1 interrupt priority level setting.
+ * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ */
+#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C1_IRQ_PRIORITY     0xA0
+#endif
+
+/**
+ * @brief I2C2 interrupt priority level setting.
+ * @note @p BASEPRI_KERNEL >= @p STM32_I2C_I2C2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
+ */
+#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2C_I2C2_IRQ_PRIORITY     0xA0
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/** @brief No pending conditions.*/
+#define I2C_NO_ERROR          0
+/*@brief external Stop or Start condition during an address or a data transfer*/
+#define I2C_BUS_ERROR         1
+/** @brief */
+#define I2C_ARBITRATION_LOSS  2
+/** @brief */
+#define I2C_ACK_FAIL          4
+/** @brief */
+#define I2C_OVERRUN_UNDERRUN  8
+/** @brief */
+#define I2C_PEC_ERROR         16
+/** @brief */
+#define I2C_TIMEOUT           32
+/** @brief */
+#define I2C_SMBUS_ALERT       64
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an I2C driver.
+ */
+typedef struct I2CDriver I2CDriver;
+
+/**
+ * @brief   Type of a structure representing an I2C driver.
+ */
+typedef struct I2CSlaveConfig I2CSlaveConfig;
+
+
+/**
+ * @brief   I2C notification callback type.
+ * @details This function must be used to send start or stop events to I2C bus,
+ *          and change states of I2CDriver.
+ *
+ * @param[in] i2cp      pointer to the @p I2CDriver object triggering the
+ *                      callback
+ * @param[in] i2cscfg   pointer to the @p I2CSlaveConfig object triggering the
+ *                      callback
+ */
+typedef void (*i2ccallback_t)(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+
+
+/**
+ * @brief   I2C error notification callback type.
+ *
+ * @param[in] i2cp      TODO: pointer to the @p I2CDriver object triggering the
+ *                      callback
+ */
+typedef void (*i2cerrorcallback_t)(void);
+
+
+/**
+ * @brief Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief I2C initialization data.
+   */
+  uint16_t              i2cc_cr1;
+  uint16_t              i2cc_cr2;
+  uint16_t              i2cc_ccr;
+  uint16_t              i2cc_trise;
+
+} I2CConfig;
+
+
+/**
+ * @brief TODO:
+ */
+typedef uint32_t i2cflags_t;
+
+/**
+ * @brief TODO:
+ */
+typedef uint8_t i2cblock_t;
+
+
+/**
+ * @brief Structure representing an I2C slave configuration.
+ * @details Each slave has its own data buffers, adress, and error flags.
+ */
+struct I2CSlaveConfig{
+  /**
+   * @brief Callback pointer.
+   * @note  Transfer finished callback. Invoke when all data transferred, or
+   *        by DMA buffer events
+   *        @p NULL then the callback is disabled.
+   */
+  i2ccallback_t         id_callback;
+  /**
+   * @brief Callback pointer.
+   * @note  TODO: I don't know, when this callback is inwoked
+   *        @p NULL then the callback is disabled.
+   */
+  i2cerrorcallback_t    id_err_callback;
+
+  i2cblock_t            *rxbuf;     // pointer to buffer
+  size_t                rxdepth;    // depth of buffer
+  size_t                rxbytes;    // count of bytes to sent in one sending
+  size_t                rxbufhead;  // head pointer to current data byte
+
+  i2cblock_t            *txbuf;
+  size_t                txdepth;
+  size_t                txbytes;
+  size_t                txbufhead;
+
+  uint8_t               slave_addr1; // 7-bit address of the slave
+  uint8_t               slave_addr2; // used in 10-bit address mode
+
+  uint16_t              error_flags;
+
+  uint8_t               rw_bit; // this flag contain R/W bit
+
+  bool_t                restart; // send restart or stop event after complete data tx/rx
+
+};
+
+
+
+/**
+ * @brief Structure representing an I2C driver.
+ */
+struct I2CDriver{
+  /**
+   * @brief Driver state.
+   */
+  i2cstate_t            id_state;
+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the bus.
+   */
+  Mutex                 id_mutex;
+#elif CH_USE_SEMAPHORES
+  Semaphore             id_semaphore;
+#endif
+#endif /* I2C_USE_MUTUAL_EXCLUSION */
+  /**
+   * @brief Current configuration data.
+   */
+  I2CConfig             *id_config;
+  /**
+   * @brief Current slave configuration data.
+   */
+  I2CSlaveConfig        *id_slave_config;
+
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Thread waiting for I/O completion.
+   */
+  Thread                *id_thread;
+  /**
+   * @brief Pointer to the I2Cx registers block.
+   */
+  I2C_TypeDef           *id_i2c;
+
+} ;
+
+
+
+
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/** @cond never*/
+#if STM32_I2C_USE_I2C1
+extern I2CDriver I2CD1;
+#endif
+
+#if STM32_I2C_USE_I2C2
+extern I2CDriver I2CD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void i2c_lld_init(void);
+void i2c_lld_start(I2CDriver *i2cp);
+void i2c_lld_stop(I2CDriver *i2cp);
+
+void i2c_lld_master_start(I2CDriver *i2cp);
+void i2c_lld_master_stop(I2CDriver *i2cp);
+
+void i2c_lld_master_transmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, bool_t restart);
+void i2c_lld_master_transmitI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+bool_t i2c_lld_txbyte(I2CDriver *i2cp); // helper function
+
+void i2c_lld_master_receive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+void i2c_lld_master_receiveI(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
+bool_t i2c_lld_rxbyte(I2CDriver *i2cp);
+
+#ifdef __cplusplus
+}
+#endif
+/** @endcond*/
+
+#endif // CH_HAL_USE_I2C
+
+#endif // _I2C_LLD_H_
diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c
new file mode 100644
index 000000000..5a0471e0f
--- /dev/null
+++ b/os/hal/src/i2c.c
@@ -0,0 +1,215 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    i2c.c

+ * @brief   I2C Driver code.

+ *

+ * @addtogroup I2C

+ * @{

+ */

+

+#include "ch.h"

+#include "hal.h"

+

+#if HAL_USE_I2C || defined(__DOXYGEN__)

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   I2C Driver initialization.

+ * @note    This function is implicitly invoked by @p halInit(), there is

+ *          no need to explicitly initialize the driver.

+ *

+ * @init

+ */

+void i2cInit(void) {

+  i2c_lld_init();

+}

+

+/**

+ * @brief   Initializes the standard part of a @p I2CDriver structure.

+ *

+ * @param[out] i2cp     pointer to the @p I2CDriver object

+ *

+ * @init

+ */

+void i2cObjectInit(I2CDriver *i2cp) {

+

+  i2cp->id_state  = I2C_STOP;

+  i2cp->id_config = NULL;

+  i2cp->id_slave_config = NULL;

+#if defined(I2C_DRIVER_EXT_INIT_HOOK)

+  I2C_DRIVER_EXT_INIT_HOOK(i2cp);

+#endif

+}

+

+/**

+ * @brief   Configures and activates the I2C peripheral.

+ *

+ * @param[in] i2cp      pointer to the @p I2CDriver object

+ * @param[in] config    pointer to the @p I2CConfig object

+ *

+ * @api

+ */

+void i2cStart(I2CDriver *i2cp, I2CConfig *config) {

+

+  chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");

+

+  chSysLock();

+  chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),

+              "i2cStart(), #1",

+              "invalid state");

+  i2cp->id_config = config;

+  i2c_lld_start(i2cp);

+  i2cp->id_state = I2C_READY;

+  chSysUnlock();

+}

+

+/**

+ * @brief   Deactivates the I2C peripheral.

+ *

+ * @param[in] i2cp      pointer to the @p I2CDriver object

+ *

+ * @api

+ */

+void i2cStop(I2CDriver *i2cp) {

+

+  chDbgCheck(i2cp != NULL, "i2cStop");

+

+  chSysLock();

+  chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),

+              "i2cStop(), #1",

+              "invalid state");

+  i2c_lld_stop(i2cp);

+  i2cp->id_state = I2C_STOP;

+  chSysUnlock();

+}

+

+/**

+ * @brief Sends data ever the I2C bus.

+ *

+ * @param[in] i2cp           pointer to the @p I2CDriver object

+ * @param[in] slave_addr1    7-bit address of the slave

+ * @param[in] slave_addr1    used in 10-bit address mode

+ * @param[in] n              number of words to send

+ * @param[in] txbuf          the pointer to the transmit buffer

+ *

+ */

+void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {

+

+  chDbgCheck((i2cp != NULL) && (i2cscfg != NULL),

+             "i2cMasterTransmit");

+  chDbgAssert(i2cp->id_state == I2C_READY,

+              "i2cMasterTransmit(), #1",

+              "not active");

+

+  i2c_lld_master_transmitI(i2cp, i2cscfg);

+}

+

+

+/**

+ * @brief Receives data from the I2C bus.

+ *

+ * @param[in] i2cp      pointer to the @p I2CDriver object

+ * @param[in] slave_addr1    7-bit address of the slave

+ * @param[in] slave_addr1    used in 10-bit address mode

+ * @param[in] n         number of words to receive

+ * @param[out] rxbuf    the pointer to the receive buffer

+ *

+ */

+void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {

+

+  chDbgCheck((i2cp != NULL) && (i2cscfg != NULL),

+             "i2cMasterReceive");

+  chDbgAssert(i2cp->id_state == I2C_READY,

+              "i2cMasterReceive(), #1",

+              "not active");

+

+  i2c_lld_master_receiveI(i2cp, i2cscfg);

+}

+

+

+

+

+

+

+#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)

+/**

+ * @brief   Gains exclusive access to the I2C bus.

+ * @details This function tries to gain ownership to the I2C bus, if the bus

+ *          is already being used then the invoking thread is queued.

+ * @pre     In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION

+ *          must be enabled.

+ *

+ * @param[in] i2cp      pointer to the @p I2CDriver object

+ *

+ * @api

+ *

+ */

+void i2cAcquireBus(I2CDriver *i2cp) {

+

+  chDbgCheck(i2cp != NULL, "i2cAcquireBus");

+

+#if CH_USE_MUTEXES

+  chMtxLock(&i2cp->id_mutex);

+#elif CH_USE_SEMAPHORES

+  chSemWait(&i2cp->id_semaphore);

+#endif

+}

+

+/**

+ * @brief   Releases exclusive access to the I2C bus.

+ * @pre     In order to use this function the option @p I2C_USE_MUTUAL_EXCLUSION

+ *          must be enabled.

+ *

+ * @param[in] i2cp      pointer to the @p I2CDriver object

+ *

+ * @api

+ */

+void i2cReleaseBus(I2CDriver *i2cp) {

+

+  chDbgCheck(i2cp != NULL, "i2cReleaseBus");

+

+#if CH_USE_MUTEXES

+  (void)i2cp;

+  chMtxUnlock();

+#elif CH_USE_SEMAPHORES

+  chSemSignal(&i2cp->id_semaphore);

+#endif

+}

+#endif /* I2C_USE_MUTUAL_EXCLUSION */

+

+#endif /* HAL_USE_I2C */

+

+/** @} */