git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6289 35acf78f-673a-0410-8e92-d51de3d6d3f4

9 files changed, 64 insertions, 29 deletions

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
index 7f0bf713b..b4dfd0850 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
@@ -19,7 +19,7 @@
 */

 

 /*

- * ST32F051x8 memory setup.

+ * STM32F051x8 memory setup.

  */

 MEMORY

 {

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
index 28a6bbe00..40608e567 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F303xC.ld
@@ -19,7 +19,7 @@
 */

 

 /*

- * ST32F303xC memory setup.

+ * STM32F303xC memory setup.

  */

 MEMORY

 {

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
index 042d9519f..c88d8e639 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F373xC.ld
@@ -19,7 +19,7 @@
 */

 

 /*

- * ST32F373xC memory setup.

+ * STM32F373xC memory setup.

  */

 MEMORY

 {

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
index 52ec669d6..ed26141ea 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F405xG.ld
@@ -19,7 +19,7 @@
 */

 

 /*

- * ST32F405xG memory setup.

+ * STM32F405xG memory setup.

  */

 MEMORY

 {

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
index 3c1648384..43e0b599d 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F407xG.ld
@@ -19,7 +19,7 @@
 */

 

 /*

- * ST32F407xG memory setup.

+ * STM32F407xG memory setup.

  */

 MEMORY

 {

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
index 5a364f30b..f3bfd2cc8 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32L152xB.ld
@@ -19,7 +19,7 @@
 */

 

 /*

- * ST32L152xB memory setup.

+ * STM32L152xB memory setup.

  */

 MEMORY

 {

diff --git a/os/hal/ports/STM32/TIMv1/st_lld.c b/os/hal/ports/STM32/TIMv1/st_lld.c
index 240328ff5..8e4a4e84e 100644
--- a/os/hal/ports/STM32/TIMv1/st_lld.c
+++ b/os/hal/ports/STM32/TIMv1/st_lld.c
@@ -26,17 +26,34 @@
 

 #if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)

 

+#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING

+

 /* The following checks and settings are unusually done here because the

    file st.h needs to not have external dependencies. In this case there

    would be a dependency on osal.h and mcuconf.h.*/

-#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) && !STM32_HAS_TIM2

+#if !defined(HAL_ST_USE_TIM5)

+

+#if !STM32_HAS_TIM2

 #error "TIM2 not present in the selected device"

 #endif

 

-#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) && !STM32_TIM2_IS_32BITS

+#if !STM32_TIM2_IS_32BITS

 #error "TIM2 is not a 32 bits timer"

 #endif

 

+#else /* defined(HAL_ST_USE_TIM5) */

+

+#if !STM32_HAS_TIM5

+#error "TIM5 not present in the selected device"

+#endif

+

+#if !STM32_TIM5_IS_32BITS

+#error "TIM5 is not a 32 bits timer"

+#endif

+#endif /* defined(HAL_ST_USE_TIM5) */

+

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */

+

 /**

  * @name    Configuration options

  * @{

@@ -90,7 +107,7 @@ OSAL_IRQ_HANDLER(SysTick_Handler) {
 

   OSAL_IRQ_EPILOGUE();

 }

-#endif

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */

 

 #if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__)

 /**

@@ -99,11 +116,15 @@ OSAL_IRQ_HANDLER(SysTick_Handler) {
  *

  * @isr

  */

+#if !defined(HAL_ST_USE_TIM5)

 OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {

+#else

+OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {

+#endif

 

   OSAL_IRQ_PROLOGUE();

 

-  STM32_TIM2->SR = 0;

+  ST_TIM->SR = 0;

 

   osalSysLockFromISR();

   osalOsTimerHandlerI();

@@ -111,7 +132,7 @@ OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
 

   OSAL_IRQ_EPILOGUE();

 }

-#endif

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

@@ -126,21 +147,29 @@ void st_lld_init(void) {
 

 #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING

   /* Free running counter mode.*/

+#if !defined(HAL_ST_USE_TIM5)

   rccEnableTIM2(FALSE);

+#else

+  rccEnableTIM5(FALSE);

+#endif

 

   /* Initializing the counter in free running mode.*/

-  STM32_TIM2->PSC    = STM32_TIMCLK1 / OSAL_SYSTICK_FREQUENCY - 1;

-  STM32_TIM2->ARR    = 0xFFFFFFFF;

-  STM32_TIM2->CCMR1  = 0;

-  STM32_TIM2->CCR[0] = 0;

-  STM32_TIM2->DIER   = 0;

-  STM32_TIM2->CR2    = 0;

-  STM32_TIM2->EGR    = TIM_EGR_UG;

-  STM32_TIM2->CR1    = TIM_CR1_CEN;

+  ST_TIM->PSC    = STM32_TIMCLK1 / OSAL_SYSTICK_FREQUENCY - 1;

+  ST_TIM->ARR    = 0xFFFFFFFF;

+  ST_TIM->CCMR1  = 0;

+  ST_TIM->CCR[0] = 0;

+  ST_TIM->DIER   = 0;

+  ST_TIM->CR2    = 0;

+  ST_TIM->EGR    = TIM_EGR_UG;

+  ST_TIM->CR1    = TIM_CR1_CEN;

 

   /* IRQ enabled.*/

+#if !defined(HAL_ST_USE_TIM5)

   nvicEnableVector(STM32_TIM2_NUMBER, STM32_ST_IRQ_PRIORITY);

+#else

+  nvicEnableVector(STM32_TIM5_NUMBER, STM32_ST_IRQ_PRIORITY);

 #endif

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */

 

 #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

   /* Periodic systick mode, the Cortex-Mx internal systick timer is used

@@ -153,7 +182,7 @@ void st_lld_init(void) {
 

   /* IRQ enabled.*/

   nvicSetSystemHandlerPriority(SysTick_IRQn, STM32_ST_IRQ_PRIORITY);

-#endif

+#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */

 }

 

 #endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */

diff --git a/os/hal/ports/STM32/TIMv1/st_lld.h b/os/hal/ports/STM32/TIMv1/st_lld.h
index fb067f202..4a969738c 100644
--- a/os/hal/ports/STM32/TIMv1/st_lld.h
+++ b/os/hal/ports/STM32/TIMv1/st_lld.h
@@ -42,6 +42,12 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+#if !defined(HAL_ST_USE_TIM5)

+#define ST_TIM                              STM32_TIM2

+#else

+#define ST_TIM                              STM32_TIM5

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -75,7 +81,7 @@ extern "C" {
  */

 static inline systime_t st_lld_get_counter(void) {

 

-  return (systime_t)(STM32_TIM2->CNT);

+  return (systime_t)(ST_TIM->CNT);

 }

 

 /**

@@ -89,9 +95,9 @@ static inline systime_t st_lld_get_counter(void) {
  */

 static inline void st_lld_start_alarm(systime_t time) {

 

-  STM32_TIM2->CCR[0] = time;

-  STM32_TIM2->SR     = 0;

-  STM32_TIM2->DIER   = STM32_TIM_DIER_CC1IE;

+  ST_TIM->CCR[0] = time;

+  ST_TIM->SR     = 0;

+  ST_TIM->DIER   = STM32_TIM_DIER_CC1IE;

 }

 

 /**

@@ -101,7 +107,7 @@ static inline void st_lld_start_alarm(systime_t time) {
  */

 static inline void st_lld_stop_alarm(void) {

 

-  STM32_TIM2->DIER = 0;

+  ST_TIM->DIER = 0;

 }

 

 /**

@@ -113,7 +119,7 @@ static inline void st_lld_stop_alarm(void) {
  */

 static inline void st_lld_set_alarm(systime_t time) {

 

-  STM32_TIM2->CCR[0] = (uint32_t)time;

+  ST_TIM->CCR[0] = (uint32_t)time;

 }

 

 /**

@@ -125,7 +131,7 @@ static inline void st_lld_set_alarm(systime_t time) {
  */

 static inline systime_t st_lld_get_alarm(void) {

 

-  return (systime_t)STM32_TIM2->CCR[0];

+  return (systime_t)ST_TIM->CCR[0];

 }

 

 /**

@@ -139,7 +145,7 @@ static inline systime_t st_lld_get_alarm(void) {
  */

 static inline bool st_lld_is_alarm_active(void) {

 

-  return (bool)((STM32_TIM2->DIER & STM32_TIM_DIER_CC1IE) != 0);

+  return (bool)((ST_TIM->DIER & STM32_TIM_DIER_CC1IE) != 0);

 }

 

 #endif /* _ST_LLD_H_ */

diff --git a/os/hal/ports/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32L1xx/stm32_registry.h
index 1a6379bcd..23d5d3264 100644
--- a/os/hal/ports/STM32L1xx/stm32_registry.h
+++ b/os/hal/ports/STM32L1xx/stm32_registry.h
@@ -104,7 +104,7 @@
 #define STM32_TIM_MAX_CHANNELS              6

 

 #define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                TRUE

+#define STM32_TIM2_IS_32BITS                FALSE

 #define STM32_TIM2_CHANNELS                 4

 

 #define STM32_HAS_TIM3                      TRUE