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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-04-06 11:45:12 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-04-06 11:45:12 +0000 |
| commit | aeb912eb7cc9930a42d8144ff3c49b7abb0dfc70 (patch) | |
| tree | 7c6917ff2e5208d7a5ed3340edaa284cab0b62fe /os | |
| parent | 6b063bc3964e363bdd54dbeae6236b6b4164a84e (diff) | |
| download | ChibiOS-aeb912eb7cc9930a42d8144ff3c49b7abb0dfc70.tar.gz ChibiOS-aeb912eb7cc9930a42d8144ff3c49b7abb0dfc70.tar.bz2 ChibiOS-aeb912eb7cc9930a42d8144ff3c49b7abb0dfc70.zip | |
Fixed bug #482.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6841 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32/OTGv1/usb_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/stm32_rcc.h | 18 |
2 files changed, 22 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.c b/os/hal/platforms/STM32/OTGv1/usb_lld.c index 3dcb0d839..7d0c3f216 100644 --- a/os/hal/platforms/STM32/OTGv1/usb_lld.c +++ b/os/hal/platforms/STM32/OTGv1/usb_lld.c @@ -861,6 +861,10 @@ void usb_lld_start(USBDriver *usbp) { rccEnableOTG_HS(FALSE);
rccResetOTG_HS();
+ /* Workaround for the problem described here:
+ http://forum.chibios.org/phpbb/viewtopic.php?f=16&t=1798 */
+ rccDisableOTG_HSULPI(TRUE);
+
/* Enables IRQ vector.*/
nvicEnableVector(STM32_OTG2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_USB_OTG2_IRQ_PRIORITY));
diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index 9178f67da..b2d45d5aa 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -664,6 +664,24 @@ * @api
*/
#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHSRST)
+
+/**
+ * @brief Enables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
+
+/**
+ * @brief Disables the OTG_HS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
/** @} */
/**
|