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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-11-18 22:45:27 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2009-11-18 22:45:27 +0000 |
| commit | a943eaecc7cd56c2a49521bf702b0524bb834aa1 (patch) | |
| tree | fdcdf70cfd84aac9f4d68dae6a38b3210c1d6e74 /os | |
| parent | 1dd5442c8c6c3b7d77133825abf147501de36093 (diff) | |
| download | ChibiOS-a943eaecc7cd56c2a49521bf702b0524bb834aa1.tar.gz ChibiOS-a943eaecc7cd56c2a49521bf702b0524bb834aa1.tar.bz2 ChibiOS-a943eaecc7cd56c2a49521bf702b0524bb834aa1.zip | |
Fixed minor problem with NVIC support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1314 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/io/platforms/STM32/spi_lld.c | 4 | ||||
| -rw-r--r-- | os/ports/GCC/ARMCM3/nvic.c | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/os/io/platforms/STM32/spi_lld.c b/os/io/platforms/STM32/spi_lld.c index 99285d0e2..598e0fd5b 100644 --- a/os/io/platforms/STM32/spi_lld.c +++ b/os/io/platforms/STM32/spi_lld.c @@ -207,17 +207,17 @@ void spi_lld_start(SPIDriver *spip) { if (spip->spd_state == SPI_STOP) {
#if USE_STM32_SPI1
if (&SPID1 == spip) {
+ dmaEnable(DMA1_ID);
NVICEnableVector(DMA1_Channel2_IRQn, STM32_SPI1_IRQ_PRIORITY);
NVICEnableVector(DMA1_Channel3_IRQn, STM32_SPI1_IRQ_PRIORITY);
- dmaEnable(DMA1_ID);
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
}
#endif
#if USE_STM32_SPI2
if (&SPID2 == spip) {
+ dmaEnable(DMA1_ID);
NVICEnableVector(DMA1_Channel4_IRQn, STM32_SPI2_IRQ_PRIORITY);
NVICEnableVector(DMA1_Channel5_IRQn, STM32_SPI2_IRQ_PRIORITY);
- dmaEnable(DMA1_ID);
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
}
#endif
diff --git a/os/ports/GCC/ARMCM3/nvic.c b/os/ports/GCC/ARMCM3/nvic.c index c34aaf4ea..e61637848 100644 --- a/os/ports/GCC/ARMCM3/nvic.c +++ b/os/ports/GCC/ARMCM3/nvic.c @@ -39,6 +39,7 @@ void NVICEnableVector(uint32_t n, uint32_t prio) { unsigned sh = (n & 3) << 3;
NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh);
+ NVIC_ICPR(n >> 5) = 1 << (n & 0x1F);
NVIC_ISER(n >> 5) = 1 << (n & 0x1F);
}
|