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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-04-29 14:47:14 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-04-29 14:47:14 +0000 |
| commit | a8752fb707e166f83c2b5b78c30f65f7e1d1ddea (patch) | |
| tree | 30ac1232e84a5dfb879f288fe0d055f2f7493c12 /os | |
| parent | 2b0b55a4dddf0c3acd0f0f7177b15c8dd46b0f74 (diff) | |
| download | ChibiOS-a8752fb707e166f83c2b5b78c30f65f7e1d1ddea.tar.gz ChibiOS-a8752fb707e166f83c2b5b78c30f65f7e1d1ddea.tar.bz2 ChibiOS-a8752fb707e166f83c2b5b78c30f65f7e1d1ddea.zip | |
Fixed bug #491.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6894 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/ext/CMSIS/ST/stm32l1xx.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/os/ext/CMSIS/ST/stm32l1xx.h b/os/ext/CMSIS/ST/stm32l1xx.h index bd77670ba..62fed8a16 100644 --- a/os/ext/CMSIS/ST/stm32l1xx.h +++ b/os/ext/CMSIS/ST/stm32l1xx.h @@ -233,15 +233,16 @@ typedef enum IRQn #ifdef STM32L1XX_MDP
TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
- TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
- DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
- DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
- AES_IRQn = 55, /*!< AES global Interrupt */
- COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+ /* CHIBIOS FIX */
+ TIM5_IRQn = 45, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 46, /*!< SPI3 global Interrupt */
+ DMA2_Channel1_IRQn = 47, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 48, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 49, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 50, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 51, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 52, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 53 /*!< Comparator Channel Acquisition global Interrupt */
#endif /* STM32L1XX_MDP */
#ifdef STM32L1XX_HD
|