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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-14 14:53:55 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-12-14 14:53:55 +0000 |
| commit | 95fc35d5f581597d26044733948f21aebf3845ac (patch) | |
| tree | f7cd93a965ac6c6babbfc0cf6d68ee800e49894b /os | |
| parent | 53a30f78fe3e5ebebc379f1f3ab0ef92448ac349 (diff) | |
| download | ChibiOS-95fc35d5f581597d26044733948f21aebf3845ac.tar.gz ChibiOS-95fc35d5f581597d26044733948f21aebf3845ac.tar.bz2 ChibiOS-95fc35d5f581597d26044733948f21aebf3845ac.zip | |
Fixed some details about ADCv3.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8600 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/ports/STM32/LLD/ADCv3/adc_lld.c | 50 |
1 files changed, 49 insertions, 1 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c index f186670dd..872fd3afe 100644 --- a/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c +++ b/os/hal/ports/STM32/LLD/ADCv3/adc_lld.c @@ -452,6 +452,23 @@ void adc_lld_init(void) { STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC1 */
+#if STM32_ADC_USE_ADC2
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD2);
+#if defined(ADC1_2_COMMON)
+ ADCD2.adcc = ADC1_2_COMMON;
+#elif defined(ADC123_COMMON)
+ ADCD2.adcc = ADC123_COMMON;
+#endif
+ ADCD2.adcm = ADC2;
+ ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
+ ADCD2.dmamode = ADC_DMA_SIZE |
+ STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif /* STM32_ADC_USE_ADC2 */
+
#if STM32_ADC_USE_ADC3
/* Driver initialization.*/
adcObjectInit(&ADCD3);
@@ -474,6 +491,19 @@ void adc_lld_init(void) { STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif /* STM32_ADC_USE_ADC3 */
+#if STM32_ADC_USE_ADC4
+ /* Driver initialization.*/
+ adcObjectInit(&ADCD4);
+ ADCD4.adcc = ADC3_4_COMMON;
+ ADCD4.adcm = ADC4;
+ ADCD4.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC4_DMA_STREAM);
+ ADCD4.dmamode = ADC_DMA_SIZE |
+ STM32_DMA_CR_PL(STM32_ADC_ADC4_DMA_PRIORITY) |
+ STM32_DMA_CR_DIR_P2M |
+ STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
+ STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
+#endif /* STM32_ADC_USE_ADC4 */
+
/* IRQs setup.*/
#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2
nvicEnableVector(STM32_ADC1_NUMBER, STM32_ADC_ADC12_IRQ_PRIORITY);
@@ -650,29 +680,47 @@ void adc_lld_stop(ADCDriver *adcp) { adc_lld_analog_off(adcp);
adc_lld_vreg_off(adcp);
+#if defined(STM32L4XX)
/* Resetting CCR options except default ones.*/
- adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+ adcp->adcc->CCR = STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
clkmask &= ~(1 << 0);
}
#endif
#if STM32_ADC_USE_ADC2
if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
clkmask &= ~(1 << 1);
}
#endif
#if STM32_ADC_USE_ADC3
if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
clkmask &= ~(1 << 2);
}
#endif
#if STM32_ADC_USE_ADC4
if (&ADCD1 == adcp) {
+#if defined(STM32F3XX)
+ /* Resetting CCR options except default ones.*/
+ adcp->adcc->CCR = STM32_ADC_ADC34_CLOCK_MODE | ADC_DMA_MDMA;
+#endif
clkmask &= ~(1 << 3);
}
#endif
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