diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-05-14 06:43:02 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-05-14 06:43:02 +0000 |
| commit | 55b7744199ce9771ac761fc708d173bc487145e8 (patch) | |
| tree | 3b7a61cd3019849544e2bbe25ace9ff658a75e75 /os | |
| parent | fee72530476c5b9eed43fde792df9de367d56800 (diff) | |
| download | ChibiOS-55b7744199ce9771ac761fc708d173bc487145e8.tar.gz ChibiOS-55b7744199ce9771ac761fc708d173bc487145e8.tar.bz2 ChibiOS-55b7744199ce9771ac761fc708d173bc487145e8.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1916 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 9 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld_F107.h | 17 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld_F10x.h | 13 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/pal_lld.c | 2 |
4 files changed, 39 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index 9dc66a3f0..25d4b4d57 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -126,7 +126,7 @@ void stm32_clock_init(void) { #endif
/* Clock settings.*/
- RCC->CFGR = STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
+ RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup and final clock selection. */
@@ -184,6 +184,13 @@ void stm32_clock_init(void) { ; /* Waits until PLL2 is stable. */
#endif
+ /* Clock settings.*/
+ RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
+ STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+ /* Flash setup and final clock selection. */
+ FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
+
/* Switching on the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
diff --git a/os/hal/platforms/STM32/hal_lld_F107.h b/os/hal/platforms/STM32/hal_lld_F107.h index 193beda68..048fa5028 100644 --- a/os/hal/platforms/STM32/hal_lld_F107.h +++ b/os/hal/platforms/STM32/hal_lld_F107.h @@ -74,6 +74,16 @@ #define STM32_OTGFSPRE_DIV2 (1 << 22) /**< HCLK*2 divided by 2. */
#define STM32_OTGFSPRE_DIV3 (0 << 22) /**< HCLK*2 divided by 3. */
+#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+#define STM32_MCO_PLL2 (8 << 24) /**< PLL2 clock on MCO pin. */
+#define STM32_MCO_PLL3DIV2 (9 << 24) /**< PLL3/2 clock on MCO pin. */
+#define STM32_MCO_XT1 (10 << 24) /**< XT1 clock on MCO pin. */
+#define STM32_MCO_PLL3 (11 << 24) /**< PLL3 clock on MCO pin. */
+
/* RCC_CFGR2 register bits definitions.*/
#define STM32_PREDIV1SRC_HSE (0 << 16) /**< PREDIV1 source is HSE. */
#define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */
@@ -188,6 +198,13 @@ #define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
+/**
+ * @brief MCO pin setting.
+ */
+#if !defined(STM32_MCO) || defined(__DOXYGEN__)
+#define STM32_MCO STM32_MCO_NOCLOCK
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/hal_lld_F10x.h b/os/hal/platforms/STM32/hal_lld_F10x.h index 67876e6b2..8e9063e64 100644 --- a/os/hal/platforms/STM32/hal_lld_F10x.h +++ b/os/hal/platforms/STM32/hal_lld_F10x.h @@ -73,6 +73,12 @@ #define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
+#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
+#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
+#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
+#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
+#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -150,6 +156,13 @@ #define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
+/**
+ * @brief MCO pin setting.
+ */
+#if !defined(STM32_MCO) || defined(__DOXYGEN__)
+#define STM32_MCO STM32_MCO_NOCLOCK
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/pal_lld.c b/os/hal/platforms/STM32/pal_lld.c index f39b64498..ae250f85d 100644 --- a/os/hal/platforms/STM32/pal_lld.c +++ b/os/hal/platforms/STM32/pal_lld.c @@ -46,7 +46,7 @@ RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
#else
- /* Defaults on Medium Density devices.*/
+ /* Defaults on Medium Density and Connection Line devices.*/
#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_AFIORST);
|