More L1-related fixes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8174 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 93 insertions, 228 deletions

diff --git a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
index 727d15891..efce27eaf 100644
--- a/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
+++ b/os/hal/ports/STM32/STM32L1xx/ext_lld_isr.c
@@ -305,11 +305,7 @@ OSAL_IRQ_HANDLER(Vector98) {
  *

  * @isr

  */

-#if defined(STM32L1XX_MDP) || defined(__DOXYGEN__)

-OSAL_IRQ_HANDLER(Vector114) {

-#else

 OSAL_IRQ_HANDLER(Vector120) {

-#endif

   uint32_t pr;

 

   OSAL_IRQ_PROLOGUE();

diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_lld.h
index b9795f391..fb3b4d72c 100644
--- a/os/hal/ports/STM32/STM32L1xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.h
@@ -31,9 +31,6 @@
  *            STM32L152xD, STM32L152xDX, STM32L152xE.

  *          - STM32L162xC, STM32L162xCA, STM32L162xD, STM32L162xDX,

  *            STM32L162xE.

- *          - STM32L1XX_MD for Ultra Low Power Medium-density devices.

- *          - STM32L1XX_MDP for Ultra Low Power Medium-density Plus devices.

- *          - STM32L1XX_HD for Ultra Low Power High-density devices.

  *          .

  *

  * @addtogroup HAL

diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
index e64ff3929..883712ea2 100644
--- a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h
@@ -260,6 +260,31 @@
  * @api

  */

 #define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)

+

+/**

+ * @brief   Enables the DMA2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)

+

+/**

+ * @brief   Disables the DMA2 peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)

+

+/**

+ * @brief   Resets the DMA2 peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)

 /** @} */

 

 /**

diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
index 962003e7e..89d570f4f 100644
--- a/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L1xx/stm32_registry.h
@@ -25,23 +25,29 @@
 #ifndef _STM32_REGISTRY_H_

 #define _STM32_REGISTRY_H_

 

-#if defined(STM32L100xB) || defined(STM32L151xB) ||                         \

-    defined(STM32L152xB) || defined(__DOXYGEN__)

-#define STM32L1XX_MD

-

-#elif defined(STM32L100xBA) || defined(STM32L100xC)  ||                     \

-      defined(STM32L151xBA) || defined(STM32L151xC)  ||                     \

-      defined(STM32L151xCA) || defined(STM32L152xBA) ||                     \

-      defined(STM32L152xC)  || defined(STM32L152xCA) ||                     \

-      defined(STM32L162xC)  || defined(STM32L162xCA)

-#define STM32L1XX_MDP

-

-#elif defined(STM32L151xD)  || defined(STM32L151xDX) ||                     \

-      defined(STM32L151xE)  || defined(STM32L152xD)  ||                     \

-      defined(STM32L152xDX) || defined(STM32L152xE)  ||                     \

-      defined(STM32L162xD)  || defined(STM32L162xDX) ||                     \

+#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)

+#define STM32L1XX_PROD_CAT      1

+

+#elif defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)

+#define STM32L1XX_PROD_CAT      2

+

+#elif defined(STM32L100xC)  || defined(STM32L151xC)   ||                    \

+      defined(STM32L151xCA) || defined(STM32L152xC)   ||                    \

+      defined(STM32L152xCA) || defined(STM32L162xC)   ||                    \

+      defined(STM32L162xCA)

+#define STM32L1XX_PROD_CAT      3

+

+#elif defined(STM32L151xD)  || defined(STM32L152xD)   ||                    \

+      defined(STM32L162xD)

+#define STM32L1XX_PROD_CAT      4

+

+#elif defined(STM32L151xE)  || defined (STM32L152xE)  ||                    \

       defined(STM32L162xE)

-#define STM32L1XX_HD

+#define STM32L1XX_PROD_CAT      5

+

+#elif defined(STM32L151xDX) || defined (STM32L152xDX) ||                    \

+      defined(STM32L162xDX)

+#define STM32L1XX_PROD_CAT      6

 

 #else

 #error "STM32L1xx device not specified"

@@ -55,8 +61,6 @@
  * @name    STM32L1xx capabilities

  * @{

  */

-#if defined(STM32L1XX_MD) || defined(STM32L1XX_MDP) || defined(__DOXYGEN__)

-

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

 #define STM32_HAS_ADC2                      FALSE

@@ -80,11 +84,6 @@
 

 /* DMA attributes.*/

 #define STM32_ADVANCED_DMA                  FALSE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      FALSE

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  FALSE

 

 #define STM32_DMA_SUPPORTS_CSELR            FALSE

 #define STM32_DMA1_NUM_CHANNELS             7

@@ -103,16 +102,37 @@
 #define STM32_DMA1_CH6_NUMBER               16

 #define STM32_DMA1_CH7_NUMBER               17

 

+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) ||               \

+    defined(__DOXYGEN__)

 #define STM32_DMA2_NUM_CHANNELS             0

+#else

+#define STM32_DMA2_NUM_CHANNELS             5

+#define STM32_DMA2_CH1_HANDLER              Vector108

+#define STM32_DMA2_CH2_HANDLER              Vector10C

+#define STM32_DMA2_CH3_HANDLER              Vector110

+#define STM32_DMA2_CH4_HANDLER              Vector114

+#define STM32_DMA2_CH5_HANDLER              Vector118

+#define STM32_DMA2_CH1_NUMBER               50

+#define STM32_DMA2_CH2_NUMBER               51

+#define STM32_DMA2_CH3_NUMBER               52

+#define STM32_DMA2_CH4_NUMBER               53

+#define STM32_DMA2_CH5_NUMBER               54

+#endif

 

 /* ETH attributes.*/

 #define STM32_HAS_ETH                       FALSE

 

 /* EXTI attributes.*/

+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) ||               \

+    defined(__DOXYGEN__)

 #define STM32_EXTI_NUM_LINES                23

+#else

+#define STM32_EXTI_NUM_LINES                24

+#endif

 #define STM32_EXTI_IMR_MASK                 0x00000000U

 

-/* GPIO attributes.*/

+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) ||               \

+    (STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)

 #define STM32_HAS_GPIOA                     TRUE

 #define STM32_HAS_GPIOB                     TRUE

 #define STM32_HAS_GPIOC                     TRUE

@@ -130,202 +150,7 @@
                                              RCC_AHBENR_GPIODEN |           \

                                              RCC_AHBENR_GPIOEEN |           \

                                              RCC_AHBENR_GPIOHEN)

-

-/* I2C attributes.*/

-#define STM32_HAS_I2C1                      TRUE

-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

-

-#define STM32_HAS_I2C2                      TRUE

-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

-

-#define STM32_HAS_I2C3                      FALSE

-#define STM32_HAS_I2C4                      FALSE

-

-/* RTC attributes.*/

-#define STM32_HAS_RTC                       TRUE

-#if defined(STM32L1XX_MDP)

-#define STM32_RTC_HAS_SUBSECONDS            TRUE

 #else

-#define STM32_RTC_HAS_SUBSECONDS            FALSE

-#endif

-#define STM32_HAS_RTC                       TRUE

-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

-#define STM32_RTC_NUM_ALARMS                2

-#define STM32_RTC_HAS_INTERRUPTS            FALSE

-

-/* SDIO attributes.*/

-#define STM32_HAS_SDIO                      TRUE

-

-/* SPI attributes.*/

-#define STM32_HAS_SPI1                      TRUE

-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

-

-#define STM32_HAS_SPI2                      TRUE

-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

-

-#define STM32_HAS_SPI3                      FALSE

-#define STM32_HAS_SPI4                      FALSE

-#define STM32_HAS_SPI5                      FALSE

-#define STM32_HAS_SPI6                      FALSE

-

-/* TIM attributes.*/

-#define STM32_TIM_MAX_CHANNELS              4

-

-#define STM32_HAS_TIM2                      TRUE

-#define STM32_TIM2_IS_32BITS                FALSE

-#define STM32_TIM2_CHANNELS                 4

-

-#define STM32_HAS_TIM3                      TRUE

-#define STM32_TIM3_IS_32BITS                FALSE

-#define STM32_TIM3_CHANNELS                 4

-

-#define STM32_HAS_TIM4                      TRUE

-#define STM32_TIM4_IS_32BITS                FALSE

-#define STM32_TIM4_CHANNELS                 4

-

-#define STM32_HAS_TIM6                      TRUE

-#define STM32_TIM6_IS_32BITS                FALSE

-#define STM32_TIM6_CHANNELS                 0

-

-#define STM32_HAS_TIM7                      TRUE

-#define STM32_TIM7_IS_32BITS                FALSE

-#define STM32_TIM7_CHANNELS                 0

-

-#define STM32_HAS_TIM9                      TRUE

-#define STM32_TIM9_IS_32BITS                FALSE

-#define STM32_TIM9_CHANNELS                 2

-

-#define STM32_HAS_TIM10                     TRUE

-#define STM32_TIM10_IS_32BITS               FALSE

-#define STM32_TIM10_CHANNELS                2

-

-#define STM32_HAS_TIM11                     TRUE

-#define STM32_TIM11_IS_32BITS               FALSE

-#define STM32_TIM11_CHANNELS                2

-

-#define STM32_HAS_TIM1                      FALSE

-#define STM32_HAS_TIM5                      FALSE

-#define STM32_HAS_TIM8                      FALSE

-#define STM32_HAS_TIM12                     FALSE

-#define STM32_HAS_TIM13                     FALSE

-#define STM32_HAS_TIM14                     FALSE

-#define STM32_HAS_TIM15                     FALSE

-#define STM32_HAS_TIM16                     FALSE

-#define STM32_HAS_TIM17                     FALSE

-#define STM32_HAS_TIM18                     FALSE

-#define STM32_HAS_TIM19                     FALSE

-#define STM32_HAS_TIM20                     FALSE

-#define STM32_HAS_TIM21                     FALSE

-#define STM32_HAS_TIM22                     FALSE

-

-/* USART attributes.*/

-#define STM32_HAS_USART1                    TRUE

-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)

-

-#define STM32_HAS_USART2                    TRUE

-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

-

-#define STM32_HAS_USART3                    TRUE

-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

-

-#define STM32_HAS_UART4                     FALSE

-#define STM32_HAS_UART5                     FALSE

-#define STM32_HAS_USART6                    FALSE

-#define STM32_HAS_UART7                     FALSE

-#define STM32_HAS_UART8                     FALSE

-

-/* USB attributes.*/

-#define STM32_HAS_USB                       TRUE

-#define STM32_USB_ACCESS_SCHEME_2x16        FALSE

-#define STM32_USB_PMA_SIZE                  512

-#define STM32_USB_HAS_BCDR                  FALSE

-#define STM32_HAS_OTG1                      FALSE

-#define STM32_HAS_OTG2                      FALSE

-

-/* LTDC attributes.*/

-#define STM32_HAS_LTDC                      FALSE

-

-/* DMA2D attributes.*/

-#define STM32_HAS_DMA2D                     FALSE

-

-/* FSMC attributes.*/

-#define STM32_HAS_FSMC                      FALSE

-

-/* CRC attributes.*/

-#define STM32_HAS_CRC                       TRUE

-#define STM32_CRC_PROGRAMMABLE              FALSE

-

-#else /* STM32L1XX_HD */

-

-/* ADC attributes.*/

-#define STM32_HAS_ADC1                      TRUE

-#define STM32_HAS_ADC2                      FALSE

-#define STM32_HAS_ADC3                      FALSE

-#define STM32_HAS_ADC4                      FALSE

-

-/* CAN attributes.*/

-#define STM32_HAS_CAN1                      FALSE

-#define STM32_HAS_CAN2                      FALSE

-#define STM32_CAN_MAX_FILTERS               0

-

-/* DAC attributes.*/

-#define STM32_HAS_DAC1_CH1                  TRUE

-#define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID(1, 2)

-

-#define STM32_HAS_DAC1_CH2                  TRUE

-#define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID(1, 3)

-

-#define STM32_HAS_DAC2_CH1                  FALSE

-#define STM32_HAS_DAC2_CH2                  FALSE

-

-

-/* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  FALSE

-

-#define STM32_DMA_SUPPORTS_CSELR            FALSE

-#define STM32_DMA1_NUM_CHANNELS             7

-#define STM32_DMA1_CH1_HANDLER              Vector6C

-#define STM32_DMA1_CH2_HANDLER              Vector70

-#define STM32_DMA1_CH3_HANDLER              Vector74

-#define STM32_DMA1_CH4_HANDLER              Vector78

-#define STM32_DMA1_CH5_HANDLER              Vector7C

-#define STM32_DMA1_CH6_HANDLER              Vector80

-#define STM32_DMA1_CH7_HANDLER              Vector84

-#define STM32_DMA1_CH1_NUMBER               11

-#define STM32_DMA1_CH2_NUMBER               12

-#define STM32_DMA1_CH3_NUMBER               13

-#define STM32_DMA1_CH4_NUMBER               14

-#define STM32_DMA1_CH5_NUMBER               15

-#define STM32_DMA1_CH6_NUMBER               16

-#define STM32_DMA1_CH7_NUMBER               17

-

-#define STM32_DMA2_NUM_CHANNELS             5

-#define STM32_DMA2_CH1_HANDLER              Vector108

-#define STM32_DMA2_CH2_HANDLER              Vector10C

-#define STM32_DMA2_CH3_HANDLER              Vector110

-#define STM32_DMA2_CH4_HANDLER              Vector114

-#define STM32_DMA2_CH5_HANDLER              Vector118

-#define STM32_DMA2_CH1_NUMBER               50

-#define STM32_DMA2_CH2_NUMBER               51

-#define STM32_DMA2_CH3_NUMBER               52

-#define STM32_DMA2_CH4_NUMBER               53

-#define STM32_DMA2_CH5_NUMBER               54

-

-/* ETH attributes.*/

-#define STM32_HAS_ETH                       FALSE

-

-/* EXTI attributes.*/

-#define STM32_EXTI_NUM_LINES                24

-#define STM32_EXTI_IMR_MASK                 0x00000000U

-

-/* GPIO attributes.*/

 #define STM32_HAS_GPIOA                     TRUE

 #define STM32_HAS_GPIOB                     TRUE

 #define STM32_HAS_GPIOC                     TRUE

@@ -345,6 +170,7 @@
                                              RCC_AHBENR_GPIOFEN |           \

                                              RCC_AHBENR_GPIOGEN |           \

                                              RCC_AHBENR_GPIOHEN)

+#endif

 

 /* I2C attributes.*/

 #define STM32_HAS_I2C1                      TRUE

@@ -356,10 +182,15 @@
 #define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

 

 #define STM32_HAS_I2C3                      FALSE

+#define STM32_HAS_I2C4                      FALSE

 

 /* RTC attributes.*/

 #define STM32_HAS_RTC                       TRUE

+#if (STM32L1XX_PROD_CAT == 1) || defined(__DOXYGEN__)

+#define STM32_RTC_HAS_SUBSECONDS            FALSE

+#else

 #define STM32_RTC_HAS_SUBSECONDS            TRUE

+#endif

 #define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

 #define STM32_RTC_NUM_ALARMS                2

 #define STM32_RTC_HAS_INTERRUPTS            FALSE

@@ -376,9 +207,14 @@
 #define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

 #define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

 

+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) ||               \

+    defined(__DOXYGEN__)

+#define STM32_HAS_SPI3                      FALSE

+#else

 #define STM32_HAS_SPI3                      TRUE

 #define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)

 #define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)

+#endif

 

 #define STM32_HAS_SPI4                      FALSE

 #define STM32_HAS_SPI5                      FALSE

@@ -399,9 +235,14 @@
 #define STM32_TIM4_IS_32BITS                FALSE

 #define STM32_TIM4_CHANNELS                 4

 

+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) ||               \

+    defined(__DOXYGEN__)

+#define STM32_HAS_TIM5                      FALSE

+#else

 #define STM32_HAS_TIM5                      TRUE

 #define STM32_TIM5_IS_32BITS                TRUE

 #define STM32_TIM5_CHANNELS                 4

+#endif

 

 #define STM32_HAS_TIM6                      TRUE

 #define STM32_TIM6_IS_32BITS                FALSE

@@ -450,6 +291,11 @@
 #define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

 #define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

 

+#if (STM32L1XX_PROD_CAT == 1) || (STM32L1XX_PROD_CAT == 2) ||               \

+    (STM32L1XX_PROD_CAT == 3) || defined(__DOXYGEN__)

+#define STM32_HAS_UART4                     FALSE

+#define STM32_HAS_UART5                     FALSE

+#else

 #define STM32_HAS_UART4                     TRUE

 #define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)

 #define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)

@@ -457,8 +303,11 @@
 #define STM32_HAS_UART5                     TRUE

 #define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 2)

 #define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 1)

+#endif

 

 #define STM32_HAS_USART6                    FALSE

+#define STM32_HAS_UART7                     FALSE

+#define STM32_HAS_UART8                     FALSE

 

 /* USB attributes.*/

 #define STM32_HAS_USB                       TRUE

@@ -481,8 +330,6 @@
 #define STM32_HAS_CRC                       TRUE

 #define STM32_CRC_PROGRAMMABLE              FALSE

 

-#endif /* STM32L1XX_HD */

-

 /** @} */

 

 #endif /* _STM32_REGISTRY_H_ */