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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-15 09:49:21 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-15 09:49:21 +0000 |
| commit | 446f34f3363f041569f80797ce4397faa1ef1e70 (patch) | |
| tree | d8bacdd8c595b7b9f10949585dee21dcaf2a1a6a /os | |
| parent | 2211987fdbd728612e3e8b4a659a104fb23c78f1 (diff) | |
| download | ChibiOS-446f34f3363f041569f80797ce4397faa1ef1e70.tar.gz ChibiOS-446f34f3363f041569f80797ce4397faa1ef1e70.tar.bz2 ChibiOS-446f34f3363f041569f80797ce4397faa1ef1e70.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5183 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/SPC56ELxx/hal_lld.c | 26 | ||||
| -rw-r--r-- | os/hal/platforms/SPC56ELxx/hal_lld.h | 7 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC56ELxx/core.s | 38 |
3 files changed, 33 insertions, 38 deletions
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c index af465bf92..ffd2121bc 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.c +++ b/os/hal/platforms/SPC56ELxx/hal_lld.c @@ -109,6 +109,32 @@ void spc_early_init(void) { #if !SPC5_NO_INIT
+#if SPC5_DISABLE_WATCHDOG
+ /* SWT disabled.*/
+ SWT.SR.R = 0xC520;
+ SWT.SR.R = 0xD928;
+ SWT.CR.R = 0xFF00000A;
+#endif
+
+ /* Enabling peripheral bridges to allow any operation.*/
+ AIPS.MPROT.R = 0x77777777;
+ AIPS.PACR0_7.R = 0;
+ AIPS.PACR8_15.R = 0;
+ AIPS.PACR16_23.R = 0;
+ AIPS.PACR24_31.R = 0;
+ AIPS.OPACR0_7.R = 0;
+ AIPS.OPACR8_15.R = 0;
+ AIPS.OPACR16_23.R = 0;
+ AIPS.OPACR24_31.R = 0;
+ AIPS.OPACR32_39.R = 0;
+ AIPS.OPACR40_47.R = 0;
+ AIPS.OPACR48_55.R = 0;
+ AIPS.OPACR56_63.R = 0;
+ AIPS.OPACR64_71.R = 0;
+ AIPS.OPACR72_79.R = 0;
+ AIPS.OPACR80_87.R = 0;
+ AIPS.OPACR88_95.R = 0;
+
/* SSCM initialization. Setting up the most restrictive handling of
invalid accesses to peripherals.*/
SSCM.ERROR.R = 3; /* PAE and RAE bits. */
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h index 7e0fb8aae..06970bec0 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.h +++ b/os/hal/platforms/SPC56ELxx/hal_lld.h @@ -242,6 +242,13 @@ #endif
/**
+ * @brief Disables the watchdog on start.
+ */
+#if !defined(SPC5_DISABLE_WATCHDOG) || defined(__DOXYGEN__)
+#define SPC5_DISABLE_WATCHDOG TRUE
+#endif
+
+/**
* @brief FMPLL0 Clock source.
*/
#if !defined(SPC5_FMPLL0_CLK_SRC) || defined(__DOXYGEN__)
diff --git a/os/ports/GCC/PPC/SPC56ELxx/core.s b/os/ports/GCC/PPC/SPC56ELxx/core.s index adeb9b953..a774f0464 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/core.s +++ b/os/ports/GCC/PPC/SPC56ELxx/core.s @@ -332,44 +332,6 @@ _coreinit: tlbwe
/*
- * PBRIDGE programmed to allow all accesses from user mode.
- */
- lis %r7, 0xFFF0
- lis %r3, 0x7777
- ori %r3, %r3, 0x7777
- stw %r3, 0(%r7) /* MPROT */
- li %r3, 0
- stw %r3, 32(%r7) /* PACR */
- stw %r3, 36(%r7)
- stw %r3, 40(%r7)
- stw %r3, 44(%r7)
- stw %r3, 64(%r7) /* OPACR */
- stw %r3, 68(%r7)
- stw %r3, 72(%r7)
- stw %r3, 76(%r7)
- stw %r3, 80(%r7)
- stw %r3, 84(%r7)
- stw %r3, 88(%r7)
- stw %r3, 92(%r7)
- stw %r3, 96(%r7)
- stw %r3, 100(%r7)
- stw %r3, 104(%r7)
- stw %r3, 108(%r7)
-
-e_lis r6,0xfff3
-e_or2i r6,0x8010
-e_li r7,0xC520
-se_stw r7,0x0(r6)
-e_li r7,0xD928
-se_stw r7,0x0(r6)
-
-e_lis r6,0xfff3
-e_or2i r6,0x8000
-e_lis r7,0xff00
-e_or2i r7,0x10A
-se_stw r7,0x0(r6) /* # WEN = 0 */
-
- /*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
|