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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-14 09:12:42 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-14 09:12:42 +0000 |
| commit | 3f53115539e279a12f04ce07ef9f021bfee310fa (patch) | |
| tree | 704ddb761770cbe71f1608e032db3b535d9eb42e /os | |
| parent | 3868c8bc2c476a7d77400b39103c5fcca5697145 (diff) | |
| download | ChibiOS-3f53115539e279a12f04ce07ef9f021bfee310fa.tar.gz ChibiOS-3f53115539e279a12f04ce07ef9f021bfee310fa.tar.bz2 ChibiOS-3f53115539e279a12f04ce07ef9f021bfee310fa.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8488 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_L053R8/board.h | 26 | ||||
| -rw-r--r-- | os/hal/boards/ST_NUCLEO_L053R8/cfg/board.chcfg | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/hal_lld.h | 15 |
3 files changed, 20 insertions, 23 deletions
diff --git a/os/hal/boards/ST_NUCLEO_L053R8/board.h b/os/hal/boards/ST_NUCLEO_L053R8/board.h index 863160d17..9a9035ba4 100644 --- a/os/hal/boards/ST_NUCLEO_L053R8/board.h +++ b/os/hal/boards/ST_NUCLEO_L053R8/board.h @@ -29,11 +29,10 @@ /*
* Board oscillators-related settings.
- * NOTE: LSE not fitted.
* NOTE: HSE not fitted.
*/
#if !defined(STM32_LSECLK)
-#define STM32_LSECLK 0U
+#define STM32_LSECLK 32768U
#endif
#define STM32_LSEDRV (3U << 11U)
@@ -138,23 +137,6 @@ #define GPIOH_PIN15 15U
/*
- * IO lines assignments.
- */
-#define LINE_USART_TX PAL_LINE(GPIOA, 2U)
-#define LINE_USART_RX PAL_LINE(GPIOA, 3U)
-#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U)
-#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
-#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
-
-#define LINE_SWO PAL_LINE(GPIOB, 3U)
-
-#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
-
-
-#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
-#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
-
-/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
@@ -167,10 +149,10 @@ #define PIN_ODR_HIGH(n) (1U << (n))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
-#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
-#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
-#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
diff --git a/os/hal/boards/ST_NUCLEO_L053R8/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO_L053R8/cfg/board.chcfg index b257ff9bb..e5ad052a5 100644 --- a/os/hal/boards/ST_NUCLEO_L053R8/cfg/board.chcfg +++ b/os/hal/boards/ST_NUCLEO_L053R8/cfg/board.chcfg @@ -12,7 +12,7 @@ <board_id>ST_NUCLEO_L053R8</board_id> <board_functions></board_functions> <subtype>STM32L053xx</subtype> - <clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0" + <clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="32768" LSEBypass="false" LSEDrive="3 High Drive (default)" /> <ports> <GPIOA> diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/os/hal/ports/STM32/STM32L0xx/hal_lld.h index 766677575..31241386b 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.h @@ -497,6 +497,21 @@ #error "Using a wrong mcuconf.h file, STM32L0xx_MCUCONF not defined"
#endif
+/*
+ * Board files sanity checks.
+ */
+#if !defined(STM32_LSECLK)
+#error "STM32_LSECLK not defined in board.h"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined in board.h"
+#endif
+
+#if !defined(STM32_HSECLK)
+#error "STM32_HSECLK not defined in board.h"
+#endif
+
/* Voltage related limits.*/
#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
/**
|