git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5871 35acf78f-673a-0410-8e92-d51de3d6d3f4

6 files changed, 12 insertions, 42 deletions

diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
index ebcf5fef5..abe7124a4 100644
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
@@ -123,7 +123,7 @@
 

 #define SPC5_EMIOS0_CLK                     (halSPCGetSystemClock() /         \

                                              SPC5_PERIPHERAL3_CLK_DIV_VALUE / \

-                                             SPC5_EMIOS0_GLOBAL_PRESCALER)

+                                             SPC5_EMIOS0_GPRE_VALUE)

 

 

 #define SPC5_HAS_EMIOS1                     TRUE

@@ -159,7 +159,7 @@
 

 #define SPC5_EMIOS1_CLK                     (halSPCGetSystemClock() /         \

                                              SPC5_PERIPHERAL3_CLK_DIV_VALUE / \

-                                             SPC5_EMIOS1_GLOBAL_PRESCALER)

+                                             SPC5_EMIOS1_GPRE_VALUE)

 

 /* FlexCAN attributes.*/

 #define SPC5_HAS_FLEXCAN0                                   TRUE

diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h
index 3ed21cb84..019f9dfb0 100644
--- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h
+++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h
@@ -121,7 +121,7 @@
 #define SPC5_EMIOS_FLAG_F23_NUMBER          209

 

 #define SPC5_EMIOS_CLK                      (SPC5_SYSCLK /                  \

-                                             SPC5_EMIOS_GLOBAL_PRESCALER)

+                                             SPC5_EMIOS_GPRE_VALUE)

 #define SPC5_EMIOS_ENABLE_CLOCK()

 #define SPC5_EMIOS_DISABLE_CLOCK()

 /** @} */

diff --git a/os/hal/platforms/SPC564Axx/spc564a_registry.h b/os/hal/platforms/SPC564Axx/spc564a_registry.h
index 42ba13741..443782d2a 100644
--- a/os/hal/platforms/SPC564Axx/spc564a_registry.h
+++ b/os/hal/platforms/SPC564Axx/spc564a_registry.h
@@ -162,7 +162,7 @@
 #define SPC5_EMIOS_FLAG_F23_NUMBER          209

 

 #define SPC5_EMIOS_CLK                      (SPC5_SYSCLK /                  \

-                                             SPC5_EMIOS_GLOBAL_PRESCALER)

+                                             SPC5_EMIOS_GPRE_VALUE)

 #define SPC5_EMIOS_ENABLE_CLOCK()

 #define SPC5_EMIOS_DISABLE_CLOCK()

 /** @} */

diff --git a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c
index 0533b50e3..d5c984434 100644
--- a/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c
+++ b/os/hal/platforms/SPC5xx/eMIOS200_v1/spc5_emios.c
@@ -74,7 +74,7 @@ void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) {
     /* Disable all unified channels.*/

     if (icup != NULL) {

       icup->emiosp->MCR.B.GPREN = 0;

-      icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);

+      icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GPRE_VALUE);

       icup->emiosp->MCR.R |= EMIOSMCR_GPREN;

 

       icup->emiosp->MCR.B.GTBE = 1U;

@@ -83,7 +83,7 @@ void active_emios_clock(ICUDriver *icup, PWMDriver *pwmp) {
 

     } else if (pwmp != NULL) {

       pwmp->emiosp->MCR.B.GPREN = 0;

-      pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GLOBAL_PRESCALER);

+      pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS_GPRE_VALUE);

       pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;

 

       pwmp->emiosp->MCR.B.GTBE = 1U;

diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
index a8167c69c..2e87c9ab1 100644
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
+++ b/os/hal/platforms/SPC5xx/eMIOS_v1/icu_lld.c
@@ -161,7 +161,7 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
       icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVFLC;

       _icu_isr_invoke_overflow_cb(icup);

     }

-    if (sr && EMIOSS_FLAG){

+    if (sr && EMIOSS_FLAG) {

       icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_FLAGC;

       if (icup->config->mode == ICU_INPUT_ACTIVE_HIGH) {

         if (icup->emiosp->CH[icup->ch_number].CSR.B.UCIN == 1U  &&        \

@@ -191,7 +191,7 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) {
         }

       }

     }

-    if(sr && EMIOSS_OVR){

+    if (sr && EMIOSS_OVR) {

       icup->emiosp->CH[icup->ch_number].CSR.R |= EMIOSS_OVRC;

     }

 

@@ -489,9 +489,6 @@ void icu_lld_init(void) {
  */

 void icu_lld_start(ICUDriver *icup) {

 

-  //uint32_t emios0_active_channels = get_emios0_active_channels();

-  //uint32_t emios1_active_channels = get_emios1_active_channels();

-

   chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_start(), #1",

                 "too many channels");

 

@@ -568,23 +565,12 @@ void icu_lld_start(ICUDriver *icup) {
               ((psc == 1) || (psc == 2) || (psc == 3) || (psc == 4)),

               "icu_lld_start(), #1", "invalid frequency");

 

-  //icup->emiosp->MCR.B.GPREN = 0;

   icup->emiosp->CH[icup->ch_number].CCR.B.UCPEN = 0;

   icup->emiosp->CH[icup->ch_number].CCR.R |=

       EMIOSC_BSL(EMIOS_BSL_INTERNAL_COUNTER) |

       EMIOSC_EDSEL | EMIOS_CCR_MODE_SAIC;

   icup->emiosp->CH[icup->ch_number].CCR.B.UCPRE = psc - 1;

   icup->emiosp->CH[icup->ch_number].CCR.R |= EMIOSC_UCPREN;

-  /*

-  if (icup->emiosp == &EMIOS_0) {

-    icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);

-  } else if (icup->emiosp == &EMIOS_1) {

-    icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);

-  }

-  icup->emiosp->MCR.R |= EMIOSMCR_GPREN;

-

-  icup->emiosp->MCR.B.GTBE = 1U;

-  */

 

   /* Set source polarity.*/

   if(icup->config->mode == ICU_INPUT_ACTIVE_HIGH){

@@ -612,9 +598,6 @@ void icu_lld_start(ICUDriver *icup) {
  */

 void icu_lld_stop(ICUDriver *icup) {

 

-  //uint32_t emios0_active_channels = get_emios0_active_channels();

-  //uint32_t emios1_active_channels = get_emios1_active_channels();

-

   chDbgAssert(get_emios0_active_channels() < 28, "icu_lld_stop(), #1",

               "too many channels");

   chDbgAssert(get_emios1_active_channels() < 28, "icu_lld_stop(), #2",

@@ -746,15 +729,6 @@ void icu_lld_enable(ICUDriver *icup) {
     icup->emiosp->CH[icup->ch_number].CCR.B.FEN = 1U;

   }

 

-

-

-  /* Enable Global Time Base.*/

-  /*

-  if (icup->emiosp->MCR.B.GTBE == 0) {

-    icup->emiosp->MCR.B.GTBE = 1U;

-  }

-  */

-

 }

 

 /**

diff --git a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
index 20ce38773..0d65a19c0 100644
--- a/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
+++ b/os/hal/platforms/SPC5xx/eMIOS_v1/spc5_emios.c
@@ -92,7 +92,7 @@ void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
     /* Disable all unified channels.*/

     if (icup != NULL) {

       icup->emiosp->MCR.B.GPREN = 0;

-      icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);

+      icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);

       icup->emiosp->MCR.R |= EMIOSMCR_GPREN;

 

       icup->emiosp->MCR.B.GTBE = 1U;

@@ -101,7 +101,7 @@ void active_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
 

     } else if (pwmp != NULL) {

       pwmp->emiosp->MCR.B.GPREN = 0;

-      pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GLOBAL_PRESCALER);

+      pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS0_GPRE_VALUE);

       pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;

 

       pwmp->emiosp->MCR.B.GTBE = 1U;

@@ -122,7 +122,7 @@ void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
     /* Disable all unified channels.*/

     if (icup != NULL) {

       icup->emiosp->MCR.B.GPREN = 0;

-      icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);

+      icup->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);

       icup->emiosp->MCR.R |= EMIOSMCR_GPREN;

 

       icup->emiosp->MCR.B.GTBE = 1U;

@@ -131,7 +131,7 @@ void active_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
 

     } else if (pwmp != NULL) {

       pwmp->emiosp->MCR.B.GPREN = 0;

-      pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GLOBAL_PRESCALER);

+      pwmp->emiosp->MCR.R = EMIOSMCR_GPRE(SPC5_EMIOS1_GPRE_VALUE);

       pwmp->emiosp->MCR.R |= EMIOSMCR_GPREN;

 

       pwmp->emiosp->MCR.B.GTBE = 1U;

@@ -148,13 +148,11 @@ void deactive_emios0_clock(ICUDriver *icup, PWMDriver *pwmp) {
   if (emios0_active_channels == 0) {

     if (icup != NULL) {

       if (icup->emiosp->UCDIS.R == 0) {

-        //icup->emiosp->MCR.B.MDIS = 0;

         halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,

                                      SPC5_EMIOS0_STOP_PCTL);

       }

     } else if (pwmp != NULL) {

       if (pwmp->emiosp->UCDIS.R == 0) {

-        //pwmp->emiosp->MCR.B.MDIS = 0;

         halSPCSetPeripheralClockMode(SPC5_EMIOS0_PCTL,

                                      SPC5_EMIOS0_STOP_PCTL);

       }

@@ -167,13 +165,11 @@ void deactive_emios1_clock(ICUDriver *icup, PWMDriver *pwmp) {
   if (emios1_active_channels == 0) {

     if (icup != NULL) {

       if (icup->emiosp->UCDIS.R == 0) {

-        //icup->emiosp->MCR.B.MDIS = 0;

         halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,

                                      SPC5_EMIOS1_STOP_PCTL);

       }

     } else if (pwmp != NULL) {

       if (pwmp->emiosp->UCDIS.R == 0) {

-        //pwmp->emiosp->MCR.B.MDIS = 0;

         halSPCSetPeripheralClockMode(SPC5_EMIOS1_PCTL,

                                      SPC5_EMIOS1_STOP_PCTL);

       }