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authorGiovanni Di Sirio <gdisirio@gmail.com>2015-03-27 10:38:28 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2015-03-27 10:38:28 +0000
commit1d8b2028ac669b9409737c7a8797f281cd41a978 (patch)
tree66f6945a878275e25f8964571afd7401ccf57f14 /os
parent3eb264f5b9653764e690af7450e09b5de92dfd2a (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7818 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
-rw-r--r--os/rt/ports/ARM/chcore.h14
1 files changed, 10 insertions, 4 deletions
diff --git a/os/rt/ports/ARM/chcore.h b/os/rt/ports/ARM/chcore.h
index 9f255ccd2..b660323c7 100644
--- a/os/rt/ports/ARM/chcore.h
+++ b/os/rt/ports/ARM/chcore.h
@@ -268,6 +268,12 @@ struct context {
((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
/**
+ * @brief Priority level verification macro.
+ * @todo Add the required parameters to armparams.h.
+ */
+#define PORT_IRQ_IS_VALID_PRIORITY(n) false
+
+/**
* @brief IRQ prologue code.
* @details This macro must be inserted at the start of all IRQ handlers
* enabled to invoke system APIs.
@@ -474,10 +480,10 @@ static inline void port_disable(void) {
__asm volatile ("bl _port_disable_thumb" : : : "r3", "lr", "memory");
#else
__asm volatile ("mrs r3, CPSR \n\t"
- "orr r3, #0x80 \n\t"
- "msr CPSR_c, r3 \n\t"
- "orr r3, #0x40 \n\t"
- "msr CPSR_c, r3" : : : "r3", "memory");
+ "orr r3, #0x80 \n\t"
+ "msr CPSR_c, r3 \n\t"
+ "orr r3, #0x40 \n\t"
+ "msr CPSR_c, r3" : : : "r3", "memory");
#endif
}