diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-14 10:48:54 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-14 10:48:54 +0000 |
| commit | 18078ccb46bbfa98c405deaa2d0f0c7c74d5c00d (patch) | |
| tree | 31d22abdf8623094a79150e0ce4dd557a1125b67 /os | |
| parent | 6a21d25cb55110ba179ee3ffe9e559102ad470a3 (diff) | |
| download | ChibiOS-18078ccb46bbfa98c405deaa2d0f0c7c74d5c00d.tar.gz ChibiOS-18078ccb46bbfa98c405deaa2d0f0c7c74d5c00d.tar.bz2 ChibiOS-18078ccb46bbfa98c405deaa2d0f0c7c74d5c00d.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5179 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os')
| -rw-r--r-- | os/hal/platforms/SPC56ELxx/hal_lld.c | 24 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC56ELxx/core.s | 197 |
2 files changed, 130 insertions, 91 deletions
diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c index 32915f161..d31e91f75 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.c +++ b/os/hal/platforms/SPC56ELxx/hal_lld.c @@ -118,8 +118,28 @@ void spc_early_init(void) { invalid accesses to peripherals.*/
SSCM.ERROR.R = 3; /* PAE and RAE bits. */
+ /* FCCU CF errors clearing.*/
+ FCCU.CFK.R = 0x618B7A50;
+ FCCU.CFS[0].R = 0xFFFFFFFF;
+ while (FCCU.CTRL.B.OPS != 3)
+ ;
+ FCCU.CFK.R = 0x618B7A50;
+ FCCU.CFS[1].R = 0xFFFFFFFF;
+ while (FCCU.CTRL.B.OPS != 3)
+ ;
+
+ /* FCCU NCF errors clearing.*/
+ FCCU.NCFK.R = 0xAB3498FE;
+ FCCU.NCFS[0].R = 0xFFFFFFFF;
+ while (FCCU.CTRL.B.OPS != 3)
+ ;
+
+ /* RGM errors clearing.*/
+ RGM.FES.R = 0xFFFF;
+ RGM.DES.R = 0xFFFF;
+
/* Enabling peripheral bridges to allow any operation.*/
- AIPS.MPROT.R = 0x77777777;
+/* AIPS.MPROT.R = 0x77777777;
AIPS.PACR0_7.R = 0;
AIPS.PACR8_15.R = 0;
AIPS.PACR16_23.R = 0;
@@ -135,7 +155,7 @@ void spc_early_init(void) { AIPS.OPACR64_71.R = 0;
AIPS.OPACR72_79.R = 0;
AIPS.OPACR80_87.R = 0;
- AIPS.OPACR88_95.R = 0;
+ AIPS.OPACR88_95.R = 0;*/
/* The system must be in DRUN mode on entry, if this is not the case then
it is considered a serious anomaly.*/
diff --git a/os/ports/GCC/PPC/SPC56ELxx/core.s b/os/ports/GCC/PPC/SPC56ELxx/core.s index cb25acf7c..a0565e09c 100644 --- a/os/ports/GCC/PPC/SPC56ELxx/core.s +++ b/os/ports/GCC/PPC/SPC56ELxx/core.s @@ -169,95 +169,6 @@ .type _coreinit, @function
_coreinit:
/*
- * RAM clearing, this device requires a write to all RAM location in
- * order to initialize the ECC detection hardware, this is going to
- * slow down the startup but there is no way around.
- */
-.clear_ecc:
- xor %r0, %r0, %r0
- xor %r1, %r1, %r1
- xor %r2, %r2, %r2
- xor %r3, %r3, %r3
- xor %r4, %r4, %r4
- xor %r5, %r5, %r5
- xor %r6, %r6, %r6
- xor %r7, %r7, %r7
- xor %r8, %r8, %r8
- xor %r9, %r9, %r9
- xor %r10, %r10, %r10
- xor %r11, %r11, %r11
- xor %r12, %r12, %r12
- xor %r13, %r13, %r13
- xor %r14, %r14, %r14
- xor %r15, %r15, %r15
- xor %r16, %r16, %r16
- xor %r17, %r17, %r17
- xor %r18, %r18, %r18
- xor %r19, %r19, %r19
- xor %r20, %r20, %r20
- xor %r21, %r21, %r21
- xor %r22, %r22, %r22
- xor %r23, %r23, %r23
- xor %r24, %r24, %r24
- xor %r25, %r25, %r25
- xor %r26, %r26, %r26
- xor %r27, %r27, %r27
- xor %r28, %r28, %r28
- xor %r29, %r29, %r29
- xor %r30, %r30, %r30
- xor %r31, %r31, %r31
- lis %r4, __ram_start__@h
- ori %r4, %r4, __ram_start__@l
- lis %r5, __ram_end__@h
- ori %r5, %r5, __ram_end__@l
-.cleareccloop:
- cmpl %cr0, %r4, %r5
- bge %cr0, .cleareccend
- stmw %r16, 0(%r4)
- addi %r4, %r4, 64
- b .cleareccloop
-.cleareccend:
-
- /*
- * Special function registers clearing, required in order to avoid
- * possible problems with lockstep mode.
- */
- mtcrf 0xFF, %r31
- mtspr 9, %r31 /* CTR */
- mtspr 22, %r31 /* DEC */
- mtspr 26, %r31 /* SRR0-1 */
- mtspr 27, %r31
- mtspr 54, %r31 /* DECAR */
- mtspr 58, %r31 /* CSRR0-1 */
- mtspr 59, %r31
- mtspr 61, %r31 /* DEAR */
- mtspr 256, %r31 /* USPRG0 */
- mtspr 272, %r31 /* SPRG1-7 */
- mtspr 273, %r31
- mtspr 274, %r31
- mtspr 275, %r31
- mtspr 276, %r31
- mtspr 277, %r31
- mtspr 278, %r31
- mtspr 279, %r31
- mtspr 285, %r31 /* TBU */
- mtspr 284, %r31 /* TBL */
- mtspr 318, %r31 /* DVC1-2 */
- mtspr 319, %r31
- mtspr 562, %r31 /* DBCNT */
- mtspr 570, %r31 /* MCSRR0 */
- mtspr 571, %r31 /* MCSRR1 */
- mtspr 604, %r31 /* SPRG8-9 */
- mtspr 605, %r31
-
- /*
- * MSR initialization.
- */
- lis %r3, MSR_DEFAULT@h
- ori %r3, %r3, MSR_DEFAULT@l
- mtMSR %r3
-
- /*
* TLB0 allocated to flash.
*/
lis %r3, TLB0_MAS0@h
@@ -366,6 +277,114 @@ _coreinit: tlbwe
/*
+ * Enabling peripheral bridges to allow all operations from all
+ * masters. Required in order to enable the following accesses to
+ * peripherals.
+ */
+ lis %r7, 0xFFF0
+ lis %r3, 0x7777
+ ori %r3, %r3, 0x7777
+ stw %r3, 0(%r7) /* MPROT */
+ li %r3, 0
+ stw %r3, 32(%r7) /* PACR */
+ stw %r3, 36(%r7)
+ stw %r3, 40(%r7)
+ stw %r3, 44(%r7)
+ stw %r3, 64(%r7) /* OPACR */
+ stw %r3, 68(%r7)
+ stw %r3, 72(%r7)
+ stw %r3, 76(%r7)
+ stw %r3, 80(%r7)
+ stw %r3, 84(%r7)
+ stw %r3, 88(%r7)
+ stw %r3, 92(%r7)
+ stw %r3, 96(%r7)
+ stw %r3, 100(%r7)
+ stw %r3, 104(%r7)
+ stw %r3, 108(%r7)
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Special function registers clearing, required in order to avoid
+ * possible problems with lockstep mode.
+ */
+ mtcrf 0xFF, %r31
+ mtspr 9, %r31 /* CTR */
+ mtspr 22, %r31 /* DEC */
+ mtspr 26, %r31 /* SRR0-1 */
+ mtspr 27, %r31
+ mtspr 54, %r31 /* DECAR */
+ mtspr 58, %r31 /* CSRR0-1 */
+ mtspr 59, %r31
+ mtspr 61, %r31 /* DEAR */
+ mtspr 256, %r31 /* USPRG0 */
+ mtspr 272, %r31 /* SPRG1-7 */
+ mtspr 273, %r31
+ mtspr 274, %r31
+ mtspr 275, %r31
+ mtspr 276, %r31
+ mtspr 277, %r31
+ mtspr 278, %r31
+ mtspr 279, %r31
+ mtspr 285, %r31 /* TBU */
+ mtspr 284, %r31 /* TBL */
+ mtspr 318, %r31 /* DVC1-2 */
+ mtspr 319, %r31
+ mtspr 562, %r31 /* DBCNT */
+ mtspr 570, %r31 /* MCSRR0 */
+ mtspr 571, %r31 /* MCSRR1 */
+ mtspr 604, %r31 /* SPRG8-9 */
+ mtspr 605, %r31
+
+ /*
* Cache enabled.
*/
mfspr %r3, 1011 /* LICSR1 */
|