Lots of MISRA-related changes in RT. Not finished yet.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7715 35acf78f-673a-0410-8e92-d51de3d6d3f4

7 files changed, 103 insertions, 102 deletions

diff --git a/os/rt/ports/ARM/compilers/GCC/chtypes.h b/os/rt/ports/ARM/compilers/GCC/chtypes.h
index c9a827dca..72674a53f 100644
--- a/os/rt/ports/ARM/compilers/GCC/chtypes.h
+++ b/os/rt/ports/ARM/compilers/GCC/chtypes.h
@@ -46,7 +46,7 @@
  * @brief   Generic 'true' boolean constant.

  */

 #if !defined(TRUE) || defined(__DOXYGEN__)

-#define TRUE                (!FALSE)

+#define TRUE                1

 #endif

 /** @} */

 

diff --git a/os/rt/ports/ARMCMx/chcore.h b/os/rt/ports/ARMCMx/chcore.h
index 4a8ebb324..23f33a6f8 100644
--- a/os/rt/ports/ARMCMx/chcore.h
+++ b/os/rt/ports/ARMCMx/chcore.h
@@ -179,7 +179,7 @@ struct context {
 /**

  * @brief   Total priority levels.

  */

-#define CORTEX_PRIORITY_LEVELS          (1 << CORTEX_PRIORITY_BITS)

+#define CORTEX_PRIORITY_LEVELS          (1U << CORTEX_PRIORITY_BITS)

 

 /**

  * @brief   Minimum priority level.

@@ -192,7 +192,7 @@ struct context {
  * @brief   Maximum priority level.

  * @details The maximum allowed priority level is always zero.

  */

-#define CORTEX_MAXIMUM_PRIORITY         0

+#define CORTEX_MAXIMUM_PRIORITY         0U

 

 /**

  * @brief   Priority level verification macro.

@@ -210,7 +210,7 @@ struct context {
  * @brief   Priority level to priority mask conversion macro.

  */

 #define CORTEX_PRIO_MASK(n)                                                 \

-  ((n) << (8 - CORTEX_PRIORITY_BITS))

+  ((n) << (8U - (unsigned)CORTEX_PRIORITY_BITS))

 

 /*===========================================================================*/

 /* External declarations.                                                    */

@@ -231,11 +231,11 @@ struct context {
 #if !defined(_FROM_ASM_)

 

 #if CH_CFG_ST_TIMEDELTA > 0

-#if !PORT_USE_ALT_TIMER

+#if PORT_USE_ALT_TIMER == FALSE

 #include "chcore_timer.h"

-#else /* PORT_USE_ALT_TIMER */

+#else /* PORT_USE_ALT_TIMER != FALSE */

 #include "chcore_timer_alt.h"

-#endif /* PORT_USE_ALT_TIMER */

+#endif /* PORT_USE_ALT_TIMER != FALSE */

 #endif /* CH_CFG_ST_TIMEDELTA > 0 */

 

 #endif /* !defined(_FROM_ASM_) */

diff --git a/os/rt/ports/ARMCMx/chcore_v6m.h b/os/rt/ports/ARMCMx/chcore_v6m.h
index 3ded54449..3c28c0f54 100644
--- a/os/rt/ports/ARMCMx/chcore_v6m.h
+++ b/os/rt/ports/ARMCMx/chcore_v6m.h
@@ -33,42 +33,6 @@
 /*===========================================================================*/

 

 /**

- * @name    Architecture and Compiler

- * @{

- */

-#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)

-/**

- * @brief   Macro defining the specific ARM architecture.

- */

-#define PORT_ARCHITECTURE_ARM_v6M

-

-/**

- * @brief   Name of the implemented architecture.

- */

-#define PORT_ARCHITECTURE_NAME          "ARMv6-M"

-

-/**

- * @brief   Name of the architecture variant.

- */

-#define PORT_CORE_VARIANT_NAME          "Cortex-M0"

-

-#elif (CORTEX_MODEL == CORTEX_M0PLUS)

-#define PORT_ARCHITECTURE_ARM_v6M

-#define PORT_ARCHITECTURE_NAME          "ARMv6-M"

-#define PORT_CORE_VARIANT_NAME          "Cortex-M0+"

-#endif

-

-/**

- * @brief   Port-specific information string.

- */

-#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)

-#define PORT_INFO                       "Preemption through NMI"

-#else

-#define PORT_INFO                       "Preemption through PendSV"

-#endif

-/** @} */

-

-/**

  * @brief   This port does not support a realtime counter.

  */

 #define PORT_SUPPORTS_RT                FALSE

@@ -132,6 +96,42 @@
 /*===========================================================================*/

 

 /**

+ * @name    Architecture and Compiler

+ * @{

+ */

+#if (CORTEX_MODEL == CORTEX_M0) || defined(__DOXYGEN__)

+/**

+ * @brief   Macro defining the specific ARM architecture.

+ */

+#define PORT_ARCHITECTURE_ARM_v6M

+

+/**

+ * @brief   Name of the implemented architecture.

+ */

+#define PORT_ARCHITECTURE_NAME          "ARMv6-M"

+

+/**

+ * @brief   Name of the architecture variant.

+ */

+#define PORT_CORE_VARIANT_NAME          "Cortex-M0"

+

+#elif (CORTEX_MODEL == CORTEX_M0PLUS)

+#define PORT_ARCHITECTURE_ARM_v6M

+#define PORT_ARCHITECTURE_NAME          "ARMv6-M"

+#define PORT_CORE_VARIANT_NAME          "Cortex-M0+"

+#endif

+

+/**

+ * @brief   Port-specific information string.

+ */

+#if !CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)

+#define PORT_INFO                       "Preemption through NMI"

+#else

+#define PORT_INFO                       "Preemption through PendSV"

+#endif

+/** @} */

+

+/**

  * @brief   Maximum usable priority for normal ISRs.

  */

 #if CORTEX_ALTERNATE_SWITCH || defined(__DOXYGEN__)

diff --git a/os/rt/ports/ARMCMx/chcore_v7m.h b/os/rt/ports/ARMCMx/chcore_v7m.h
index 80faaefc9..3d72723fb 100644
--- a/os/rt/ports/ARMCMx/chcore_v7m.h
+++ b/os/rt/ports/ARMCMx/chcore_v7m.h
@@ -33,46 +33,6 @@
 /*===========================================================================*/

 

 /**

- * @name    Architecture and Compiler

- * @{

- */

-#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

-/**

- * @brief   Macro defining the specific ARM architecture.

- */

-#define PORT_ARCHITECTURE_ARM_v7M

-

-/**

- * @brief   Name of the implemented architecture.

- */

-#define PORT_ARCHITECTURE_NAME          "ARMv7-M"

-

-/**

- * @brief   Name of the architecture variant.

- */

-#define PORT_CORE_VARIANT_NAME          "Cortex-M3"

-

-#elif (CORTEX_MODEL == CORTEX_M4)

-#define PORT_ARCHITECTURE_ARM_v7ME

-#define PORT_ARCHITECTURE_NAME          "ARMv7-ME"

-#if CORTEX_USE_FPU

-#define PORT_CORE_VARIANT_NAME          "Cortex-M4F"

-#else

-#define PORT_CORE_VARIANT_NAME          "Cortex-M4"

-#endif

-#endif

-

-/**

- * @brief   Port-specific information string.

- */

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

-#define PORT_INFO                       "Advanced kernel mode"

-#else

-#define PORT_INFO                       "Compact kernel mode"

-#endif

-/** @} */

-

-/**

  * @brief   This port supports a realtime counter.

  */

 #define PORT_SUPPORTS_RT                TRUE

@@ -80,7 +40,7 @@
 /**

  * @brief   Disabled value for BASEPRI register.

  */

-#define CORTEX_BASEPRI_DISABLED         0

+#define CORTEX_BASEPRI_DISABLED         0U

 

 /*===========================================================================*/

 /* Module pre-compile time settings.                                         */

@@ -149,7 +109,7 @@
  *          priority level.

  */

 #if !defined(CORTEX_PRIORITY_SVCALL)

-#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1)

+#define CORTEX_PRIORITY_SVCALL          (CORTEX_MAXIMUM_PRIORITY + 1U)

 #elif !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL)

 /* If it is externally redefined then better perform a validity check on it.*/

 #error "invalid priority level specified for CORTEX_PRIORITY_SVCALL"

@@ -159,7 +119,7 @@
  * @brief   NVIC VTOR initialization expression.

  */

 #if !defined(CORTEX_VTOR_INIT) || defined(__DOXYGEN__)

-#define CORTEX_VTOR_INIT                0x00000000

+#define CORTEX_VTOR_INIT                0x00000000U

 #endif

 

 /**

@@ -175,11 +135,51 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+/**

+ * @name    Architecture and Compiler

+ * @{

+ */

+#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)

+/**

+ * @brief   Macro defining the specific ARM architecture.

+ */

+#define PORT_ARCHITECTURE_ARM_v7M

+

+/**

+ * @brief   Name of the implemented architecture.

+ */

+#define PORT_ARCHITECTURE_NAME          "ARMv7-M"

+

+/**

+ * @brief   Name of the architecture variant.

+ */

+#define PORT_CORE_VARIANT_NAME          "Cortex-M3"

+

+#elif (CORTEX_MODEL == CORTEX_M4)

+#define PORT_ARCHITECTURE_ARM_v7ME

+#define PORT_ARCHITECTURE_NAME          "ARMv7-ME"

+#if CORTEX_USE_FPU

+#define PORT_CORE_VARIANT_NAME          "Cortex-M4F"

+#else

+#define PORT_CORE_VARIANT_NAME          "Cortex-M4"

+#endif

+#endif

+

+/**

+ * @brief   Port-specific information string.

+ */

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

+#define PORT_INFO                       "Advanced kernel mode"

+#else

+#define PORT_INFO                       "Compact kernel mode"

+#endif

+/** @} */

+

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

 /**

  * @brief   Maximum usable priority for normal ISRs.

  */

-#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1)

+#define CORTEX_MAX_KERNEL_PRIORITY      (CORTEX_PRIORITY_SVCALL + 1U)

 

 /**

  * @brief   BASEPRI level within kernel lock.

@@ -188,7 +188,7 @@
   CORTEX_PRIO_MASK(CORTEX_MAX_KERNEL_PRIORITY)

 #else

 

-#define CORTEX_MAX_KERNEL_PRIORITY      0

+#define CORTEX_MAX_KERNEL_PRIORITY      0U

 #endif

 

 /**

@@ -336,7 +336,7 @@ struct port_intctx {
  * @param[in] ntp       the thread to be switched in

  * @param[in] otp       the thread to be switched out

  */

-#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)

+#if (CH_DBG_ENABLE_STACK_CHECK == FALSE) || defined(__DOXYGEN__)

 #define port_switch(ntp, otp) _port_switch(ntp, otp)

 #else

 #define port_switch(ntp, otp) {                                             \

@@ -383,7 +383,7 @@ static inline void port_init(void) {
   DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;

 

   /* Initialization of the system vectors used by the port.*/

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   NVIC_SetPriority(SVCall_IRQn, CORTEX_PRIORITY_SVCALL);

 #endif

   NVIC_SetPriority(PendSV_IRQn, CORTEX_PRIORITY_PENDSV);

@@ -397,7 +397,7 @@ static inline void port_init(void) {
 static inline syssts_t port_get_irq_status(void) {

   uint32_t sts;

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   sts = __get_BASEPRI();

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

   sts = __get_PRIMASK();

@@ -416,7 +416,7 @@ static inline syssts_t port_get_irq_status(void) {
  */

 static inline bool port_irq_enabled(syssts_t sts) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   return sts == CORTEX_BASEPRI_DISABLED;

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

   return (sts & 1) == 0;

@@ -432,7 +432,7 @@ static inline bool port_irq_enabled(syssts_t sts) {
  */

 static inline bool port_is_isr_context(void) {

 

-  return (bool)((__get_IPSR() & 0x1FF) != 0);

+  return (bool)((__get_IPSR() & 0x1FFU) != 0U);

 }

 

 /**

@@ -442,7 +442,7 @@ static inline bool port_is_isr_context(void) {
  */

 static inline void port_lock(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

   __disable_irq();

@@ -456,7 +456,7 @@ static inline void port_lock(void) {
  */

 static inline void port_unlock(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY

+#if CORTEX_SIMPLIFIED_PRIORITY == FALSE

   __set_BASEPRI(CORTEX_BASEPRI_DISABLED);

 #else /* CORTEX_SIMPLIFIED_PRIORITY */

   __enable_irq();

@@ -502,7 +502,7 @@ static inline void port_disable(void) {
  */

 static inline void port_suspend(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

   __set_BASEPRI(CORTEX_BASEPRI_KERNEL);

   __enable_irq();

 #else

@@ -516,7 +516,7 @@ static inline void port_suspend(void) {
  */

 static inline void port_enable(void) {

 

-#if !CORTEX_SIMPLIFIED_PRIORITY || defined(__DOXYGEN__)

+#if (CORTEX_SIMPLIFIED_PRIORITY == FALSE) || defined(__DOXYGEN__)

   __set_BASEPRI(CORTEX_BASEPRI_DISABLED);

 #endif

   __enable_irq();

@@ -532,7 +532,7 @@ static inline void port_enable(void) {
  */

 static inline void port_wait_for_interrupt(void) {

 

-#if CORTEX_ENABLE_WFI_IDLE

+#if CORTEX_ENABLE_WFI_IDLE == TRUE

   __WFI();

 #endif

 }

diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h b/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h
index cc403c99a..25ed63a90 100644
--- a/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h
+++ b/os/rt/ports/ARMCMx/compilers/GCC/chtypes.h
@@ -40,13 +40,14 @@
  */

 #if !defined(FALSE) || defined(__DOXYGEN__)

 #define FALSE               0

+

 #endif

 

 /**

  * @brief   Generic 'true' boolean constant.

  */

 #if !defined(TRUE) || defined(__DOXYGEN__)

-#define TRUE                (!FALSE)

+#define TRUE                1

 #endif

 /** @} */

 

diff --git a/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h b/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h
index 2ee7892c9..252bba104 100644
--- a/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h
+++ b/os/rt/ports/SIMIA32/compilers/GCC/chtypes.h
@@ -46,7 +46,7 @@
  * @brief   Generic 'true' boolean constant.

  */

 #if !defined(TRUE) || defined(__DOXYGEN__)

-#define TRUE                (!FALSE)

+#define TRUE                1

 #endif

 /** @} */

 

diff --git a/os/rt/ports/e200/compilers/GCC/chtypes.h b/os/rt/ports/e200/compilers/GCC/chtypes.h
index 4e9f49c36..87bb6b74d 100644
--- a/os/rt/ports/e200/compilers/GCC/chtypes.h
+++ b/os/rt/ports/e200/compilers/GCC/chtypes.h
@@ -46,7 +46,7 @@
  * @brief   Generic 'true' boolean constant.

  */

 #if !defined(TRUE) || defined(__DOXYGEN__)

-#define TRUE                (!FALSE)

+#define TRUE                1

 #endif

 /** @} */