git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6184 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 298 insertions, 0 deletions

diff --git a/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s
new file mode 100644
index 000000000..36864a2c9
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.s
@@ -0,0 +1,139 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011,2012,2013 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+*/

+

+/**

+ * @file    ARMCMx/GCC/chcoreasm_v7m.s

+ * @brief   ARMv7-M architecture port low level code.

+ *

+ * @addtogroup ARMCMx_CORE

+ * @{

+ */

+

+#define _FROM_ASM_

+#include "chconf.h"

+#include "chcore.h"

+

+#if !defined(FALSE) || defined(__DOXYGEN__)

+#define FALSE   0

+#endif

+

+#if !defined(TRUE) || defined(__DOXYGEN__)

+#define TRUE    1

+#endif

+

+#if !defined(__DOXYGEN__)

+

+

+                .set    CONTEXT_OFFSET, 12

+                .set    SCB_ICSR, 0xE000ED04

+                .set    ICSR_PENDSVSET, 0x10000000

+

+                .syntax unified

+                .cpu cortex-m4

+#if CORTEX_USE_FPU

+                .fpu fpv4-sp-d16

+#else

+                .fpu softvfp

+#endif

+

+                .thumb

+                .text

+

+/*--------------------------------------------------------------------------*

+ * Performs a context switch between two threads.

+ *--------------------------------------------------------------------------*/

+                .thumb_func

+                .globl  _port_switch

+_port_switch:

+                push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}

+#if CORTEX_USE_FPU

+                vpush   {s16-s31}

+#endif

+                str     sp, [r1, #CONTEXT_OFFSET]

+                ldr     sp, [r0, #CONTEXT_OFFSET]

+#if CORTEX_USE_FPU

+                vpop    {s16-s31}

+#endif

+                pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}

+

+/*--------------------------------------------------------------------------*

+ * Start a thread by invoking its work function.

+ *

+ * Threads execution starts here, the code leaves the system critical zone

+ * and then jumps into the thread function passed in register R4. The

+ * register R5 contains the thread parameter. The function chThdExit() is

+ * called on thread function return.

+ *--------------------------------------------------------------------------*/

+                .thumb_func

+                .globl  _port_thread_start

+_port_thread_start:

+#if CH_DBG_SYSTEM_STATE_CHECK

+                bl      _dbg_check_unlock

+#endif

+#if CH_DBG_STATISTICS

+                bl      _stats_stop_measure_crit_thd

+#endif

+#if !CORTEX_SIMPLIFIED_PRIORITY

+                movs    r3, #0

+                msr     BASEPRI, r3

+#else /* CORTEX_SIMPLIFIED_PRIORITY */

+                cpsie   i

+#endif /* CORTEX_SIMPLIFIED_PRIORITY */

+                mov     r0, r5

+                blx     r4

+                bl      chThdExit

+

+/*--------------------------------------------------------------------------*

+ * Post-IRQ switch code.

+ *

+ * Exception handlers return here for context switching.

+ *--------------------------------------------------------------------------*/

+                .thumb_func

+                .globl  _port_switch_from_isr

+_port_switch_from_isr:

+#if CH_DBG_STATISTICS

+                bl      _stats_start_measure_crit_thd

+#endif

+#if CH_DBG_SYSTEM_STATE_CHECK

+                bl      _dbg_check_lock

+#endif

+                bl      chSchDoReschedule

+#if CH_DBG_SYSTEM_STATE_CHECK

+                bl      _dbg_check_unlock

+#endif

+#if CH_DBG_STATISTICS

+                bl      _stats_stop_measure_crit_thd

+#endif

+                .globl  _port_exit_from_isr

+_port_exit_from_isr:

+#if CORTEX_SIMPLIFIED_PRIORITY

+                movw    r3, #:lower16:SCB_ICSR

+                movt    r3, #:upper16:SCB_ICSR

+                mov     r2, ICSR_PENDSVSET

+                str     r2, [r3, #0]

+                cpsie   i

+#else /* !CORTEX_SIMPLIFIED_PRIORITY */

+                svc     #0

+#endif /* !CORTEX_SIMPLIFIED_PRIORITY */

+.L1:            b       .L1

+

+#endif /* !defined(__DOXYGEN__) */

+

+/** @} */

diff --git a/os/rt/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld b/os/rt/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
new file mode 100644
index 000000000..69684e5cf
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/ld/STM32F051x8.ld
@@ -0,0 +1,159 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

+                 2011,2012,2013 Giovanni Di Sirio.

+

+    This file is part of ChibiOS/RT.

+

+    ChibiOS/RT is free software; you can redistribute it and/or modify

+    it under the terms of the GNU General Public License as published by

+    the Free Software Foundation; either version 3 of the License, or

+    (at your option) any later version.

+

+    ChibiOS/RT is distributed in the hope that it will be useful,

+    but WITHOUT ANY WARRANTY; without even the implied warranty of

+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+    GNU General Public License for more details.

+

+    You should have received a copy of the GNU General Public License

+    along with this program.  If not, see <http://www.gnu.org/licenses/>.

+

+                                      ---

+

+    A special exception to the GPL can be applied should you wish to distribute

+    a combined work that includes ChibiOS/RT, without being obliged to provide

+    the source code for any proprietary components. See the file exception.txt

+    for full details of how and when the exception can be applied.

+*/

+

+/*

+ * ST32F051x8 memory setup.

+ */

+__main_stack_size__     = 0x0400;

+__process_stack_size__  = 0x0400;

+

+MEMORY

+{

+    flash : org = 0x08000000, len = 64k

+    ram : org = 0x20000000, len = 8k

+}

+

+__ram_start__           = ORIGIN(ram);

+__ram_size__            = LENGTH(ram);

+__ram_end__             = __ram_start__ + __ram_size__;

+

+ENTRY(ResetHandler)

+

+SECTIONS

+{

+    . = 0;

+    _text = .;

+

+    startup : ALIGN(16) SUBALIGN(16)

+    {

+        KEEP(*(vectors))

+    } > flash

+

+    constructors : ALIGN(4) SUBALIGN(4)

+    {

+        PROVIDE(__init_array_start = .);

+        KEEP(*(SORT(.init_array.*)))

+        KEEP(*(.init_array))

+        PROVIDE(__init_array_end = .);

+    } > flash

+

+    destructors : ALIGN(4) SUBALIGN(4)

+    {

+        PROVIDE(__fini_array_start = .);

+        KEEP(*(.fini_array))

+        KEEP(*(SORT(.fini_array.*)))

+        PROVIDE(__fini_array_end = .);

+    } > flash

+

+    .text : ALIGN(16) SUBALIGN(16)

+    {

+        *(.text.startup.*)

+        *(.text)

+        *(.text.*)

+        *(.rodata)

+        *(.rodata.*)

+        *(.glue_7t)

+        *(.glue_7)

+        *(.gcc*)

+    } > flash

+

+    .ARM.extab :

+    {

+        *(.ARM.extab* .gnu.linkonce.armextab.*)

+    } > flash

+

+    .ARM.exidx : {

+        PROVIDE(__exidx_start = .);

+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

+        PROVIDE(__exidx_end = .);

+     } > flash

+

+    .eh_frame_hdr :

+    {

+        *(.eh_frame_hdr)

+    } > flash

+

+    .eh_frame : ONLY_IF_RO

+    {

+        *(.eh_frame)

+    } > flash

+    

+    .textalign : ONLY_IF_RO

+    {

+        . = ALIGN(8);

+    } > flash

+

+    _etext = .;

+    _textdata = _etext;

+

+    .stacks :

+    {

+        . = ALIGN(8);

+        __main_stack_base__ = .;

+        . += __main_stack_size__;

+        . = ALIGN(8);

+        __main_stack_end__ = .;

+        __process_stack_base__ = .;

+        __main_thread_stack_base__ = .;

+        . += __process_stack_size__;

+        . = ALIGN(8);

+        __process_stack_end__ = .;

+        __main_thread_stack_end__ = .;

+    } > ram

+

+    .data :

+    {

+        . = ALIGN(4);

+        PROVIDE(_data = .);

+        *(.data)

+        . = ALIGN(4);

+        *(.data.*)

+        . = ALIGN(4);

+        *(.ramtext)

+        . = ALIGN(4);

+        PROVIDE(_edata = .);

+    } > ram AT > flash

+

+    .bss :

+    {

+        . = ALIGN(4);

+        PROVIDE(_bss_start = .);

+        *(.bss)

+        . = ALIGN(4);

+        *(.bss.*)

+        . = ALIGN(4);

+        *(COMMON)

+        . = ALIGN(4);

+        PROVIDE(_bss_end = .);

+    } > ram    

+}

+

+PROVIDE(end = .);

+_end            = .;

+

+__heap_base__   = _end;

+__heap_end__    = __ram_end__;