diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-18 08:41:01 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-02-18 08:41:01 +0000 |
| commit | 3c730b67311dd5f752e7e0aef7c275a96b48b82e (patch) | |
| tree | d49bee861bec769da9e2200e7ae3fcb4199f5e2c /os/ports | |
| parent | ef0c3e57380eab05a177a87c2c7fdd73ec6a3415 (diff) | |
| download | ChibiOS-3c730b67311dd5f752e7e0aef7c275a96b48b82e.tar.gz ChibiOS-3c730b67311dd5f752e7e0aef7c275a96b48b82e.tar.bz2 ChibiOS-3c730b67311dd5f752e7e0aef7c275a96b48b82e.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5231 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/ports')
| -rw-r--r-- | os/ports/GCC/PPC/SPC563Mxx/bam.s | 43 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC563Mxx/core.s | 210 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC563Mxx/ivor.s | 258 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld | 1 | ||||
| -rw-r--r-- | os/ports/GCC/PPC/SPC563Mxx/port.mk | 3 |
5 files changed, 223 insertions, 292 deletions
diff --git a/os/ports/GCC/PPC/SPC563Mxx/bam.s b/os/ports/GCC/PPC/SPC563Mxx/bam.s index 4348cf21e..6b3012a72 100644 --- a/os/ports/GCC/PPC/SPC563Mxx/bam.s +++ b/os/ports/GCC/PPC/SPC563Mxx/bam.s @@ -28,42 +28,19 @@ #if !defined(__DOXYGEN__)
- /* BAM info, SWT off, WTE off, VLE from settings.*/
+ /* BAM record.*/
.section .bam, "ax"
+#if PPC_USE_VLE
.long 0x015A0000
- .long .clear_ecc
+#else
+ .long 0x005A0000
+#endif
+ .long .init
+
+.init:
+ bl _coreinit
+ bl _ivinit
- /* RAM clearing, this device requires a write to all RAM location in
- order to initialize the ECC detection hardware, this is going to
- slow down the startup but there is no way around.*/
-.clear_ecc:
- xor %r16, %r16, %r16
- xor %r17, %r17, %r17
- xor %r18, %r18, %r18
- xor %r19, %r19, %r19
- xor %r20, %r20, %r20
- xor %r21, %r21, %r21
- xor %r22, %r22, %r22
- xor %r23, %r23, %r23
- xor %r24, %r24, %r24
- xor %r25, %r25, %r25
- xor %r26, %r26, %r26
- xor %r27, %r27, %r27
- xor %r28, %r28, %r28
- xor %r29, %r29, %r29
- xor %r30, %r30, %r30
- xor %r31, %r31, %r31
- lis %r4, __ram_start__@h
- ori %r4, %r4, __ram_start__@l
- lis %r5, __ram_end__@h
- ori %r5, %r5, __ram_end__@l
-.cleareccloop:
- cmpl cr0, %r4, %r5
- bge cr0, .cleareccend
- stmw %r16, 0(%r4)
- addi %r4, %r4, 64
- b .cleareccloop
-.cleareccend:
b _boot_address
#endif /* !defined(__DOXYGEN__) */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/core.s b/os/ports/GCC/PPC/SPC563Mxx/core.s new file mode 100644 index 000000000..5d4b1bb8d --- /dev/null +++ b/os/ports/GCC/PPC/SPC563Mxx/core.s @@ -0,0 +1,210 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012,2013 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file SPC563Mxx/core.s
+ * @brief e200z3 core configuration.
+ *
+ * @addtogroup PPC_CORE
+ * @{
+ */
+
+/**
+ * @name BUCSR registers definitions
+ * @{
+ */
+#define BUCSR_BPEN 0x00000001
+#define BUCSR_BALLOC_BFI 0x00000200
+/** @} */
+
+/**
+ * @name BUCSR default settings
+ * @{
+ */
+#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
+/** @} */
+
+/**
+ * @name MSR register definitions
+ * @{
+ */
+#define MSR_UCLE 0x04000000
+#define MSR_SPE 0x02000000
+#define MSR_WE 0x00040000
+#define MSR_CE 0x00020000
+#define MSR_EE 0x00008000
+#define MSR_PR 0x00004000
+#define MSR_FP 0x00002000
+#define MSR_ME 0x00001000
+#define MSR_FE0 0x00000800
+#define MSR_DE 0x00000200
+#define MSR_FE1 0x00000100
+#define MSR_IS 0x00000020
+#define MSR_DS 0x00000010
+#define MSR_RI 0x00000002
+/** @} */
+
+/**
+ * @name MSR default settings
+ * @{
+ */
+#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
+/** @} */
+
+#if !defined(__DOXYGEN__)
+
+ .section .coreinit, "ax"
+
+ .align 2
+ .globl _coreinit
+ .type _coreinit, @function
+_coreinit:
+
+ /*
+ * RAM clearing, this device requires a write to all RAM location in
+ * order to initialize the ECC detection hardware, this is going to
+ * slow down the startup but there is no way around.
+ */
+ xor %r0, %r0, %r0
+ xor %r1, %r1, %r1
+ xor %r2, %r2, %r2
+ xor %r3, %r3, %r3
+ xor %r4, %r4, %r4
+ xor %r5, %r5, %r5
+ xor %r6, %r6, %r6
+ xor %r7, %r7, %r7
+ xor %r8, %r8, %r8
+ xor %r9, %r9, %r9
+ xor %r10, %r10, %r10
+ xor %r11, %r11, %r11
+ xor %r12, %r12, %r12
+ xor %r13, %r13, %r13
+ xor %r14, %r14, %r14
+ xor %r15, %r15, %r15
+ xor %r16, %r16, %r16
+ xor %r17, %r17, %r17
+ xor %r18, %r18, %r18
+ xor %r19, %r19, %r19
+ xor %r20, %r20, %r20
+ xor %r21, %r21, %r21
+ xor %r22, %r22, %r22
+ xor %r23, %r23, %r23
+ xor %r24, %r24, %r24
+ xor %r25, %r25, %r25
+ xor %r26, %r26, %r26
+ xor %r27, %r27, %r27
+ xor %r28, %r28, %r28
+ xor %r29, %r29, %r29
+ xor %r30, %r30, %r30
+ xor %r31, %r31, %r31
+ lis %r4, __ram_start__@h
+ ori %r4, %r4, __ram_start__@l
+ lis %r5, __ram_end__@h
+ ori %r5, %r5, __ram_end__@l
+.cleareccloop:
+ cmpl %cr0, %r4, %r5
+ bge %cr0, .cleareccend
+ stmw %r16, 0(%r4)
+ addi %r4, %r4, 64
+ b .cleareccloop
+.cleareccend:
+
+ /*
+ * Branch prediction enabled.
+ */
+ li %r3, BUCSR_DEFAULT
+ mtspr 1013, %r3 /* BUCSR */
+
+ blr
+
+ /*
+ * Exception vectors initialization.
+ */
+ .global _ivinit
+ .type _ivinit, @function
+_ivinit:
+ /* MSR initialization.*/
+ lis %r3, MSR_DEFAULT@h
+ ori %r3, %r3, MSR_DEFAULT@l
+ mtMSR %r3
+
+ /* IVPR initialization.*/
+ lis %r3, __ivpr_base__@h
+ ori %r3, %r3, __ivpr_base__@l
+ mtIVPR %r3
+
+ /* IVORs initialization.*/
+ lis %r3, _unhandled_exception@h
+ ori %r3, %r3, _unhandled_exception@l
+
+ mtspr 400, %r3 /* IVOR0-15 */
+ mtspr 401, %r3
+ mtspr 402, %r3
+ mtspr 403, %r3
+ mtspr 404, %r3
+ mtspr 405, %r3
+ mtspr 406, %r3
+ mtspr 407, %r3
+ mtspr 408, %r3
+ mtspr 409, %r3
+ mtspr 410, %r3
+ mtspr 411, %r3
+ mtspr 412, %r3
+ mtspr 413, %r3
+ mtspr 414, %r3
+ mtspr 415, %r3
+ mtspr 528, %r3 /* IVOR32-34 */
+ mtspr 529, %r3
+ mtspr 530, %r3
+
+ blr
+
+ /*
+ * Unhandled exceptions handler.
+ */
+ .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
+ .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
+ .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15, _IVOR32, _IVOR33
+ .weak _IVOR34
+ .weak _unhandled_exception
+_IVOR0:
+_IVOR1:
+_IVOR2:
+_IVOR3:
+_IVOR5:
+_IVOR6:
+_IVOR7:
+_IVOR8:
+_IVOR9:
+_IVOR11:
+_IVOR12:
+_IVOR13:
+_IVOR14:
+_IVOR15:
+_IVOR32:
+_IVOR33:
+_IVOR34:
+ .type _unhandled_exception, @function
+_unhandled_exception:
+ b _unhandled_exception
+
+#endif /* !defined(__DOXYGEN__) */
+
+/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/ivor.s b/os/ports/GCC/PPC/SPC563Mxx/ivor.s deleted file mode 100644 index 12cdcd15c..000000000 --- a/os/ports/GCC/PPC/SPC563Mxx/ivor.s +++ /dev/null @@ -1,258 +0,0 @@ -/*
- ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
- 2011,2012,2013 Giovanni Di Sirio.
-
- This file is part of ChibiOS/RT.
-
- ChibiOS/RT is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- ChibiOS/RT is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file SPC563Mxx/ivor.s
- * @brief SPC563Mxx IVORx handlers.
- *
- * @addtogroup PPC_CORE
- * @{
- */
-
-/*
- * Imports the PPC configuration headers.
- */
-#define _FROM_ASM_
-#include "chconf.h"
-#include "chcore.h"
-
-#if !defined(__DOXYGEN__)
- /*
- * INTC registers address.
- */
- .equ INTC_IACKR, 0xfff48010
- .equ INTC_EOIR, 0xfff48018
-
- .section .handlers, "ax"
-
- /*
- * Unhandled exceptions handler.
- */
- .weak _IVOR0
-_IVOR0:
- .weak _IVOR1
-_IVOR1:
- .weak _IVOR2
-_IVOR2:
- .weak _IVOR3
-_IVOR3:
- .weak _IVOR5
-_IVOR5:
- .weak _IVOR6
-_IVOR6:
- .weak _IVOR7
-_IVOR7:
- .weak _IVOR8
-_IVOR8:
- .weak _IVOR9
-_IVOR9:
- .weak _IVOR11
-_IVOR11:
- .weak _IVOR12
-_IVOR12:
- .weak _IVOR13
-_IVOR13:
- .weak _IVOR14
-_IVOR14:
- .weak _IVOR15
-_IVOR15:
- .weak _unhandled_exception
- .type _unhandled_exception, @function
-_unhandled_exception:
- b _unhandled_exception
-
- /*
- * _IVOR10 handler (Book-E decrementer).
- */
- .align 4
- .globl _IVOR10
- .type _IVOR10, @function
-_IVOR10:
- /* Creation of the external stack frame (extctx structure).*/
- stwu %sp, -80(%sp) /* Size of the extctx structure.*/
-#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
- e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
- e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
- e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
-#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
- stw %r0, 32(%sp) /* Saves GPR0. */
- mfSRR0 %r0
- stw %r0, 8(%sp) /* Saves PC. */
- mfSRR1 %r0
- stw %r0, 12(%sp) /* Saves MSR. */
- mfCR %r0
- stw %r0, 16(%sp) /* Saves CR. */
- mfLR %r0
- stw %r0, 20(%sp) /* Saves LR. */
- mfCTR %r0
- stw %r0, 24(%sp) /* Saves CTR. */
- mfXER %r0
- stw %r0, 28(%sp) /* Saves XER. */
- stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
- stw %r4, 40(%sp)
- stw %r5, 44(%sp)
- stw %r6, 48(%sp)
- stw %r7, 52(%sp)
- stw %r8, 56(%sp)
- stw %r9, 60(%sp)
- stw %r10, 64(%sp)
- stw %r11, 68(%sp)
- stw %r12, 72(%sp)
-#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-
- /* Reset DIE bit in TSR register.*/
- lis %r3, 0x0800 /* DIS bit mask. */
- mtspr 336, %r3 /* TSR register. */
-
-#if CH_DBG_SYSTEM_STATE_CHECK
- bl dbg_check_enter_isr
- bl dbg_check_lock_from_isr
-#endif
- bl chSysTimerHandlerI
-#if CH_DBG_SYSTEM_STATE_CHECK
- bl dbg_check_unlock_from_isr
- bl dbg_check_leave_isr
-#endif
-
- /* System tick handler invocation.*/
-#if CH_DBG_SYSTEM_STATE_CHECK
- bl dbg_check_lock
-#endif
- bl chSchIsPreemptionRequired
- cmpli cr0, %r3, 0
- beq cr0, _ivor_exit
- bl chSchDoReschedule
- b _ivor_exit
-
- /*
- * _IVOR4 handler (Book-E external interrupt).
- */
- .align 4
- .globl _IVOR4
- .type _IVOR4, @function
-_IVOR4:
- /* Creation of the external stack frame (extctx structure).*/
- stwu %sp, -80(%sp) /* Size of the extctx structure.*/
-#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
- e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
- e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
- e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
-#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
- stw %r0, 32(%sp) /* Saves GPR0. */
- mfSRR0 %r0
- stw %r0, 8(%sp) /* Saves PC. */
- mfSRR1 %r0
- stw %r0, 12(%sp) /* Saves MSR. */
- mfCR %r0
- stw %r0, 16(%sp) /* Saves CR. */
- mfLR %r0
- stw %r0, 20(%sp) /* Saves LR. */
- mfCTR %r0
- stw %r0, 24(%sp) /* Saves CTR. */
- mfXER %r0
- stw %r0, 28(%sp) /* Saves XER. */
- stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
- stw %r4, 40(%sp)
- stw %r5, 44(%sp)
- stw %r6, 48(%sp)
- stw %r7, 52(%sp)
- stw %r8, 56(%sp)
- stw %r9, 60(%sp)
- stw %r10, 64(%sp)
- stw %r11, 68(%sp)
- stw %r12, 72(%sp)
-#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
-
- /* Software vector address from the INTC register.*/
- lis %r3, INTC_IACKR@h
- ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */
- lwz %r3, 0(%r3) /* IACKR register value. */
- lwz %r3, 0(%r3)
- mtCTR %r3 /* Software handler address. */
-
-#if PPC_USE_IRQ_PREEMPTION
- /* Allows preemption while executing the software handler.*/
- wrteei 1
-#endif
-
- /* Exectes the software handler.*/
- bctrl
-
-#if PPC_USE_IRQ_PREEMPTION
- /* Prevents preemption again.*/
- wrteei 0
-#endif
-
- /* Informs the INTC that the interrupt has been served.*/
- mbar 0
- lis %r3, INTC_EOIR@h
- ori %r3, %r3, INTC_EOIR@l
- stw %r3, 0(%r3) /* Writing any value should do. */
-
- /* Verifies if a reschedule is required.*/
-#if CH_DBG_SYSTEM_STATE_CHECK
- bl dbg_check_lock
-#endif
- bl chSchIsPreemptionRequired
- cmpli cr0, %r3, 0
- beq cr0, _ivor_exit
- bl chSchDoReschedule
-
- /* Context restore.*/
- .globl _ivor_exit
-_ivor_exit:
-#if CH_DBG_SYSTEM_STATE_CHECK
- bl dbg_check_unlock
-#endif
-#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
- e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */
- e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */
- e_lmvsrrw 8(%sp) /* Restores PC, MSR. */
-#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
- lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */
- lwz %r4, 40(%sp)
- lwz %r5, 44(%sp)
- lwz %r6, 48(%sp)
- lwz %r7, 52(%sp)
- lwz %r8, 56(%sp)
- lwz %r9, 60(%sp)
- lwz %r10, 64(%sp)
- lwz %r11, 68(%sp)
- lwz %r12, 72(%sp)
- lwz %r0, 8(%sp)
- mtSRR0 %r0 /* Restores PC. */
- lwz %r0, 12(%sp)
- mtSRR1 %r0 /* Restores MSR. */
- lwz %r0, 16(%sp)
- mtCR %r0 /* Restores CR. */
- lwz %r0, 20(%sp)
- mtLR %r0 /* Restores LR. */
- lwz %r0, 24(%sp)
- mtCTR %r0 /* Restores CTR. */
- lwz %r0, 28(%sp)
- mtXER %r0 /* Restores XER. */
- lwz %r0, 32(%sp) /* Restores GPR0. */
-#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
- addi %sp, %sp, 80 /* Back to the previous frame. */
- rfi
-
-#endif /* !defined(__DOXYGEN__) */
-
-/** @} */
diff --git a/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld b/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld index 9d0de08f5..d96dd9970 100644 --- a/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld +++ b/os/ports/GCC/PPC/SPC563Mxx/ld/SPC563M64.ld @@ -48,6 +48,7 @@ SECTIONS {
__ivpr_base__ = .;
KEEP(*(.bam))
+ KEEP(*(.coreinit))
KEEP(*(.crt0))
KEEP(*(.handlers))
. = ALIGN(0x800);
diff --git a/os/ports/GCC/PPC/SPC563Mxx/port.mk b/os/ports/GCC/PPC/SPC563Mxx/port.mk index 16241904c..5f5a1b309 100644 --- a/os/ports/GCC/PPC/SPC563Mxx/port.mk +++ b/os/ports/GCC/PPC/SPC563Mxx/port.mk @@ -2,8 +2,9 @@ PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/bam.s \
+ ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/core.s \
${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/vectors.s \
- ${CHIBIOS}/os/ports/GCC/PPC/SPC563Mxx/ivor.s \
+ ${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
${CHIBIOS}/os/ports/GCC/PPC/crt0.s
PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
|