git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3315 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 95 insertions, 19 deletions

diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c
index 01a28a8b4..1bec4d879 100644
--- a/os/hal/platforms/STM32/mac_lld.c
+++ b/os/hal/platforms/STM32/mac_lld.c
@@ -49,9 +49,6 @@
 #error "STM32_HCLK below minimum frequency for ETH operations (20MHz)"

 #endif

 

-/* PHY address.*/

-#define MACMIIDR_PA     (32 << 11)

-

 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

@@ -83,14 +80,14 @@ static uint32_t tb[MAC_TRANSMIT_BUFFERS * BUFFER_SLICE];
  *

  * @param[in] reg       register number

  * @param[in] value     new register value

+ *

+ * @notapi

  */

-static void mii_write_phy(uint16_t reg, uint16_t value) {

-  uint32_t miiar;

+void _stm32_eth_write_phy(uint32_t reg, uint32_t value) {

 

-  miiar = ETH->MACMIIAR | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;

-  miiar = (miiar & ~ETH_MACMIIAR_MR) | (reg << 6);

   ETH->MACMIIDR = value;

-  ETH->MACMIIAR = miiar;

+  ETH->MACMIIAR = BOARD_PHY_ADDR | (reg << 6) | MACMIIDR_CR |

+                  ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;

   while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)

     ;

 }

@@ -99,21 +96,23 @@ static void mii_write_phy(uint16_t reg, uint16_t value) {
  * @brief   Reads a PHY register.

  *

  * @param[in] reg       register number

+ *

+ * @notapi

  */

-static uint16_t mii_read_phy(uint16_t reg) {

-  uint32_t miiar;

+static uint32_t _stm32_eth_read_phy(uint32_t reg) {

 

-  miiar = ETH->MACMIIAR | ETH_MACMIIAR_MB;

-  miiar = (miiar & ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_MW)) | (reg << 6);

-  ETH->MACMIIAR = miiar;

+  ETH->MACMIIAR = BOARD_PHY_ADDR | (reg << 6) | MACMIIDR_CR |

+                  ETH_MACMIIAR_MB;

   while ((ETH->MACMIIAR & ETH_MACMIIAR_MB) != 0)

     ;

-  return (uint16_t)ETH->MACMIIDR;

+  return ETH->MACMIIDR;

 }

 

+

 /**

  * @brief   MII/RMII interface initialization.

  */

+#if 0

 static void mii_init(void) {

   uint32_t i;

 

@@ -126,6 +125,7 @@ static void mii_init(void) {
   /* Wrong or defective board.*/

   chSysHalt();

 }

+#endif

 

 /*===========================================================================*/

 /* Driver interrupt handlers.                                                */

@@ -148,7 +148,7 @@ void mac_lld_init(void) {
   /* Descriptor tables are initialized in linked mode, note that the first

      word is not initialized here but in mac_lld_start().*/

   for (i = 0; i < MAC_RECEIVE_BUFFERS; i++) {

-    rd[i].rdes1 = RDES1_RCH | MAC_BUFFERS_SIZE;

+    rd[i].rdes1 = STM32_RDES1_RCH | MAC_BUFFERS_SIZE;

     rd[i].rdes2 = (uint32_t)&rb[i * BUFFER_SLICE];

     rd[i].rdes3 = (uint32_t)&rb[((i + 1) % MAC_RECEIVE_BUFFERS) *

                                 BUFFER_SLICE];

@@ -173,10 +173,10 @@ void mac_lld_start(MACDriver *macp) {
 

   /* Resets the state of all descriptors.*/

   for (i = 0; i < MAC_RECEIVE_BUFFERS; i++)

-    rd[i].rdes0 = RDES0_OWN;

+    rd[i].rdes0 = STM32_RDES0_OWN;

   rxptr = (stm32_eth_rx_descriptor_t *)rd;

   for (i = 0; i < MAC_TRANSMIT_BUFFERS; i++)

-    td[i].tdes0 = TDES0_TCH;

+    td[i].tdes0 = STM32_TDES0_TCH;

   txptr = (stm32_eth_tx_descriptor_t *)td;

 

   /* Soft reset of the MAC core and wait until the reset is complete.*/

@@ -185,7 +185,7 @@ void mac_lld_start(MACDriver *macp) {
     ;

 

   /* MII initialization.*/

-  mii_init();

+//  mii_init();

 

   /* Descriptor chains pointers.*/

   ETH->DMARDLAR = (uint32_t)rd;

diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h
index 8647bd296..f21f4c129 100644
--- a/os/hal/platforms/STM32/mac_lld.h
+++ b/os/hal/platforms/STM32/mac_lld.h
@@ -1,6 +1,6 @@
 /*

     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,

-                 2011 Giovanni Di Sirio.

+           2011 Giovanni Di Sirio.

 

     This file is part of ChibiOS/RT.

 

@@ -35,6 +35,81 @@
 /* Driver constants.                                                         */

 /*===========================================================================*/

 

+/**

+ * @name    RDES0 constants

+ * @{

+ */

+#define STM32_RDES0_OWN             0x80000000

+#define STM32_RDES0_AFM             0x40000000

+#define STM32_RDES0_FL_MASK         0x3FFF0000

+#define STM32_RDES0_ES              0x00008000

+#define STM32_RDES0_DESERR          0x00004000

+#define STM32_RDES0_SAF             0x00002000

+#define STM32_RDES0_LE              0x00001000

+#define STM32_RDES0_OE              0x00000800

+#define STM32_RDES0_VLAN            0x00000400

+#define STM32_RDES0_FS              0x00000200

+#define STM32_RDES0_LS              0x00000100

+#define STM32_RDES0_IPHCE           0x00000080

+#define STM32_RDES0_LCO             0x00000040

+#define STM32_RDES0_FT              0x00000020

+#define STM32_RDES0_RWT             0x00000010

+#define STM32_RDES0_RE              0x00000008

+#define STM32_RDES0_DE              0x00000004

+#define STM32_RDES0_CE              0x00000002

+#define STM32_RDES0_PCE             0x00000001

+/** @} */

+

+/**

+ * @name    RDES1 constants

+ * @{

+ */

+#define STM32_RDES1_DIC             0x80000000

+#define STM32_RDES1_RBS2_MASK       0x1FFF0000

+#define STM32_RDES1_RER             0x00008000

+#define STM32_RDES1_RCH             0x00004000

+#define STM32_RDES1_RBS1_MASK       0x00001FFF

+/** @} */

+

+/**

+ * @name    TDES0 constants

+ * @{

+ */

+#define STM32_TDES0_OWN             0x80000000

+#define STM32_TDES0_IC              0x40000000

+#define STM32_TDES0_LS              0x20000000

+#define STM32_TDES0_FS              0x10000000

+#define STM32_TDES0_DC              0x08000000

+#define STM32_TDES0_DP              0x04000000

+#define STM32_TDES0_TTSE            0x02000000

+#define STM32_TDES0_CIC_MASK        0x00C00000

+#define STM32_TDES0_TER             0x00200000

+#define STM32_TDES0_TCH             0x00100000

+#define STM32_TDES0_TTSS            0x00020000

+#define STM32_TDES0_IHE             0x00010000

+#define STM32_TDES0_ES              0x00008000

+#define STM32_TDES0_JT              0x00004000

+#define STM32_TDES0_FF              0x00002000

+#define STM32_TDES0_IPE             0x00001000

+#define STM32_TDES0_LCA             0x00000800

+#define STM32_TDES0_NC              0x00000400

+#define STM32_TDES0_LCO             0x00000200

+#define STM32_TDES0_EC              0x00000100

+#define STM32_TDES0_VF              0x00000080

+#define STM32_TDES0_CC_MASK         0x00000078

+#define STM32_TDES0_ED              0x00000004

+#define STM32_TDES0_UF              0x00000002

+#define STM32_TDES0_DB              0x00000001

+/** @} */

+

+/**

+ * @name    TDES1 constants

+ * @{

+ */

+#define STM32_TDES1_TBS2_MASK       0x1FFF0000

+#define STM32_TDES1_TBS1_MASK       0x00001FFF

+/** @} */

+

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk
index 89179f65f..1a8c42bc7 100644
--- a/os/hal/platforms/STM32F1xx/platform.mk
+++ b/os/hal/platforms/STM32F1xx/platform.mk
@@ -6,6 +6,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \

 			  ${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \

+			  ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \

               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \