diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-05-04 14:38:02 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-05-04 14:38:02 +0000 |
| commit | f8c8c48fa989c71ab9b2e26677329ed108a779fb (patch) | |
| tree | 42d272bc3ce491b431da5bd66d5403d1af171e27 /os/hal | |
| parent | 3e42a8fe7620e26912ed27f626f771b6bd757b31 (diff) | |
| download | ChibiOS-f8c8c48fa989c71ab9b2e26677329ed108a779fb.tar.gz ChibiOS-f8c8c48fa989c71ab9b2e26677329ed108a779fb.tar.bz2 ChibiOS-f8c8c48fa989c71ab9b2e26677329ed108a779fb.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2920 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32/sdc_lld.c | 29 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/sdc_lld.h | 8 |
2 files changed, 28 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c index 69c04a41a..ae84f812e 100644 --- a/os/hal/platforms/STM32/sdc_lld.c +++ b/os/hal/platforms/STM32/sdc_lld.c @@ -96,9 +96,10 @@ void sdc_lld_start(SDCDriver *sdcp) { RCC->AHBENR |= RCC_AHBENR_SDIOEN;
}
/* Configuration, card clock is initially stopped.*/
- SDIO->POWER = 0;
- SDIO->CLKCR = 0;
- SDIO->DCTRL = 0;
+ SDIO->POWER = 0;
+ SDIO->CLKCR = 0;
+ SDIO->DCTRL = 0;
+ SDIO->DTIMER = STM32_SDC_DATATIMEOUT;
}
/**
@@ -111,9 +112,10 @@ void sdc_lld_start(SDCDriver *sdcp) { void sdc_lld_stop(SDCDriver *sdcp) {
if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) {
- SDIO->POWER = 0;
- SDIO->CLKCR = 0;
- SDIO->DCTRL = 0;
+ SDIO->POWER = 0;
+ SDIO->CLKCR = 0;
+ SDIO->DCTRL = 0;
+ SDIO->DTIMER = 0;
/* Clock deactivation.*/
NVICDisableVector(SDIO_IRQn);
@@ -319,11 +321,20 @@ bool_t sdc_lld_read_blocks(SDCDriver *sdcp, uint8_t *buf, uint32_t n) { msg_t msg;
chSysLock();
+ /* Prepares the DMA channel.*/
dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4],
- n * SDC_BLOCK_SIZE, buf,
+ (n * SDC_BLOCK_SIZE) / sizeof (uint32_t), buf,
(STM32_SDC_SDIO_DMA_PRIORITY << 12) |
- DMA_CCR1_MINC | DMA_CCR1_EN);
-
+ DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 |
+ DMA_CCR1_MINC);
+ SDIO->DLEN = n;
+ /* Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/
+ SDIO->DCTRL = SDIO_DCTRL_RWMOD |
+ SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_3 |
+ SDIO_DCTRL_DMAEN |
+ SDIO_DCTRL_DTEN;
+ /* DMA channel activation.*/
+ dmaEnableChannel(&STM32_DMA2, STM32_DMA_CHANNEL_4);
chDbgAssert(sdcp->thread == NULL, "sdc_lld_read_blocks(), #1", "not NULL");
sdcp->thread = chThdSelf();
chSchGoSleepS(THD_STATE_SUSPENDED);
diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h index 4b27b92c1..3f12dd4fc 100644 --- a/os/hal/platforms/STM32/sdc_lld.h +++ b/os/hal/platforms/STM32/sdc_lld.h @@ -35,11 +35,19 @@ /* Driver constants. */
/*===========================================================================*/
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
+ * @brief SDIO data timeout in SDIO clock cycles.
+ */
+#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__)
+#define STM32_SDC_DATATIMEOUT 0x000FFFFF
+#endif
+
+/**
* @brief SDIO DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__)
|