git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5127 35acf78f-673a-0410-8e92-d51de3d6d3f4

4 files changed, 72 insertions, 20 deletions

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
index a3c66cc51..acfc175af 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.c
@@ -53,7 +53,7 @@ CH_IRQ_HANDLER(vector59) {
   chSysUnlockFromIsr();

 

   /* Resets the PIT channel 3 IRQ flag.*/

-  PIT.CH[0].TFLG.R = 1;

+  PIT.CHANNEL[0].TFLG.R = 1;

 

   CH_IRQ_EPILOGUE();

 }

@@ -90,10 +90,10 @@ void hal_lld_init(void) {
                                SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));

   reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;

   PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */

-  PIT.CH[0].LDVAL.R = reg;

-  PIT.CH[0].CVAL.R  = reg;

-  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */

-  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */

+  PIT.CHANNEL[0].LDVAL.R = reg;

+  PIT.CHANNEL[0].CVAL.R  = reg;

+  PIT.CHANNEL[0].TFLG.R  = 1;   /* Interrupt flag cleared.                  */

+  PIT.CHANNEL[0].TCTRL.R = 3;   /* Timer active, interrupt enabled.         */

 }

 

 /**

@@ -107,7 +107,7 @@ void hal_lld_init(void) {
 void spc_clock_init(void) {

 

   /* Waiting for IRC stabilization before attempting anything else.*/

-  while (!ME.GS.B.S_RC)

+  while (!ME.GS.B.S_IRCOSC)

     ;

 

 #if !SPC5_NO_INIT

@@ -130,7 +130,7 @@ void spc_clock_init(void) {
 

   /* Run modes initialization.*/

   ME.MER.R          = SPC5_ME_ME_BITS;          /* Enabled run modes.       */

-  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */

+//  ME.TEST.R         = SPC5_ME_TEST_MC_BITS;     /* TEST run mode.           */

   ME.SAFE.R         = SPC5_ME_SAFE_MC_BITS;     /* SAFE run mode.           */

   ME.DRUN.R         = SPC5_ME_DRUN_MC_BITS;     /* DRUN run mode.           */

   ME.RUN[0].R       = SPC5_ME_RUN0_MC_BITS;     /* RUN0 run mode.           */

@@ -164,10 +164,10 @@ void spc_clock_init(void) {
     chSysHalt();

 

   /* CFLASH settings calculated for a maximum clock of 64MHz.*/

-  CFLASH.PFCR0.B.BK0_APC  = 2;

+/*  CFLASH.PFCR0.B.BK0_APC  = 2;

   CFLASH.PFCR0.B.BK0_RWSC = 2;

   CFLASH.PFCR1.B.BK1_APC  = 2;

-  CFLASH.PFCR1.B.BK1_RWSC = 2;

+  CFLASH.PFCR1.B.BK1_RWSC = 2;*/

 

 #endif /* !SPC5_NO_INIT */

 }

@@ -196,7 +196,7 @@ bool_t halSPCSetRunMode(spc5_runmode_t mode) {
     ;

 

   /* Verifies that the mode has been effectively switched.*/

-  if (ME.GS.B.S_CURRENTMODE != mode)

+  if (ME.GS.B.S_CURRENT_MODE != mode)

     return CH_FAILED;

 

   return CH_SUCCESS;

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.h b/os/hal/platforms/SPC56ELxx/hal_lld.h
index 4ddd73597..fbfef7294 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.h
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.h
@@ -69,7 +69,7 @@
 /**

  * @brief   Maximum FMPLLs input clock frequency.

  */

-#define SPC5_FMPLLIN_MAX            16000000

+#define SPC5_FMPLLIN_MAX            40000000

 

 /**

  * @brief   Maximum FMPLLs VCO clock frequency.

@@ -84,7 +84,7 @@
 /**

  * @brief   Maximum FMPLL0 output clock frequency.

  */

-#define SPC5_FMPLL0_CLK_MAX         64000000

+#define SPC5_FMPLL0_CLK_MAX         120000000

 

 /**

  * @brief   Maximum FMPLL1 output clock frequency.

@@ -105,6 +105,26 @@
 /** @} */

 

 /**

+ * @name    MC_CGM_AC3_SC register bits definitions

+ * @{

+ */

+#define SPC5_GCM_AC3_SC_SELCTL_MASK (15U << 24)

+#define SPC5_GCM_AC3_SC_SELCTL(n)   ((n) << 24)

+#define SPC5_GCM_AC3_SC_SELCTL_IRC  SPC5_GCM_AC3_SC_SELCTL(0)

+#define SPC5_GCM_AC3_SC_SELCTL_XOSC SPC5_GCM_AC3_SC_SELCTL(1)

+/** @} */

+

+/**

+ * @name    MC_CGM_AC4_SC register bits definitions

+ * @{

+ */

+#define SPC5_GCM_AC4_SC_SELCTL_MASK (15U << 24)

+#define SPC5_GCM_AC4_SC_SELCTL(n)   ((n) << 24)

+#define SPC5_GCM_AC4_SC_SELCTL_IRC  SPC5_GCM_AC4_SC_SELCTL(0)

+#define SPC5_GCM_AC4_SC_SELCTL_XOSC SPC5_GCM_AC4_SC_SELCTL(1)

+/** @} */

+

+/**

  * @name    FMPLL_CR register bits definitions

  * @{

  */

@@ -231,6 +251,13 @@
 #endif

 

 /**

+ * @brief   FMPLL0 Clock source.

+ */

+#if !defined(SPC5_FMPLL0_CLOCK_SOURCE) || defined(__DOXYGEN__)

+#define SPC5_FMPLL0_CLOCK_SOURCE    SPC5_GCM_AC3_SC_SELCTL_XOSC

+#endif

+

+/**

  * @brief   FMPLL0 IDF divider value.

  * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.

  */

@@ -255,6 +282,13 @@
 #endif

 

 /**

+ * @brief   FMPLL1 Clock source.

+ */

+#if !defined(SPC5_FMPLL1_CLOCK_SOURCE) || defined(__DOXYGEN__)

+#define SPC5_FMPLL1_CLOCK_SOURCE    SPC5_GCM_AC4_SC_SELCTL_XOSC

+#endif

+

+/**

  * @brief   FMPLL1 IDF divider value.

  * @note    The default value is calculated for XOSC=40MHz and PHI=64MHz.

  */

@@ -601,6 +635,15 @@
 #error "invalid SPC5_XOSC_CLK value specified"

 #endif

 

+/* Check on SPC5_FMPLL0_CLOCK_SOURCE.*/

+#if SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_IRC

+#define SPC5_FMPLL0_INPUT_CLK   SPC5_IRC_CLK

+#elif SPC5_FMPLL0_CLOCK_SOURCE == SPC5_GCM_AC3_SC_SELCTL_XOSC

+#define SPC5_FMPLL0_INPUT_CLK   SPC5_XOSC_CLK

+#else

+#error "invalid SPC5_FMPLL0_CLOCK_SOURCE value specified"

+#endif

+

 /* Check on SPC5_FMPLL0_IDF_VALUE.*/

 #if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)

 #error "invalid SPC5_FMPLL0_IDF_VALUE value specified"

@@ -628,7 +671,7 @@
  * @brief   SPC5_FMPLL0_VCO_CLK clock point.

  */

 #define SPC5_FMPLL0_VCO_CLK                                                 \

-  ((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)

+  ((SPC5_FMPLL0_INPUT_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)

 

 /* Check on FMPLL0 VCO output.*/

 #if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \

@@ -647,6 +690,15 @@
 #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"

 #endif

 

+/* Check on SPC5_FMPLL1_CLOCK_SOURCE.*/

+#if SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_IRC

+#define SPC5_FMPLL1_INPUT_CLK   SPC5_IRC_CLK

+#elif SPC5_FMPLL1_CLOCK_SOURCE == SPC5_GCM_AC4_SC_SELCTL_XOSC

+#define SPC5_FMPLL1_INPUT_CLK   SPC5_XOSC_CLK

+#else

+#error "invalid SPC5_FMPLL1_CLOCK_SOURCE value specified"

+#endif

+

 /* Check on SPC5_FMPLL1_IDF_VALUE.*/

 #if (SPC5_FMPLL1_IDF_VALUE < 1) || (SPC5_FMPLL1_IDF_VALUE > 15)

 #error "invalid SPC5_FMPLL1_IDF_VALUE value specified"

@@ -674,7 +726,7 @@
  * @brief   SPC5_FMPLL1_VCO_CLK clock point.

  */

 #define SPC5_FMPLL1_VCO_CLK                                                 \

-  ((SPC5_XOSC_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)

+  ((SPC5_FMPLL1_INPUT_CLK / SPC5_FMPLL1_IDF_VALUE) * SPC5_FMPLL1_NDIV_VALUE)

 

 /* Check on FMPLL1 VCO output.*/

 #if (SPC5_FMPLL1_VCO_CLK < SPC5_FMPLLVCO_MIN) ||                            \

diff --git a/os/hal/platforms/SPC56ELxx/platform.mk b/os/hal/platforms/SPC56ELxx/platform.mk
index 53b94c39d..61f1cf3de 100644
--- a/os/hal/platforms/SPC56ELxx/platform.mk
+++ b/os/hal/platforms/SPC56ELxx/platform.mk
@@ -1,9 +1,9 @@
-# List of all the SPC560Pxx platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx/hal_lld.c \

+# List of all the SPC56ELxx platform files.

+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx/hal_lld.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c

 

 # Required include directories

-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Pxx \

+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56ELxx \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1

diff --git a/os/hal/platforms/SPC56ELxx/spc56el_registry.h b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
index 22d8aed75..5e3595be0 100644
--- a/os/hal/platforms/SPC56ELxx/spc56el_registry.h
+++ b/os/hal/platforms/SPC56ELxx/spc56el_registry.h
@@ -20,8 +20,8 @@
  * @{

  */

 

-#ifndef _SPC560P_REGISTRY_H_

-#define _SPC560P_REGISTRY_H_

+#ifndef _SPC56EL_REGISTRY_H_

+#define _SPC56EL_REGISTRY_H_

 

 /*===========================================================================*/

 /* Platform capabilities.                                                    */

@@ -61,6 +61,6 @@
 #define SPC5_SIUL_NUM_PADSELS               36

 /** @} */

 

-#endif /* _SPC560P_REGISTRY_H_ */

+#endif /* _SPC56EL_REGISTRY_H_ */

 

 /** @} */