diff options
| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-07 19:38:13 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-07 19:38:13 +0000 |
| commit | c7bb99a1e5b0a630df0f9a42190172bfe3472596 (patch) | |
| tree | 98724e58cd797adc5b0e510b0b6251a848be0f5f /os/hal | |
| parent | b9ec6e234f310fa36f91d8046e2b5c68a879e0c2 (diff) | |
| download | ChibiOS-c7bb99a1e5b0a630df0f9a42190172bfe3472596.tar.gz ChibiOS-c7bb99a1e5b0a630df0f9a42190172bfe3472596.tar.bz2 ChibiOS-c7bb99a1e5b0a630df0f9a42190172bfe3472596.zip | |
GPT. Fixed some inconsistencies in F4x port.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3574 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32/gpt_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 21 |
2 files changed, 20 insertions, 3 deletions
diff --git a/os/hal/platforms/STM32/gpt_lld.c b/os/hal/platforms/STM32/gpt_lld.c index e40843ccb..34468ccc3 100644 --- a/os/hal/platforms/STM32/gpt_lld.c +++ b/os/hal/platforms/STM32/gpt_lld.c @@ -249,7 +249,7 @@ void gpt_lld_init(void) { #if STM32_GPT_USE_TIM8
/* Driver initialization.*/
- GPTD5.tim = STM32_TIM8;
+ GPTD8.tim = STM32_TIM8;
gptObjectInit(&GPTD8);
#endif
}
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 0650c84f8..061ce1304 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -292,8 +292,25 @@ /* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C1_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 0) | \
+ STM32_DMA_STREAM_ID_MSK(1, 5)))
+#define STM32_I2C1_RX_DMA_CHN 0x00100001
+#define STM32_I2C1_TX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 7)) | \
+ (STM32_DMA_STREAM_ID_MSK(1, 6)))
+#define STM32_I2C1_TX_DMA_CHN 0x10000000
+
#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C2_RX_DMA_MSK ((STM32_DMA_STREAM_ID_MSK(1, 2) | \
+ STM32_DMA_STREAM_ID_MSK(1, 3)))
+#define STM32_I2C2_RX_DMA_CHN 0x00007700
+#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
+#define STM32_I2C2_TX_DMA_CHN 0x70000000
+
#define STM32_HAS_I2C3 TRUE
+#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C3_RX_DMA_CHN 0x00000300
+#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C3_TX_DMA_CHN 0x00030000
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
@@ -330,8 +347,8 @@ #define STM32_HAS_TIM3 TRUE
#define STM32_HAS_TIM4 TRUE
#define STM32_HAS_TIM5 TRUE
-#define STM32_HAS_TIM6 FALSE
-#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM6 TRUE
+#define STM32_HAS_TIM7 TRUE
#define STM32_HAS_TIM8 TRUE
#define STM32_HAS_TIM9 TRUE
#define STM32_HAS_TIM10 TRUE
|