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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-11 19:36:26 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-09-11 19:36:26 +0000 |
| commit | c3c4b3af583f8da32b34932950f9eb056b41b3da (patch) | |
| tree | e63338f26d2ae1b2a4024953c86646340f1cafde /os/hal | |
| parent | 67ac09b2f3e66f2a59261d189a0128644918727c (diff) | |
| download | ChibiOS-c3c4b3af583f8da32b34932950f9eb056b41b3da.tar.gz ChibiOS-c3c4b3af583f8da32b34932950f9eb056b41b3da.tar.bz2 ChibiOS-c3c4b3af583f8da32b34932950f9eb056b41b3da.zip | |
Fixed GPIO port index calculation.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10573 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c index 1acd4e5f1..b112a9e07 100644 --- a/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c @@ -224,7 +224,7 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = ((uint32_t)port >> 10U) & 0xFU;
+ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | (portidx << croff);
@@ -272,7 +272,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { /* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = ((uint32_t)port >> 10U) & 0xFU;
+ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
crport = (AFIO->EXTICR[cridx] >> croff) & 0xFU;
diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c index dc0fd71c9..2d9bca949 100644 --- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c @@ -253,7 +253,7 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = ((uint32_t)port >> 10U) & 0xFU;
+ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
@@ -301,7 +301,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { /* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = ((uint32_t)port >> 10U) & 0xFU;
+ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;
diff --git a/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c index 018f85d7e..a7d91cd29 100644 --- a/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c +++ b/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c @@ -249,7 +249,7 @@ void _pal_lld_enablepadevent(ioportid_t port, /* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = ((uint32_t)port >> 10U) & 0xFU;
+ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
@@ -297,7 +297,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { /* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = ((uint32_t)port >> 10U) & 0xFU;
+ portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;
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