diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-17 07:41:10 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-12-17 07:41:10 +0000 |
| commit | af25622db89ab50b7bad608792b1cb5a42b900c5 (patch) | |
| tree | bf5fd69cf108be36930c8cb361059b70ed09d334 /os/hal | |
| parent | 968d0cf6e9e8f362021e4288cd3336fe7922e00e (diff) | |
| download | ChibiOS-af25622db89ab50b7bad608792b1cb5a42b900c5.tar.gz ChibiOS-af25622db89ab50b7bad608792b1cb5a42b900c5.tar.bz2 ChibiOS-af25622db89ab50b7bad608792b1cb5a42b900c5.zip | |
Fixed some forgotten details.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3621 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32F1xx/hal_lld_f103.h | 3 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 26 |
2 files changed, 16 insertions, 13 deletions
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 77672ad01..398167ca8 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -340,6 +340,7 @@ /* RTC attributes.*/
#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -486,6 +487,7 @@ /* RTC attributes.*/
#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
@@ -632,6 +634,7 @@ /* RTC attributes.*/
#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index a43268377..7ab2dff84 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -133,19 +133,19 @@ * @name PWR_CR register bits definitions
* @{
*/
-#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
-#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
-#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
-
-#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
-#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
-#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
+#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
+#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
+#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
+
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
/** @} */
/**
|