git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6160 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 7 insertions, 7 deletions

diff --git a/os/hal/platforms/STM32/TIMv1/icu_lld.c b/os/hal/platforms/STM32/TIMv1/icu_lld.c
index 67f3a3816..09be838a6 100644
--- a/os/hal/platforms/STM32/TIMv1/icu_lld.c
+++ b/os/hal/platforms/STM32/TIMv1/icu_lld.c
@@ -610,7 +610,7 @@ void icu_lld_enable(ICUDriver *icup) {
   }

   if (icup->config->overflow_cb != NULL)

     icup->tim->DIER |= STM32_TIM_DIER_UIE;

-  icup->tim->CR1  = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;

+  icup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;

 }

 

 /**

diff --git a/os/hal/platforms/STM32/TIMv1/stm32_tim.h b/os/hal/platforms/STM32/TIMv1/stm32_tim.h
index 66f05bb28..ce0274c33 100644
--- a/os/hal/platforms/STM32/TIMv1/stm32_tim.h
+++ b/os/hal/platforms/STM32/TIMv1/stm32_tim.h
@@ -180,7 +180,7 @@
 #define STM32_TIM_CCMR1_OC1PE               (1U << 3)

 

 #define STM32_TIM_CCMR1_OC1M_MASK           ((7U << 4) | (1U << 16))

-#define STM32_TIM_CCMR1_OC1M(n)             ((((n) & 3) << 4) |             \

+#define STM32_TIM_CCMR1_OC1M(n)             ((((n) & 7) << 4) |             \

                                              (((n) >> 2) << 16))

 

 #define STM32_TIM_CCMR1_OC1CE               (1U << 7)

@@ -192,7 +192,7 @@
 #define STM32_TIM_CCMR1_OC2PE               (1U << 11)

 

 #define STM32_TIM_CCMR1_OC2M_MASK           ((7U << 12) | (1U << 24))

-#define STM32_TIM_CCMR1_OC2M(n)             ((((n) & 3) << 12) |            \

+#define STM32_TIM_CCMR1_OC2M(n)             ((((n) & 7) << 12) |            \

                                              (((n) >> 2) << 24))

 

 #define STM32_TIM_CCMR1_OC2CE               (1U << 15)

@@ -226,7 +226,7 @@
 #define STM32_TIM_CCMR2_OC3PE               (1U << 3)

 

 #define STM32_TIM_CCMR2_OC3M_MASK           ((7U << 4) | (1U << 16))

-#define STM32_TIM_CCMR2_OC3M(n)             ((((n) & 3) << 4) |             \

+#define STM32_TIM_CCMR2_OC3M(n)             ((((n) & 7) << 4) |             \

                                              (((n) >> 2) << 16))

 

 #define STM32_TIM_CCMR2_OC3CE               (1U << 7)

@@ -238,7 +238,7 @@
 #define STM32_TIM_CCMR2_OC4PE               (1U << 11)

 

 #define STM32_TIM_CCMR2_OC4M_MASK           ((7U << 12) | (1U << 24))

-#define STM32_TIM_CCMR2_OC4M(n)             ((((n) & 3) << 12) |            \

+#define STM32_TIM_CCMR2_OC4M(n)             ((((n) & 7) << 12) |            \

                                              (((n) >> 2) << 24))

 

 #define STM32_TIM_CCMR2_OC4CE               (1U << 15)

@@ -354,7 +354,7 @@
 #define STM32_TIM_CCMR3_OC5PE               (1U << 3)

 

 #define STM32_TIM_CCMR3_OC5M_MASK           ((7U << 4) | (1U << 16))

-#define STM32_TIM_CCMR3_OC5M(n)             ((((n) & 3) << 4) |             \

+#define STM32_TIM_CCMR3_OC5M(n)             ((((n) & 7) << 4) |             \

                                              (((n) >> 2) << 16))

 

 #define STM32_TIM_CCMR3_OC5CE               (1U << 7)

@@ -363,7 +363,7 @@
 #define STM32_TIM_CCMR3_OC6PE               (1U << 11)

 

 #define STM32_TIM_CCMR3_OC6M_MASK           ((7U << 12) | (1U << 24))

-#define STM32_TIM_CCMR3_OC6M(n)             ((((n) & 3) << 12) |            \

+#define STM32_TIM_CCMR3_OC6M(n)             ((((n) & 7) << 12) |            \

                                              (((n) >> 2) << 24))

 

 #define STM32_TIM_CCMR3_OC6CE               (1U << 15)