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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-04-29 14:47:03 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-04-29 14:47:03 +0000 |
| commit | 634ea27d8e36bca2a15932941da65ea3d4a4457a (patch) | |
| tree | d204f806119a825a62fa037fc50b7d056dcd6117 /os/hal | |
| parent | 9b7b88dbe922226c92d056ae04e2096ee734ad4d (diff) | |
| download | ChibiOS-634ea27d8e36bca2a15932941da65ea3d4a4457a.tar.gz ChibiOS-634ea27d8e36bca2a15932941da65ea3d4a4457a.tar.bz2 ChibiOS-634ea27d8e36bca2a15932941da65ea3d4a4457a.zip | |
Fixed bug #491.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6892 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32L1xx/stm32l1xx.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 62a0a658e..f938db6b1 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -231,15 +231,16 @@ typedef enum IRQn #ifdef STM32L1XX_MDP
TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
- TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
- SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
- DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
- DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
- AES_IRQn = 55, /*!< AES global Interrupt */
- COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+ /* CHIBIOS FIX */
+ TIM5_IRQn = 45, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 46, /*!< SPI3 global Interrupt */
+ DMA2_Channel1_IRQn = 47, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 48, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 49, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 50, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 51, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 52, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 53 /*!< Comparator Channel Acquisition global Interrupt */
#endif
#ifdef STM32L1XX_HD
|