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author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-02-04 09:55:51 +0000 |
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committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-02-04 09:55:51 +0000 |
commit | 6034aab6e6c48c4de3f8488957350c8824c60adb (patch) | |
tree | 47a44c98ab34636f66ebd84a02ff9a13170f8d82 /os/hal | |
parent | 0f5f6dd222ffa0571e63cdfba6e6e8c1bddc4beb (diff) | |
download | ChibiOS-6034aab6e6c48c4de3f8488957350c8824c60adb.tar.gz ChibiOS-6034aab6e6c48c4de3f8488957350c8824c60adb.tar.bz2 ChibiOS-6034aab6e6c48c4de3f8488957350c8824c60adb.zip |
I2C. Nop.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@2704 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
-rw-r--r-- | os/hal/platforms/STM32/i2c_lld.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index e362284e4..9e519d412 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -89,7 +89,12 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { return; } else { - //i2c_lld_rxbyte(i2cp); // read first byte + /* In order to generate the non-acknowledge pulse after the last received + * data byte, the ACK bit must be cleared just after reading the second + * last data byte (after second last RxNE event). + */ + if (i2cp->id_slave_config->rxbytes > 1) + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // set ACK bit i2cp->id_state = I2C_MRECEIVE; // change status return; } @@ -118,6 +123,11 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { if ((i2cp->id_state == I2C_MWAIT_TF) && (i2cp->id_i2c->SR1 & I2C_SR1_RXNE | I2C_SR1_BTF | I2C_SR1_TXE)){ chSysLockFromIsr(); i2cp->id_slave_config->id_callback(i2cp, i2cp->id_slave_config); + + i = i2cp->id_i2c->SR1; + n = i2cp->id_i2c->SR2; + m = i2cp->id_i2c->CR1; + chSysUnlockFromIsr(); return; } @@ -294,11 +304,15 @@ bool_t i2c_lld_rxbyte(I2CDriver *i2cp) { #define rxdepth i2cp->id_slave_config->rxdepth #define rxbytes i2cp->id_slave_config->rxbytes + /* In order to generate the non-acknowledge pulse after the last received + * data byte, the ACK bit must be cleared just after reading the second + * last data byte (after second last RxNE event). + */ if (rxbufhead < rxbytes){ - if ((rxbytes - rxbufhead) == 1){ + rxbuf[rxbufhead] = i2cp->id_i2c->DR; + if ((rxbytes - rxbufhead) <= 2){ i2cp->id_i2c->CR1 &= (~I2C_CR1_ACK);// clear ACK bit for automatically send NACK } - rxbuf[rxbufhead] = i2cp->id_i2c->DR; rxbufhead++; return(FALSE); } |