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authorGiovanni Di Sirio <gdisirio@gmail.com>2015-02-05 12:45:05 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2015-02-05 12:45:05 +0000
commitf5a8502a288742f80cbaeb094911d75efff82b28 (patch)
treefd5ba619d678b48da913f3621939b126427d7077 /os/hal/src/mmc_spi.c
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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/yosys.h"
#include "kernel/satgen.h"
#include "kernel/sigtools.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct EquivInductWorker
{
	Module *module;
	SigMap sigmap;

	vector<Cell*> cells;
	pool<Cell*> workset;

	ezSatPtr ez;
	SatGen satgen;

	int max_seq;
	int success_counter;

	dict<int, int> ez_step_is_consistent;
	pool<Cell*> cell_warn_cache;
	SigPool undriven_signals;

	EquivInductWorker(Module *module, const pool<Cell*> &unproven_equiv_cells, bool model_undef, int max_seq) : module(module), sigmap(module),
			cells(module->selected_cells()), workset(unproven_equiv_cells),
			satgen(ez.get(), &sigmap), max_seq(max_seq), success_counter(0)
	{
		satgen.model_undef = model_undef;
	}

	void create_timestep(int step)
	{
		vector<int> ez_equal_terms;

		for (auto cell : cells) {
			if (!satgen.importCell(cell, step) && !cell_warn_cache.count(cell)) {
				log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
				cell_warn_cache.insert(cell);
			}
			if (cell->type == "$equiv") {
				SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
				SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
				if (bit_a != bit_b) {
					int ez_a = satgen.importSigBit(bit_a, step);
					int ez_b = satgen.importSigBit(bit_b, step);
					int cond = ez->IFF(ez_a, ez_b);
					if (satgen.model_undef)
						cond = ez->OR(cond, satgen.importUndefSigBit(bit_a, step));
					ez_equal_terms.push_back(cond);
				}
			}
		}

		if (satgen.model_undef) {
			for (auto bit : undriven_signals.export_all())
				ez->assume(ez->NOT(satgen.importUndefSigBit(bit, step)));
		}

		log_assert(!ez_step_is_consistent.count(step));
		ez_step_is_consistent[step] = ez->expression(ez->OpAnd, ez_equal_terms);
	}

	void run()
	{
		log("Found %d unproven $equiv cells in module %s:\n", GetSize(workset), log_id(module));

		if (satgen.model_undef) {
			for (auto cell : cells)
				if (yosys_celltypes.cell_known(cell->type))
					for (auto &conn : cell->connections())
						if (yosys_celltypes.cell_input(cell->type, conn.first))
							undriven_signals.add(sigmap(conn.second));
			for (auto cell : cells)
				if (yosys_celltypes.cell_known(cell->type))
					for (auto &conn : cell->connections())
						if (yosys_celltypes.cell_output(cell->type, conn.first))
							undriven_signals.del(sigmap(conn.second));
		}

		create_timestep(1);

		if (satgen.model_undef) {
			for (auto bit : satgen.initial_state.export_all())
				ez->assume(ez->NOT(satgen.importUndefSigBit(bit, 1)));
			log("  Undef modelling: force def on %d initial reg values and %d inputs.\n",
				GetSize(satgen.initial_state), GetSize(undriven_signals));
		}

		for (int step = 1; step <= max_seq; step++)
		{
			ez->assume(ez_step_is_consistent[step]);

			log("  Proving existence of base case for step %d. (%d clauses over %d variables)\n", step, ez->numCnfClauses(), ez->numCnfVariables());
			if (!ez->solve()) {
				log("  Proof for base case failed. Circuit inherently diverges!\n");
				return;
			}

			create_timestep(step+1);
			int new_step_not_consistent = ez->NOT(ez_step_is_consistent[step+1]);
			ez->bind(new_step_not_consistent);

			log("  Proving induction step %d. (%d clauses over %d variables)\n", step, ez->numCnfClauses(), ez->numCnfVariables());
			if (!ez->solve(new_step_not_consistent)) {