git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6242 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 199 insertions, 0 deletions

diff --git a/os/hal/ports/STM32F0xx/hal_lld.c b/os/hal/ports/STM32F0xx/hal_lld.c
new file mode 100644
index 000000000..09ab62923
--- /dev/null
+++ b/os/hal/ports/STM32F0xx/hal_lld.c
@@ -0,0 +1,199 @@
+/*

+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio

+

+    Licensed under the Apache License, Version 2.0 (the "License");

+    you may not use this file except in compliance with the License.

+    You may obtain a copy of the License at

+

+        http://www.apache.org/licenses/LICENSE-2.0

+

+    Unless required by applicable law or agreed to in writing, software

+    distributed under the License is distributed on an "AS IS" BASIS,

+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

+    See the License for the specific language governing permissions and

+    limitations under the License.

+*/

+

+/**

+ * @file    STM32F0xx/hal_lld.c

+ * @brief   STM32F0xx HAL subsystem low level driver source.

+ *

+ * @addtogroup HAL

+ * @{

+ */

+

+#include "hal.h"

+

+/*===========================================================================*/

+/* Driver local definitions.                                                 */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported variables.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local variables and types.                                         */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver local functions.                                                   */

+/*===========================================================================*/

+

+/**

+ * @brief   Initializes the backup domain.

+ * @note    WARNING! Changing clock source impossible without resetting

+ *          of the whole BKP domain.

+ */

+static void hal_lld_backup_domain_init(void) {

+

+  /* Backup domain access enabled and left open.*/

+  PWR->CR |= PWR_CR_DBP;

+

+  /* Reset BKP domain if different clock source selected.*/

+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){

+    /* Backup domain reset.*/

+    RCC->BDCR = RCC_BDCR_BDRST;

+    RCC->BDCR = 0;

+  }

+

+  /* If enabled then the LSE is started.*/

+#if STM32_LSE_ENABLED

+#if defined(STM32_LSE_BYPASS)

+  /* LSE Bypass.*/

+  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;

+#else

+  /* No LSE Bypass.*/

+  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;

+#endif

+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)

+    ;                                     /* Waits until LSE is stable.   */

+#endif

+

+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK

+  /* If the backup domain hasn't been initialized yet then proceed with

+     initialization.*/

+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {

+    /* Selects clock source.*/

+    RCC->BDCR |= STM32_RTCSEL;

+

+    /* RTC clock enabled.*/

+    RCC->BDCR |= RCC_BDCR_RTCEN;

+  }

+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */

+}

+

+/*===========================================================================*/

+/* Driver interrupt handlers.                                                */

+/*===========================================================================*/

+

+/*===========================================================================*/

+/* Driver exported functions.                                                */

+/*===========================================================================*/

+

+/**

+ * @brief   Low level HAL driver initialization.

+ *

+ * @notapi

+ */

+void hal_lld_init(void) {

+

+  /* Reset of all peripherals.*/

+  rccResetAPB1(0xFFFFFFFF);

+  rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);

+

+  /* PWR clock enabled.*/

+  rccEnablePWRInterface(FALSE);

+

+  /* Initializes the backup domain.*/

+  hal_lld_backup_domain_init();

+

+#if defined(STM32_DMA_REQUIRED)

+  dmaInit();

+#endif

+

+  /* Programmable voltage detector enable.*/

+#if STM32_PVD_ENABLE

+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);

+#endif /* STM32_PVD_ENABLE */

+}

+

+/**

+ * @brief   STM32 clocks and PLL initialization.

+ * @note    All the involved constants come from the file @p board.h.

+ * @note    This function should be invoked just after the system reset.

+ *

+ * @special

+ */

+void stm32_clock_init(void) {

+

+#if !STM32_NO_INIT

+  /* HSI setup, it enforces the reset situation in order to handle possible

+     problems with JTAG probes and re-initializations.*/

+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */

+  while (!(RCC->CR & RCC_CR_HSIRDY))

+    ;                                       /* Wait until HSI is stable.    */

+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */

+  RCC->CFGR = 0;                            /* CFGR reset value.            */

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

+    ;                                       /* Waits until HSI is selected. */

+

+#if STM32_HSE_ENABLED

+  /* HSE activation.*/

+#if defined(STM32_HSE_BYPASS)

+  /* HSE Bypass.*/

+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;

+#else

+  /* No HSE Bypass.*/

+  RCC->CR |= RCC_CR_HSEON;

+#endif

+  while (!(RCC->CR & RCC_CR_HSERDY))

+    ;                                       /* Waits until HSE is stable.   */

+#endif

+

+#if STM32_HSE14_ENABLED

+  /* HSI14 activation.*/

+  RCC->CR2 |= RCC_CR2_HSI14ON;

+  while (!(RCC->CR2 & RCC_CR2_HSI14RDY))

+    ;                                       /* Waits until HSI14 is stable. */

+#endif

+

+#if STM32_LSI_ENABLED

+  /* LSI activation.*/

+  RCC->CSR |= RCC_CSR_LSION;

+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)

+    ;                                       /* Waits until LSI is stable.   */

+#endif

+

+  /* Clock settings.*/

+  RCC->CFGR  = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |

+               STM32_ADCPRE | STM32_PPRE   | STM32_HPRE;

+  RCC->CFGR2 = STM32_PREDIV;

+  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW |

+               STM32_USART1SW;

+

+#if STM32_ACTIVATE_PLL

+  /* PLL activation.*/

+  RCC->CR   |= RCC_CR_PLLON;

+  while (!(RCC->CR & RCC_CR_PLLRDY))

+    ;                                       /* Waits until PLL is stable.   */

+#endif

+

+  /* Flash setup and final clock selection.   */

+  FLASH->ACR = STM32_FLASHBITS;

+

+  /* Switching to the configured clock source if it is different from HSI.*/

+#if (STM32_SW != STM32_SW_HSI)

+  /* Switches clock source.*/

+  RCC->CFGR |= STM32_SW;

+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

+    ;                                       /* Waits selection complete.    */

+#endif

+

+  /* SYSCFG clock enabled here because it is a multi-functional unit shared

+     among multiple drivers.*/

+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);

+#endif /* !STM32_NO_INIT */

+}

+

+/** @} */