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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-03-16 16:17:22 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-03-16 16:17:22 +0000 |
| commit | d2228809d1e2232362f6f951bc1667057a5d0b00 (patch) | |
| tree | 5e8ddd4ba5d36db695c0d1c3a497bc6a59e7ce96 /os/hal/ports/STM32 | |
| parent | bff3b1b8952403052cef7cdb6c12d41a3208a6f9 (diff) | |
| download | ChibiOS-d2228809d1e2232362f6f951bc1667057a5d0b00.tar.gz ChibiOS-d2228809d1e2232362f6f951bc1667057a5d0b00.tar.bz2 ChibiOS-d2228809d1e2232362f6f951bc1667057a5d0b00.zip | |
Fixed bug #1021.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12699 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
Diffstat (limited to 'os/hal/ports/STM32')
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/hal_lld.h | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 2c6e75b6b..11af45327 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -2432,58 +2432,58 @@ /**
* @brief USART4 clock.
*/
-#define STM32_USART4CLK STM32_PCLK1
+#define STM32_UART4CLK STM32_PCLK1
/**
* @brief USART5 clock.
*/
-#define STM32_USART5CLK STM32_PCLK1
+#define STM32_UART5CLK STM32_PCLK1
/**
* @brief USART7 clock.
*/
-#define STM32_USART7CLK STM32_PCLK1
+#define STM32_UART7CLK STM32_PCLK1
/**
* @brief USART8 clock.
*/
-#define STM32_USART8CLK STM32_PCLK2
+#define STM32_UART8CLK STM32_PCLK1
#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL2_Q_CK
#define STM32_USART2CLK STM32_PLL2_Q_CK
#define STM32_USART3CLK STM32_PLL2_Q_CK
-#define STM32_USART4CLK STM32_PLL2_Q_CK
-#define STM32_USART5CLK STM32_PLL2_Q_CK
-#define STM32_USART7CLK STM32_PLL2_Q_CK
-#define STM32_USART8CLK STM32_PLL2_Q_CK
+#define STM32_UART4CLK STM32_PLL2_Q_CK
+#define STM32_UART5CLK STM32_PLL2_Q_CK
+#define STM32_UART7CLK STM32_PLL2_Q_CK
+#define STM32_UART8CLK STM32_PLL2_Q_CK
#elif STM32_USART234578SEL == STM32_USART234578SEL_PLL3_Q_CK
#define STM32_USART2CLK STM32_PLL3_Q_CK
#define STM32_USART3CLK STM32_PLL3_Q_CK
-#define STM32_USART4CLK STM32_PLL3_Q_CK
-#define STM32_USART5CLK STM32_PLL3_Q_CK
-#define STM32_USART7CLK STM32_PLL3_Q_CK
-#define STM32_USART8CLK STM32_PLL3_Q_CK
+#define STM32_UART4CLK STM32_PLL3_Q_CK
+#define STM32_UART5CLK STM32_PLL3_Q_CK
+#define STM32_UART7CLK STM32_PLL3_Q_CK
+#define STM32_UART8CLK STM32_PLL3_Q_CK
#elif STM32_USART234578SEL == STM32_USART234578SEL_HSI_KER_CK
#define STM32_USART2CLK STM32_HSI_CK
#define STM32_USART3CLK STM32_HSI_CK
-#define STM32_USART4CLK STM32_HSI_CK
-#define STM32_USART5CLK STM32_HSI_CK
-#define STM32_USART7CLK STM32_HSI_CK
-#define STM32_USART8CLK STM32_HSI_CK
+#define STM32_UART4CLK STM32_HSI_CK
+#define STM32_UART5CLK STM32_HSI_CK
+#define STM32_UART7CLK STM32_HSI_CK
+#define STM32_UART8CLK STM32_HSI_CK
#elif STM32_USART234578SEL == STM32_USART234578SEL_CSI_KER_CK
#define STM32_USART2CLK STM32_CSI_CK
#define STM32_USART3CLK STM32_CSI_CK
-#define STM32_USART4CLK STM32_CSI_CK
-#define STM32_USART5CLK STM32_CSI_CK
-#define STM32_USART7CLK STM32_CSI_CK
-#define STM32_USART8CLK STM32_CSI_CK
+#define STM32_UART4CLK STM32_CSI_CK
+#define STM32_UART5CLK STM32_CSI_CK
+#define STM32_UART7CLK STM32_CSI_CK
+#define STM32_UART8CLK STM32_CSI_CK
#elif STM32_USART234578SEL == STM32_USART234578SEL_LSE_CK
#define STM32_USART2CLK STM32_LSE_CK
#define STM32_USART3CLK STM32_LSE_CK
-#define STM32_USART4CLK STM32_LSE_CK
-#define STM32_USART6CLK STM32_LSE_CK
-#define STM32_USART7CLK STM32_LSE_CK
-#define STM32_USART8CLK STM32_LSE_CK
+#define STM32_UART4CLK STM32_LSE_CK
+#define STM32_UART6CLK STM32_LSE_CK
+#define STM32_UART7CLK STM32_LSE_CK
+#define STM32_UART8CLK STM32_LSE_CK
#else
#error "invalid source selected for STM32_USART234578SEL clock"
#endif
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