diff options
| author | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-11-25 16:02:00 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-11-25 16:02:00 +0000 |
| commit | c0eefeeb5c531642953fc8a1126fee276ccc5133 (patch) | |
| tree | d8c5b5402cec5e0e15fe2ed9fe7da77ec2df97d0 /os/hal/ports/STM32 | |
| parent | c8700fc5eeeeb71fce78f169b49ffd62c4748414 (diff) | |
| download | ChibiOS-c0eefeeb5c531642953fc8a1126fee276ccc5133.tar.gz ChibiOS-c0eefeeb5c531642953fc8a1126fee276ccc5133.tar.bz2 ChibiOS-c0eefeeb5c531642953fc8a1126fee276ccc5133.zip | |
RTC update for F4.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12442 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h | 8 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 113 |
2 files changed, 33 insertions, 88 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h index 3dee3dee2..52ff026c5 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h @@ -1187,14 +1187,6 @@ /* External declarations. */
/*===========================================================================*/
-/* Various helpers.*/
-#include "nvic.h"
-#include "cache.h"
-#include "mpu_v7m.h"
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 46135aa89..71bdc5720 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -84,6 +84,39 @@ */
/*===========================================================================*/
+/* Common. */
+/*===========================================================================*/
+
+/* RNG attributes.*/
+#define STM32_HAS_RNG1 TRUE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#if !defined(STM32F2XX)
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#else
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#endif
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
+#define STM32_RTC_NUM_ALARMS 2
+#define STM32_RTC_STORAGE_SIZE 80
+#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
+#define STM32_RTC_WKUP_HANDLER Vector4C
+#define STM32_RTC_ALARM_HANDLER VectorE4
+#define STM32_RTC_TAMP_STAMP_NUMBER 2
+#define STM32_RTC_WKUP_NUMBER 3
+#define STM32_RTC_ALARM_NUMBER 41
+#define STM32_RTC_ALARM_EXTI 17
+#define STM32_RTC_TAMP_STAMP_EXTI 21
+#define STM32_RTC_WKUP_EXTI 22
+#define STM32_RTC_IRQ_ENABLE() do { \
+ nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI21_PRIORITY); \
+ nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI22_PRIORITY); \
+ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
+} while (false)
+
+
+/*===========================================================================*/
/* STM32F469xx, STM32F479xx. */
/*===========================================================================*/
@@ -247,13 +280,6 @@ #define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -627,13 +653,6 @@ #define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -985,13 +1004,6 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -1365,13 +1377,6 @@ #define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -1742,13 +1747,6 @@ #define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -2074,13 +2072,6 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -2386,13 +2377,6 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@@ -2690,30 +2674,6 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#if !defined(STM32F2XX)
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#else
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#endif
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_TAMP_STAMP_HANDLER Vector48
-#define STM32_RTC_WKUP_HANDLER Vector49
-#define STM32_RTC_ALARM_HANDLER VectorE4
-#define STM32_RTC_TAMP_STAMP_NUMBER 2
-#define STM32_RTC_WKUP_NUMBER 3
-#define STM32_RTC_ALARM_NUMBER 41
-#define STM32_RTC_ALARM_EXTI 17
-#define STM32_RTC_TAMP_STAMP_EXTI 21
-#define STM32_RTC_WKUP_EXTI 22
-#define STM32_RTC_IRQ_ENABLE() do { \
- nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI21_PRIORITY); \
- nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI22_PRIORITY); \
- nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
-} while (false)
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
@@ -3041,13 +3001,6 @@ /* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 FALSE
-/* RTC attributes.*/
-#define STM32_HAS_RTC TRUE
-#define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
-#define STM32_RTC_NUM_ALARMS 2
-#define STM32_RTC_HAS_INTERRUPTS FALSE
-
/* SDIO attributes.*/
#define STM32_HAS_SDIO TRUE
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|