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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-28 10:55:48 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-28 10:55:48 +0000 |
| commit | 56cf40e555db653dc503afe4e750f23ef5cb66d6 (patch) | |
| tree | c6784562e3034df9520dd1f070e2c82d03f5c9f6 /os/hal/ports/STM32/STM32L4xx | |
| parent | 03f609e27c2dca200fce5b42f3a3467570e718bd (diff) | |
| download | ChibiOS-56cf40e555db653dc503afe4e750f23ef5cb66d6.tar.gz ChibiOS-56cf40e555db653dc503afe4e750f23ef5cb66d6.tar.bz2 ChibiOS-56cf40e555db653dc503afe4e750f23ef5cb66d6.zip | |
STM32 LPUART1 support added.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8539 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L4xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 22 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_rcc.h | 32 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 5 |
4 files changed, 59 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index 30aa83ad7..b4298d3ae 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -243,7 +243,7 @@ void stm32_clock_init(void) { STM32_CLK48SEL | STM32_LPTIM2SEL | STM32_LPTIM1SEL |
STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL |
STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL |
- STM32_USART2SEL | STM32_USART1SEL;
+ STM32_USART2SEL | STM32_USART1SEL | STM32_LPUART1SEL;
#if STM32_SAI2SEL != STM32_SAI2SEL_OFF
ccipr |= STM32_SAI2SEL;
#endif
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index ec107d911..2827f2fa2 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -645,6 +645,13 @@ #endif
/**
+ * @brief LPUART1 clock source.
+ */
+#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#endif
+
+/**
* @brief I2C1 clock source.
*/
#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__)
@@ -1833,6 +1840,21 @@ #endif
/**
+ * @brief LPUART1 clock frequency.
+ */
+#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN)
+#define STM32_LPUART1CLK STM32_PCLK1
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
+#define STM32_LPUART1CLK STM32_SYSCLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
+#define STM32_LPUART1CLK STM32_HSI16CLK
+#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
+#define STM32_LPUART1CLK STM32_LSECLK
+#else
+#error "invalid source selected for LPUART1 clock"
+#endif
+
+/**
* @brief I2C1 clock frequency.
*/
#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN)
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h index 434ddde16..c45341540 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_rcc.h @@ -1064,6 +1064,38 @@ * @api
*/
#define rccDisableUART5(lp) rccDisableAPB1R1(RCC_APB1ENR1_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1R1(RCC_APB1RSTR1_UART5RST)
+
+/**
+ * @brief Enables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPUART1(lp) rccEnableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
+
+/**
+ * @brief Disables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableLPUART1(lp) rccDisableAPB1R2(RCC_APB1ENR2_LPUART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPUART1() rccResetAPB1R2(RCC_APB1RSTR2_LPUART1RST)
/** @} */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 640753f3b..dea76f8e2 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -370,13 +370,16 @@ #define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
#define STM32_UART5_TX_DMA_CHN 0x00000002
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER Vector158
+#define STM32_LPUART1_NUMBER 70
+
#define STM32_HAS_USART6 FALSE
#define STM32_HAS_UART7 FALSE
#define STM32_HAS_UART8 FALSE
/* USB attributes.*/
#define STM32_HAS_USB FALSE
-
#define STM32_HAS_OTG1 TRUE
#define STM32_OTG1_HANDLER Vector14C
#define STM32_OTG1_NUMBER 67
|