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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-28 10:55:48 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-28 10:55:48 +0000 |
| commit | 56cf40e555db653dc503afe4e750f23ef5cb66d6 (patch) | |
| tree | c6784562e3034df9520dd1f070e2c82d03f5c9f6 /os/hal/ports/STM32/STM32L0xx | |
| parent | 03f609e27c2dca200fce5b42f3a3467570e718bd (diff) | |
| download | ChibiOS-56cf40e555db653dc503afe4e750f23ef5cb66d6.tar.gz ChibiOS-56cf40e555db653dc503afe4e750f23ef5cb66d6.tar.bz2 ChibiOS-56cf40e555db653dc503afe4e750f23ef5cb66d6.zip | |
STM32 LPUART1 support added.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8539 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 25 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_registry.h | 16 |
2 files changed, 41 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 892cd1c9b..44981343d 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -584,6 +584,31 @@ * @api
*/
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableLPUART1(lp) rccEnableAPB1(RCC_APB1ENR_LPUART1EN, lp)
+
+/**
+ * @brief Disables the LPUART1 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableLPUART1(lp) rccDisableAPB1(RCC_APB1ENR_LPUART1EN, lp)
+
+/**
+ * @brief Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetLPUART1() rccResetAPB1(RCC_APB1RSTR_LPUART1RST)
/** @} */
/**
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index 4a1ad5acb..a92a5ffa4 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -249,6 +249,10 @@ STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE
@@ -491,10 +495,16 @@ STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE
#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
/* USB attributes.*/
#define STM32_HAS_USB TRUE
@@ -739,10 +749,16 @@ STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
+#define STM32_HAS_LPUART1 TRUE
+#define STM32_LPUART1_HANDLER VectorB4
+#define STM32_LPUART1_NUMBER 29
+
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE
#define STM32_HAS_USART6 FALSE
+#define STM32_HAS_UART7 FALSE
+#define STM32_HAS_UART8 FALSE
/* USB attributes.*/
#define STM32_HAS_USB TRUE
|