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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
| commit | c953aa5ac86e4f913c41333a773a0903e0860d35 (patch) | |
| tree | d2c00d4f0eaf25892e5d4f4ade85b2866e2c38de /os/hal/ports/STM32/STM32F7xx | |
| parent | df330879bb5c5630e847e2e9eec471080b0d18a4 (diff) | |
| download | ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.gz ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.bz2 ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.zip | |
Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep modes. Now RCC macros are able to set or clear the LP bit of a peripheral.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 15 |
2 files changed, 12 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 87698308f..20af00675 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -88,7 +88,7 @@ static void hal_lld_backup_domain_init(void) { #endif /* HAL_USE_RTC */
#if STM32_BKPRAM_ENABLE
- rccEnableBKPSRAM(false);
+ rccEnableBKPSRAM(true);
PWR->CSR1 |= PWR_CSR1_BRE;
while ((PWR->CSR1 & PWR_CSR1_BRR) == 0)
@@ -299,7 +299,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
- rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
}
/** @} */
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 094d6900f..a34ced725 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -62,6 +62,8 @@ RCC->APB1ENR |= (mask); \
if (lp) \
RCC->APB1LPENR |= (mask); \
+ else \
+ RCC->APB1LPENR &= ~(mask); \
}
/**
@@ -73,7 +75,6 @@ */
#define rccDisableAPB1(mask) { \
RCC->APB1ENR &= ~(mask); \
- RCC->APB1LPENR &= ~(mask); \
}
/**
@@ -100,6 +101,8 @@ RCC->APB2ENR |= (mask); \
if (lp) \
RCC->APB2LPENR |= (mask); \
+ else \
+ RCC->APB2LPENR &= ~(mask); \
}
/**
@@ -111,7 +114,6 @@ */
#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
- RCC->APB2LPENR &= ~(mask); \
}
/**
@@ -138,6 +140,8 @@ RCC->AHB1ENR |= (mask); \
if (lp) \
RCC->AHB1LPENR |= (mask); \
+ else \
+ RCC->AHB1LPENR &= ~(mask); \
}
/**
@@ -149,7 +153,6 @@ */
#define rccDisableAHB1(mask) { \
RCC->AHB1ENR &= ~(mask); \
- RCC->AHB1LPENR &= ~(mask); \
}
/**
@@ -176,6 +179,8 @@ RCC->AHB2ENR |= (mask); \
if (lp) \
RCC->AHB2LPENR |= (mask); \
+ else \
+ RCC->AHB2LPENR &= ~(mask); \
}
/**
@@ -187,7 +192,6 @@ */
#define rccDisableAHB2(mask) { \
RCC->AHB2ENR &= ~(mask); \
- RCC->AHB2LPENR &= ~(mask); \
}
/**
@@ -214,6 +218,8 @@ RCC->AHB3ENR |= (mask); \
if (lp) \
RCC->AHB3LPENR |= (mask); \
+ else \
+ RCC->AHB3LPENR &= ~(mask); \
}
/**
@@ -225,7 +231,6 @@ */
#define rccDisableAHB3(mask) { \
RCC->AHB3ENR &= ~(mask); \
- RCC->AHB3LPENR &= ~(mask); \
}
/**
|