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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-04 12:49:40 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-04 12:49:40 +0000 |
| commit | bf86c9d9beb4bfc9ce8505c873bc909d53f6424f (patch) | |
| tree | 1f2a2fbaa94e726b7ab2b65ca9d8999837d95096 /os/hal/ports/STM32/STM32F7xx | |
| parent | 1f474f2dd6c28baeaa95bb54c7a08a38e6d4e18c (diff) | |
| download | ChibiOS-bf86c9d9beb4bfc9ce8505c873bc909d53f6424f.tar.gz ChibiOS-bf86c9d9beb4bfc9ce8505c873bc909d53f6424f.tar.bz2 ChibiOS-bf86c9d9beb4bfc9ce8505c873bc909d53f6424f.zip | |
Added support up to STM32 UART8 in v2 drivers.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8155 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 90 |
1 files changed, 72 insertions, 18 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 5b24de152..cce276e1b 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -1359,24 +1359,6 @@ #define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
/**
- * @brief Enables the USART6 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
-
-/**
- * @brief Disables the USART6 peripheral clock.
- *
- * @param[in] lp low power enable flag
- *
- * @api
- */
-#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
-
-/**
* @brief Enables the UART4 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
@@ -1431,11 +1413,83 @@ #define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
/**
+ * @brief Enables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
+ * @brief Disables the USART6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp)
+
+/**
* @brief Resets the USART6 peripheral.
*
* @api
*/
#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST)
+
+/**
+ * @brief Enables the UART7 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp)
+
+/**
+ * @brief Disables the UART7 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp)
+
+/**
+ * @brief Resets the UART7 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST)
+
+/**
+ * @brief Enables the UART8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp)
+
+/**
+ * @brief Disables the UART8 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp)
+
+/**
+ * @brief Resets the UART8 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST)
/** @} */
/**
|