diff options
| author | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-12-26 07:31:13 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@110e8d01-0319-4d1e-a829-52ad28d1bb01> | 2018-12-26 07:31:13 +0000 |
| commit | 1a9aa9ad975d4f520d5b88c17eb634dfe46a2012 (patch) | |
| tree | fb9e75c689a9d06307c02be0ce731ec9cc07f45c /os/hal/ports/STM32/STM32F7xx | |
| parent | 2b17172903e9829979e45ff388a58ea1b0ff80fd (diff) | |
| download | ChibiOS-1a9aa9ad975d4f520d5b88c17eb634dfe46a2012.tar.gz ChibiOS-1a9aa9ad975d4f520d5b88c17eb634dfe46a2012.tar.bz2 ChibiOS-1a9aa9ad975d4f520d5b88c17eb634dfe46a2012.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12483 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_rcc.h | 57 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/stm32_registry.h | 12 |
2 files changed, 69 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h index 68fc7f18b..f092c5b64 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h @@ -1502,6 +1502,7 @@ * @api
*/
#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)
+/** @} */
/**
* @name DMA2D peripheral specific RCC operations
@@ -1560,6 +1561,62 @@ /** @} */
/**
+ * @name HASH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the CRYP peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRYP(lp) rccEnableAHB2(RCC_AHB2ENR_CRYPEN, lp)
+
+/**
+ * @brief Disables the CRYP peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableCRYP() rccDisableAHB2(RCC_AHB2ENR_CRYPEN)
+
+/**
+ * @brief Resets the CRYP peripheral.
+ *
+ * @api
+ */
+#define rccResetCRYP() rccResetAHB2(RCC_AHB2RSTR_CRYPRST)
+/** @} */
+
+/**
+ * @name HASH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the HASH peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableHASH(lp) rccEnableAHB2(RCC_AHB2ENR_HASHEN, lp)
+
+/**
+ * @brief Disables the HASH peripheral clock.
+ *
+ * @api
+ */
+#define rccDisableHASH() rccDisableAHB2(RCC_AHB2ENR_HASHEN)
+
+/**
+ * @brief Resets the HASH peripheral.
+ *
+ * @api
+ */
+#define rccResetHASH() rccResetAHB2(RCC_AHB2RSTR_HASHRST)
+/** @} */
+
+/**
* @name FSMC peripherals specific RCC operations
* @{
*/
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h index 241315b92..05652cca0 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h @@ -62,6 +62,18 @@ nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \
} while (false)
+#if defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F756xx) || \
+ defined(STM32F777xx) || defined(STM32F779xx) || defined(__DOXYGEN__)
+#define STM32_HAS_HASH1 TRUE
+#define STM32_HAS_AES1 TRUE
+#define STM32_HASH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_HASH1_DMA_CHN 0x20000000
+
+#else /* Devices without cryp nor hash.*/
+#define STM32_HAS_HASH1 FALSE
+#define STM32_HAS_AES1 FALSE
+#endif
+
/*===========================================================================*/
/* STM32F722xx, STM32F723xx, STM32F732xx, STM32F733xx. */
/*===========================================================================*/
|