Merged LTDC DMA2D code in STM32F4xx HAL.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8052 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 138 insertions, 0 deletions

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 4bb3f4fcd..03cd5f06f 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -232,6 +232,17 @@ void stm32_clock_init(void) {
     ;

 #endif

 

+#if STM32_ACTIVATE_PLLSAI

+  /* PLLSAI activation.*/

+  RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;

+  RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;

+  RCC->CR |= RCC_CR_PLLSAION;

+

+  /* Waiting for PLL lock.*/

+  while (!(RCC->CR & RCC_CR_PLLSAIRDY))

+    ;

+#endif

+

   /* Other clock-related settings (dividers, MCO etc).*/

   RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |

               STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index c466a8274..ab5a327de 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -362,6 +362,13 @@
 #define STM32_I2SSRC_PLLI2S     (0 << 23)   /**< I2SSRC is PLLI2S.          */

 #define STM32_I2SSRC_CKIN       (1 << 23)   /**< I2S_CKIN is PLLI2S.        */

 

+#define STM32_SAISRC_NOCLOCK    (0 << 23)   /**< No clock.                  */

+#define STM32_SAISRC_PLL        (1 << 23)   /**< SAI_CKIN is PLL.           */

+#define STM32_SAIR_DIV2         (0 << 16)   /**< R divided by 2.            */

+#define STM32_SAIR_DIV4         (1 << 16)   /**< R divided by 4.            */

+#define STM32_SAIR_DIV8         (2 << 16)   /**< R divided by 8.            */

+#define STM32_SAIR_DIV16        (3 << 16)   /**< R divided by 16.           */

+

 #define STM32_MCO1PRE_MASK      (7 << 24)   /**< MCO1PRE mask.              */

 #define STM32_MCO1PRE_DIV1      (0 << 24)   /**< MCO1 divided by 1.         */

 #define STM32_MCO1PRE_DIV2      (4 << 24)   /**< MCO1 divided by 2.         */

@@ -1278,6 +1285,52 @@
 #error "invalid STM32_PLLI2SR_VALUE value specified"

 #endif

 

+/*

+ * PLLSAI enable check.

+ */

+#if !defined(STM32_SAISRC)

+#define STM32_SAISRC                STM32_SAISRC_NOCLOCK

+#endif

+

+/**

+ * @brief   PLL activation flag.

+ */

+#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)

+#define STM32_ACTIVATE_PLLSAI       TRUE

+#else

+#define STM32_ACTIVATE_PLLSAI       FALSE

+#endif

+

+/**

+ * @brief   STM32_PLLSAIN field.

+ */

+#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) ||        \

+    defined(__DOXYGEN__)

+#define STM32_PLLSAIN               (STM32_PLLSAIN_VALUE << 6)

+#else

+#error "invalid STM32_PLLSAIN_VALUE value specified"

+#endif

+

+/**

+ * @brief   STM32_PLLSAIQ field.

+ */

+#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) ||          \

+    defined(__DOXYGEN__)

+#define STM32_PLLSAIQ               (STM32_PLLSAIQ_VALUE << 24)

+#else

+#error "invalid STM32_PLLSAIR_VALUE value specified"

+#endif

+

+/**

+ * @brief   STM32_PLLSAIR field.

+ */

+#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) ||           \

+    defined(__DOXYGEN__)

+#define STM32_PLLSAIR               (STM32_PLLSAIR_VALUE << 28)

+#else

+#error "invalid STM32_PLLSAIR_VALUE value specified"

+#endif

+

 /**

  * @brief   PLL VCO frequency.

  */

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
index 1c9a90a0a..548fc62c7 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h
@@ -158,6 +158,22 @@
 

 #define STM32_FSMC_NUMBER           48

 

+/*

+ * LTDC

+ */

+#define STM32_LTDC_EV_HANDLER       Vector1A0

+#define STM32_LTDC_ER_HANDLER       Vector1A4

+

+#define STM32_LTDC_EV_NUMBER        88

+#define STM32_LTDC_ER_NUMBER        89

+

+/*

+ * DMA2D

+ */

+#define STM32_DMA2D_HANDLER         Vector1A8

+

+#define STM32_DMA2D_NUMBER          90

+

 /** @} */

 

 /*===========================================================================*/

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index 393fa5994..b86c85d58 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -1468,6 +1468,36 @@
 #define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST)

 

 /**

+ * @name    DMA2D peripheral specific RCC operations

+ * @{

+ */

+/**

+ * @brief   Enables the DMA2D peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp)

+

+/**

+ * @brief   Disables the DMA2D peripheral clock.

+ *

+ * @param[in] lp        low power enable flag

+ *

+ * @api

+ */

+#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp)

+

+/**

+ * @brief   Resets the DMA2D peripheral.

+ *

+ * @api

+ */

+#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST)

+/** @} */

+

+/**

  * @name    FSMC peripherals specific RCC operations

  * @{

  */

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index b875fe02a..c3fa55879 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -322,6 +322,12 @@
 #define STM32_HAS_OTG1                      TRUE

 #define STM32_HAS_OTG2                      TRUE

 

+/* LTDC attributes.*/

+#define STM32_HAS_LTDC                      TRUE

+

+/* DMA2D attributes.*/

+#define STM32_HAS_DMA2D                     TRUE

+

 /* FSMC attributes.*/

 #define STM32_HAS_FSMC                      TRUE

 #define STM32_FSMC_IS_FMC                   TRUE

@@ -334,6 +340,7 @@
                                              STM32_DMA_STREAM_ID_MSK(2, 6) |\

                                              STM32_DMA_STREAM_ID_MSK(2, 7))

 #define STM32_FSMC_DMA_CHN                  0x03010201

+

 #endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */

 

 /*===========================================================================*/

@@ -591,6 +598,12 @@
 #define STM32_HAS_OTG1                      TRUE

 #define STM32_HAS_OTG2                      TRUE

 

+/* LTDC attributes.*/

+#define STM32_HAS_LTDC                      FALSE

+

+/* DMA2D attributes.*/

+#define STM32_HAS_DMA2D                     FALSE

+

 /* FSMC attributes.*/

 #define STM32_HAS_FSMC                      TRUE

 #define STM32_FSMC_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

@@ -602,6 +615,7 @@
                                              STM32_DMA_STREAM_ID_MSK(2, 6) |\

                                              STM32_DMA_STREAM_ID_MSK(2, 7))

 #define STM32_FSMC_DMA_CHN                  0x03010201

+

 #endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */

 

 /*===========================================================================*/

@@ -815,8 +829,15 @@
 #define STM32_HAS_OTG1                      TRUE

 #define STM32_HAS_OTG2                      FALSE

 

+/* LTDC attributes.*/

+#define STM32_HAS_LTDC                      FALSE

+

+/* DMA2D attributes.*/

+#define STM32_HAS_DMA2D                     FALSE

+

 /* FSMC attributes.*/

 #define STM32_HAS_FSMC                      FALSE

+

 #endif /* defined(STM32F401xx) */

 

 /*===========================================================================*/

@@ -1029,8 +1050,15 @@
 #define STM32_HAS_OTG1                      TRUE

 #define STM32_HAS_OTG2                      FALSE

 

+/* LTDC attributes.*/

+#define STM32_HAS_LTDC                      FALSE

+

+/* DMA2D attributes.*/

+#define STM32_HAS_DMA2D                     FALSE

+

 /* FSMC attributes.*/

 #define STM32_HAS_FSMC                      FALSE

+

 #endif

 /** @} */