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| author | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-12-27 19:35:13 +0000 |
|---|---|---|
| committer | barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-12-27 19:35:13 +0000 |
| commit | e486e61a2208575ba9d6d663ef27ac23eb5a4f99 (patch) | |
| tree | fe736baf973e0c629a8e1067b5da6ccc76edaad7 /os/hal/ports/STM32/STM32F1xx | |
| parent | 81ca2c65f3e774aa805447ff79ab796aab58a3d0 (diff) | |
| download | ChibiOS-e486e61a2208575ba9d6d663ef27ac23eb5a4f99.tar.gz ChibiOS-e486e61a2208575ba9d6d663ef27ac23eb5a4f99.tar.bz2 ChibiOS-e486e61a2208575ba9d6d663ef27ac23eb5a4f99.zip | |
Fixed typos in comments.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7600 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F1xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h | 8 |
3 files changed, 8 insertions, 8 deletions
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h b/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h index b9fac165e..d886fe78e 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld_f100.h @@ -71,7 +71,7 @@ #define STM32_PLLIN_MAX 24000000
/**
- * @brief Maximum PLLs input clock frequency.
+ * @brief Minimum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 1000000
@@ -81,7 +81,7 @@ #define STM32_PLLOUT_MAX 24000000
/**
- * @brief Maximum PLL output clock frequency.
+ * @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h b/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h index ff010ba2c..6b8aaec43 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld_f103.h @@ -71,7 +71,7 @@ #define STM32_PLLIN_MAX 25000000
/**
- * @brief Maximum PLLs input clock frequency.
+ * @brief Minimum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 1000000
@@ -81,7 +81,7 @@ #define STM32_PLLOUT_MAX 72000000
/**
- * @brief Maximum PLL output clock frequency.
+ * @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
diff --git a/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h b/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h index 20880b28c..703c25e2a 100644 --- a/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/ports/STM32/STM32F1xx/hal_lld_f105_f107.h @@ -71,7 +71,7 @@ #define STM32_PLL1IN_MAX 12000000
/**
- * @brief Maximum PLL1 input clock frequency.
+ * @brief Minimum PLL1 input clock frequency.
*/
#define STM32_PLL1IN_MIN 3000000
@@ -81,7 +81,7 @@ #define STM32_PLL23IN_MAX 5000000
/**
- * @brief Maximum PLL2 and PLL3 input clock frequency.
+ * @brief Minimum PLL2 and PLL3 input clock frequency.
*/
#define STM32_PLL23IN_MIN 3000000
@@ -91,7 +91,7 @@ #define STM32_PLL1VCO_MAX 144000000
/**
- * @brief Maximum PLL1 VCO clock frequency.
+ * @brief Minimum PLL1 VCO clock frequency.
*/
#define STM32_PLL1VCO_MIN 36000000
@@ -101,7 +101,7 @@ #define STM32_PLL23VCO_MAX 148000000
/**
- * @brief Maximum PLL2 and PLL3 VCO clock frequency.
+ * @brief Minimum PLL2 and PLL3 VCO clock frequency.
*/
#define STM32_PLL23VCO_MIN 80000000
|