Fixed bug 3041414. Various improvements to the STM32 HAL.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2119 35acf78f-673a-0410-8e92-d51de3d6d3f4

11 files changed, 244 insertions, 214 deletions

diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c
index 908966ac7..1a2a3b725 100644
--- a/os/hal/platforms/STM32/adc_lld.c
+++ b/os/hal/platforms/STM32/adc_lld.c
@@ -35,7 +35,7 @@
 /*===========================================================================*/

 

 /** @brief ADC1 driver identifier.*/

-#if USE_STM32_ADC1 || defined(__DOXYGEN__)

+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)

 ADCDriver ADCD1;

 #endif

 

@@ -51,7 +51,7 @@ ADCDriver ADCD1;
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if USE_STM32_ADC1 || defined(__DOXYGEN__)

+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)

 /**

  * @brief   ADC1 DMA interrupt handler (channel 1).

  */

@@ -111,7 +111,7 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
  */

 void adc_lld_init(void) {

 

-#if USE_STM32_ADC1

+#if STM32_ADC_USE_ADC1

   /* ADC reset, ensures reset state in order to avoid trouble with JTAGs.*/

   RCC->APB2RSTR = RCC_APB2RSTR_ADC1RST;

   RCC->APB2RSTR = 0;

@@ -120,7 +120,7 @@ void adc_lld_init(void) {
   adcObjectInit(&ADCD1);

   ADCD1.ad_adc = ADC1;

   ADCD1.ad_dmap = STM32_DMA1;

-  ADCD1.ad_dmaprio = STM32_ADC1_DMA_PRIORITY << 12;

+  ADCD1.ad_dmaprio = STM32_ADC_ADC1_DMA_PRIORITY << 12;

 

   /* Temporary activation.*/

   RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;

@@ -152,11 +152,11 @@ void adc_lld_start(ADCDriver *adcp) {
 

   /* If in stopped state then enables the ADC and DMA clocks.*/

   if (adcp->ad_state == ADC_STOP) {

-#if USE_STM32_ADC1

+#if STM32_ADC_USE_ADC1

     if (&ADCD1 == adcp) {

       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA1_Channel1_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_ADC1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY));

       DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR;

       RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;

     }

@@ -178,7 +178,7 @@ void adc_lld_stop(ADCDriver *adcp) {
 

   /* If in ready state then disables the ADC clock.*/

   if (adcp->ad_state == ADC_READY) {

-#if USE_STM32_ADC1

+#if STM32_ADC_USE_ADC1

     if (&ADCD1 == adcp) {

       ADC1->CR1 = 0;

       ADC1->CR2 = 0;

diff --git a/os/hal/platforms/STM32/adc_lld.h b/os/hal/platforms/STM32/adc_lld.h
index 426ae7924..aacea62cc 100644
--- a/os/hal/platforms/STM32/adc_lld.h
+++ b/os/hal/platforms/STM32/adc_lld.h
@@ -65,22 +65,22 @@
  * @details If set to @p TRUE the support for ADC1 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_ADC1) || defined(__DOXYGEN__)

-#define USE_STM32_ADC1              TRUE

+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)

+#define STM32_ADC_USE_ADC1                  TRUE

 #endif

 

 /**

  * @brief   ADC1 DMA priority (0..3|lowest..highest).

  */

-#if !defined(STM32_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC1_DMA_PRIORITY     3

+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ADC_ADC1_DMA_PRIORITY         3

 #endif

 

 /**

  * @brief   ADC1 interrupt priority level setting.

  */

-#if !defined(STM32_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC1_IRQ_PRIORITY     5

+#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_ADC_ADC1_IRQ_PRIORITY         5

 #endif

 

 /**

@@ -96,6 +96,10 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+#if !STM32_ADC_USE_ADC1

+#error "ADC driver activated but no ADC peripheral assigned"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -251,7 +255,7 @@ typedef struct {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if USE_STM32_ADC1 && !defined(__DOXYGEN__)

+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)

 extern ADCDriver ADCD1;

 #endif

 

diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c
index 6e20d856e..7b390bb7e 100644
--- a/os/hal/platforms/STM32/can_lld.c
+++ b/os/hal/platforms/STM32/can_lld.c
@@ -35,7 +35,7 @@
 /*===========================================================================*/

 

 /** @brief ADC1 driver identifier.*/

-#if USE_STM32_CAN1 || defined(__DOXYGEN__)

+#if STM32_CAN_USE_CAN1 || defined(__DOXYGEN__)

 CANDriver CAND1;

 #endif

 

@@ -154,7 +154,7 @@ CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) {
  */

 void can_lld_init(void) {

 

-#if USE_STM32_CAN1

+#if STM32_CAN_USE_CAN1

   /* CAN reset, ensures reset state in order to avoid trouble with JTAGs.*/

   RCC->APB1RSTR = RCC_APB1RSTR_CAN1RST;

   RCC->APB1RSTR = 0;

@@ -173,16 +173,16 @@ void can_lld_init(void) {
 void can_lld_start(CANDriver *canp) {

 

   /* Clock activation.*/

-#if USE_STM32_CAN1

+#if STM32_CAN_USE_CAN1

   if (&CAND1 == canp) {

     NVICEnableVector(USB_HP_CAN1_TX_IRQn,

-                     CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));

+                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

     NVICEnableVector(USB_LP_CAN1_RX0_IRQn,

-                     CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));

+                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

     NVICEnableVector(CAN1_RX1_IRQn,

-                     CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));

+                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

     NVICEnableVector(CAN1_SCE_IRQn,

-                     CORTEX_PRIORITY_MASK(STM32_CAN1_IRQ_PRIORITY));

+                     CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));

     RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;

   }

 #endif

@@ -258,7 +258,7 @@ void can_lld_stop(CANDriver *canp) {
 

   /* If in ready state then disables the CAN peripheral.*/

   if (canp->cd_state == CAN_READY) {

-#if USE_STM32_CAN1

+#if STM32_CAN_USE_CAN1

     if (&CAND1 == canp) {

       CAN1->MCR = 0x00010002;                   /* Register reset value.    */

       CAN1->IER = 0x00000000;                   /* All sources disabled.    */

diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h
index fd4784fc7..3a314e424 100644
--- a/os/hal/platforms/STM32/can_lld.h
+++ b/os/hal/platforms/STM32/can_lld.h
@@ -78,15 +78,15 @@
  * @details If set to @p TRUE the support for ADC1 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_CAN1) || defined(__DOXYGEN__)

-#define USE_STM32_CAN1              TRUE

+#if !defined(STM32_CAN_USE_CAN1) || defined(__DOXYGEN__)

+#define STM32_CAN_USE_CAN1                  TRUE

 #endif

 

 /**

  * @brief   CAN1 interrupt priority level setting.

  */

-#if !defined(STM32_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_CAN1_IRQ_PRIORITY     11

+#if !defined(STM32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_CAN_CAN1_IRQ_PRIORITY         11

 #endif

 

 /*===========================================================================*/

@@ -97,6 +97,10 @@
 #error "CAN sleep mode not supported in this architecture"

 #endif

 

+#if !STM32_CAN_USE_CAN1

+#error "CAN driver activated but no CAN peripheral assigned"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -292,7 +296,7 @@ typedef struct {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if USE_STM32_CAN1 && !defined(__DOXYGEN__)

+#if STM32_CAN_USE_CAN1 && !defined(__DOXYGEN__)

 extern CANDriver CAND1;

 #endif

 

diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index bc7e45522..851cf07c2 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -38,7 +38,7 @@
  * @brief   PWM1 driver identifier.

  * @note    The driver PWM1 allocates the complex timer TIM1 when enabled.

  */

-#if defined(USE_STM32_PWM1) || defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__)

 PWMDriver PWMD1;

 #endif

 

@@ -46,7 +46,7 @@ PWMDriver PWMD1;
  * @brief   PWM2 driver identifier.

  * @note    The driver PWM2 allocates the timer TIM2 when enabled.

  */

-#if defined(USE_STM32_PWM2) || defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__)

 PWMDriver PWMD2;

 #endif

 

@@ -54,7 +54,7 @@ PWMDriver PWMD2;
  * @brief   PWM3 driver identifier.

  * @note    The driver PWM3 allocates the timer TIM3 when enabled.

  */

-#if defined(USE_STM32_PWM3) || defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__)

 PWMDriver PWMD3;

 #endif

 

@@ -91,7 +91,7 @@ static void stop_channels(PWMDriver *pwmp) {
   pwmp->pd_tim->CCMR2 = 0;                  /* Channels 3 and 4 frozen.     */

 }

 

-#if USE_STM32_PWM2 || USE_STM32_PWM3 || USE_STM32_PWM4 || defined(__DOXYGEN__)

+#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || USE_STM32_PWM4 || defined(__DOXYGEN__)

 /**

  * @brief   Common TIM2...TIM4 IRQ handler.

  * @note    It is assumed that the various sources are only activated if the

@@ -115,13 +115,13 @@ static void serve_interrupt(PWMDriver *pwmp) {
   if ((sr & TIM_SR_UIF) != 0)

     pwmp->pd_config->pc_callback();

 }

-#endif /* USE_STM32_PWM2 || USE_STM32_PWM3 || USE_STM32_PWM4 */

+#endif /* STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || USE_STM32_PWM4 */

 

 /*===========================================================================*/

 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if USE_STM32_PWM1

+#if STM32_PWM_USE_TIM1

 /**

  * @brief   TIM1 update interrupt handler.

  * @note    It is assumed that this interrupt is only activated if the callback

@@ -162,9 +162,9 @@ CH_IRQ_HANDLER(TIM1_CC_IRQHandler) {
 

   CH_IRQ_EPILOGUE();

 }

-#endif /* USE_STM32_PWM1 */

+#endif /* STM32_PWM_USE_TIM1 */

 

-#if USE_STM32_PWM2

+#if STM32_PWM_USE_TIM2

 /**

  * @brief TIM2 interrupt handler.

  */

@@ -176,9 +176,9 @@ CH_IRQ_HANDLER(TIM2_IRQHandler) {
 

   CH_IRQ_EPILOGUE();

 }

-#endif /* USE_STM32_PWM2 */

+#endif /* STM32_PWM_USE_TIM2 */

 

-#if USE_STM32_PWM3

+#if STM32_PWM_USE_TIM3

 /**

  * @brief TIM3 interrupt handler.

  */

@@ -190,7 +190,7 @@ CH_IRQ_HANDLER(TIM3_IRQHandler) {
 

   CH_IRQ_EPILOGUE();

 }

-#endif /* USE_STM32_PWM3 */

+#endif /* STM32_PWM_USE_TIM3 */

 

 #if USE_STM32_PWM4

 /**

@@ -215,7 +215,7 @@ CH_IRQ_HANDLER(TIM4_IRQHandler) {
  */

 void pwm_lld_init(void) {

 

-#if USE_STM32_PWM1

+#if STM32_PWM_USE_TIM1

   /* TIM1 reset, ensures reset state in order to avoid trouble with JTAGs.*/

   RCC->APB2RSTR = RCC_APB2RSTR_TIM1RST;

   RCC->APB2RSTR = 0;

@@ -226,7 +226,7 @@ void pwm_lld_init(void) {
   PWMD1.pd_tim = TIM1;

 #endif

 

-#if USE_STM32_PWM2

+#if STM32_PWM_USE_TIM2

   /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/

   RCC->APB1RSTR = RCC_APB1RSTR_TIM2RST;

   RCC->APB1RSTR = 0;

@@ -237,7 +237,7 @@ void pwm_lld_init(void) {
   PWMD2.pd_tim = TIM2;

 #endif

 

-#if USE_STM32_PWM3

+#if STM32_PWM_USE_TIM3

   /* TIM2 reset, ensures reset state in order to avoid trouble with JTAGs.*/

   RCC->APB1RSTR = RCC_APB1RSTR_TIM3RST;

   RCC->APB1RSTR = 0;

@@ -270,33 +270,33 @@ void pwm_lld_start(PWMDriver *pwmp) {
 

   if (pwmp->pd_state == PWM_STOP) {

     /* Clock activation.*/

-#if USE_STM32_PWM1

+#if STM32_PWM_USE_TIM1

     if (&PWMD1 == pwmp) {

       NVICEnableVector(TIM1_UP_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_PWM_PWM1_IRQ_PRIORITY));

       NVICEnableVector(TIM1_CC_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_PWM1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_PWM_PWM1_IRQ_PRIORITY));

       RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;

     }

 #endif

-#if USE_STM32_PWM2

+#if STM32_PWM_USE_TIM2

     if (&PWMD2 == pwmp) {

       NVICEnableVector(TIM2_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_PWM2_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_PWM_PWM2_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;

     }

 #endif

-#if USE_STM32_PWM3

+#if STM32_PWM_USE_TIM3

     if (&PWMD3 == pwmp) {

       NVICEnableVector(TIM3_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_PWM3_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_PWM_PWM3_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

     }

 #endif

 #if USE_STM32_PWM4

     if (&PWMD4 == pwmp) {

       NVICEnableVector(TIM4_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_PWM4_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_PWM_PWM4_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_TIM4EN;

     }

 #endif

@@ -367,26 +367,26 @@ void pwm_lld_stop(PWMDriver *pwmp) {
     pwmp->pd_tim->BDTR = 0;

     pwmp->pd_tim->DIER = 0;

 

-#if USE_STM32_PWM1

+#if STM32_PWM_USE_TIM1

     if (&PWMD1 == pwmp) {

       NVICDisableVector(TIM1_UP_IRQn);

       NVICDisableVector(TIM1_CC_IRQn);

       RCC->APB2ENR &= ~RCC_APB2ENR_TIM1EN;

     }

 #endif

-#if USE_STM32_PWM2

+#if STM32_PWM_USE_TIM2

     if (&PWMD2 == pwmp) {

       NVICDisableVector(TIM2_IRQn);

       RCC->APB1ENR &= ~RCC_APB1ENR_TIM2EN;

     }

 #endif

-#if USE_STM32_PWM3

+#if STM32_PWM_USE_TIM3

     if (&PWMD3 == pwmp) {

       NVICDisableVector(TIM3_IRQn);

       RCC->APB1ENR &= ~RCC_APB1ENR_TIM3EN;

     }

 #endif

-#if USE_STM32_PWM2

+#if STM32_PWM_USE_TIM4

     if (&PWMD4 == pwmp) {

       NVICDisableVector(TIM4_IRQn);

       RCC->APB1ENR &= ~RCC_APB1ENR_TIM4EN;

diff --git a/os/hal/platforms/STM32/pwm_lld.h b/os/hal/platforms/STM32/pwm_lld.h
index 8605bb314..79606654d 100644
--- a/os/hal/platforms/STM32/pwm_lld.h
+++ b/os/hal/platforms/STM32/pwm_lld.h
@@ -37,7 +37,7 @@
 /**

  * @brief   Number of PWM channels per PWM driver.

  */

-#define PWM_CHANNELS                4

+#define PWM_CHANNELS                        4

 

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

@@ -48,8 +48,8 @@
  * @details If set to @p TRUE the support for PWM1 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_PWM1) || defined(__DOXYGEN__)

-#define USE_STM32_PWM1              TRUE

+#if !defined(STM32_PWM_USE_TIM1) || defined(__DOXYGEN__)

+#define STM32_PWM_USE_TIM1                  TRUE

 #endif

 

 /**

@@ -57,8 +57,8 @@
  * @details If set to @p TRUE the support for PWM2 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_PWM2) || defined(__DOXYGEN__)

-#define USE_STM32_PWM2              TRUE

+#if !defined(STM32_PWM_USE_TIM2) || defined(__DOXYGEN__)

+#define STM32_PWM_USE_TIM2                  TRUE

 #endif

 

 /**

@@ -66,8 +66,8 @@
  * @details If set to @p TRUE the support for PWM3 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_PWM3) || defined(__DOXYGEN__)

-#define USE_STM32_PWM3              TRUE

+#if !defined(STM32_PWM_USE_TIM3) || defined(__DOXYGEN__)

+#define STM32_PWM_USE_TIM3                  TRUE

 #endif

 

 /**

@@ -75,46 +75,52 @@
  * @details If set to @p TRUE the support for PWM4 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_PWM4) || defined(__DOXYGEN__)

-#define USE_STM32_PWM4              TRUE

+#if !defined(STM32_PWM_USE_TIM4) || defined(__DOXYGEN__)

+#define STM32_PWM_USE_TIM4                  TRUE

 #endif

 

 /**

  * @brief   PWM1 interrupt priority level setting.

  */

-#if !defined(STM32_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_PWM1_IRQ_PRIORITY     7

+#if !defined(STM32_PWM_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_PWM_PWM1_IRQ_PRIORITY         7

 #endif

 

 /**

  * @brief   PWM2 interrupt priority level setting.

  */

-#if !defined(STM32_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_PWM2_IRQ_PRIORITY     7

+#if !defined(STM32_PWM_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_PWM_PWM2_IRQ_PRIORITY         7

 #endif

 

 /**

  * @brief   PWM3 interrupt priority level setting.

  */

-#if !defined(STM32_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_PWM3_IRQ_PRIORITY     7

+#if !defined(STM32_PWM_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_PWM_PWM3_IRQ_PRIORITY         7

 #endif

 

 /**

  * @brief   PWM4 interrupt priority level setting.

  */

-#if !defined(STM32_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_PWM4_IRQ_PRIORITY     7

+#if !defined(STM32_PWM_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_PWM_PWM4_IRQ_PRIORITY         7

 #endif

 

 /*===========================================================================*/

 /* Configuration checks.                                                     */

 /*===========================================================================*/

 

-#if USE_STM32_PWM4 && defined(STM32F10X_LD)

+#if STM32_PWM_USE_TIM4 && defined(STM32F10X_LD)

 #error "TIM4 not present in low density STM32 devices"

 #endif

 

+#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \

+    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \

+    !STM32_SERIAL_USE_UART5

+#error "PWM driver activated but no TIM peripheral assigned"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -209,19 +215,19 @@ typedef struct {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if defined(USE_STM32_PWM1) && !defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM1) && !defined(__DOXYGEN__)

 extern PWMDriver PWMD1;

 #endif

 

-#if defined(USE_STM32_PWM2) && !defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM2) && !defined(__DOXYGEN__)

 extern PWMDriver PWMD2;

 #endif

 

-#if defined(USE_STM32_PWM3) && !defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM3) && !defined(__DOXYGEN__)

 extern PWMDriver PWMD3;

 #endif

 

-#if defined(USE_STM32_PWM4) && !defined(__DOXYGEN__)

+#if defined(STM32_PWM_USE_TIM4) && !defined(__DOXYGEN__)

 extern PWMDriver PWMD4;

 #endif

 

diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/serial_lld.c
index d46d660e2..f6df553e6 100644
--- a/os/hal/platforms/STM32/serial_lld.c
+++ b/os/hal/platforms/STM32/serial_lld.c
@@ -35,31 +35,29 @@
 /*===========================================================================*/

 

 /** @brief USART1 serial driver identifier.*/

-#if USE_STM32_USART1 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)

 SerialDriver SD1;

 #endif

 

 /** @brief USART2 serial driver identifier.*/

-#if USE_STM32_USART2 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)

 SerialDriver SD2;

 #endif

 

 /** @brief USART3 serial driver identifier.*/

-#if USE_STM32_USART3 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)

 SerialDriver SD3;

 #endif

 

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)

 /** @brief UART4 serial driver identifier.*/

-#if USE_STM32_UART4 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)

 SerialDriver SD4;

 #endif

 

 /** @brief UART5 serial driver identifier.*/

-#if USE_STM32_UART5 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)

 SerialDriver SD5;

 #endif

-#endif

 

 /*===========================================================================*/

 /* Driver local variables.                                                   */

@@ -121,9 +119,9 @@ static void usart_deinit(USART_TypeDef *u) {
   u->CR3 = 0;

 }

 

-#if USE_STM32_USART1 || USE_STM32_USART2 || USE_STM32_USART3 ||             \

-    ((USE_STM32_USART4 || USE_STM32_USART5) &&                              \

-     (defined(STM32F10X_HD) || defined(STM32F10X_CL)))

+#if STM32_SERIAL_USE_USART1 || STM32_SERIAL_USE_USART2 ||                   \

+    STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4  ||                   \

+    USE_STM32_USART5

 /**

  * @brief   Error handling routine.

  *

@@ -184,48 +182,46 @@ static void serve_interrupt(SerialDriver *sdp) {
 }

 #endif

 

-#if USE_STM32_USART1 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)

 static void notify1(void) {

 

   USART1->CR1 |= USART_CR1_TXEIE;

 }

 #endif

 

-#if USE_STM32_USART2 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)

 static void notify2(void) {

 

   USART2->CR1 |= USART_CR1_TXEIE;

 }

 #endif

 

-#if USE_STM32_USART3 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)

 static void notify3(void) {

 

   USART3->CR1 |= USART_CR1_TXEIE;

 }

 #endif

 

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)

-#if USE_STM32_UART4 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)

 static void notify4(void) {

 

   UART4->CR1 |= USART_CR1_TXEIE;

 }

 #endif

 

-#if USE_STM32_UART5 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)

 static void notify5(void) {

 

   UART5->CR1 |= USART_CR1_TXEIE;

 }

 #endif

-#endif

 

 /*===========================================================================*/

 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if USE_STM32_USART1 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)

 CH_IRQ_HANDLER(USART1_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

@@ -236,7 +232,7 @@ CH_IRQ_HANDLER(USART1_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_USART2 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)

 CH_IRQ_HANDLER(USART2_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

@@ -247,7 +243,7 @@ CH_IRQ_HANDLER(USART2_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_USART3 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)

 CH_IRQ_HANDLER(USART3_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

@@ -258,8 +254,7 @@ CH_IRQ_HANDLER(USART3_IRQHandler) {
 }

 #endif

 

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)

-#if USE_STM32_UART4 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)

 CH_IRQ_HANDLER(UART4_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

@@ -270,7 +265,7 @@ CH_IRQ_HANDLER(UART4_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_UART5 || defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)

 CH_IRQ_HANDLER(UART5_IRQHandler) {

 

   CH_IRQ_PROLOGUE();

@@ -280,7 +275,6 @@ CH_IRQ_HANDLER(UART5_IRQHandler) {
   CH_IRQ_EPILOGUE();

 }

 #endif

-#endif

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

@@ -291,32 +285,30 @@ CH_IRQ_HANDLER(UART5_IRQHandler) {
  */

 void sd_lld_init(void) {

 

-#if USE_STM32_USART1

+#if STM32_SERIAL_USE_USART1

   sdObjectInit(&SD1, NULL, notify1);

   SD1.usart = USART1;

 #endif

 

-#if USE_STM32_USART2

+#if STM32_SERIAL_USE_USART2

   sdObjectInit(&SD2, NULL, notify2);

   SD2.usart = USART2;

 #endif

 

-#if USE_STM32_USART3

+#if STM32_SERIAL_USE_USART3

   sdObjectInit(&SD3, NULL, notify3);

   SD3.usart = USART3;

 #endif

 

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL)

-#if USE_STM32_UART4

+#if STM32_SERIAL_USE_UART4

   sdObjectInit(&SD4, NULL, notify4);

   SD4.usart = UART4;

 #endif

 

-#if USE_STM32_UART5

+#if STM32_SERIAL_USE_UART5

   sdObjectInit(&SD5, NULL, notify5);

   SD5.usart = UART5;

 #endif

-#endif

 }

 

 /**

@@ -333,43 +325,41 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
     config = &default_config;

 

   if (sdp->state == SD_STOP) {

-#if USE_STM32_USART1

+#if STM32_SERIAL_USE_USART1

     if (&SD1 == sdp) {

       RCC->APB2ENR |= RCC_APB2ENR_USART1EN;

       NVICEnableVector(USART1_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_USART1_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));

     }

 #endif

-#if USE_STM32_USART2

+#if STM32_SERIAL_USE_USART2

     if (&SD2 == sdp) {

       RCC->APB1ENR |= RCC_APB1ENR_USART2EN;

       NVICEnableVector(USART2_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_USART2_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));

     }

 #endif

-#if USE_STM32_USART3

+#if STM32_SERIAL_USE_USART3

     if (&SD3 == sdp) {

       RCC->APB1ENR |= RCC_APB1ENR_USART3EN;

       NVICEnableVector(USART3_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_USART3_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));

     }

 #endif

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL)

-#if USE_STM32_UART4

+#if STM32_SERIAL_USE_UART4

     if (&SD4 == sdp) {

       RCC->APB1ENR |= RCC_APB1ENR_UART4EN;

       NVICEnableVector(UART4_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_UART4_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));

     }

 #endif

-#if USE_STM32_UART5

+#if STM32_SERIAL_USE_UART5

     if (&SD5 == sdp) {

       RCC->APB1ENR |= RCC_APB1ENR_UART5EN;

       NVICEnableVector(UART5_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_UART5_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));

     }

 #endif

-#endif

   }

   usart_init(sdp, config);

 }

@@ -385,43 +375,41 @@ void sd_lld_stop(SerialDriver *sdp) {
 

   if (sdp->state == SD_READY) {

     usart_deinit(sdp->usart);

-#if USE_STM32_USART1

+#if STM32_SERIAL_USE_USART1

     if (&SD1 == sdp) {

       RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;

       NVICDisableVector(USART1_IRQn);

       return;

     }

 #endif

-#if USE_STM32_USART2

+#if STM32_SERIAL_USE_USART2

     if (&SD2 == sdp) {

       RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;

       NVICDisableVector(USART2_IRQn);

       return;

     }

 #endif

-#if USE_STM32_USART3

+#if STM32_SERIAL_USE_USART3

     if (&SD3 == sdp) {

       RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;

       NVICDisableVector(USART3_IRQn);

       return;

     }

 #endif

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL)

-#if USE_STM32_UART4

+#if STM32_SERIAL_USE_UART4

     if (&SD4 == sdp) {

       RCC->APB1ENR &= ~RCC_APB1ENR_UART4EN;

       NVICDisableVector(UART4_IRQn);

       return;

     }

 #endif

-#if USE_STM32_UART5

+#if STM32_SERIAL_USE_UART5

     if (&SD5 == sdp) {

       RCC->APB1ENR &= ~RCC_APB1ENR_UART5EN;

       NVICDisableVector(UART5_IRQn);

       return;

     }

 #endif

-#endif

   }

 }

 

diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h
index 3df8b7e70..011dd865a 100644
--- a/os/hal/platforms/STM32/serial_lld.h
+++ b/os/hal/platforms/STM32/serial_lld.h
@@ -43,8 +43,8 @@
  * @details If set to @p TRUE the support for USART1 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(USE_STM32_USART1) || defined(__DOXYGEN__)

-#define USE_STM32_USART1            TRUE

+#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USE_USART1             TRUE

 #endif

 

 /**

@@ -52,8 +52,8 @@
  * @details If set to @p TRUE the support for USART2 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_USART2) || defined(__DOXYGEN__)

-#define USE_STM32_USART2            TRUE

+#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USE_USART2             TRUE

 #endif

 

 /**

@@ -61,19 +61,17 @@
  * @details If set to @p TRUE the support for USART3 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(USE_STM32_USART3) || defined(__DOXYGEN__)

-#define USE_STM32_USART3            TRUE

+#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USE_USART3             TRUE

 #endif

 

-

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)

 /**

  * @brief   UART4 driver enable switch.

  * @details If set to @p TRUE the support for UART4 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(USE_STM32_UART4) || defined(__DOXYGEN__)

-#define USE_STM32_UART4             TRUE

+#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USE_UART4              TRUE

 #endif

 

 /**

@@ -81,52 +79,65 @@
  * @details If set to @p TRUE the support for UART5 is included.

  * @note    The default is @p FALSE.

  */

-#if !defined(USE_STM32_USART3) || defined(__DOXYGEN__)

-#define USE_STM32_UART5             TRUE

-#endif

+#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USE_UART5              TRUE

 #endif

 

 /**

  * @brief   USART1 interrupt priority level setting.

  */

-#if !defined(STM32_USART1_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_USART1_PRIORITY       12

+#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USART1_PRIORITY        12

 #endif

 

 /**

  * @brief   USART2 interrupt priority level setting.

  */

-#if !defined(STM32_USART2_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_USART2_PRIORITY       12)

+#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USART2_PRIORITY        12)

 #endif

 

 /**

  * @brief   USART3 interrupt priority level setting.

  */

-#if !defined(STM32_USART3_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_USART3_PRIORITY       12

+#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SERIAL_USART3_PRIORITY        12

 #endif

 

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)

 /**

  * @brief   UART4 interrupt priority level setting.

  */

-#if !defined(STM32_UART4_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_UART4_PRIORITY        12

+#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SERIAL_UART4_PRIORITY         12

 #endif

 

 /**

  * @brief   UART5 interrupt priority level setting.

  */

-#if !defined(STM32_UART5_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_UART5_PRIORITY        12

-#endif

+#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SERIAL_UART5_PRIORITY         12

 #endif

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+#if STM32_SERIAL_USE_UART4 &&                                               \

+    !(defined(STM32F10X_HD) || defined(STM32F10X_CL))

+#error "UART4 only present in HD and CL devices"

+#endif

+

+#if STM32_SERIAL_USE_UART5 &&                                               \

+    !(defined(STM32F10X_HD) || defined(STM32F10X_CL))

+#error "UART5 only present in HD and CL devices"

+#endif

+

+#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \

+    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \

+    !STM32_SERIAL_USE_UART5

+#error "SERIAL driver activated but no USART/UART peripheral assigned"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -202,23 +213,21 @@ typedef struct {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if USE_STM32_USART1 && !defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)

 extern SerialDriver SD1;

 #endif

-#if USE_STM32_USART2 && !defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)

 extern SerialDriver SD2;

 #endif

-#if USE_STM32_USART3 && !defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)

 extern SerialDriver SD3;

 #endif

-#if defined(STM32F10X_HD) || defined(STM32F10X_CL)

-#if USE_STM32_UART4 && !defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)

 extern SerialDriver SD4;

 #endif

-#if USE_STM32_UART5 && !defined(__DOXYGEN__)

+#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)

 extern SerialDriver SD5;

 #endif

-#endif

 

 #ifdef __cplusplus

 extern "C" {

diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c
index 95501626c..31e2f097a 100644
--- a/os/hal/platforms/STM32/spi_lld.c
+++ b/os/hal/platforms/STM32/spi_lld.c
@@ -35,17 +35,17 @@
 /*===========================================================================*/

 

 /** @brief SPI1 driver identifier.*/

-#if USE_STM32_SPI1 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)

 SPIDriver SPID1;

 #endif

 

 /** @brief SPI2 driver identifier.*/

-#if USE_STM32_SPI2 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)

 SPIDriver SPID2;

 #endif

 

 /** @brief SPI3 driver identifier.*/

-#if USE_STM32_SPI3 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)

 SPIDriver SPID3;

 #endif

 

@@ -112,7 +112,7 @@ static void spi_start_wait(SPIDriver *spip, size_t n,
 /* Driver interrupt handlers.                                                */

 /*===========================================================================*/

 

-#if USE_STM32_SPI1 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__)

 /**

  * @brief   SPI1 RX DMA interrupt handler (channel 2).

  */

@@ -122,7 +122,7 @@ CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
 

   spi_stop(&SPID1);

   if ((DMA1->ISR & DMA_ISR_TEIF2) != 0) {

-    STM32_SPI1_DMA_ERROR_HOOK();

+    STM32_SPI_SPI1_DMA_ERROR_HOOK();

   }

   DMA1->IFCR = DMA_IFCR_CGIF2  | DMA_IFCR_CTCIF2 |

                DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;

@@ -137,7 +137,7 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
 

   CH_IRQ_PROLOGUE();

 

-  STM32_SPI1_DMA_ERROR_HOOK();

+  STM32_SPI_SPI1_DMA_ERROR_HOOK();

   DMA1->IFCR = DMA_IFCR_CGIF3  | DMA_IFCR_CTCIF3 |

                DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3;

 

@@ -145,7 +145,7 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_SPI2 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__)

 /**

  * @brief   SPI2 RX DMA interrupt handler (channel 4).

  */

@@ -155,7 +155,7 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
 

   spi_stop(&SPID2);

   if ((DMA1->ISR & DMA_ISR_TEIF4) != 0) {

-    STM32_SPI2_DMA_ERROR_HOOK();

+    STM32_SPI_SPI2_DMA_ERROR_HOOK();

   }

   DMA1->IFCR = DMA_IFCR_CGIF4  | DMA_IFCR_CTCIF4 |

                DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;

@@ -170,7 +170,7 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
 

   CH_IRQ_PROLOGUE();

 

-  STM32_SPI2_DMA_ERROR_HOOK();

+  STM32_SPI_SPI2_DMA_ERROR_HOOK();

   DMA1->IFCR = DMA_IFCR_CGIF5  | DMA_IFCR_CTCIF5 |

                DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;

 

@@ -178,7 +178,7 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
 }

 #endif

 

-#if USE_STM32_SPI3 || defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__)

 /**

  * @brief   SPI3 RX DMA interrupt handler (DMA2, channel 1).

  */

@@ -188,7 +188,7 @@ CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
 

   spi_stop(&SPID3);

   if ((DMA2->ISR & DMA_ISR_TEIF1) != 0) {

-    STM32_SPI3_DMA_ERROR_HOOK();

+    STM32_SPI_SPI3_DMA_ERROR_HOOK();

   }

   DMA2->IFCR = DMA_IFCR_CGIF1  | DMA_IFCR_CTCIF1 |

                DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;

@@ -203,7 +203,7 @@ CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
 

   CH_IRQ_PROLOGUE();

 

-  STM32_SPI3_DMA_ERROR_HOOK();

+  STM32_SPI_SPI3_DMA_ERROR_HOOK();

   DMA2->IFCR = DMA_IFCR_CGIF2  | DMA_IFCR_CTCIF2 |

                DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;

 

@@ -222,7 +222,7 @@ void spi_lld_init(void) {
 

   dummytx = 0xFFFF;

 

-#if USE_STM32_SPI1

+#if STM32_SPI_USE_SPI1

   RCC->APB2RSTR     = RCC_APB2RSTR_SPI1RST;

   RCC->APB2RSTR     = 0;

   spiObjectInit(&SPID1);

@@ -230,10 +230,10 @@ void spi_lld_init(void) {
   SPID1.spd_spi     = SPI1;

   SPID1.spd_dmarx   = DMA1_Channel2;

   SPID1.spd_dmatx   = DMA1_Channel3;

-  SPID1.spd_dmaprio = STM32_SPI1_DMA_PRIORITY << 12;

+  SPID1.spd_dmaprio = STM32_SPI_SPI1_DMA_PRIORITY << 12;

 #endif

 

-#if USE_STM32_SPI2

+#if STM32_SPI_USE_SPI2

   RCC->APB1RSTR     = RCC_APB1RSTR_SPI2RST;

   RCC->APB1RSTR     = 0;

   spiObjectInit(&SPID2);

@@ -241,10 +241,10 @@ void spi_lld_init(void) {
   SPID2.spd_spi     = SPI2;

   SPID2.spd_dmarx   = DMA1_Channel4;

   SPID2.spd_dmatx   = DMA1_Channel5;

-  SPID2.spd_dmaprio = STM32_SPI2_DMA_PRIORITY << 12;

+  SPID2.spd_dmaprio = STM32_SPI_SPI2_DMA_PRIORITY << 12;

 #endif

 

-#if USE_STM32_SPI3

+#if STM32_SPI_USE_SPI3

   RCC->APB1RSTR     = RCC_APB1RSTR_SPI3RST;

   RCC->APB1RSTR     = 0;

   spiObjectInit(&SPID3);

@@ -252,7 +252,7 @@ void spi_lld_init(void) {
   SPID3.spd_spi     = SPI3;

   SPID3.spd_dmarx   = DMA2_Channel1;

   SPID3.spd_dmatx   = DMA2_Channel2;

-  SPID3.spd_dmaprio = STM32_SPI3_DMA_PRIORITY << 12;

+  SPID3.spd_dmaprio = STM32_SPI_SPI3_DMA_PRIORITY << 12;

 #endif

 }

 

@@ -265,33 +265,33 @@ void spi_lld_start(SPIDriver *spip) {
 

   /* If in stopped state then enables the SPI and DMA clocks.*/

   if (spip->spd_state == SPI_STOP) {

-#if USE_STM32_SPI1

+#if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA1_Channel2_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY));

       NVICEnableVector(DMA1_Channel3_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI1_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY));

       RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;

     }

 #endif

-#if USE_STM32_SPI2

+#if STM32_SPI_USE_SPI2

     if (&SPID2 == spip) {

       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA1_Channel4_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY));

       NVICEnableVector(DMA1_Channel5_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI2_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;

     }

 #endif

-#if USE_STM32_SPI3

+#if STM32_SPI_USE_SPI3

     if (&SPID3 == spip) {

       dmaEnable(DMA2_ID);   /* NOTE: Must be enabled before the IRQs.*/

       NVICEnableVector(DMA2_Channel1_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI3_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY));

       NVICEnableVector(DMA2_Channel2_IRQn,

-                       CORTEX_PRIORITY_MASK(STM32_SPI3_IRQ_PRIORITY));

+                       CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY));

       RCC->APB1ENR |= RCC_APB1ENR_SPI3EN;

     }

 #endif

@@ -315,7 +315,7 @@ void spi_lld_stop(SPIDriver *spip) {
 

   /* If in ready state then disables the SPI clock.*/

   if (spip->spd_state == SPI_READY) {

-#if USE_STM32_SPI1

+#if STM32_SPI_USE_SPI1

     if (&SPID1 == spip) {

       NVICDisableVector(DMA1_Channel2_IRQn);

       NVICDisableVector(DMA1_Channel3_IRQn);

@@ -323,7 +323,7 @@ void spi_lld_stop(SPIDriver *spip) {
       RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;

     }

 #endif

-#if USE_STM32_SPI2

+#if STM32_SPI_USE_SPI2

     if (&SPID2 == spip) {

       NVICDisableVector(DMA1_Channel4_IRQn);

       NVICDisableVector(DMA1_Channel5_IRQn);

@@ -331,7 +331,7 @@ void spi_lld_stop(SPIDriver *spip) {
       RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;

     }

 #endif

-#if USE_STM32_SPI3

+#if STM32_SPI_USE_SPI3

     if (&SPID3 == spip) {

       NVICDisableVector(DMA2_Channel1_IRQn);

       NVICDisableVector(DMA2_Channel2_IRQn);

diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h
index b93497e41..fd91f6746 100644
--- a/os/hal/platforms/STM32/spi_lld.h
+++ b/os/hal/platforms/STM32/spi_lld.h
@@ -43,8 +43,8 @@
  * @details If set to @p TRUE the support for SPI1 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_SPI1) || defined(__DOXYGEN__)

-#define USE_STM32_SPI1              TRUE

+#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)

+#define STM32_SPI_USE_SPI1                  TRUE

 #endif

 

 /**

@@ -52,8 +52,8 @@
  * @details If set to @p TRUE the support for SPI2 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_SPI2) || defined(__DOXYGEN__)

-#define USE_STM32_SPI2              TRUE

+#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)

+#define STM32_SPI_USE_SPI2                  TRUE

 #endif

 

 /**

@@ -61,8 +61,8 @@
  * @details If set to @p TRUE the support for SPI3 is included.

  * @note    The default is @p TRUE.

  */

-#if !defined(USE_STM32_SPI3) || defined(__DOXYGEN__)

-#define USE_STM32_SPI3              FALSE

+#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)

+#define STM32_SPI_USE_SPI3                  FALSE

 #endif

 

 /**

@@ -71,8 +71,8 @@
  *          because of the channels ordering the RX channel has always priority

  *          over the TX channel.

  */

-#if !defined(STM32_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI1_DMA_PRIORITY     2

+#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI1_DMA_PRIORITY         2

 #endif

 

 /**

@@ -81,8 +81,8 @@
  *          because of the channels ordering the RX channel has always priority

  *          over the TX channel.

  */

-#if !defined(STM32_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI2_DMA_PRIORITY     2

+#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI2_DMA_PRIORITY         2

 #endif

 

 /**

@@ -91,29 +91,29 @@
  *          because of the channels ordering the RX channel has always priority

  *          over the TX channel.

  */

-#if !defined(STM32_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI3_DMA_PRIORITY     2

+#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI3_DMA_PRIORITY         2

 #endif

 

 /**

  * @brief   SPI1 interrupt priority level setting.

  */

-#if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI1_IRQ_PRIORITY     10

+#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI1_IRQ_PRIORITY         10

 #endif

 

 /**

  * @brief   SPI2 interrupt priority level setting.

  */

-#if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI2_IRQ_PRIORITY     10

+#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI2_IRQ_PRIORITY         10

 #endif

 

 /**

  * @brief   SPI3 interrupt priority level setting.

  */

-#if !defined(STM32_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_SPI3_IRQ_PRIORITY     10

+#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI3_IRQ_PRIORITY         10

 #endif

 

 /**

@@ -121,8 +121,8 @@
  * @note    The default action for DMA errors is a system halt because DMA error

  *          can only happen because programming errors.

  */

-#if !defined(STM32_SPI1_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

-#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()

+#if !defined(STM32_SPI_SPI1_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI1_DMA_ERROR_HOOK()     chSysHalt()

 #endif

 

 /**

@@ -130,8 +130,8 @@
  * @note    The default action for DMA errors is a system halt because DMA error

  *          can only happen because programming errors.

  */

-#if !defined(STM32_SPI2_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

-#define STM32_SPI2_DMA_ERROR_HOOK() chSysHalt()

+#if !defined(STM32_SPI_SPI2_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI2_DMA_ERROR_HOOK()     chSysHalt()

 #endif

 

 /**

@@ -139,14 +139,23 @@
  * @note    The default action for DMA errors is a system halt because DMA error

  *          can only happen because programming errors.

  */

-#if !defined(STM32_SPI3_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

-#define STM32_SPI3_DMA_ERROR_HOOK() chSysHalt()

+#if !defined(STM32_SPI_SPI3_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

+#define STM32_SPI_SPI3_DMA_ERROR_HOOK()     chSysHalt()

 #endif

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+#if STM32_SPI_USE_SPI3 &&                                                   \

+    !(defined(STM32F10X_HD) || defined(STM32F10X_CL))

+#error "SPI only present in HD and CL devices"

+#endif

+

+#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3

+#error "SPI driver activated but no SPI peripheral assigned"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

@@ -200,15 +209,15 @@ typedef struct {
 /* External declarations.                                                    */

 /*===========================================================================*/

 

-#if USE_STM32_SPI1 && !defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)

 extern SPIDriver SPID1;

 #endif

 

-#if USE_STM32_SPI2 && !defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)

 extern SPIDriver SPID2;

 #endif

 

-#if USE_STM32_SPI3 && !defined(__DOXYGEN__)

+#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)

 extern SPIDriver SPID3;

 #endif

 

diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h
index 1e294e212..e0d0851d6 100644
--- a/os/hal/platforms/STM32/uart_lld.h
+++ b/os/hal/platforms/STM32/uart_lld.h
@@ -146,6 +146,16 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+#if STM32_UART_USE_UART4 &&                                                 \

+    !(defined(STM32F10X_HD) || defined(STM32F10X_CL))

+#error "UART4 only present in HD and CL devices"

+#endif

+

+#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 &&                     \

+    !STM32_UART_USE_USART3 && !STM32_UART_USE_UART4

+#error "UART driver activated but no USART/UART peripheral assigned"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/