git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5848 35acf78f-673a-0410-8e92-d51de3d6d3f4

14 files changed, 273 insertions, 132 deletions

diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.c b/os/hal/platforms/SPC560Dxx/hal_lld.c
index b027e1ac4..229051979 100644
--- a/os/hal/platforms/SPC560Dxx/hal_lld.c
+++ b/os/hal/platforms/SPC560Dxx/hal_lld.c
@@ -96,6 +96,9 @@ void hal_lld_init(void) {
   PIT.CH[0].CVAL.R  = reg;

   PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */

   PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */

+

+  /* EDMA initialization.*/

+  edmaInit();

 }

 

 /**

diff --git a/os/hal/platforms/SPC560Dxx/platform.mk b/os/hal/platforms/SPC560Dxx/platform.mk
index 6505aa352..8e6c8d73a 100644
--- a/os/hal/platforms/SPC560Dxx/platform.mk
+++ b/os/hal/platforms/SPC560Dxx/platform.mk
@@ -1,11 +1,13 @@
 # List of all the SPC560Dxx platform files.

 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx/hal_lld.c \

+              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c

 

 # Required include directories

 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx \

+              ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \

               ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1

diff --git a/os/hal/platforms/SPC560Dxx/spc560d_registry.h b/os/hal/platforms/SPC560Dxx/spc560d_registry.h
index ea5206860..72fd5b36c 100644
--- a/os/hal/platforms/SPC560Dxx/spc560d_registry.h
+++ b/os/hal/platforms/SPC560Dxx/spc560d_registry.h
@@ -42,6 +42,12 @@
 #define SPC5_DSPI_FIFO_DEPTH                4

 #define SPC5_DSPI0_PCTL                     4

 #define SPC5_DSPI1_PCTL                     5

+#define SPC5_DSPI0_TX1_DMA_CH_ID            4

+#define SPC5_DSPI0_TX2_DMA_CH_ID            5

+#define SPC5_DSPI0_RX_DMA_CH_ID             6

+#define SPC5_DSPI1_TX1_DMA_CH_ID            7

+#define SPC5_DSPI1_TX2_DMA_CH_ID            8

+#define SPC5_DSPI1_RX_DMA_CH_ID             9

 #define SPC5_DSPI0_TX1_DMA_DEV_ID           1

 #define SPC5_DSPI0_TX2_DMA_DEV_ID           0

 #define SPC5_DSPI0_RX_DMA_DEV_ID            2

@@ -65,6 +71,7 @@
 #define SPC5_HAS_EDMA                       TRUE

 #define SPC5_EDMA_NCHANNELS                 16

 #define SPC5_EDMA_HAS_MUX                   TRUE

+#define SPC5_EDMA_MUX_PCTL                  23

 

 /* LINFlex attributes.*/

 #define SPC5_HAS_LINFLEX0                   TRUE

diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c
index 1a6cc24af..799908d46 100644
--- a/os/hal/platforms/SPC560Pxx/hal_lld.c
+++ b/os/hal/platforms/SPC560Pxx/hal_lld.c
@@ -96,6 +96,9 @@ void hal_lld_init(void) {
   PIT.CH[0].CVAL.R  = reg;

   PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */

   PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */

+

+  /* EDMA initialization.*/

+  edmaInit();

 }

 

 /**

diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c
index 7e2f32319..22979e61b 100644
--- a/os/hal/platforms/SPC563Mxx/hal_lld.c
+++ b/os/hal/platforms/SPC563Mxx/hal_lld.c
@@ -94,6 +94,9 @@ void hal_lld_init(void) {
   INTC.MCR.R   = 0;

   INTC.CPR.R   = 0;

   INTC.IACKR.R = (uint32_t)_vectors;

+

+  /* EDMA initialization.*/

+  edmaInit();

 }

 

 /**

diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h
index dc1145532..b26a65de9 100644
--- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h
+++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h
@@ -40,12 +40,12 @@
 #define SPC5_HAS_DSPI3                      FALSE

 #define SPC5_HAS_DSPI4                      FALSE

 #define SPC5_DSPI_FIFO_DEPTH                16

-#define SPC5_DSPI1_TX1_DMA_DEV_ID           12

-#define SPC5_DSPI1_TX2_DMA_DEV_ID           25

-#define SPC5_DSPI1_RX_DMA_DEV_ID            13

-#define SPC5_DSPI2_TX1_DMA_DEV_ID           14

-#define SPC5_DSPI2_TX2_DMA_DEV_ID           26

-#define SPC5_DSPI2_RX_DMA_DEV_ID            15

+#define SPC5_DSPI1_TX1_DMA_CH_ID            12

+#define SPC5_DSPI1_TX2_DMA_CH_ID            25

+#define SPC5_DSPI1_RX_DMA_CH_ID             13

+#define SPC5_DSPI2_TX1_DMA_CH_ID            14

+#define SPC5_DSPI2_TX2_DMA_CH_ID            26

+#define SPC5_DSPI2_RX_DMA_CH_ID             15

 #define SPC5_DSPI1_EOQF_HANDLER             vector132

 #define SPC5_DSPI1_EOQF_NUMBER              132

 #define SPC5_DSPI1_TFFF_HANDLER             vector133

diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c
index 7d87468ec..f6b220c85 100644
--- a/os/hal/platforms/SPC564Axx/hal_lld.c
+++ b/os/hal/platforms/SPC564Axx/hal_lld.c
@@ -106,6 +106,9 @@ void hal_lld_init(void) {
   INTC.MCR.R   = 0;

   INTC.CPR.R   = 0;

   INTC.IACKR.R = (uint32_t)_vectors;

+

+  /* EDMA initialization.*/

+  edmaInit();

 }

 

 /**

diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c
index 29ca160eb..4a3976f50 100644
--- a/os/hal/platforms/SPC56ELxx/hal_lld.c
+++ b/os/hal/platforms/SPC56ELxx/hal_lld.c
@@ -79,6 +79,9 @@ void hal_lld_init(void) {
   INTC.MCR.R        = 0;

   INTC.CPR.R        = 0;

   INTC.IACKR.R      = (uint32_t)_vectors;

+

+  /* EDMA initialization.*/

+  edmaInit();

 }

 

 /**

diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
index ad0e48115..f5db08a75 100644
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
+++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
@@ -94,7 +94,11 @@ SPIDriver SPID5;
  * @brief   DMA configuration for DSPI0 TX1.

  */

 static const edma_channel_config_t spi_dspi0_tx1_dma_config = {

-  SPC5_DSPI0_TX1_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO,

+  SPC5_DSPI0_TX1_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI0_TX1_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI0_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1

 };

 

@@ -102,7 +106,11 @@ static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
  * @brief   DMA configuration for DSPI0 TX2.

  */

 static const edma_channel_config_t spi_dspi0_tx2_dma_config = {

-  SPC5_DSPI0_TX2_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO,

+  SPC5_DSPI0_TX2_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  0,

+#endif

+  SPC5_SPI_DSPI0_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1

 };

 

@@ -110,7 +118,11 @@ static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
  * @brief   DMA configuration for DSPI0 RX.

  */

 static const edma_channel_config_t spi_dspi0_rx_dma_config = {

-  SPC5_DSPI0_RX_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO,

+  SPC5_DSPI0_RX_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI0_RX_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI0_DMA_IRQ_PRIO,

   spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1

 };

 #endif /* SPC5_SPI_USE_DSPI0 */

@@ -120,7 +132,11 @@ static const edma_channel_config_t spi_dspi0_rx_dma_config = {
  * @brief   DMA configuration for DSPI1 TX1.

  */

 static const edma_channel_config_t spi_dspi1_tx1_dma_config = {

-  SPC5_DSPI1_TX1_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO,

+  SPC5_DSPI1_TX1_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI1_TX1_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI1_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2

 };

 

@@ -128,7 +144,11 @@ static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
  * @brief   DMA configuration for DSPI1 TX2.

  */

 static const edma_channel_config_t spi_dspi1_tx2_dma_config = {

-  SPC5_DSPI1_TX2_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO,

+  SPC5_DSPI1_TX2_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  0,

+#endif

+  SPC5_SPI_DSPI1_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2

 };

 

@@ -136,7 +156,11 @@ static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
  * @brief   DMA configuration for DSPI1 RX.

  */

 static const edma_channel_config_t spi_dspi1_rx_dma_config = {

-  SPC5_DSPI1_RX_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO,

+  SPC5_DSPI1_RX_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI1_RX_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI1_DMA_IRQ_PRIO,

   spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2

 };

 #endif /* SPC5_SPI_USE_DSPI1 */

@@ -146,7 +170,11 @@ static const edma_channel_config_t spi_dspi1_rx_dma_config = {
  * @brief   DMA configuration for DSPI2 TX1.

  */

 static const edma_channel_config_t spi_dspi2_tx1_dma_config = {

-  SPC5_DSPI2_TX1_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO,

+  SPC5_DSPI2_TX1_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI2_TX1_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI2_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3

 };

 

@@ -154,7 +182,11 @@ static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
  * @brief   DMA configuration for DSPI2 TX2.

  */

 static const edma_channel_config_t spi_dspi2_tx2_dma_config = {

-  SPC5_DSPI2_TX2_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO,

+  SPC5_DSPI2_TX2_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  0,

+#endif

+  SPC5_SPI_DSPI2_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3

 };

 

@@ -162,7 +194,11 @@ static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
  * @brief   DMA configuration for DSPI2 RX.

  */

 static const edma_channel_config_t spi_dspi2_rx_dma_config = {

-  SPC5_DSPI2_RX_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO,

+  SPC5_DSPI2_RX_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI2_RX_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI2_DMA_IRQ_PRIO,

   spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3

 };

 #endif /* SPC5_SPI_USE_DSPI2 */

@@ -172,7 +208,11 @@ static const edma_channel_config_t spi_dspi2_rx_dma_config = {
  * @brief   DMA configuration for DSPI3 TX1.

  */

 static const edma_channel_config_t spi_dspi3_tx1_dma_config = {

-  SPC5_DSPI3_TX1_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO,

+  SPC5_DSPI3_TX1_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI3_TX1_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI3_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4

 };

 

@@ -180,7 +220,11 @@ static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
  * @brief   DMA configuration for DSPI3 TX2.

  */

 static const edma_channel_config_t spi_dspi3_tx2_dma_config = {

-  SPC5_DSPI3_TX2_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO,

+  SPC5_DSPI3_TX2_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  0,

+#endif

+  SPC5_SPI_DSPI3_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4

 };

 

@@ -188,7 +232,11 @@ static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
  * @brief   DMA configuration for DSPI3 RX.

  */

 static const edma_channel_config_t spi_dspi3_rx_dma_config = {

-  SPC5_DSPI3_RX_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO,

+  SPC5_DSPI3_RX_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI3_RX_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI3_DMA_IRQ_PRIO,

   spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4

 };

 #endif /* SPC5_SPI_USE_DSPI3 */

@@ -198,7 +246,11 @@ static const edma_channel_config_t spi_dspi3_rx_dma_config = {
  * @brief   DMA configuration for DSPI4 TX1.

  */

 static const edma_channel_config_t spi_dspi4_tx1_dma_config = {

-  SPC5_DSPI4_TX1_DMA_DEV_ID, SPC5_SPI_DSPI4_DMA_PRIO, SPC5_SPI_DSPI4_DMA_IRQ_PRIO,

+  SPC5_DSPI4_TX1_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI4_TX1_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI4_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5

 };

 

@@ -206,7 +258,11 @@ static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
  * @brief   DMA configuration for DSPI4 TX2.

  */

 static const edma_channel_config_t spi_dspi4_tx2_dma_config = {

-  SPC5_DSPI4_TX2_DMA_DEV_ID, SPC5_SPI_DSPI4_DMA_PRIO, SPC5_SPI_DSPI4_DMA_IRQ_PRIO,

+  SPC5_DSPI4_TX2_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  0,

+#endif

+  SPC5_SPI_DSPI4_DMA_IRQ_PRIO,

   spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5

 };

 

@@ -214,7 +270,11 @@ static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
  * @brief   DMA configuration for DSPI4 RX.

  */

 static const edma_channel_config_t spi_dspi4_rx_dma_config = {

-  SPC5_DSPI4_RX_DMA_DEV_ID, SPC5_SPI_DSPI4_DMA_PRIO, SPC5_SPI_DSPI4_DMA_IRQ_PRIO,

+  SPC5_DSPI4_RX_DMA_CH_ID,

+#if SPC5_EDMA_HAS_MUX

+  SPC5_DSPI4_RX_DMA_DEV_ID,

+#endif

+  SPC5_SPI_DSPI4_DMA_IRQ_PRIO,

   spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID5

 };

 #endif /* SPC5_SPI_USE_DSPI4 */

diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
index 95c4c72ab..b79e13a8e 100644
--- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
+++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
@@ -74,6 +74,14 @@
 #endif

 

 /**

+ * @brief   SPID5 driver enable switch.

+ * @details If set to @p TRUE the support for DSPI4 is included.

+ */

+#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__)

+#define SPC5_SPI_USE_DSPI4                  FALSE

+#endif

+

+/**

  * @brief   DSPI0 MCR PCS defaults.

  */

 #if !defined(SPC5_SPI_DSPI0_MCR) || defined(__DOXYGEN__)

@@ -130,31 +138,17 @@
 #endif

 

 /**

- * @brief   DSPI0 DMA priority.

- */

-#if !defined(SPC5_SPI_DSPI0_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_SPI_DSPI0_DMA_PRIO             10

-#endif

-

-/**

- * @brief   DSPI1 DMA priority.

+ * @brief   DSPI4 MCR PCS defaults.

  */

-#if !defined(SPC5_SPI_DSPI1_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_SPI_DSPI1_DMA_PRIO             10

-#endif

-

-/**

- * @brief   DSPI2 DMA priority.

- */

-#if !defined(SPC5_SPI_DSPI2_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_SPI_DSPI2_DMA_PRIO             10

-#endif

-

-/**

- * @brief   DSPI3 DMA priority.

- */

-#if !defined(SPC5_SPI_DSPI3_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_SPI_DSPI3_DMA_PRIO             10

+#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__)

+#define SPC5_SPI_DSPI4_MCR                  (SPC5_MCR_PCSIS0 |              \

+                                             SPC5_MCR_PCSIS1 |              \

+                                             SPC5_MCR_PCSIS2 |              \

+                                             SPC5_MCR_PCSIS3 |              \

+                                             SPC5_MCR_PCSIS4 |              \

+                                             SPC5_MCR_PCSIS5 |              \

+                                             SPC5_MCR_PCSIS6 |              \

+                                             SPC5_MCR_PCSIS7)

 #endif

 

 /**

@@ -186,6 +180,13 @@
 #endif

 

 /**

+ * @brief   DSPI4 DMA IRQ priority.

+ */

+#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__)

+#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO         10

+#endif

+

+/**

  * @brief   SPI DMA error hook.

  */

 #if !defined(SPC5_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)

@@ -221,6 +222,13 @@
 #endif

 

 /**

+ * @brief   DSPI4 DMA priority.

+ */

+#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__)

+#define SPC5_SPI_DSPI4_IRQ_PRIO             10

+#endif

+

+/**

  * @brief   DSPI0 peripheral configuration when started.

  * @note    The default configuration is 1 (always run) in run mode and

  *          2 (only halt) in low power mode. The defaults of the run modes

diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
index e13356197..7aad4027f 100644
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
+++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
@@ -31,6 +31,15 @@
 /* Driver local definitions.                                                 */

 /*===========================================================================*/

 

+static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES};

+#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__)

+static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES};

+#endif

+#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__)

+static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES};

+static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES};

+#endif

+

 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

@@ -1290,64 +1299,74 @@ void edmaInit(void) {
   SPC5_EDMA.EEIRL.R = 0x00000000;

   SPC5_EDMA.IRQRL.R = 0xFFFFFFFF;

   SPC5_EDMA.ERL.R =   0xFFFFFFFF;

-  for (i = 0; i < SPC5_EDMA_NCHANNELS; i++)

-    SPC5_EDMA.CPR[i].R = 0;

+#if SPC5_EDMA_NCHANNELS > 32

+  SPC5_EDMA.ERQRH.R = 0x00000000;

+  SPC5_EDMA.EEIRH.R = 0x00000000;

+  SPC5_EDMA.IRQRH.R = 0xFFFFFFFF;

+  SPC5_EDMA.ERH.R =   0xFFFFFFFF;

+#endif

+  /* Initializing all the channels with a different priority withing the

+     channels group.*/

+  for (i = 0; i < 16; i++) {

+    SPC5_EDMA.CPR[i].R = g0[i];

+#if SPC5_EDMA_NCHANNELS > 16

+    SPC5_EDMA.CPR[i + 16].R = g1[i];

+#endif

+#if SPC5_EDMA_NCHANNELS > 32

+    SPC5_EDMA.CPR[i + 32].R = g2[i];

+    SPC5_EDMA.CPR[i + 48].R = g3[i];

+#endif

+  }

 

   /* Error interrupt source.*/

   INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;

+

+#if defined(SPC5_EDMA_MUX_PCTL)

+  /* DMA MUX PCTL setup, only if required.*/

+  halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL);

+#endif

 }

 

 /**

  * @brief   EDMA channel allocation.

  *

  * @param[in] ccfg      channel configuration

- * @return              The channel TCD pointer.

+ * @return              The channel number.

  * @retval EDMA_ERROR   if the channel cannot be allocated.

  *

  * @special

  */

 edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {

-  edma_channel_t channel;

 

-  chDbgCheck((ccfg != NULL) && ((ccfg->dma_prio & 15) < 16) &&

-             (ccfg->dma_irq_prio < 16),

+  chDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16),

              "edmaChannelAllocate");

 

-#if SPC5_EDMA_HAS_MUX

-  /* Searching for a free channel, we have the MUX so any channel is

-     acceptable.*/

-  for (channel = 0; channel < SPC5_EDMA_NCHANNELS; channel++)

-    if (channels[channel] == NULL)

-      break;

-  if (channel >= SPC5_EDMA_NCHANNELS)

-    return EDMA_ERROR;                          /* No free channels.        */

+  /* If the channel is already taken then an error is returned.*/

+  if (channels[ccfg->dma_channel] != NULL)

+    return EDMA_ERROR;                          /* Already taken.           */

 

+#if SPC5_EDMA_HAS_MUX

   /* Programming the MUX.*/

-  SPC5_DMAMUX.CHCONFIG[channel].R = (uint8_t)(0x80 | ccfg->dma_periph);

-#else /* !SPC5_EDMA_HAS_MUX */

-  /* There is no MUX so we can just check that the specified channels is

-     available.*/

-  channel = (edma_channel_t)ccfg->dma_periph;

-  if (channels[channel] != NULL)

-    return EDMA_ERROR;                          /* Already taken.           */

+  SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 |

+                                                        ccfg->dma_periph);

 #endif /* !SPC5_EDMA_HAS_MUX */

 

   /* Associating the configuration to the channel.*/

-  channels[channel] = ccfg;

+  channels[ccfg->dma_channel] = ccfg;

 

   /* If an error callback is defined then the error interrupt source is

      enabled for the channel.*/

   if (ccfg->dma_error_func != NULL)

-    SPC5_EDMA.SEEIR.R = channel;

+    SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel;

 

   /* Setting up IRQ priority for the selected channel.*/

-  INTC.PSR[11 + channel].R = ccfg->dma_irq_prio;

+  INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio;

 

-  return channel;

+  return ccfg->dma_channel;

 }

 

 /**

- * @brief   EDMA channel allocation.

+ * @brief   EDMA channel release.

  *

  * @param[in] channel   the channel number

  *

diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
index b5e4ea8f7..e66574e4a 100644
--- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
+++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
@@ -37,6 +37,30 @@
 #define EDMA_ERROR                  -1

 

 /**

+ * @name    EDMA CR register definitions

+ * @{

+ */

+#define EDMA_CR_CX                  (1U << 17)

+#define EDMA_CR_ECX                 (1U << 16)

+#define EDMA_CR_GRP3PRI_MASK        (3U << 14)

+#define EDMA_CR_GRP3PRI(n)          ((n) << 14)

+#define EDMA_CR_GRP2PRI_MASK        (3U << 12)

+#define EDMA_CR_GRP2PRI(n)          ((n) << 12)

+#define EDMA_CR_GRP1PRI_MASK        (3U << 10)

+#define EDMA_CR_GRP1PRI(n)          ((n) << 10)

+#define EDMA_CR_GRP0PRI_MASK        (3U << 8)

+#define EDMA_CR_GRP0PRI(n)          ((n) << 8)

+#define EDMA_CR_EMLM                (1U << 7)

+#define EDMA_CR_CLM                 (1U << 6)

+#define EDMA_CR_HALT                (1U << 5)

+#define EDMA_CR_HOE                 (1U << 4)

+#define EDMA_CR_ERGA                (1U << 3)

+#define EDMA_CR_ERCA                (1U << 2)

+#define EDMA_CR_EDBG                (1U << 1)

+#define EDMA_CR_EBW                 (1U << 0)

+/** @} */

+

+/**

  * @name    EDMA mode constants

  * @{

  */

@@ -62,21 +86,68 @@
  * @brief   Default EDMA CR register initialization.

  */

 #if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)

-#define SPC5_EDMA_CR_SETTING                0x0000C400

+#define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP3PRI(3) |           \

+                                             EDMA_CR_GRP2PRI(2) |           \

+                                             EDMA_CR_GRP1PRI(1) |           \

+                                             EDMA_CR_GRP0PRI(0) |           \

+                                             EDMA_CR_ERGA)

 #endif

 

 /**

- * @brief   EDMA critical error handler, must not return.

+ * @brief   Static priorities for channels group 0.

  */

-#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)

-#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()

+#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__)

+#define SPC5_EDMA_GROUP0_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#endif

+

+/**

+ * @brief   Static priorities for channels group 1.

+ */

+#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__)

+#define SPC5_EDMA_GROUP1_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#endif

+

+/**

+ * @brief   Static priorities for channels group 2.

+ */

+#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__)

+#define SPC5_EDMA_GROUP2_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

+#endif

+

+/**

+ * @brief   Static priorities for channels group 3.

+ */

+#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__)

+#define SPC5_EDMA_GROUP3_PRIORITIES                                         \

+  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15

 #endif

 

 /**

  * @brief   EDMA error handler IRQ priority.

  */

 #if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__)

-#define SPC5_EDMA_ERROR_IRQ_PRIO            12

+#define SPC5_EDMA_ERROR_IRQ_PRIO            2

+#endif

+

+/**

+ * @brief   EDMA peripheral configuration when started.

+ * @note    The default configuration is 1 (always run) in run mode and

+ *          2 (only halt) in low power mode. The defaults of the run modes

+ *          are defined in @p hal_lld.h.

+ */

+#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__)

+#define SPC5_EDMA_MUX_START_PCTL            (SPC5_ME_PCTL_RUN(1) |          \

+                                             SPC5_ME_PCTL_LP(2))

+#endif

+

+/**

+ * @brief   EDMA critical error handler, must not return.

+ */

+#if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__)

+#define SPC5_EDMA_ERROR_HANDLER()           chSysHalt()

 #endif

 

 /*===========================================================================*/

@@ -648,10 +719,11 @@ typedef void (*edma_error_callback_t)(edma_channel_t channel,
  * @brief   Type of an EDMA channel configuration structure.

  */

 typedef struct {

+  edma_channel_t        dma_channel;    /**< @brief Channel to be allocated.*/

+#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__)

   uint8_t               dma_periph;     /**< @brief Peripheral to be

                                              associated to the channel.     */

-  uint8_t               dma_prio;       /**< @brief Priority register value

-                                             for this channel.              */

+#endif

   uint8_t               dma_irq_prio;   /**< @brief IRQ priority level for

                                              this channel.                  */

   edma_callback_t       dma_func;       /**< @brief Channel callback,

diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
index 9017ec1e8..cb479fa1b 100644
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
+++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
@@ -108,7 +108,7 @@ static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR;
  * @brief   DMA configuration for EQADC CFIFO0.

  */

 static const edma_channel_config_t adc_cfifo0_dma_config = {

-  0, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,

+  0, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,

   NULL, adc_serve_dma_error_irq, &ADCD1

 };

 

@@ -116,7 +116,7 @@ static const edma_channel_config_t adc_cfifo0_dma_config = {
  * @brief   DMA configuration for EQADC RFIFO0.

  */

 static const edma_channel_config_t adc_rfifo0_dma_config = {

-  1, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,

+  1, SPC5_ADC_FIFO0_DMA_IRQ_PRIO,

   adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD1

 };

 #endif /* SPC5_ADC_USE_ADC0_Q0 */

@@ -126,7 +126,7 @@ static const edma_channel_config_t adc_rfifo0_dma_config = {
  * @brief   DMA configuration for EQADC CFIFO1.

  */

 static const edma_channel_config_t adc_cfifo1_dma_config = {

-  2, SPC5_ADC_FIFO1_DMA_PRIO, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,

+  2, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,

   NULL, adc_serve_dma_error_irq, &ADCD2

 };

 

@@ -134,7 +134,7 @@ static const edma_channel_config_t adc_cfifo1_dma_config = {
  * @brief   DMA configuration for EQADC RFIFO1.

  */

 static const edma_channel_config_t adc_rfifo1_dma_config = {

-  3, SPC5_ADC_FIFO1_DMA_PRIO, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,

+  3, SPC5_ADC_FIFO1_DMA_IRQ_PRIO,

   adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD2

 };

 #endif /* SPC5_ADC_USE_ADC0_Q1 */

@@ -144,7 +144,7 @@ static const edma_channel_config_t adc_rfifo1_dma_config = {
  * @brief   DMA configuration for EQADC CFIFO2.

  */

 static const edma_channel_config_t adc_cfifo2_dma_config = {

-  4, SPC5_ADC_FIFO2_DMA_PRIO, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,

+  4, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,

   NULL, adc_serve_dma_error_irq, &ADCD3

 };

 

@@ -152,7 +152,7 @@ static const edma_channel_config_t adc_cfifo2_dma_config = {
  * @brief   DMA configuration for EQADC RFIFO2.

  */

 static const edma_channel_config_t adc_rfifo2_dma_config = {

-  5, SPC5_ADC_FIFO2_DMA_PRIO, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,

+  5, SPC5_ADC_FIFO2_DMA_IRQ_PRIO,

   adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD3

 };

 #endif /* SPC5_ADC_USE_ADC0_Q2 */

@@ -162,7 +162,7 @@ static const edma_channel_config_t adc_rfifo2_dma_config = {
  * @brief   DMA configuration for EQADC CFIFO3.

  */

 static const edma_channel_config_t adc_cfifo3_dma_config = {

-  6, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,

+  6, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,

   NULL, adc_serve_dma_error_irq, &ADCD4

 };

 

@@ -170,7 +170,7 @@ static const edma_channel_config_t adc_cfifo3_dma_config = {
  * @brief   DMA configuration for EQADC RFIFO3.

  */

 static const edma_channel_config_t adc_rfifo3_dma_config = {

-  7, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,

+  7, SPC5_ADC_FIFO3_DMA_IRQ_PRIO,

   adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD4

 };

 #endif /* SPC5_ADC_USE_ADC1_Q3 */

@@ -180,7 +180,7 @@ static const edma_channel_config_t adc_rfifo3_dma_config = {
  * @brief   DMA configuration for EQADC CFIFO4.

  */

 static const edma_channel_config_t adc_cfifo4_dma_config = {

-  8, SPC5_ADC_FIFO4_DMA_PRIO, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,

+  8, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,

   NULL, adc_serve_dma_error_irq, &ADCD5

 };

 

@@ -188,7 +188,7 @@ static const edma_channel_config_t adc_cfifo4_dma_config = {
  * @brief   DMA configuration for EQADC RFIFO4.

  */

 static const edma_channel_config_t adc_rfifo4_dma_config = {

-  9, SPC5_ADC_FIFO4_DMA_PRIO, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,

+  9, SPC5_ADC_FIFO4_DMA_IRQ_PRIO,

   adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD5

 };

 #endif /* SPC5_ADC_USE_ADC1_Q4 */

@@ -198,7 +198,7 @@ static const edma_channel_config_t adc_rfifo4_dma_config = {
  * @brief   DMA configuration for EQADC CFIFO5.

  */

 static const edma_channel_config_t adc_cfifo5_dma_config = {

-  10, SPC5_ADC_FIFO5_DMA_PRIO, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,

+  10, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,

   NULL, adc_serve_dma_error_irq, &ADCD6

 };

 

@@ -206,7 +206,7 @@ static const edma_channel_config_t adc_cfifo5_dma_config = {
  * @brief   DMA configuration for EQADC RFIFO5.

  */

 static const edma_channel_config_t adc_rfifo5_dma_config = {

-  11, SPC5_ADC_FIFO5_DMA_PRIO, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,

+  11, SPC5_ADC_FIFO5_DMA_IRQ_PRIO,

   adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD6

 };

 #endif /* SPC5_ADC_USE_ADC1_Q5 */

diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
index 5a16967ff..6be4ca5d4 100644
--- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
+++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
@@ -347,48 +347,6 @@
 #endif

 

 /**

- * @brief   EQADC CFIFO0 and RFIFO0 DMA priority.

- */

-#if !defined(SPC5_ADC_FIFO0_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_ADC_FIFO0_DMA_PRIO             12

-#endif

-

-/**

- * @brief   EQADC CFIFO1 and RFIFO1 DMA priority.

- */

-#if !defined(SPC5_ADC_FIFO1_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_ADC_FIFO1_DMA_PRIO             12

-#endif

-

-/**

- * @brief   EQADC CFIFO2 and RFIFO2 DMA priority.

- */

-#if !defined(SPC5_ADC_FIFO2_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_ADC_FIFO2_DMA_PRIO             12

-#endif

-

-/**

- * @brief   EQADC CFIFO3 and RFIFO3 DMA priority.

- */

-#if !defined(SPC5_ADC_FIFO3_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_ADC_FIFO3_DMA_PRIO             12

-#endif

-

-/**

- * @brief   EQADC CFIFO4 and RFIFO4 DMA priority.

- */

-#if !defined(SPC5_ADC_FIFO4_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_ADC_FIFO4_DMA_PRIO             12

-#endif

-

-/**

- * @brief   EQADC CFIFO5 and RFIFO5 DMA priority.

- */

-#if !defined(SPC5_ADC_FIFO5_DMA_PRIO) || defined(__DOXYGEN__)

-#define SPC5_ADC_FIFO5_DMA_PRIO             12

-#endif

-

-/**

  * @brief   EQADC CFIFO0 and RFIFO0 DMA IRQ priority.

  */

 #if !defined(SPC5_ADC0_FIFO0_DMA_IRQ_PRIO) || defined(__DOXYGEN__)